[Intel-gfx] [PATCH v2 3/4] drm/i915: Add new frontbuffer tracking interface to queue flush

[Jouni Högander]

We want to wait dma fences in dirtyfb ioctl. As we don't want to make
dirtyfb ioctl as blocking call we need to use
dma_fence_add_callback. Callback used for dma_fence_add_callback is
called from atomic context. Due to this we need to add a new
frontbuffer tracking interface to queue flush.

v2: Check if flush work is already pending

Signed-off-by: Jouni Högander 
---
 .../gpu/drm/i915/display/intel_frontbuffer.c  | 33 +++
 .../gpu/drm/i915/display/intel_frontbuffer.h  |  4 +++
 2 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c 
b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 17a7aa8b28c2..d33b6021d9ed 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -202,6 +202,39 @@ void __intel_fb_flush(struct intel_frontbuffer *front,
frontbuffer_flush(i915, frontbuffer_bits, origin);
 }
 
+static void intel_frontbuffer_flush_work(struct work_struct *work)
+{
+   struct intel_frontbuffer *front =
+   container_of(work, struct intel_frontbuffer, flush_work);
+
+   i915_gem_object_flush_if_display(front->obj);
+   intel_frontbuffer_flush(front, ORIGIN_DIRTYFB);
+   intel_frontbuffer_put(front);
+}
+
+/**
+ * intel_frontbuffer_queue_flush - queue flushing frontbuffer object
+ * @front: GEM object to flush
+ *
+ * This function is targeted for our dirty callback for queueing flush when
+ * dma fence is signales
+ */
+void intel_frontbuffer_queue_flush(struct intel_frontbuffer *front)
+{
+   unsigned int frontbuffer_bits;
+
+   if (!front)
+   return;
+
+   frontbuffer_bits = atomic_read(>bits);
+   if (!frontbuffer_bits || work_pending(>flush_work))
+   return;
+
+   kref_get(>ref);
+   INIT_WORK(>flush_work, intel_frontbuffer_flush_work);
+   schedule_work(>flush_work);
+}
+
 static int frontbuffer_active(struct i915_active *ref)
 {
struct intel_frontbuffer *front =
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.h 
b/drivers/gpu/drm/i915/display/intel_frontbuffer.h
index 3c474ed937fb..11760b5ce9fa 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.h
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.h
@@ -47,6 +47,8 @@ struct intel_frontbuffer {
struct i915_active write;
struct drm_i915_gem_object *obj;
struct rcu_head rcu;
+
+   struct work_struct flush_work;
 };
 
 /*
@@ -163,6 +165,8 @@ static inline void intel_frontbuffer_flush(struct 
intel_frontbuffer *front,
__intel_fb_flush(front, origin, frontbuffer_bits);
 }
 
+void intel_frontbuffer_queue_flush(struct intel_frontbuffer *front);
+
 void intel_frontbuffer_track(struct intel_frontbuffer *old,
 struct intel_frontbuffer *new,
 unsigned int frontbuffer_bits);
-- 
2.34.1

[Intel-gfx] [PATCH v2 4/4] drm/i915: Handle dma fences in dirtyfb callback

[Jouni Högander]

Take into account dma fences in dirtyfb callback. If there is no
unsignaled dma fences perform flush immediately. If there are
unsignaled dma fences perform invalidate and add callback which will
queue flush when the fence gets signaled.

v2: Use dma_resv_get_singleton

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_fb.c | 57 +++--
 1 file changed, 54 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index 446bbf7986b6..56a21377680d 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -7,6 +7,9 @@
 #include 
 #include 
 
+#include 
+#include 
+
 #include "i915_drv.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
@@ -1896,6 +1899,21 @@ static int intel_user_framebuffer_create_handle(struct 
drm_framebuffer *fb,
return drm_gem_handle_create(file, >base, handle);
 }
 
+struct frontbuffer_fence_cb {
+   struct dma_fence_cb base;
+   struct intel_frontbuffer *front;
+};
+
+static void intel_user_framebuffer_fence_wake(struct dma_fence *dma,
+ struct dma_fence_cb *data)
+{
+   struct frontbuffer_fence_cb *cb = container_of(data, typeof(*cb), base);
+
+   intel_frontbuffer_queue_flush(cb->front);
+   kfree(cb);
+   dma_fence_put(dma);
+}
+
 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
struct drm_file *file,
unsigned int flags, unsigned int color,
@@ -1903,11 +1921,44 @@ static int intel_user_framebuffer_dirty(struct 
drm_framebuffer *fb,
unsigned int num_clips)
 {
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+   struct intel_frontbuffer *front = to_intel_frontbuffer(fb);
+   struct dma_fence *fence;
+   struct frontbuffer_fence_cb *cb;
+   int ret = 0;
+
+   if (dma_resv_test_signaled(obj->base.resv, dma_resv_usage_rw(false)))
+   goto flush;
+
+   intel_frontbuffer_invalidate(front, ORIGIN_DIRTYFB);
+
+   ret = dma_resv_get_singleton(obj->base.resv, dma_resv_usage_rw(false),
+);
+   if (ret || !fence)
+   goto flush;
+
+   cb = kmalloc(sizeof(*cb), GFP_KERNEL);
+   if (!cb) {
+   dma_fence_put(fence);
+   ret = -ENOMEM;
+   goto flush;
+   }
 
-   i915_gem_object_flush_if_display(obj);
-   intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
+   cb->front = front;
 
-   return 0;
+   ret = dma_fence_add_callback(fence, >base,
+intel_user_framebuffer_fence_wake);
+   if (ret) {
+   intel_user_framebuffer_fence_wake(fence, >base);
+   if (ret == -ENOENT)
+   ret = 0;
+   }
+
+   return ret;
+
+flush:
+   i915_gem_object_flush_if_display(obj);
+   intel_frontbuffer_flush(front, ORIGIN_DIRTYFB);
+   return ret;
 }
 
 static const struct drm_framebuffer_funcs intel_fb_funcs = {
-- 
2.34.1

[Intel-gfx] [PATCH v2 0/4] Handle dma fences in dirtyfb ioctl

[Jouni Högander]

Currently i915 dirtyfb ioctl is not taking dma fences into
account. This works with features like FBC, PSR, DRRS because our gem
code is triggering flush again when rendering completes. We are
targeting in getting rid of frontbuffer tracking code: Flusing hook
from gem code will be removed as well.

This patch set is adding dma fence handling into i915 dirtyfb ioctl.

v2:
 - Clear fbc and psr busy bits on flip
 - Check if flush work is already pending
 - Use dma_resv_get_singleton

Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 

Jouni Högander (4):
  drm/i915/fbc: Clear frontbuffer busy bits on flip
  drm/i915/psr: Clear frontbuffer busy bits on flip
  drm/i915: Add new frontbuffer tracking interface to queue flush
  drm/i915: Handle dma fences in dirtyfb callback

 drivers/gpu/drm/i915/display/intel_fb.c   | 57 ++-
 drivers/gpu/drm/i915/display/intel_fbc.c  |  6 +-
 .../gpu/drm/i915/display/intel_frontbuffer.c  | 33 +++
 .../gpu/drm/i915/display/intel_frontbuffer.h  |  4 ++
 drivers/gpu/drm/i915/display/intel_psr.c  |  6 ++
 5 files changed, 99 insertions(+), 7 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH v2 2/4] drm/i915/psr: Clear frontbuffer busy bits on flip

[Jouni Högander]

We are planning to move flush performed from work queue. This
means it is possible to have invalidate -> flip -> flush sequence.
Handle this by clearing possible busy bits on flip.

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 04ab034a8d57..3a18334665fa 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2230,6 +2230,12 @@ static void _intel_psr_post_plane_update(const struct 
intel_atomic_state *state,
if (crtc_state->crc_enabled && psr->enabled)
psr_force_hw_tracking_exit(intel_dp);
 
+   /*
+* Clear possible busy bits in case we have
+* invalidate -> flip -> flush sequence.
+*/
+   intel_dp->psr.busy_frontbuffer_bits = 0;
+
mutex_unlock(>lock);
}
 }
-- 
2.34.1

[Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Clear frontbuffer busy bits on flip

[Jouni Högander]

We are planning to move flush performed from work queue. This
means it is possible to have invalidate -> flip -> flush sequence.
Handle this by clearing possible busy bits on flip.

Signed-off-by: Ville Syrjälä 
Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..3c0a143264d2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1299,11 +1299,9 @@ static void __intel_fbc_post_update(struct intel_fbc 
*fbc)
lockdep_assert_held(>lock);
 
fbc->flip_pending = false;
+   fbc->busy_bits = 0;
 
-   if (!fbc->busy_bits)
-   intel_fbc_activate(fbc);
-   else
-   intel_fbc_deactivate(fbc, "frontbuffer write");
+   intel_fbc_activate(fbc);
 }
 
 void intel_fbc_post_update(struct intel_atomic_state *state,
-- 
2.34.1

[Intel-gfx] ✗ Fi.CI.IGT: failure for Replace acronym with full platform name in defines.

[Patchwork]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/121387/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13426_full -> Patchwork_121387v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_121387v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_121387v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_121387v1_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_flip@plain-flip-ts-check@a-vga1:
- shard-snb:  [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-snb4/igt@kms_flip@plain-flip-ts-ch...@a-vga1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-snb7/igt@kms_flip@plain-flip-ts-ch...@a-vga1.html

  
Known issues


  Here are the changes found in Patchwork_121387v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl:  [PASS][3] -> [FAIL][4] ([i915#7742])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-rkl-6/igt@drm_fdinfo@most-busy-check-...@rcs0.html

  * igt@drm_fdinfo@most-busy-idle-check-all@ccs0:
- shard-mtlp: NOTRUN -> [SKIP][5] ([i915#8414]) +5 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-mtlp-7/igt@drm_fdinfo@most-busy-idle-check-...@ccs0.html

  * igt@gem_barrier_race@remote-request@rcs0:
- shard-glk:  NOTRUN -> [ABORT][6] ([i915#7461] / [i915#8211])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-glk1/igt@gem_barrier_race@remote-requ...@rcs0.html

  * igt@gem_basic@multigpu-create-close:
- shard-rkl:  NOTRUN -> [SKIP][7] ([i915#7697])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-rkl-4/igt@gem_ba...@multigpu-create-close.html

  * igt@gem_eio@reset-stress:
- shard-dg1:  [PASS][8] -> [FAIL][9] ([i915#5784])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-dg1-18/igt@gem_...@reset-stress.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-dg1-16/igt@gem_...@reset-stress.html

  * igt@gem_exec_balancer@invalid-bonds:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#4036])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-mtlp-3/igt@gem_exec_balan...@invalid-bonds.html

  * igt@gem_exec_balancer@parallel-balancer:
- shard-rkl:  NOTRUN -> [SKIP][11] ([i915#4525])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-rkl-4/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl:  [PASS][12] -> [FAIL][13] ([i915#2842]) +2 similar 
issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-rkl-2/igt@gem_exec_fair@basic-p...@vecs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-rkl-2/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_reloc@basic-cpu-gtt-active:
- shard-rkl:  NOTRUN -> [SKIP][14] ([i915#3281])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-rkl-4/igt@gem_exec_re...@basic-cpu-gtt-active.html

  * igt@gem_exec_reloc@basic-gtt:
- shard-mtlp: NOTRUN -> [SKIP][15] ([i915#3281])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-mtlp-7/igt@gem_exec_re...@basic-gtt.html

  * igt@gem_exec_suspend@basic-s3@smem:
- shard-snb:  NOTRUN -> [DMESG-WARN][16] ([i915#8841]) +4 similar 
issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-snb6/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2:  [PASS][17] -> [ABORT][18] ([i915#7975] / [i915#8213])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-dg2-11/igt@gem_exec_suspend@basic-s4-devi...@lmem0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/shard-dg2-10/igt@gem_exec_suspend@basic-s4-devi...@lmem0.html
- shard-dg1:  [PASS][19] -> [ABORT][20] ([i915#7975] / [i915#8213])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-dg1-15/igt@gem_exec_suspend@basic-s4-devi...@lmem0.html
   [20]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests 
(rev8)
URL   : https://patchwork.freedesktop.org/series/117713/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13426_full -> Patchwork_117713v8_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_117713v8_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_117713v8_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_117713v8_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gt_timelines:
- shard-apl:  [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-apl4/igt@i915_selftest@live@gt_timelines.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-apl7/igt@i915_selftest@live@gt_timelines.html

  * igt@kms_flip@blocking-absolute-wf_vblank-interruptible@b-vga1:
- shard-snb:  [PASS][3] -> [ABORT][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-snb2/igt@kms_flip@blocking-absolute-wf_vblank-interrupti...@b-vga1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-snb2/igt@kms_flip@blocking-absolute-wf_vblank-interrupti...@b-vga1.html

  * igt@perf_pmu@rc6-suspend:
- shard-dg2:  [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-dg2-8/igt@perf_...@rc6-suspend.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-dg2-2/igt@perf_...@rc6-suspend.html

  
Known issues


  Here are the changes found in Patchwork_117713v8_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl:  [PASS][7] -> [FAIL][8] ([i915#7742])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-rkl-7/igt@drm_fdinfo@most-busy-check-...@rcs0.html

  * igt@drm_fdinfo@most-busy-idle-check-all@ccs0:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#8414]) +5 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-mtlp-5/igt@drm_fdinfo@most-busy-idle-check-...@ccs0.html

  * igt@gem_basic@multigpu-create-close:
- shard-rkl:  NOTRUN -> [SKIP][10] ([i915#7697])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-rkl-2/igt@gem_ba...@multigpu-create-close.html

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [PASS][11] -> [FAIL][12] ([i915#6268])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-tglu-9/igt@gem_ctx_e...@basic-nohangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-tglu-9/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_eio@kms:
- shard-dg2:  [PASS][13] -> [INCOMPLETE][14] ([i915#7892])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-dg2-8/igt@gem_...@kms.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-dg2-1/igt@gem_...@kms.html
- shard-apl:  [PASS][15] -> [FAIL][16] ([i915#8764])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-apl1/igt@gem_...@kms.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-apl6/igt@gem_...@kms.html

  * igt@gem_eio@reset-stress:
- shard-dg1:  [PASS][17] -> [FAIL][18] ([i915#5784])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-dg1-18/igt@gem_...@reset-stress.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-dg1-13/igt@gem_...@reset-stress.html

  * igt@gem_exec_balancer@invalid-bonds:
- shard-mtlp: NOTRUN -> [SKIP][19] ([i915#4036])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-mtlp-2/igt@gem_exec_balan...@invalid-bonds.html

  * igt@gem_exec_balancer@parallel-balancer:
- shard-rkl:  NOTRUN -> [SKIP][20] ([i915#4525])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/shard-rkl-2/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_capture@capture@vcs0-smem:
- shard-mtlp: [PASS][21] -> [DMESG-WARN][22] ([i915#5591])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-mtlp-2/igt@gem_exec_capture@capt...@vcs0-smem.html
   [22]: 

Re: [Intel-gfx] [PATCH v7] drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests

[Ceraolo Spurio, Daniele]

On 7/20/2023 4:01 PM, Alan Previn wrote:

On MTL, if the GSC Proxy init flows haven't completed, submissions to the
GSC engine will fail. Those init flows are dependent on the mei's
gsc_proxy component that is loaded in parallel with i915 and a
worker that could potentially start after i915 driver init is done.

That said, all subsytems that access the GSC engine today does check
for such init flow completion before using the GSC engine. However,
selftests currently don't wait on anything before starting.

To fix this, add a waiter function at the start of __run_selftests
that waits for gsc-proxy init flows to complete. Selftests shouldn't
care if the proxy-init failed as that should be flagged elsewhere.

Difference from prior versions:
v7: - Change the fw status to INTEL_UC_FIRMWARE_LOAD_FAIL if the
  proxy-init fails so that intel_gsc_uc_fw_proxy_get_status
  catches it. (Daniele)
v6: - Add a helper that returns something more than a boolean
  so we selftest can stop waiting if proxy-init hadn't
  completed but failed (Daniele).
v5: - Move the call to __wait_gsc_proxy_completed from common
  __run_selftests dispatcher to the group-level selftest
  function (Trvtko).
- change the pr_info to pr_warn if we hit the timeout.
v4: - Remove generalized waiters function table framework (Tvrtko).
- Remove mention of CI-framework-timeout from comments (Tvrtko).
v3: - Rebase to latest drm-tip.
v2: - Based on internal testing, increase the timeout for gsc-proxy
  specific case to 8 seconds.

Signed-off-by: Alan Previn 


Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
  drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 14 +
  drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h |  1 +
  drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 13 +++-
  .../gpu/drm/i915/selftests/i915_selftest.c| 31 +++
  4 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index ab1a456f833d..163021705210 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -45,6 +45,20 @@ bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc 
*gsc, bool needs_wakere
   HECI1_FWSTS1_PROXY_STATE_NORMAL;
  }
  
+int intel_gsc_uc_fw_proxy_get_status(struct intel_gsc_uc *gsc)

+{
+   if (!(IS_ENABLED(CONFIG_INTEL_MEI_GSC_PROXY)))
+   return -ENODEV;
+   if (!intel_uc_fw_is_loadable(>fw))
+   return -ENODEV;
+   if (__intel_uc_fw_status(>fw) == INTEL_UC_FIRMWARE_LOAD_FAIL)
+   return -ENOLINK;
+   if (!intel_gsc_uc_fw_proxy_init_done(gsc, true))
+   return -EAGAIN;
+
+   return 0;
+}
+
  bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
  {
return gsc_uc_get_fw_status(gsc_uc_to_gt(gsc)->uncore, false) &
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
index ad2167ce9137..bc9dd0de8aaf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
@@ -16,5 +16,6 @@ int intel_gsc_fw_get_binary_info(struct intel_uc_fw *gsc_fw, 
const void *data, s
  int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc);
  bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc);
  bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc, bool 
needs_wakeref);
+int intel_gsc_uc_fw_proxy_get_status(struct intel_gsc_uc *gsc);
  
  #endif

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
index 034b53a71541..0d3b22a74365 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
@@ -62,8 +62,18 @@ static void gsc_work(struct work_struct *work)
}
  
  		ret = intel_gsc_proxy_request_handler(gsc);

-   if (ret)
+   if (ret) {
+   if (actions & GSC_ACTION_FW_LOAD) {
+   /*
+* A proxy failure right after firmware load 
means the proxy-init
+* step has failed so mark GSC as not usable 
after this
+*/
+   drm_err(>i915->drm,
+   "GSC proxy handler failed to init\n");
+   intel_uc_fw_change_status(>fw, 
INTEL_UC_FIRMWARE_LOAD_FAIL);
+   }
goto out_put;
+   }
  
  		/* mark the GSC FW init as done the first time we run this */

if (actions & GSC_ACTION_FW_LOAD) {
@@ -78,6 +88,7 @@ static void gsc_work(struct work_struct *work)
} else {
drm_err(>i915->drm,
"GSC status reports proxy init not 
complete\n");
+ 

[Intel-gfx] ✓ Fi.CI.BAT: success for Replace acronym with full platform name in defines.

[Patchwork]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/121387/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13426 -> Patchwork_121387v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/index.html

Participating hosts (41 -> 41)
--

  Additional (2): fi-kbl-soraka bat-adlp-11 
  Missing(2): fi-tgl-1115g4 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_121387v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_auth@basic-auth:
- bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#4423] / [i915#8011])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-adlp-11/igt@core_a...@basic-auth.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_module_load@load:
- bat-adlp-11:NOTRUN -> [DMESG-WARN][4] ([i915#4423])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-adlp-11/igt@i915_module_l...@load.html

  * igt@i915_pm_rpm@basic-rte:
- fi-skl-guc: [PASS][5] -> [FAIL][6] ([i915#7940])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-skl-guc/igt@i915_pm_...@basic-rte.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/fi-skl-guc/igt@i915_pm_...@basic-rte.html
- fi-kbl-7567u:   [PASS][7] -> [FAIL][8] ([i915#7940])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-kbl-7567u/igt@i915_pm_...@basic-rte.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/fi-kbl-7567u/igt@i915_pm_...@basic-rte.html

  * igt@i915_selftest@live@gt_mocs:
- bat-mtlp-6: [PASS][9] -> [DMESG-FAIL][10] ([i915#7059])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#7913])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@slpc:
- bat-mtlp-6: [PASS][12] -> [DMESG-WARN][13] ([i915#6367])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-mtlp-6/igt@i915_selftest@l...@slpc.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-mtlp-6/igt@i915_selftest@l...@slpc.html
- bat-rpls-2: NOTRUN -> [DMESG-WARN][14] ([i915#6367])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
- bat-rpls-1: NOTRUN -> [DMESG-WARN][15] ([i915#6367])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][16] ([i915#6687] / [i915#7978] / 
[i915#8668])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][17] ([i915#7828])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-jsl-3:  NOTRUN -> [SKIP][18] ([i915#7828])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-jsl-3/igt@kms_chamelium_...@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][19] ([fdo#109271]) +15 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-2: NOTRUN -> [SKIP][20] ([i915#1845])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121387v1/bat-rpls-2/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3:  [ABORT][21] ([i915#5122]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
   [22]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Replace acronym with full platform name in defines.

[Patchwork]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/121387/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Replace acronym with full platform name in defines.

[Patchwork]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/121387/
State : warning

== Summary ==

Error: dim checkpatch failed
26b2934657f0 drm/i915/hsw: s/HSW/HASWELL for platform/subplatform defines
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#46: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:57:
+#define HAS_IPS(i915)  (IS_HASWELL_ULT(i915) || 
IS_BROADWELL(i915))

-:124: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#124: FILE: drivers/gpu/drm/i915/i915_drv.h:595:
+#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
(INTEL_DEVID(i915) & 0xFF00) == 0x0C00)

-:136: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#136: FILE: drivers/gpu/drm/i915/i915_drv.h:605:
+#define IS_HASWELL_GT3(i915)   (IS_HASWELL(i915) && \
 INTEL_INFO(i915)->gt == 3)

-:139: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#139: FILE: drivers/gpu/drm/i915/i915_drv.h:607:
+#define IS_HASWELL_GT1(i915)   (IS_HASWELL(i915) && \
 INTEL_INFO(i915)->gt == 1)

-:152: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#152: FILE: drivers/gpu/drm/i915/i915_drv.h:864:
+#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
 2 : HAS_L3_DPF(i915))

total: 0 errors, 0 warnings, 5 checks, 138 lines checked
918824b50d4c drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform defines
-:69: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#69: FILE: drivers/gpu/drm/i915/i915_drv.h:601:
+#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
 INTEL_INFO(i915)->gt == 3)

total: 0 errors, 0 warnings, 1 checks, 81 lines checked
0a3dbaf76831 drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines
-:71: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#71: FILE: drivers/gpu/drm/i915/i915_drv.h:620:
+#define IS_SKYLAKE_GT2(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)

-:74: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#74: FILE: drivers/gpu/drm/i915/i915_drv.h:622:
+#define IS_SKYLAKE_GT3(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)

-:77: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#77: FILE: drivers/gpu/drm/i915/i915_drv.h:624:
+#define IS_SKYLAKE_GT4(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 4)

total: 0 errors, 0 warnings, 3 checks, 58 lines checked
985ef963e0e6 drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines
-:106: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#106: FILE: drivers/gpu/drm/i915/i915_drv.h:626:
+#define IS_KABYLAKE_GT2(i915)  (IS_KABYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)

-:109: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#109: FILE: drivers/gpu/drm/i915/i915_drv.h:628:
+#define IS_KABYLAKE_GT3(i915)  (IS_KABYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)

total: 0 errors, 0 warnings, 2 checks, 89 lines checked
dfe80846f681 drm/i915/cfl: s/CFL/COFFEELAKE for platform/subplatform defines
-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#43: FILE: drivers/gpu/drm/i915/i915_drv.h:634:
+#define IS_COFFEELAKE_GT2(i915)(IS_COFFEELAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)

-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#46: FILE: drivers/gpu/drm/i915/i915_drv.h:636:
+#define IS_COFFEELAKE_GT3(i915)(IS_COFFEELAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)

total: 0 errors, 0 warnings, 2 checks, 28 lines checked
be676d5fe142 drm/i915/cml: s/CML/COMETLAKE for platform/subplatform defines
-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#43: FILE: drivers/gpu/drm/i915/i915_drv.h:643:
+#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)

total: 0 errors, 0 warnings, 1 checks, 25 lines checked
512da45fb53f drm/i915/rkl: s/RKL/ROCKETLAKE for platform/subplatform defines
b0b6ca2cb60d drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines
-:38: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#38: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:448:
+   if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
+   (DISPLAY_VER(dev_priv) >= 12)) {

-:101: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#101: FILE: 

[Intel-gfx] PR for ADLP DMC v2.20 and MTL DMC v2.13

[Gustavo Sousa]

The following changes since commit b6ea35ff6b9869470a0c68813f1668acb3d356a8:

  copy-firmware: Fix linking directories when using compression (2023-07-25 
06:53:30 -0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware dmc-adlp_2.20-mtl_2.13

for you to fetch changes up to fd6e13ca2a1141aeede3666f72d2a006a3903fc0:

  i915: Update MTL DMC to v2.13 (2023-07-26 13:59:54 -0300)


Gustavo Sousa (2):
  i915: Update ADLP DMC to v2.20
  i915: Update MTL DMC to v2.13

 WHENCE|   4 ++--
 i915/adlp_dmc.bin | Bin 79044 -> 79088 bytes
 i915/mtl_dmc.bin  | Bin 49104 -> 52164 bytes
 3 files changed, 2 insertions(+), 2 deletions(-)

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915/gt: Simplify shmem_create_from_object map_type selection

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/gt: Simplify 
shmem_create_from_object map_type selection
URL   : https://patchwork.freedesktop.org/series/121373/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13426_full -> Patchwork_121373v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_121373v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_121373v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_121373v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fence@basic-wait-all:
- shard-rkl:  [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-rkl-6/igt@gem_exec_fe...@basic-wait-all.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-rkl-1/igt@gem_exec_fe...@basic-wait-all.html

  
Known issues


  Here are the changes found in Patchwork_121373v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_fdinfo@busy-hang@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8414]) +11 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-mtlp-3/igt@drm_fdinfo@busy-h...@rcs0.html

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl:  [PASS][4] -> [FAIL][5] ([i915#7742])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-rkl-7/igt@drm_fdinfo@most-busy-check-...@rcs0.html

  * igt@gem_basic@multigpu-create-close:
- shard-rkl:  NOTRUN -> [SKIP][6] ([i915#7697])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-rkl-4/igt@gem_ba...@multigpu-create-close.html

  * igt@gem_ccs@ctrl-surf-copy:
- shard-mtlp: NOTRUN -> [SKIP][7] ([i915#5325])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-mtlp-3/igt@gem_...@ctrl-surf-copy.html

  * igt@gem_ctx_persistence@file:
- shard-snb:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-snb2/igt@gem_ctx_persiste...@file.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#8555])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-mtlp-3/igt@gem_ctx_persiste...@heartbeat-hostile.html

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-apl:  [PASS][10] -> [TIMEOUT][11] ([i915#3063])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-apl6/igt@gem_...@in-flight-contexts-10ms.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-apl4/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_exec_balancer@parallel-balancer:
- shard-rkl:  NOTRUN -> [SKIP][12] ([i915#4525])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-rkl-4/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_capture@pi@ccs0:
- shard-mtlp: [PASS][13] -> [FAIL][14] ([i915#7765])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-mtlp-1/igt@gem_exec_capture@p...@ccs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-mtlp-2/igt@gem_exec_capture@p...@ccs0.html

  * igt@gem_exec_capture@pi@vcs0:
- shard-mtlp: [PASS][15] -> [FAIL][16] ([i915#4475])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-mtlp-1/igt@gem_exec_capture@p...@vcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-mtlp-2/igt@gem_exec_capture@p...@vcs0.html

  * igt@gem_exec_endless@dispatch@vcs0:
- shard-mtlp: [PASS][17] -> [TIMEOUT][18] ([i915#3778] / 
[i915#7941])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-mtlp-3/igt@gem_exec_endless@dispa...@vcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-mtlp-1/igt@gem_exec_endless@dispa...@vcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-rkl:  [PASS][19] -> [FAIL][20] ([i915#2846])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/shard-rkl-4/igt@gem_exec_f...@basic-deadline.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/shard-rkl-2/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-rkl:  [PASS][21] -> 

[Intel-gfx] [PATCH v4 13/14] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa 

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c| 2 +-
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/intel_step.c   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index 852bea0208ce..cc9569af7f0c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -94,7 +94,7 @@ static int guc_hwconfig_fill_buffer(struct intel_guc *guc, 
struct intel_hwconfig
 
 static bool has_table(struct drm_i915_private *i915)
 {
-   if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915))
+   if (IS_ALDERLAKE_P(i915) && !IS_ALDERLAKE_P_N(i915))
return true;
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
return true;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 7aadad5639c3..5ccf452e32bf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -295,7 +295,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct 
intel_uc_fw *uc_fw)
 * ADL-S, otherwise the GuC might attempt to fetch a config table that
 * does not exist.
 */
-   if (IS_ADLP_N(i915))
+   if (IS_ALDERLAKE_P_N(i915))
p = INTEL_ALDERLAKE_S;
 
GEM_BUG_ON(uc_fw->type >= ARRAY_SIZE(blobs_all));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d3a621e5a36b..853687d9e3f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -586,7 +586,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 #define IS_ADLS_RPLS(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_N(i915) \
+#define IS_ALDERLAKE_P_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_RAPTORLAKE_P(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index 7601122765b7..5553de469fa0 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -192,7 +192,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_XEHPSDV(i915)) {
revids = xehpsdv_revids;
size = ARRAY_SIZE(xehpsdv_revids);
-   } else if (IS_ADLP_N(i915)) {
+   } else if (IS_ALDERLAKE_P_N(i915)) {
revids = adlp_n_revids;
size = ARRAY_SIZE(adlp_n_revids);
} else if (IS_RAPTORLAKE_P(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH v3 07/14] drm/i915/rkl: s/RKL/ROCKETLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace RKL with
ROCKETLAKE.Replace IS_RKL_GRAPHICS_STEP with
IS_ROCKETLAKE && IS_DISPLAY_STEP.

v2:
- s/RKL/rkl in the subject prefix(Anusha)

v3:
- Unrolled wrapper IS_RKL_DISPLAY_STEP.
- Replace IS_PLATFORM && IS_DISPLAY_STEP (Jani/Tvrtko)

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h| 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 38225e5d311e..9e01054c2430 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1609,7 +1609,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private 
*dev_priv)
return;
 
if (IS_ALDERLAKE_S(dev_priv) ||
-   IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   (IS_ROCKETLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_B0)))
/* Wa_1409767108 */
table = wa_1409767108_buddy_page_masks;
else
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e6f77498d46c..f46846574420 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -660,8 +660,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_TIGERLAKE(__i915) && \
 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_RKL_DISPLAY_STEP(p, since, until) \
-   (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
(IS_ALDERLAKE_S(__i915) && \
-- 
2.34.1

[Intel-gfx] [PATCH v2 12/14] drm/i915/rplu: s/ADLP_RPLU/RAPTORLAKE_U in RPLU defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

v2:
- Replace IS_ADLP_RPLU with IS_RAPTORLAKE_U (Tvrtko/Lucas)
- Change the subject

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 57113fb01fb2..2fb030b1ff1d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3570,7 +3570,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, 
STEP_A0, STEP_B0)) {
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
dev_priv->display.funcs.cdclk = _cdclk_funcs;
-   } else if (IS_ADLP_RPLU(dev_priv)) {
+   } else if (IS_RAPTORLAKE_U(dev_priv)) {
dev_priv->display.cdclk.table = rplu_cdclk_table;
dev_priv->display.funcs.cdclk = _cdclk_funcs;
} else {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4e07ba69642d..d3a621e5a36b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -590,7 +590,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_RAPTORLAKE_P(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_RPLU(i915) \
+#define IS_RAPTORLAKE_U(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
(INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-- 
2.34.1

[Intel-gfx] [PATCH v4 09/14] drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace TGL with
TIGERLAKE.Replace IS_TGL_DISPLAY_STEP with
IS_TIGERLAKE() && IS_DISPLAY_STEP().

v2:
- s/TGL/tgl in the subject prefix(Anusha)

v3:
- Unrolled wrapper IS_TGL_DISPLAY_STEP and Replace 
- Replace IS_PLATFORM && DISPLAY_STEP (Jani/Tvrtko).

v4:
- Removed unused macros

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 2 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h| 5 +
 drivers/gpu/drm/i915/intel_step.c  | 2 +-
 4 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 35e6e3a5ddf1..de809e2d9cac 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1410,7 +1410,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
if (crtc_state->port_clock > 27) {
-   if (IS_TGL_UY(dev_priv)) {
+   if (IS_TIGERLAKE_UY(dev_priv)) {
return 
intel_get_buf_trans(_uy_combo_phy_trans_dp_hbr2,
   n_entries);
} else {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..4ed1244c1a17 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2196,7 +2196,7 @@ static bool gen12_plane_has_mc_ccs(struct 
drm_i915_private *i915,
 
/* Wa_14010477008 */
if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
-   IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
+   (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
return false;
 
/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 704c0991e7d3..44f3a368607e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -646,15 +646,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_WITH_PORT_F(i915) \
IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
-#define IS_TGL_UY(i915) \
+#define IS_TIGERLAKE_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
 
 
 
-#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
-   (IS_TIGERLAKE(__i915) && \
-IS_DISPLAY_STEP(__i915, since, until))
 
 
 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index 5e4816417b99..4ca22d0c945b 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -213,7 +213,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ROCKETLAKE(i915)) {
revids = rkl_revids;
size = ARRAY_SIZE(rkl_revids);
-   } else if (IS_TGL_UY(i915)) {
+   } else if (IS_TIGERLAKE_UY(i915)) {
revids = tgl_uy_revids;
size = ARRAY_SIZE(tgl_uy_revids);
} else if (IS_TIGERLAKE(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH v3 14/14] drm/i915/adls: s/ADLS_RPLS/RAPTORLAKE_S in platform and subplatform defines

[Dnyaneshwar Bhadane]

Driver refers to the platform Alderlake S as ADLS_RPLS in places
and RAPTORLAKE_S in some.

v2:
- Unrolled wrapper IS_ADLS_GRAPHICS_STEP

v3:
- Replace IS_RAPTORLAKE_S instead of IS_ADLS_RPLS. (Tvrtko/Lucas).
- Remove unused macro IS_ADLS_GRAPHICS/DISPLAY_STEP
- Change the subject 

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c   | 2 +-
 drivers/gpu/drm/i915/i915_drv.h | 9 +
 drivers/gpu/drm/i915/intel_step.c   | 2 +-
 4 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c 
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 8286e79522d1..dcb272327281 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -858,7 +858,7 @@ void intel_display_device_info_runtime_init(struct 
drm_i915_private *i915)
BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < 
I915_MAX_PORTS);
 
/* Wa_14011765242: adl-s A0,A1 */
-   if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
+   if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
for_each_pipe(i915, pipe)
display_runtime->num_scalers[pipe] = 0;
else if (DISPLAY_VER(i915) >= 11) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 18250fb64bd8..98b103375b7a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -43,7 +43,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
}
 
/* Intermediate platforms are HuC authentication only */
-   if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
+   if (IS_ALDERLAKE_S(i915) && !IS_RAPTORLAKE_S(i915)) {
i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
return;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 853687d9e3f8..9ddba8a8ab1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -584,7 +584,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
-#define IS_ADLS_RPLS(i915) \
+#define IS_RAPTORLAKE_S(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ALDERLAKE_P_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
@@ -654,13 +654,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 
 
-#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
-   (IS_ALDERLAKE_S(__i915) && \
-IS_DISPLAY_STEP(__i915, since, until))
-
-#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
-   (IS_ALDERLAKE_S(__i915) && \
-IS_GRAPHICS_STEP(__i915, since, until))
 
 
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index 5553de469fa0..c02a6f156a00 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -201,7 +201,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ALDERLAKE_P(i915)) {
revids = adlp_revids;
size = ARRAY_SIZE(adlp_revids);
-   } else if (IS_ADLS_RPLS(i915)) {
+   } else if (IS_RAPTORLAKE_S(i915)) {
revids = adls_rpls_revids;
size = ARRAY_SIZE(adls_rpls_revids);
} else if (IS_ALDERLAKE_S(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH v2 11/14] drm/i915/rplp: s/ADLP_RPLP/RAPTORLAKE_P for RPLP defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P.

v2:
- Replace IS_ADLP_RPLP with IS_RAPTORLAKE_P. (Tvrtko/Lucas)
- Change the subject

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/i915_drv.h   | 2 +-
 drivers/gpu/drm/i915/intel_step.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c24be1875769..4e07ba69642d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -588,7 +588,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
-#define IS_ADLP_RPLP(i915) \
+#define IS_RAPTORLAKE_P(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_RPLU(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index 4ca22d0c945b..7601122765b7 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ADLP_N(i915)) {
revids = adlp_n_revids;
size = ARRAY_SIZE(adlp_n_revids);
-   } else if (IS_ADLP_RPLP(i915)) {
+   } else if (IS_RAPTORLAKE_P(i915)) {
revids = adlp_rplp_revids;
size = ARRAY_SIZE(adlp_rplp_revids);
} else if (IS_ALDERLAKE_P(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH v3 10/14] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[Dnyaneshwar Bhadane]

Driver refers to the platform Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

v2:
- Unrolled wrapper IS_ADLP_GRAPHICS_STEP and Replace
- Added IS_ALDERLAKE_P() && IS_GRAPHICS_STEP() (Jani/Tvrtko).

v3:
- Removed unused macros of display steps.

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c   | 8 
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h| 7 ---
 5 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index eab0f0dd057e..57113fb01fb2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3567,7 +3567,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
/* Wa_22011320316:adl-p[a0] */
-   if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+   if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, 
STEP_A0, STEP_B0)) {
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
dev_priv->display.funcs.cdclk = _cdclk_funcs;
} else if (IS_ADLP_RPLU(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4c4108d404f6..664bce4c679b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3785,7 +3785,7 @@ static void adlp_cmtg_clock_gating_wa(struct 
drm_i915_private *i915, struct inte
 {
u32 val;
 
-   if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
+   if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 
||
pll->info->id != DPLL_ID_ICL_DPLL0)
return;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 94ec41b9d5ae..97d5eef10130 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -748,7 +748,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
}
 
/* Wa_22012278275:adl-p */
-   if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
+   if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_E0)) {
static const u8 map[] = {
2, /* 5 lines */
1, /* 6 lines */
@@ -918,7 +918,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
return;
 
/* Wa_16011303918:adl-p */
-   if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_B0))
return;
 
/*
@@ -1086,7 +1086,7 @@ static bool intel_psr2_config_valid(struct intel_dp 
*intel_dp,
return false;
}
 
-   if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+   if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_B0)) {
drm_dbg_kms(_priv->drm, "PSR2 not completely functional in 
this stepping\n");
return false;
}
@@ -1144,7 +1144,7 @@ static bool intel_psr2_config_valid(struct intel_dp 
*intel_dp,
 
/* Wa_16011303918:adl-p */
if (crtc_state->vrr.enable &&
-   IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+   IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_B0)) {
drm_dbg_kms(_priv->drm,
"PSR2 not enabled, not compatible with HW stepping 
+ VRR\n");
return false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 4ed1244c1a17..ffc15d278a39 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private 
*i915,
return false;
 
/* Wa_22011186057 */
-   if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+   if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
 
if (DISPLAY_VER(i915) >= 11)
@@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct 
drm_i915_private *i915,
return false;
 
/* Wa_22011186057 */
-   if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+   if (IS_ALDERLAKE_P(i915) && 

[Intel-gfx] [PATCH v4 08/14] drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace JSL with
JASPERLAKE. Unroll IS_JSL_EHL() define  with IS_JASPERLAKE() ||
IS_ELKHARTLAKE() condition. Change in the display step define for
Jasperlake.

v2:
- Change subject prefix skl instead of SKL(Anusha)

v3:
- Remove the use of define IS_JSL_EHL.
- Replace with IS_JASPERLAKE() || IS_ELKHARTLAKE()
- Unrolled wrapper IS_JSL_ELK_DISPLAY_STEP 

v4:
- Removed unused macro

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/icl_dsi.c|  5 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c|  4 +--
 .../gpu/drm/i915/display/intel_combo_phy.c|  7 +++--
 drivers/gpu/drm/i915/display/intel_ddi.c  |  7 +++--
 drivers/gpu/drm/i915/display/intel_display.c  |  5 ++--
 drivers/gpu/drm/i915/display/intel_dp.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++
 drivers/gpu/drm/i915/display/intel_hdmi.c |  3 +-
 drivers/gpu/drm/i915/display/intel_psr.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  3 +-
 drivers/gpu/drm/i915/i915_drv.h   |  8 ++---
 drivers/gpu/drm/i915/intel_step.c |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c  |  8 +++--
 15 files changed, 49 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index f7ebc146f96d..fd048b14717d 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -444,7 +444,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct 
intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-   if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
+   if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
+   (DISPLAY_VER(dev_priv) >= 12)) {
intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 
@@ -553,7 +554,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
}
}
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys)
intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f683802ce931..eab0f0dd057e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3155,7 +3155,7 @@ static int intel_compute_max_dotclk(struct 
drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
if (dev_priv->display.cdclk.hw.ref == 24000)
dev_priv->display.cdclk.max_cdclk_freq = 552000;
else
@@ -3583,7 +3583,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
-   } else if (IS_JSL_EHL(dev_priv)) {
+   } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c 
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 922a6d87b553..6e143833c819 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, 
enum phy phy)
 
if (IS_ALDERLAKE_S(i915))
return phy == PHY_A;
-   else if (IS_JSL_EHL(i915) ||
+   else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||
 IS_ROCKETLAKE(i915) ||
 IS_DG1(i915))
return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct 
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 IREFGEN, IREFGEN);
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
if (ehl_vbt_ddi_d_present(dev_priv))
expected_val = 

[Intel-gfx] [PATCH v1 05/14] drm/i915/cfl: s/CFL/COFFEELAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace CFL with
COFFEELAKE.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h| 8 
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 39eab9ea02dd..cd85b9fed129 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1740,9 +1740,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder 
*encoder)
encoder->get_buf_trans = icl_get_mg_buf_trans;
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
encoder->get_buf_trans = bxt_get_buf_trans;
-   } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
+   } else if (IS_CML_ULX(i915) || IS_COFFEELAKE_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
encoder->get_buf_trans = kbl_y_get_buf_trans;
-   } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
+   } else if (IS_CML_ULT(i915) || IS_COFFEELAKE_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || 
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ba075bb183db..04107696e966 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -627,13 +627,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 INTEL_INFO(i915)->gt == 2)
 #define IS_KABYLAKE_GT3(i915)  (IS_KABYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)
-#define IS_CFL_ULT(i915) \
+#define IS_COFFEELAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_CFL_ULX(i915) \
+#define IS_COFFEELAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_CFL_GT2(i915)   (IS_COFFEELAKE(i915) && \
+#define IS_COFFEELAKE_GT2(i915)(IS_COFFEELAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)
-#define IS_CFL_GT3(i915)   (IS_COFFEELAKE(i915) && \
+#define IS_COFFEELAKE_GT3(i915)(IS_COFFEELAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)
 
 #define IS_CML_ULT(i915) \
-- 
2.34.1

[Intel-gfx] [PATCH v4 06/14] drm/i915/cml: s/CML/COMETLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace CML with
COMETLAKE.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h| 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index cd85b9fed129..35e6e3a5ddf1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1740,9 +1740,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder 
*encoder)
encoder->get_buf_trans = icl_get_mg_buf_trans;
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
encoder->get_buf_trans = bxt_get_buf_trans;
-   } else if (IS_CML_ULX(i915) || IS_COFFEELAKE_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
+   } else if (IS_COMETLAKE_ULX(i915) || IS_COFFEELAKE_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
encoder->get_buf_trans = kbl_y_get_buf_trans;
-   } else if (IS_CML_ULT(i915) || IS_COFFEELAKE_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
+   } else if (IS_COMETLAKE_ULT(i915) || IS_COFFEELAKE_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || 
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04107696e966..e6f77498d46c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -636,11 +636,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COFFEELAKE_GT3(i915)(IS_COFFEELAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)
 
-#define IS_CML_ULT(i915) \
+#define IS_COMETLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_CML_ULX(i915) \
+#define IS_COMETLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_CML_GT2(i915)   (IS_COMETLAKE(i915) && \
+#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)
 
 #define IS_ICL_WITH_PORT_F(i915) \
-- 
2.34.1

[Intel-gfx] [PATCH v4 04/14] drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace KBL with
KABYLAKE.Replace IS_KBL_GRAPHICS_STEP with
IS_KABYLAKE () && IS_GRAPHICS_STEP().

v2:
- s/KBL/kbl in the subject prefix(Anusha)

v3:
- Unrolled wrapper IS_KBL_GRAPHICS_STEP.
- Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani)

v4:
- Removed unused macro.

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c|  6 +++---
 drivers/gpu/drm/i915/i915_drv.h| 12 
 drivers/gpu/drm/i915/intel_clock_gating.c  |  4 ++--
 5 files changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index e85eab21b09d..39eab9ea02dd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1740,9 +1740,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder 
*encoder)
encoder->get_buf_trans = icl_get_mg_buf_trans;
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
encoder->get_buf_trans = bxt_get_buf_trans;
-   } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
+   } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
encoder->get_buf_trans = kbl_y_get_buf_trans;
-   } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
+   } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || 
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 8a3cbb01bcbe..a4ff55aa5e55 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -43,7 +43,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
vf_flush_wa = true;
 
/* WaForGAMHang:kbl */
-   if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))
+   if (IS_KABYLAKE(rq->i915) && IS_GRAPHICS_STEP(rq->i915, 0, 
STEP_C0))
dc_flush_wa = true;
}
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b0b7d448364a..a8ba843029bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -600,7 +600,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs 
*engine,
gen9_ctx_workarounds_init(engine, wal);
 
/* WaToEnableHwFixForPushConstHWBug:kbl */
-   if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
+   if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
@@ -1204,7 +1204,7 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
gen9_gt_workarounds_init(gt, wal);
 
/* WaDisableDynamicCreditSharing:kbl */
-   if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
+   if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
wa_write_or(wal,
GAMT_CHKN_BIT_REG,
GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -2945,7 +2945,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct 
i915_wa_list *wal)
struct drm_i915_private *i915 = engine->i915;
 
/* WaKBLVECSSemaphoreWaitPoll:kbl */
-   if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
+   if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
wa_write(wal,
 RING_SEMA_WAIT_POLL(engine->mmio_base),
 1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7f7ca135000..ba075bb183db 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -613,9 +613,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_SKYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_KBL_ULT(i915) \
+#define IS_KABYLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_KBL_ULX(i915) \
+#define IS_KABYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_SKYLAKE_GT2(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)
@@ -623,9 +623,9 @@ 

[Intel-gfx] [PATCH v4 03/14] drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace SKL with
SKYLAKE and Replace IS_SKL_GRAPHICS_STEP with
IS_SKYLAKE() && IS_GRAPHICS_STEP().

v2:
- Change subject skl instead of SKL(Anusha)

v3:
- Unrolled wrapper IS_SKL_GRAPHICS_STEP.
- Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani)

v4:
- Removed the unused macro.

Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 

---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c|  2 +-
 drivers/gpu/drm/i915/i915_drv.h| 13 ++---
 3 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 5b2665a9d86d..e85eab21b09d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1746,9 +1746,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder 
*encoder)
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || 
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
-   } else if (IS_SKL_ULX(i915)) {
+   } else if (IS_SKYLAKE_ULX(i915)) {
encoder->get_buf_trans = skl_y_get_buf_trans;
-   } else if (IS_SKL_ULT(i915)) {
+   } else if (IS_SKYLAKE_ULT(i915)) {
encoder->get_buf_trans = skl_u_get_buf_trans;
} else if (IS_SKYLAKE(i915)) {
encoder->get_buf_trans = skl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9634ab8d738b..b0b7d448364a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1192,7 +1192,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
/* WaInPlaceDecompressionHang:skl */
-   if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
+   if (IS_SKYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, STEP_A0, 
STEP_H0))
wa_write_or(wal,
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6607f233461a..d7f7ca135000 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -609,19 +609,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 /* ULX machines are also considered ULT. */
 #define IS_HASWELL_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(i915) \
+#define IS_SKYLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(i915) \
+#define IS_SKYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_KBL_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_KBL_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(i915)   (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT2(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)
-#define IS_SKL_GT3(i915)   (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT3(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)
-#define IS_SKL_GT4(i915)   (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT4(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 4)
 #define IS_KBL_GT2(i915)   (IS_KABYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)
@@ -649,7 +649,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TGL_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
-#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && 
IS_GRAPHICS_STEP(p, since, until))
 
 #define IS_KBL_GRAPHICS_STEP(i915, since, until) \
(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
@@ -800,7 +799,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(i915)   \
-   (IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
+   (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
-- 
2.34.1

[Intel-gfx] [PATCH v1 02/14] drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace BDW with
BROADWELL.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  4 ++--
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h  |  6 +++---
 drivers/gpu/drm/i915/soc/intel_pch.c | 10 +-
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f18e1f8ef22e..f683802ce931 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3200,9 +3200,9 @@ void intel_update_max_cdclk(struct drm_i915_private 
*dev_priv)
 */
if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
dev_priv->display.cdclk.max_cdclk_freq = 45;
-   else if (IS_BDW_ULX(dev_priv))
+   else if (IS_BROADWELL_ULX(dev_priv))
dev_priv->display.cdclk.max_cdclk_freq = 45;
-   else if (IS_BDW_ULT(dev_priv))
+   else if (IS_BROADWELL_ULT(dev_priv))
dev_priv->display.cdclk.max_cdclk_freq = 54;
else
dev_priv->display.cdclk.max_cdclk_freq = 675000;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 6352c530bd7b..e401bcb234c2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7377,7 +7377,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private 
*dev_priv)
if (DISPLAY_VER(dev_priv) >= 9)
return false;
 
-   if (IS_HASWELL_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
+   if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
return false;
 
if (HAS_PCH_LPT_H(dev_priv) &&
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 589d009032fc..9634ab8d738b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -420,7 +420,7 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs 
*engine,
 /* WaForceContextSaveRestoreNonCoherent:bdw */
 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
-(IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
+(IS_BROADWELL_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 }
 
 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1003154ec71e..6607f233461a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -594,11 +594,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
(INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(i915) \
+#define IS_BROADWELL_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
-#define IS_BDW_ULX(i915) \
+#define IS_BROADWELL_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_BDW_GT3(i915)   (IS_BROADWELL(i915) && \
+#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
 INTEL_INFO(i915)->gt == 3)
 #define IS_HASWELL_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c 
b/drivers/gpu/drm/i915/soc/intel_pch.c
index bf829f85be7e..382a4a8015b4 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -32,21 +32,21 @@ intel_pch_type(const struct drm_i915_private *dev_priv, 
unsigned short id)
drm_WARN_ON(_priv->drm,
!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
drm_WARN_ON(_priv->drm,
-   IS_HASWELL_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
+   IS_HASWELL_ULT(dev_priv) || 
IS_BROADWELL_ULT(dev_priv));
return PCH_LPT;
case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
drm_dbg_kms(_priv->drm, "Found LynxPoint LP PCH\n");
drm_WARN_ON(_priv->drm,
!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
drm_WARN_ON(_priv->drm,
-   !IS_HASWELL_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
+   !IS_HASWELL_ULT(dev_priv) && 
!IS_BROADWELL_ULT(dev_priv));
return PCH_LPT;
case INTEL_PCH_WPT_DEVICE_ID_TYPE:

[Intel-gfx] [PATCH v4 00/14] Replace acronym with full platform name in defines.

[Dnyaneshwar Bhadane]

Replacing the acronym used in platform/sub platform defines.
This series covers Haswell, Broadwell, Skylake, Kabylake, Coffeelake,
Cometlake, Rocketlake, Jasperlake, Elkhartlake, Tigerlake, Alderlake,
platform define.This way there is a consistent pattern 
to how platforms are referred.splitting to per paltform for easier 
cherrypicks, if needed.

v2:
 - Reordered patches by incrementing platform generations.(Anusha)
 - Changeed the commit subject with lowercase platform names.
v3:
 - The IS_PLATFORM_(DISPLAY/MEDIA/GRAPHICS)_STEPS replace with Unrolled
 format. i.e. IS_PLATFORM_FULL_NAME () && IS_DISPLAY_STEPS()

v4:
 - Removed the MTL platform from the renaming series (Mat Ropper)
 - Removed the unused display steps macro.
 - Resolved conflicts.

Anusha Srivatsa (1):
  drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines

Dnyaneshwar Bhadane (13):
  drm/i915/hsw: s/HSW/HASWELL for platform/subplatform defines
  drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform defines
  drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines
  Follow consistent naming convention. Replace KBL with KABYLAKE.Replace
IS_KBL_GRAPHICS_STEP with IS_KABYLAKE () && IS_GRAPHICS_STEP().
  drm/i915/cfl: s/CFL/COFFEELAKE for platform/subplatform defines
  drm/i915/cml: s/CML/COMETLAKE for platform/subplatform defines
  drm/i915/rkl: s/RKL/ROCKETLAKE for platform/subplatform defines
  drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines
  drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform defines
  drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
  drm/i915/rplp: s/ADLP_RPLP/RAPTORLAKE_P for RPLP defines
  drm/i915/rplu: s/ADLP_RPLU/RAPTORLAKE_U in RPLU defines
  drm/i915/adls: s/ADLS_RPLS/RAPTORLAKE_S in platform and subplatform
defines

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Matt Roper 
Cc: Anusha Srivatsa 
Cc: matthew Atwood 

 drivers/gpu/drm/i915/display/icl_dsi.c|  5 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c| 14 +--
 .../gpu/drm/i915/display/intel_combo_phy.c|  7 +-
 drivers/gpu/drm/i915/display/intel_ddi.c  |  7 +-
 .../drm/i915/display/intel_ddi_buf_trans.c| 10 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  7 +-
 .../drm/i915/display/intel_display_device.c   |  2 +-
 .../drm/i915/display/intel_display_device.h   |  2 +-
 .../drm/i915/display/intel_display_power.c|  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |  4 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 33 ---
 drivers/gpu/drm/i915/display/intel_hdmi.c |  3 +-
 .../gpu/drm/i915/display/intel_pch_refclk.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c  | 10 +-
 .../drm/i915/display/skl_universal_plane.c|  6 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  2 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 13 +--
 .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  2 +-
 drivers/gpu/drm/i915/i915_driver.c|  2 +-
 drivers/gpu/drm/i915/i915_drv.h   | 94 +++
 drivers/gpu/drm/i915/intel_clock_gating.c |  4 +-
 drivers/gpu/drm/i915/intel_step.c | 10 +-
 drivers/gpu/drm/i915/soc/intel_pch.c  | 18 ++--
 28 files changed, 127 insertions(+), 142 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH v1 01/14] drm/i915/hsw: s/HSW/HASWELL for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace HSW with
HASWELL.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c|  2 +-
 drivers/gpu/drm/i915/display/intel_display_device.h |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_pch_refclk.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c  |  2 +-
 drivers/gpu/drm/i915/i915_driver.c  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h | 12 ++--
 drivers/gpu/drm/i915/soc/intel_pch.c| 10 +-
 10 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index dcc1f6941b60..f18e1f8ef22e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -470,7 +470,7 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
cdclk_config->cdclk = 45;
else if (freq == LCPLL_CLK_FREQ_450)
cdclk_config->cdclk = 45;
-   else if (IS_HSW_ULT(dev_priv))
+   else if (IS_HASWELL_ULT(dev_priv))
cdclk_config->cdclk = 337500;
else
cdclk_config->cdclk = 54;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 43cba98f7753..6352c530bd7b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7377,7 +7377,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private 
*dev_priv)
if (DISPLAY_VER(dev_priv) >= 9)
return false;
 
-   if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
+   if (IS_HASWELL_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
return false;
 
if (HAS_PCH_LPT_H(dev_priv) &&
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h 
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 3324bd453ca7..215e682bd8b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -54,7 +54,7 @@ struct drm_printer;
 #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
 #define HAS_HW_SAGV_WM(i915)   (DISPLAY_VER(i915) >= 13 && 
!IS_DGFX(i915))
 #define HAS_IPC(i915)  (DISPLAY_INFO(i915)->has_ipc)
-#define HAS_IPS(i915)  (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
+#define HAS_IPS(i915)  (IS_HASWELL_ULT(i915) || 
IS_BROADWELL(i915))
 #define HAS_LSPCON(i915)   (IS_DISPLAY_VER(i915, 9, 10))
 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || 
DISPLAY_VER(i915) >= 14)
 #define HAS_MSO(i915)  (DISPLAY_VER(i915) >= 12)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 03675620e3ea..f5407569300a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -510,7 +510,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
} else if (DISPLAY_VER(dev_priv) == 9) {
source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
-   } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
+   } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
   IS_BROADWELL(dev_priv)) {
source_rates = hsw_rates;
size = ARRAY_SIZE(hsw_rates);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6b2d8a1e2aa9..66afdb91fcdf 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -927,7 +927,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private 
*dev_priv,
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
-   if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
+   if (IS_HASWELL(dev_priv) && !IS_HASWELL_ULT(dev_priv)) {
refclk = dev_priv->display.dpll.ref_clks.nssc;
break;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c 
b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index f4c09cc37a5e..9583e86b602a 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -423,7 +423,7 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private 
*dev_priv,
if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
return true;
 
-   if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
+   if ((IS_BROADWELL(dev_priv) || IS_HASWELL_ULT(dev_priv)) &&
 

Re: [Intel-gfx] [PATCH 16/17] cgroup/drm: Expose memory stats

[Tejun Heo]

Hello,

On Wed, Jul 26, 2023 at 05:44:28PM +0100, Tvrtko Ursulin wrote:
...
> > So, yeah, if you want to add memory controls, we better think through how
> > the fd ownership migration should work.
> 
> It would be quite easy to make the implicit migration fail - just the matter
> of failing the first ioctl, which is what triggers the migration, after the
> file descriptor access from a new owner.

So, it'd be best if there's no migration involved at all as per the
discussion with Maarten.

> But I don't think I can really add that in the RFC given I have no hard
> controls or anything like that.
> 
> With GPU usage throttling it doesn't really apply, at least I don't think it
> does, since even when migrated to a lower budget group it would just get
> immediately de-prioritized.
> 
> I don't think hard GPU time limits are feasible in general, and while soft
> might be, again I don't see that any limiting would necessarily have to run
> immediately on implicit migration.

Yeah, I wouldn't worry about hard allocation of GPU time. CPU RT control
does that but it's barely used.

> Second part of the story are hypothetical/future memory controls.
> 
> I think first thing to say is that implicit migration is important, but it
> is not really established to use the file descriptor from two places or to
> migrate more than once. It is simply fresh fd which gets sent to clients
> from Xorg, which is one of the legacy ways of doing things.
> 
> So we probably can just ignore that given no significant amount of memory
> ownership would be getting migrated.

So, if this is the case, it'd be better to clarify this. ie. if the summary is:

fd gets assigned to the user with a certain action at which point the fd
doesn't have significant resources attached to it and the fd can't be moved
to some other cgroup afterwards.

then, everything is pretty simple. No need to worry about migration at all.
fd just gets assigned once at the beginning and everything gets accounted
towards that afterwards.

> And for drm.memory.stat I think what I have is good enough - both private
> and shared data get accounted, for any clients that have handles to
> particular buffers.
> 
> Maarten was working on memory controls so maybe he would have more thoughts
> on memory ownership and implicit migration.
> 
> But I don't think there is anything incompatible with that and
> drm.memory.stats as proposed here, given how the categories reported are the
> established ones from the DRM fdinfo spec, and it is fact of the matter that
> we can have multiple memory regions per driver.
> 
> The main thing that would change between this RFC and future memory controls
> in the area of drm.memory.stat is the implementation - it would have to get
> changed under the hood from "collect on query" to "account at
> allocation/free/etc". But that is just implementation details.

I'd much prefer to straighten out this before adding a prelimiary stat only
thing. If the previously described ownership model is sufficient, none of
this is complicated, right? We can just add counters to track the resources
and print them out.

Thanks.

-- 
tejun

Re: [Intel-gfx] [PATCH 16/17] cgroup/drm: Expose memory stats

[Tejun Heo]

Hello,

On Wed, Jul 26, 2023 at 12:14:24PM +0200, Maarten Lankhorst wrote:
> > So, yeah, if you want to add memory controls, we better think through how
> > the fd ownership migration should work.
>
> I've taken a look at the series, since I have been working on cgroup memory
> eviction.
> 
> The scheduling stuff will work for i915, since it has a purely software
> execlist scheduler, but I don't think it will work for GuC (firmware)
> scheduling or other drivers that use the generic drm scheduler.
> 
> For something like this,  you would probably want it to work inside the drm
> scheduler first. Presumably, this can be done by setting a weight on each
> runqueue, and perhaps adding a callback to update one for a running queue.
> Calculating the weights hierarchically might be fun..

I don't have any idea on this front. The basic idea of making high level
distribution decisions in core code and letting individual drivers enforce
that in a way which fits them the best makes sense to me but I don't know
enough to have an opinion here.

> I have taken a look at how the rest of cgroup controllers change ownership
> when moved to a different cgroup, and the answer was: not at all. If we

For persistent resources, that's the general rule. Whoever instantiates a
resource gets to own it until the resource gets freed. There is an exception
with the pid controller and there are discussions around whether we want
some sort of migration behavior with memcg but yes by and large instantiator
being the owner is the general model cgroup follows.

> attempt to create the scheduler controls only on the first time the fd is
> used, you could probably get rid of all the tracking.
> This can be done very easily with the drm scheduler.
>
> WRT memory, I think the consensus is to track system memory like normal
> memory. Stolen memory doesn't need to be tracked. It's kernel only memory,
> used for internal bookkeeping  only.
> 
> The only time userspace can directly manipulate stolen memory, is by mapping
> the pinned initial framebuffer to its own address space. The only allocation
> it can do is when a framebuffer is displayed, and framebuffer compression
> creates some stolen memory. Userspace is not
> aware of this though, and has no way to manipulate those contents.

So, my dumb understanding:

* Ownership of an fd can be established on the first ioctl call and doesn't
  need to be migrated afterwards. There are no persistent resources to
  migration on the first call.

* Memory then can be tracked in a similar way to memcg. Memory gets charged
  to the initial instantiator and doesn't need to be moved around
  afterwards. There may be some discrepancies around stolen memory but the
  magnitude of inaccuracy introduced that way is limited and bound and can
  be safely ignored.

Is that correct?

Thanks.

-- 
tejun

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Replace acronym with full platform name in defines.

[Patchwork]

== Series Details ==

Series: Replace acronym with full platform name in defines.
URL   : https://patchwork.freedesktop.org/series/121385/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/121385/revisions/1/mbox/ not 
applied
Applying: drm/i915/hsw: s/HSW/HASWELL for platform/subplatform defines
Applying: drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform defines
Applying: drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines
Applying: drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/gt/gen8_engine_cs.c
M   drivers/gpu/drm/i915/gt/intel_workarounds.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_workarounds.c
Auto-merging drivers/gpu/drm/i915/gt/gen8_engine_cs.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/gen8_engine_cs.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0004 drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform 
defines
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

[Intel-gfx] [PATCH v1 13/14] drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines

[Dnyaneshwar Bhadane]

From: Anusha Srivatsa 

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c| 2 +-
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/intel_step.c   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index 852bea0208ce..cc9569af7f0c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -94,7 +94,7 @@ static int guc_hwconfig_fill_buffer(struct intel_guc *guc, 
struct intel_hwconfig
 
 static bool has_table(struct drm_i915_private *i915)
 {
-   if (IS_ALDERLAKE_P(i915) && !IS_ADLP_N(i915))
+   if (IS_ALDERLAKE_P(i915) && !IS_ALDERLAKE_P_N(i915))
return true;
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
return true;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 7aadad5639c3..5ccf452e32bf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -295,7 +295,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct 
intel_uc_fw *uc_fw)
 * ADL-S, otherwise the GuC might attempt to fetch a config table that
 * does not exist.
 */
-   if (IS_ADLP_N(i915))
+   if (IS_ALDERLAKE_P_N(i915))
p = INTEL_ALDERLAKE_S;
 
GEM_BUG_ON(uc_fw->type >= ARRAY_SIZE(blobs_all));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d3a621e5a36b..853687d9e3f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -586,7 +586,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 #define IS_ADLS_RPLS(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_N(i915) \
+#define IS_ALDERLAKE_P_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_RAPTORLAKE_P(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index 4d0a9f0b8201..fa80e87165e4 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -192,7 +192,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_XEHPSDV(i915)) {
revids = xehpsdv_revids;
size = ARRAY_SIZE(xehpsdv_revids);
-   } else if (IS_ADLP_N(i915)) {
+   } else if (IS_ALDERLAKE_P_N(i915)) {
revids = adlp_n_revids;
size = ARRAY_SIZE(adlp_n_revids);
} else if (IS_RAPTORLAKE_P(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH v3 14/14] drm/i915/adls: s/ADLS_RPLS/RAPTORLAKE_S in platform and subplatform defines

[Dnyaneshwar Bhadane]

Driver refers to the platform Alderlake S as ADLS_RPLS in places
and RAPTORLAKE_S in some.

v2:
- Unrolled wrapper IS_ADLS_GRAPHICS_STEP

v3:
- Replace IS_RAPTORLAKE_S instead of IS_ADLS_RPLS. (Tvrtko/Lucas).
- Remove unused macro IS_ADLS_GRAPHICS/DISPLAY_STEP
- Change the subject 

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c   | 2 +-
 drivers/gpu/drm/i915/i915_drv.h | 9 +
 drivers/gpu/drm/i915/intel_step.c   | 2 +-
 4 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c 
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 8286e79522d1..dcb272327281 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -858,7 +858,7 @@ void intel_display_device_info_runtime_init(struct 
drm_i915_private *i915)
BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < 
I915_MAX_PORTS);
 
/* Wa_14011765242: adl-s A0,A1 */
-   if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
+   if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
for_each_pipe(i915, pipe)
display_runtime->num_scalers[pipe] = 0;
else if (DISPLAY_VER(i915) >= 11) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 18250fb64bd8..98b103375b7a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -43,7 +43,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
}
 
/* Intermediate platforms are HuC authentication only */
-   if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
+   if (IS_ALDERLAKE_S(i915) && !IS_RAPTORLAKE_S(i915)) {
i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
return;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 853687d9e3f8..9ddba8a8ab1a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -584,7 +584,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
-#define IS_ADLS_RPLS(i915) \
+#define IS_RAPTORLAKE_S(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ALDERLAKE_P_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
@@ -654,13 +654,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 
 
-#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
-   (IS_ALDERLAKE_S(__i915) && \
-IS_DISPLAY_STEP(__i915, since, until))
-
-#define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
-   (IS_ALDERLAKE_S(__i915) && \
-IS_GRAPHICS_STEP(__i915, since, until))
 
 
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index fa80e87165e4..29210070f6f0 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -201,7 +201,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ALDERLAKE_P(i915)) {
revids = adlp_revids;
size = ARRAY_SIZE(adlp_revids);
-   } else if (IS_ADLS_RPLS(i915)) {
+   } else if (IS_RAPTORLAKE_S(i915)) {
revids = adls_rpls_revids;
size = ARRAY_SIZE(adls_rpls_revids);
} else if (IS_ALDERLAKE_S(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH v3 10/14] drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step

[Dnyaneshwar Bhadane]

Driver refers to the platform Alderlake P as ADLP in places
and ALDERLAKE_P in some. Making the consistent change
to avoid confusion of the right naming convention for
the platform.

v2:
- Unrolled wrapper IS_ADLP_GRAPHICS_STEP and Replace
- Added IS_ALDERLAKE_P() && IS_GRAPHICS_STEP() (Jani/Tvrtko).

v3:
- Removed unused macros of display steps.

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 

---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c   | 8 
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h| 7 ---
 5 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index eab0f0dd057e..57113fb01fb2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3567,7 +3567,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
/* Wa_22011320316:adl-p[a0] */
-   if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+   if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, 
STEP_A0, STEP_B0)) {
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
dev_priv->display.funcs.cdclk = _cdclk_funcs;
} else if (IS_ADLP_RPLU(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b44e8aa46b18..bab3e40a59f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3785,7 +3785,7 @@ static void adlp_cmtg_clock_gating_wa(struct 
drm_i915_private *i915, struct inte
 {
u32 val;
 
-   if (!IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0) ||
+   if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 
||
pll->info->id != DPLL_ID_ICL_DPLL0)
return;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 94ec41b9d5ae..97d5eef10130 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -748,7 +748,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
}
 
/* Wa_22012278275:adl-p */
-   if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
+   if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_E0)) {
static const u8 map[] = {
2, /* 5 lines */
1, /* 6 lines */
@@ -918,7 +918,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
return;
 
/* Wa_16011303918:adl-p */
-   if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_B0))
return;
 
/*
@@ -1086,7 +1086,7 @@ static bool intel_psr2_config_valid(struct intel_dp 
*intel_dp,
return false;
}
 
-   if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+   if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_B0)) {
drm_dbg_kms(_priv->drm, "PSR2 not completely functional in 
this stepping\n");
return false;
}
@@ -1144,7 +1144,7 @@ static bool intel_psr2_config_valid(struct intel_dp 
*intel_dp,
 
/* Wa_16011303918:adl-p */
if (crtc_state->vrr.enable &&
-   IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
+   IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_B0)) {
drm_dbg_kms(_priv->drm,
"PSR2 not enabled, not compatible with HW stepping 
+ VRR\n");
return false;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 4ed1244c1a17..ffc15d278a39 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2174,7 +2174,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private 
*i915,
return false;
 
/* Wa_22011186057 */
-   if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+   if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
 
if (DISPLAY_VER(i915) >= 11)
@@ -2200,7 +2200,7 @@ static bool gen12_plane_has_mc_ccs(struct 
drm_i915_private *i915,
return false;
 
/* Wa_22011186057 */
-   if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+   if (IS_ALDERLAKE_P(i915) && 

[Intel-gfx] [PATCH v4 09/14] drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace TGL with
TIGERLAKE.Replace IS_TGL_DISPLAY_STEP with
IS_TIGERLAKE() && IS_DISPLAY_STEP().

v2:
- s/TGL/tgl in the subject prefix(Anusha)

v3:
- Unrolled wrapper IS_TGL_DISPLAY_STEP and Replace 
- Replace IS_PLATFORM && DISPLAY_STEP (Jani/Tvrtko).

v4:
- Removed unused macros

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 2 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h| 5 +
 drivers/gpu/drm/i915/intel_step.c  | 2 +-
 4 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 35e6e3a5ddf1..de809e2d9cac 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1410,7 +1410,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
if (crtc_state->port_clock > 27) {
-   if (IS_TGL_UY(dev_priv)) {
+   if (IS_TIGERLAKE_UY(dev_priv)) {
return 
intel_get_buf_trans(_uy_combo_phy_trans_dp_hbr2,
   n_entries);
} else {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..4ed1244c1a17 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2196,7 +2196,7 @@ static bool gen12_plane_has_mc_ccs(struct 
drm_i915_private *i915,
 
/* Wa_14010477008 */
if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
-   IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
+   (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
return false;
 
/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 704c0991e7d3..44f3a368607e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -646,15 +646,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_WITH_PORT_F(i915) \
IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
-#define IS_TGL_UY(i915) \
+#define IS_TIGERLAKE_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
 
 
 
-#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
-   (IS_TIGERLAKE(__i915) && \
-IS_DISPLAY_STEP(__i915, since, until))
 
 
 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index f9068086b956..de0abe99951b 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -213,7 +213,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ROCKETLAKE(i915)) {
revids = rkl_revids;
size = ARRAY_SIZE(rkl_revids);
-   } else if (IS_TGL_UY(i915)) {
+   } else if (IS_TIGERLAKE_UY(i915)) {
revids = tgl_uy_revids;
size = ARRAY_SIZE(tgl_uy_revids);
} else if (IS_TIGERLAKE(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH v4 08/14] drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace JSL with
JASPERLAKE. Unroll IS_JSL_EHL() define  with IS_JASPERLAKE() ||
IS_ELKHARTLAKE() condition. Change in the display step define for
Jasperlake.

v2:
- Change subject prefix skl instead of SKL(Anusha)

v3:
- Remove the use of define IS_JSL_EHL.
- Replace with IS_JASPERLAKE() || IS_ELKHARTLAKE()
- Unrolled wrapper IS_JSL_ELK_DISPLAY_STEP 

v4:
- Removed unused macro

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 

---
 drivers/gpu/drm/i915/display/icl_dsi.c|  5 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c|  4 +--
 .../gpu/drm/i915/display/intel_combo_phy.c|  7 +++--
 drivers/gpu/drm/i915/display/intel_ddi.c  |  7 +++--
 drivers/gpu/drm/i915/display/intel_display.c  |  5 ++--
 drivers/gpu/drm/i915/display/intel_dp.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++
 drivers/gpu/drm/i915/display/intel_hdmi.c |  3 +-
 drivers/gpu/drm/i915/display/intel_psr.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  3 +-
 drivers/gpu/drm/i915/i915_drv.h   |  8 ++---
 drivers/gpu/drm/i915/intel_step.c |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c  |  8 +++--
 15 files changed, 49 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index f7ebc146f96d..4eb296bd224f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -444,7 +444,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct 
intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-   if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
+   if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
+   (DISPLAY_VER(dev_priv) >= 12)) {
intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 
@@ -553,7 +554,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
}
}
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys)
intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f683802ce931..eab0f0dd057e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3155,7 +3155,7 @@ static int intel_compute_max_dotclk(struct 
drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
if (dev_priv->display.cdclk.hw.ref == 24000)
dev_priv->display.cdclk.max_cdclk_freq = 552000;
else
@@ -3583,7 +3583,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
-   } else if (IS_JSL_EHL(dev_priv)) {
+   } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c 
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 922a6d87b553..81147a323e1e 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, 
enum phy phy)
 
if (IS_ALDERLAKE_S(i915))
return phy == PHY_A;
-   else if (IS_JSL_EHL(i915) ||
+   else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||
 IS_ROCKETLAKE(i915) ||
 IS_DG1(i915))
return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct 
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 IREFGEN, IREFGEN);
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
if (ehl_vbt_ddi_d_present(dev_priv))
expected_val = 

[Intel-gfx] [PATCH v2 12/14] drm/i915/rplu: s/ADLP_RPLU/RAPTORLAKE_U in RPLU defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P

v2:
- Replace IS_ADLP_RPLU with IS_RAPTORLAKE_U (Tvrtko/Lucas)
- Change the subject

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 

---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 57113fb01fb2..2fb030b1ff1d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3570,7 +3570,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, 
STEP_A0, STEP_B0)) {
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
dev_priv->display.funcs.cdclk = _cdclk_funcs;
-   } else if (IS_ADLP_RPLU(dev_priv)) {
+   } else if (IS_RAPTORLAKE_U(dev_priv)) {
dev_priv->display.cdclk.table = rplu_cdclk_table;
dev_priv->display.funcs.cdclk = _cdclk_funcs;
} else {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4e07ba69642d..d3a621e5a36b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -590,7 +590,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 #define IS_RAPTORLAKE_P(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_RPLU(i915) \
+#define IS_RAPTORLAKE_U(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
(INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-- 
2.34.1

[Intel-gfx] [PATCH v1 05/14] drm/i915/cfl: s/CFL/COFFEELAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace CFL with
COFFEELAKE.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h| 8 
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 39eab9ea02dd..cd85b9fed129 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1740,9 +1740,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder 
*encoder)
encoder->get_buf_trans = icl_get_mg_buf_trans;
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
encoder->get_buf_trans = bxt_get_buf_trans;
-   } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
+   } else if (IS_CML_ULX(i915) || IS_COFFEELAKE_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
encoder->get_buf_trans = kbl_y_get_buf_trans;
-   } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
+   } else if (IS_CML_ULT(i915) || IS_COFFEELAKE_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || 
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ba075bb183db..04107696e966 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -627,13 +627,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 INTEL_INFO(i915)->gt == 2)
 #define IS_KABYLAKE_GT3(i915)  (IS_KABYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)
-#define IS_CFL_ULT(i915) \
+#define IS_COFFEELAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_CFL_ULX(i915) \
+#define IS_COFFEELAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_CFL_GT2(i915)   (IS_COFFEELAKE(i915) && \
+#define IS_COFFEELAKE_GT2(i915)(IS_COFFEELAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)
-#define IS_CFL_GT3(i915)   (IS_COFFEELAKE(i915) && \
+#define IS_COFFEELAKE_GT3(i915)(IS_COFFEELAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)
 
 #define IS_CML_ULT(i915) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 11/14] drm/i915/rplp: s/ADLP_RPLP/RAPTORLAKE_P for RPLP defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace ADLP with
ALDERLAKE_P.

v2:
- Replace IS_ADLP_RPLP with IS_RAPTORLAKE_P. (Tvrtko/Lucas)
- Change the subject

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/i915_drv.h   | 2 +-
 drivers/gpu/drm/i915/intel_step.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c24be1875769..4e07ba69642d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -588,7 +588,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
-#define IS_ADLP_RPLP(i915) \
+#define IS_RAPTORLAKE_P(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_RPLU(i915) \
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index de0abe99951b..4d0a9f0b8201 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -195,7 +195,7 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ADLP_N(i915)) {
revids = adlp_n_revids;
size = ARRAY_SIZE(adlp_n_revids);
-   } else if (IS_ADLP_RPLP(i915)) {
+   } else if (IS_RAPTORLAKE_P(i915)) {
revids = adlp_rplp_revids;
size = ARRAY_SIZE(adlp_rplp_revids);
} else if (IS_ALDERLAKE_P(i915)) {
-- 
2.34.1

[Intel-gfx] [PATCH v4 03/14] drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace SKL with
SKYLAKE and Replace IS_SKL_GRAPHICS_STEP with
IS_SKYLAKE() && IS_GRAPHICS_STEP().

v2:
- Change subject skl instead of SKL(Anusha)

v3:
- Unrolled wrapper IS_SKL_GRAPHICS_STEP.
- Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani)

v4:
- Removed the unused macro.

Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c|  2 +-
 drivers/gpu/drm/i915/i915_drv.h| 13 ++---
 3 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 5b2665a9d86d..e85eab21b09d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1746,9 +1746,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder 
*encoder)
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || 
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
-   } else if (IS_SKL_ULX(i915)) {
+   } else if (IS_SKYLAKE_ULX(i915)) {
encoder->get_buf_trans = skl_y_get_buf_trans;
-   } else if (IS_SKL_ULT(i915)) {
+   } else if (IS_SKYLAKE_ULT(i915)) {
encoder->get_buf_trans = skl_u_get_buf_trans;
} else if (IS_SKYLAKE(i915)) {
encoder->get_buf_trans = skl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f2a5fb7fdca6..85176eabcda0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1192,7 +1192,7 @@ skl_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
 
/* WaInPlaceDecompressionHang:skl */
-   if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
+   if (IS_SKYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, STEP_A0, 
STEP_H0))
wa_write_or(wal,
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6607f233461a..d7f7ca135000 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -609,19 +609,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 /* ULX machines are also considered ULT. */
 #define IS_HASWELL_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(i915) \
+#define IS_SKYLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(i915) \
+#define IS_SKYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_KBL_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_KBL_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(i915)   (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT2(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)
-#define IS_SKL_GT3(i915)   (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT3(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)
-#define IS_SKL_GT4(i915)   (IS_SKYLAKE(i915) && \
+#define IS_SKYLAKE_GT4(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 4)
 #define IS_KBL_GT2(i915)   (IS_KABYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)
@@ -649,7 +649,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TGL_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
-#define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && 
IS_GRAPHICS_STEP(p, since, until))
 
 #define IS_KBL_GRAPHICS_STEP(i915, since, until) \
(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
@@ -800,7 +799,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(i915)   \
-   (IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
+   (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
-- 
2.34.1

[Intel-gfx] [PATCH v1 06/14] drm/i915/cml: s/CML/COMETLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace CML with
COMETLAKE.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h| 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index cd85b9fed129..35e6e3a5ddf1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1740,9 +1740,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder 
*encoder)
encoder->get_buf_trans = icl_get_mg_buf_trans;
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
encoder->get_buf_trans = bxt_get_buf_trans;
-   } else if (IS_CML_ULX(i915) || IS_COFFEELAKE_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
+   } else if (IS_COMETLAKE_ULX(i915) || IS_COFFEELAKE_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
encoder->get_buf_trans = kbl_y_get_buf_trans;
-   } else if (IS_CML_ULT(i915) || IS_COFFEELAKE_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
+   } else if (IS_COMETLAKE_ULT(i915) || IS_COFFEELAKE_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || 
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04107696e966..e6f77498d46c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -636,11 +636,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COFFEELAKE_GT3(i915)(IS_COFFEELAKE(i915) && \
 INTEL_INFO(i915)->gt == 3)
 
-#define IS_CML_ULT(i915) \
+#define IS_COMETLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_CML_ULX(i915) \
+#define IS_COMETLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_CML_GT2(i915)   (IS_COMETLAKE(i915) && \
+#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
 INTEL_INFO(i915)->gt == 2)
 
 #define IS_ICL_WITH_PORT_F(i915) \
-- 
2.34.1

[Intel-gfx] [PATCH v4 04/14] drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace KBL with
KABYLAKE.Replace IS_KBL_GRAPHICS_STEP with
IS_KABYLAKE () && IS_GRAPHICS_STEP().

v2:
- s/KBL/kbl in the subject prefix(Anusha)

v3:
- Unrolled wrapper IS_KBL_GRAPHICS_STEP.
- Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani)

v4:
- Removed unused macro.

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c |  4 ++--
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c|  6 +++---
 drivers/gpu/drm/i915/i915_drv.h| 12 
 drivers/gpu/drm/i915/intel_clock_gating.c  |  4 ++--
 5 files changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index e85eab21b09d..39eab9ea02dd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1740,9 +1740,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder 
*encoder)
encoder->get_buf_trans = icl_get_mg_buf_trans;
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
encoder->get_buf_trans = bxt_get_buf_trans;
-   } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
+   } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || 
IS_KABYLAKE_ULX(i915)) {
encoder->get_buf_trans = kbl_y_get_buf_trans;
-   } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
+   } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || 
IS_KABYLAKE_ULT(i915)) {
encoder->get_buf_trans = kbl_u_get_buf_trans;
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || 
IS_KABYLAKE(i915)) {
encoder->get_buf_trans = kbl_get_buf_trans;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 23857cc08eca..971cddb6d760 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -43,7 +43,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
vf_flush_wa = true;
 
/* WaForGAMHang:kbl */
-   if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
+   if (IS_KABYLAKE(rq->engine->i915) && 
IS_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
dc_flush_wa = true;
}
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 85176eabcda0..3b4a5b49418d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -600,7 +600,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs 
*engine,
gen9_ctx_workarounds_init(engine, wal);
 
/* WaToEnableHwFixForPushConstHWBug:kbl */
-   if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
+   if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
@@ -1204,7 +1204,7 @@ kbl_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
gen9_gt_workarounds_init(gt, wal);
 
/* WaDisableDynamicCreditSharing:kbl */
-   if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
+   if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
wa_write_or(wal,
GAMT_CHKN_BIT_REG,
GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -2945,7 +2945,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct 
i915_wa_list *wal)
struct drm_i915_private *i915 = engine->i915;
 
/* WaKBLVECSSemaphoreWaitPoll:kbl */
-   if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
+   if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
wa_write(wal,
 RING_SEMA_WAIT_POLL(engine->mmio_base),
 1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7f7ca135000..ba075bb183db 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -613,9 +613,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_SKYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_KBL_ULT(i915) \
+#define IS_KABYLAKE_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_KBL_ULX(i915) \
+#define IS_KABYLAKE_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_SKYLAKE_GT2(i915)   (IS_SKYLAKE(i915) && \
 INTEL_INFO(i915)->gt == 

[Intel-gfx] [PATCH v3 07/14] drm/i915/rkl: s/RKL/ROCKETLAKE for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace RKL with
ROCKETLAKE.Replace IS_RKL_GRAPHICS_STEP with
IS_ROCKETLAKE && IS_DISPLAY_STEP.

v2:
- s/RKL/rkl in the subject prefix(Anusha)

v3:
- Unrolled wrapper IS_RKL_DISPLAY_STEP.
- Replace IS_PLATFORM && IS_DISPLAY_STEP (Jani/Tvrtko)

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Anusha Srivatsa 
Signed-off-by: Dnyaneshwar Bhadane 

---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h| 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 38225e5d311e..9e01054c2430 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1609,7 +1609,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private 
*dev_priv)
return;
 
if (IS_ALDERLAKE_S(dev_priv) ||
-   IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+   (IS_ROCKETLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, 
STEP_B0)))
/* Wa_1409767108 */
table = wa_1409767108_buddy_page_masks;
else
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e6f77498d46c..f46846574420 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -660,8 +660,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_TIGERLAKE(__i915) && \
 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_RKL_DISPLAY_STEP(p, since, until) \
-   (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 
 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
(IS_ALDERLAKE_S(__i915) && \
-- 
2.34.1

[Intel-gfx] [PATCH v1 02/14] drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace BDW with
BROADWELL.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  4 ++--
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h  |  6 +++---
 drivers/gpu/drm/i915/soc/intel_pch.c | 10 +-
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f18e1f8ef22e..f683802ce931 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3200,9 +3200,9 @@ void intel_update_max_cdclk(struct drm_i915_private 
*dev_priv)
 */
if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
dev_priv->display.cdclk.max_cdclk_freq = 45;
-   else if (IS_BDW_ULX(dev_priv))
+   else if (IS_BROADWELL_ULX(dev_priv))
dev_priv->display.cdclk.max_cdclk_freq = 45;
-   else if (IS_BDW_ULT(dev_priv))
+   else if (IS_BROADWELL_ULT(dev_priv))
dev_priv->display.cdclk.max_cdclk_freq = 54;
else
dev_priv->display.cdclk.max_cdclk_freq = 675000;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 6352c530bd7b..e401bcb234c2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7377,7 +7377,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private 
*dev_priv)
if (DISPLAY_VER(dev_priv) >= 9)
return false;
 
-   if (IS_HASWELL_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
+   if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
return false;
 
if (HAS_PCH_LPT_H(dev_priv) &&
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b177c588698b..f2a5fb7fdca6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -420,7 +420,7 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs 
*engine,
 /* WaForceContextSaveRestoreNonCoherent:bdw */
 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
-(IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
+(IS_BROADWELL_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 }
 
 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1003154ec71e..6607f233461a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -594,11 +594,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
(INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(i915) \
+#define IS_BROADWELL_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
-#define IS_BDW_ULX(i915) \
+#define IS_BROADWELL_ULX(i915) \
IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_BDW_GT3(i915)   (IS_BROADWELL(i915) && \
+#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
 INTEL_INFO(i915)->gt == 3)
 #define IS_HASWELL_ULT(i915) \
IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c 
b/drivers/gpu/drm/i915/soc/intel_pch.c
index bf829f85be7e..382a4a8015b4 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -32,21 +32,21 @@ intel_pch_type(const struct drm_i915_private *dev_priv, 
unsigned short id)
drm_WARN_ON(_priv->drm,
!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
drm_WARN_ON(_priv->drm,
-   IS_HASWELL_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
+   IS_HASWELL_ULT(dev_priv) || 
IS_BROADWELL_ULT(dev_priv));
return PCH_LPT;
case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
drm_dbg_kms(_priv->drm, "Found LynxPoint LP PCH\n");
drm_WARN_ON(_priv->drm,
!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
drm_WARN_ON(_priv->drm,
-   !IS_HASWELL_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
+   !IS_HASWELL_ULT(dev_priv) && 
!IS_BROADWELL_ULT(dev_priv));
return PCH_LPT;
case INTEL_PCH_WPT_DEVICE_ID_TYPE:

[Intel-gfx] [PATCH v1 01/14] drm/i915/hsw: s/HSW/HASWELL for platform/subplatform defines

[Dnyaneshwar Bhadane]

Follow consistent naming convention. Replace HSW with
HASWELL.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c|  2 +-
 drivers/gpu/drm/i915/display/intel_display_device.h |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_pch_refclk.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c  |  2 +-
 drivers/gpu/drm/i915/i915_driver.c  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h | 12 ++--
 drivers/gpu/drm/i915/soc/intel_pch.c| 10 +-
 10 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index dcc1f6941b60..f18e1f8ef22e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -470,7 +470,7 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
cdclk_config->cdclk = 45;
else if (freq == LCPLL_CLK_FREQ_450)
cdclk_config->cdclk = 45;
-   else if (IS_HSW_ULT(dev_priv))
+   else if (IS_HASWELL_ULT(dev_priv))
cdclk_config->cdclk = 337500;
else
cdclk_config->cdclk = 54;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 43cba98f7753..6352c530bd7b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7377,7 +7377,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private 
*dev_priv)
if (DISPLAY_VER(dev_priv) >= 9)
return false;
 
-   if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
+   if (IS_HASWELL_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
return false;
 
if (HAS_PCH_LPT_H(dev_priv) &&
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h 
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 3324bd453ca7..215e682bd8b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -54,7 +54,7 @@ struct drm_printer;
 #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
 #define HAS_HW_SAGV_WM(i915)   (DISPLAY_VER(i915) >= 13 && 
!IS_DGFX(i915))
 #define HAS_IPC(i915)  (DISPLAY_INFO(i915)->has_ipc)
-#define HAS_IPS(i915)  (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
+#define HAS_IPS(i915)  (IS_HASWELL_ULT(i915) || 
IS_BROADWELL(i915))
 #define HAS_LSPCON(i915)   (IS_DISPLAY_VER(i915, 9, 10))
 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || 
DISPLAY_VER(i915) >= 14)
 #define HAS_MSO(i915)  (DISPLAY_VER(i915) >= 12)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 03675620e3ea..f5407569300a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -510,7 +510,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
} else if (DISPLAY_VER(dev_priv) == 9) {
source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
-   } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
+   } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
   IS_BROADWELL(dev_priv)) {
source_rates = hsw_rates;
size = ARRAY_SIZE(hsw_rates);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6b2d8a1e2aa9..66afdb91fcdf 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -927,7 +927,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private 
*dev_priv,
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
-   if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
+   if (IS_HASWELL(dev_priv) && !IS_HASWELL_ULT(dev_priv)) {
refclk = dev_priv->display.dpll.ref_clks.nssc;
break;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c 
b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index f4c09cc37a5e..9583e86b602a 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -423,7 +423,7 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private 
*dev_priv,
if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
return true;
 
-   if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
+   if ((IS_BROADWELL(dev_priv) || IS_HASWELL_ULT(dev_priv)) &&
 

[Intel-gfx] [PATCH v4 00/14] Replace acronym with full platform name in defines.

[Dnyaneshwar Bhadane]

Replacing the acronym used in platform/sub platform defines.
This series covers Haswell, Broadwell, Skylake, Kabylake, Coffeelake,
Cometlake, Rocketlake, Jasperlake, Elkhartlake, Tigerlake, Alderlake,
platoform define.This way there is a consistent pattern 
to how platforms are referred.splitting to per paltform for easier 
cherrypicks, if needed.

v2:
 - Reordered patches by incrementing platform generations.(Anusha)
 - Changeed the commit subject with lowercase platform names.
v3:
 - The IS_PLATFORM_(DISPLAY/MEDIA/GRAPHICS)_STEPS replace with Unrolled
 format. i.e. IS_PLATFORM_FULL_NAME () && IS_DISPLAY_STEPS()

v4:
 - Removed the MTL platform from the renaming series (Mat Ropper)
 - Removed the unused display steps macro.

Anusha Srivatsa (1):
  drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN defines

Dnyaneshwar Bhadane (13):
  drm/i915/hsw: s/HSW/HASWELL for platform/subplatform defines
  drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform defines
  drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform defines
  drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines
  drm/i915/cfl: s/CFL/COFFEELAKE for platform/subplatform defines
  drm/i915/cml: s/CML/COMETLAKE for platform/subplatform defines
  drm/i915/rkl: s/RKL/ROCKETLAKE for platform/subplatform defines
  drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines
  drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform defines
  drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics step
  drm/i915/rplp: s/ADLP/ALDERLAKE_P for RPLP defines
  drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines
  drm/i915/adls: s/ADLS/ALDERLAKE_S in platform and subplatform defines

Cc: Tvrtko Ursulin 
Cc: Jani Nikula 
Cc: Matt Roper 
Cc: Anusha Srivatsa 
Cc: matthew Atwood 

 drivers/gpu/drm/i915/display/icl_dsi.c|  5 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c| 14 +--
 .../gpu/drm/i915/display/intel_combo_phy.c|  7 +-
 drivers/gpu/drm/i915/display/intel_ddi.c  |  7 +-
 .../drm/i915/display/intel_ddi_buf_trans.c| 10 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  7 +-
 .../drm/i915/display/intel_display_device.c   |  2 +-
 .../drm/i915/display/intel_display_device.h   |  2 +-
 .../drm/i915/display/intel_display_power.c|  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |  4 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 33 ---
 drivers/gpu/drm/i915/display/intel_hdmi.c |  3 +-
 .../gpu/drm/i915/display/intel_pch_refclk.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c  | 10 +-
 .../drm/i915/display/skl_universal_plane.c|  6 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  2 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 13 +--
 .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  2 +-
 drivers/gpu/drm/i915/i915_driver.c|  2 +-
 drivers/gpu/drm/i915/i915_drv.h   | 94 +++
 drivers/gpu/drm/i915/intel_clock_gating.c |  4 +-
 drivers/gpu/drm/i915/intel_step.c | 10 +-
 drivers/gpu/drm/i915/soc/intel_pch.c  | 18 ++--
 28 files changed, 127 insertions(+), 142 deletions(-)

-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests 
(rev8)
URL   : https://patchwork.freedesktop.org/series/117713/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13426 -> Patchwork_117713v8


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/index.html

Participating hosts (41 -> 39)
--

  Additional (1): bat-adlp-11 
  Missing(3): bat-rpls-2 fi-tgl-1115g4 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_117713v8 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-blb-e6850:   [PASS][1] -> [FAIL][2] ([i915#8622])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-blb-e6850/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/fi-blb-e6850/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@i915_module_load@load:
- bat-adlp-11:NOTRUN -> [ABORT][3] ([i915#4423])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/bat-adlp-11/igt@i915_module_l...@load.html

  * igt@i915_pm_rpm@basic-rte:
- fi-skl-guc: [PASS][4] -> [FAIL][5] ([i915#7940])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-skl-guc/igt@i915_pm_...@basic-rte.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/fi-skl-guc/igt@i915_pm_...@basic-rte.html

  * igt@i915_selftest@live@gt_mocs:
- bat-mtlp-6: [PASS][6] -> [DMESG-FAIL][7] ([i915#7059])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][8] -> [ABORT][9] ([i915#7911] / [i915#7920])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/bat-rpls-1/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [PASS][10] -> [DMESG-FAIL][11] ([i915#6763])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-mtlp-6/igt@i915_selftest@l...@workarounds.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/bat-mtlp-6/igt@i915_selftest@l...@workarounds.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-jsl-3:  NOTRUN -> [SKIP][12] ([i915#7828])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/bat-jsl-3/igt@kms_chamelium_...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][13] -> [ABORT][14] ([i915#8442] / [i915#8668])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3:  [ABORT][15] ([i915#5122]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- bat-adlp-9: [FAIL][17] ([i915#7940]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-adlp-9/igt@i915_pm_...@basic-pci-d3-state.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/bat-adlp-9/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
- fi-kbl-x1275:   [FAIL][19] ([i915#8843]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-kbl-x1275/igt@i915_pm_...@basic-rte.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/fi-kbl-x1275/igt@i915_pm_...@basic-rte.html
- fi-kbl-guc: [FAIL][21] ([i915#8843]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-kbl-guc/igt@i915_pm_...@basic-rte.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/fi-kbl-guc/igt@i915_pm_...@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
- fi-rkl-11600:   [FAIL][23] ([i915#7940]) -> [PASS][24]
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-rkl-11600/igt@i915_pm_...@module-reload.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v8/fi-rkl-11600/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: 

Re: [Intel-gfx] [PATCH v6 3/4] drm: Expand max DRM device number to full MINORBITS

[Simon Ser]

On Monday, July 24th, 2023 at 23:14, Michał Winiarski 
 wrote:

> Having a limit of 64 DRM devices is not good enough for modern world
> where we have multi-GPU servers, SR-IOV virtual functions and virtual
> devices used for testing.
> Let's utilize full minor range for DRM devices.
> To avoid regressing the existing userspace, we're still maintaining the
> numbering scheme where 0-63 is used for primary, 64-127 is reserved
> (formerly for control) and 128-191 is used for render.
> For minors >= 192, we're allocating minors dynamically on a first-come,
> first-served basis.

In general the approach looks good to me. Old libdrm will see the new
nodes as nodes with an unknown type when it tries to infer the nod type
from the minor, which is as good as it gets.

We do need patches to stop trying to infer the node type from the minor
in libdrm, though. Emil has suggested using sysfs, which we already do
in a few places in libdrm.

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests (rev7)

[Teres Alexis, Alan Previn]

> IGT changes
> Possible regressions
> 
>   *   igt@vgem_basic@dmabuf-fence-before:
>  *   fi-kbl-soraka: 
> PASS
>  -> 
> INCOMPLETE
> 
This failure is unrelated because of two reasons - #1, the patch will only be 
in effect on MTL and #2, the patch is only part of self-test startup but this 
is not a self-test
failure.

Re: [Intel-gfx] [PATCH i-g-t 3/3] gputop: Add memory information

[Kamil Konieczny]

Hi Tvrtko,

On 2023-07-05 at 17:31:05 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Show total and resident memory usage for clients which support it.
> 
> For simplicity all memory regions are summed up and shown under a single
> heading.
> 
> Co-developed-by: Rob Clark 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  tools/gputop.c | 34 +-
>  1 file changed, 33 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/gputop.c b/tools/gputop.c
> index 681f0a6bb748..b5b360cbb063 100644
> --- a/tools/gputop.c
> +++ b/tools/gputop.c
> @@ -28,6 +28,7 @@
>  
>  #include "igt_drm_clients.h"
>  #include "igt_drm_fdinfo.h"
> +#include "drmtest.h"
>  
>  static const char *bars[] = { " ", "▏", "▎", "▍", "▌", "▋", "▊", "▉", "█" };
>  
> @@ -80,7 +81,11 @@ print_client_header(struct igt_drm_client *c, int lines, 
> int con_w, int con_h,
>   return lines;
>  
>   putchar('\n');
> - len = printf("%*s ", c->clients->max_pid_len, "PID");
> + if (c->regions->num_regions)
> + len = printf("%*s  MEM  RSS ",
> +  c->clients->max_pid_len, "PID");
> + else
> + len = printf("%*s ", c->clients->max_pid_len, "PID");
>  
>   if (c->engines->num_engines) {
>   unsigned int i;
> @@ -121,12 +126,28 @@ newheader(const struct igt_drm_client *c, const struct 
> igt_drm_client *pc)
>   return !pc || c->drm_minor != pc->drm_minor;
>  }
>  
> +static int
> +print_size(uint64_t sz)
> +{
> + char units[] = {'B', 'K', 'M', 'G'};
> + unsigned u;
--- ^
Better:
unsigned int u;

With that add my r-b tag,

Regards,
Kamil

> +
> + for (u = 0; u < ARRAY_SIZE(units) - 1; u++) {
> + if (sz < 1024)
> + break;
> + sz /= 1024;
> + }
> +
> + return printf("%7"PRIu64"%c ", sz, units[u]);
> +}
> +
>  static int
>  print_client(struct igt_drm_client *c, struct igt_drm_client **prevc,
>double t, int lines, int con_w, int con_h,
>unsigned int period_us, int *engine_w)
>  {
>   unsigned int i;
> + uint64_t sz;
>   int len;
>  
>   /* Filter out idle clients. */
> @@ -143,6 +164,17 @@ print_client(struct igt_drm_client *c, struct 
> igt_drm_client **prevc,
>   *prevc = c;
>  
>   len = printf("%*s ", c->clients->max_pid_len, c->pid_str);
> +
> + if (c->regions->num_regions) {
> + for (sz = 0, i = 0; i < c->regions->max_region_id; i++)
> + sz += c->memory[i].total;
> + len += print_size(sz);
> +
> + for (sz = 0, i = 0; i < c->regions->max_region_id; i++)
> + sz += c->memory[i].resident;
> + len += print_size(sz);
> + }
> +
>   lines++;
>  
>   for (i = 0; c->samples > 1 && i <= c->engines->max_engine_id; i++) {
> -- 
> 2.39.2
> 

Re: [Intel-gfx] [PATCH i-g-t 1/3] lib/igt_drm_fdinfo: Parse memory usage

[Kamil Konieczny]

Hi Tvrtko,

please check your patches with Linux kernel script checkpatch.pl
Some of it's warnings seems strange, like:

WARNING: Co-developed-by and Signed-off-by: name/email do not match
#12:
Co-developed-by: Rob Clark 
Signed-off-by: Tvrtko Ursulin 

On 2023-07-05 at 17:31:03 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Add parsing and memory storage for the memory usage related fdinfo stats.
> 
> Uses the same approach as the engine utilization code by either auto-
> discovering different memory regions, or allowing for the caller to pass
> in a map with predefined index to name relationship.
> 
> Co-developed-by: Rob Clark 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  lib/igt_drm_clients.c   |   3 +-
>  lib/igt_drm_fdinfo.c| 142 ++--
>  lib/igt_drm_fdinfo.h|  24 ++-
>  tests/i915/drm_fdinfo.c |   8 +--
>  tools/intel_gpu_top.c   |   2 +-
>  5 files changed, 165 insertions(+), 14 deletions(-)
> 
> diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
> index f0294ba81c42..fdea42752a81 100644
> --- a/lib/igt_drm_clients.c
> +++ b/lib/igt_drm_clients.c
> @@ -491,7 +491,8 @@ igt_drm_clients_scan(struct igt_drm_clients *clients,
>  
>   if (!__igt_parse_drm_fdinfo(dirfd(fdinfo_dir),
>   fdinfo_dent->d_name, ,
> - name_map, map_entries))
> + name_map, map_entries,
> + NULL, 0))
>   continue;
>  
>   if (filter_client && !filter_client(clients, ))
> diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
> index b5f8a8679a71..d08632dfb690 100644
> --- a/lib/igt_drm_fdinfo.c
> +++ b/lib/igt_drm_fdinfo.c
> @@ -124,13 +124,81 @@ static const char *find_kv(const char *buf, const char 
> *key, size_t keylen)
>   return *p ? p : NULL;
>  }
>  
> +static int parse_region(char *line, struct drm_client_fdinfo *info,
> + size_t prefix_len,
> + const char **region_map, unsigned int region_entries,
> + uint64_t *val)
> +{
> + char *name, *p, *unit = NULL;
> + ssize_t name_len;
> + int found = -1;
> + unsigned int i;
> +
> + p = index(line, ':');
> + if (!p || p == line)
> + return -1;
> +
> + name_len = p - line - prefix_len;
> + if (name_len < 1)
> + return -1;
> +
> + name = line + prefix_len;
> +
> + if (region_map) {
> + for (i = 0; i < region_entries; i++) {
> + if (!strncmp(name, region_map[i], name_len)) {
> + found = i;
> + break;
> + }
> + }
> + } else {
> + for (i = 0; i < info->num_regions; i++) {
> + if (!strncmp(name, info->region_names[i], name_len)) {
> + found = i;
> + break;
> + }
> + }
> +
> + if (found < 0) {
> + assert((info->num_regions + 1) < 
> ARRAY_SIZE(info->region_names));
> + assert((strlen(name) + 1) < 
> sizeof(info->region_names[0]));
> + strncpy(info->region_names[info->num_regions], name, 
> name_len);
> + found = info->num_regions;
> + }
> + }
> +
> + if (found < 0)
> + goto out;
> +
> + while (*++p && isspace(*p));
-- ^
According to checkpatch:
while (*++p && isspace(*p))
;

> + *val = strtoull(p, NULL, 10);
> +
> + p = index(p, ' ');
> + if (!p)
> + goto out;
> +
> + unit = ++p;
> + if (!strcmp(unit, "KiB")) {
> + *val *= 1024;
> + } else if (!strcmp(unit, "MiB")) {
--- ^^
No need for separate 'else':
if (!strcmp(unit, "MiB")) {

> + *val *= 1024 * 1024;
> + } else if (!strcmp(unit, "GiB")) {
--- ^^
Same here.

Regards,
Kamil

> + *val *= 1024 * 1024 * 1024;
> + }
> +
> +out:
> + return found;
> +}
> +
>  unsigned int
>  __igt_parse_drm_fdinfo(int dir, const char *fd, struct drm_client_fdinfo 
> *info,
> -const char **name_map, unsigned int map_entries)
> +const char **name_map, unsigned int map_entries,
> +const char **region_map, unsigned int region_entries)
>  {
> + bool regions_found[DRM_CLIENT_FDINFO_MAX_REGIONS] = { };
> + unsigned int good = 0, num_capacity = 0;
>   char buf[4096], *_buf = buf;
>   char *l, *ctx = NULL;
> - unsigned int good = 0, num_capacity = 0;
>   size_t count;
>  
>   count = read_fdinfo(buf, sizeof(buf), dir, fd);
> @@ -173,18 +241,79 @@ __igt_parse_drm_fdinfo(int dir, const char *fd, struct 
> 

Re: [Intel-gfx] [PATCH i-g-t 2/3] lib/igt_drm_clients: Store memory info in the client

[Kamil Konieczny]

Hi Tvrtko,

On 2023-07-05 at 17:31:04 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Define the storage structure and copy over memory data as parsed by the
> fdinfo helpers.
> 
> Signed-off-by: Tvrtko Ursulin 
> Cc: Rob Clark 
> ---
>  lib/igt_drm_clients.c | 31 +++
>  lib/igt_drm_clients.h | 11 +++
>  2 files changed, 42 insertions(+)
> 
> diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
> index fdea42752a81..0db5b64effea 100644
> --- a/lib/igt_drm_clients.c
> +++ b/lib/igt_drm_clients.c
> @@ -103,6 +103,8 @@ igt_drm_client_update(struct igt_drm_client *c, unsigned 
> int pid, char *name,
>   c->clients->max_name_len = len;
>   }
>  
> + /* Engines */
> +
>   c->last_runtime = 0;
>   c->total_runtime = 0;
>  
> @@ -118,6 +120,13 @@ igt_drm_client_update(struct igt_drm_client *c, unsigned 
> int pid, char *name,
>   c->last[i] = info->busy[i];
>   }
>  
> + /* Memory regions */
> + for (i = 0; i <= c->regions->max_region_id; i++) {
> + assert(i < ARRAY_SIZE(info->region_mem));
> +
> + c->memory[i] = info->region_mem[i];
> + }
> +
>   c->samples++;
>   c->status = IGT_DRM_CLIENT_ALIVE;
>  }
> @@ -154,6 +163,8 @@ igt_drm_client_add(struct igt_drm_clients *clients,
>   c->id = info->id;
>   c->drm_minor = drm_minor;
>   c->clients = clients;
> +
> + /* Engines */
>   c->engines = malloc(sizeof(*c->engines));
>   assert(c->engines);
>   memset(c->engines, 0, sizeof(*c->engines));
> @@ -178,6 +189,26 @@ igt_drm_client_add(struct igt_drm_clients *clients,
>   c->last = calloc(c->engines->max_engine_id + 1, sizeof(c->last));
>   assert(c->val && c->last);
>  
> + /* Memory regions */
> + c->regions = malloc(sizeof(*c->regions));
> + assert(c->regions);
> + memset(c->regions, 0, sizeof(*c->regions));
> + c->regions->names = calloc(info->last_region_index + 1,
> +sizeof(*c->regions->names));
> + assert(c->regions->names);
> +
> + for (i = 0; i <= info->last_region_index; i++) {
> + if (!info->region_names[i])

This do not compile:
../lib/igt_drm_clients.c:201:21: error: the comparison will always evaluate as 
‘true’ for the address of ‘region_names’ will never be NULL [-Werror=address]
  201 | if (!info->region_names[i])
  | ^
In file included from ../lib/igt_drm_clients.h:11,
 from ../lib/igt_drm_clients.c:20:
../lib/igt_drm_fdinfo.h:57:14: note: ‘region_names’ declared here
   57 | char region_names[DRM_CLIENT_FDINFO_MAX_REGIONS][256];
  |  ^~~~

did you mean:

if (!info->region_names[i][0])

Regards,
Kamil

> + continue;
> +
> + c->regions->names[i] = strdup(info->region_names[i]);
> + assert(c->regions->names[i]);
> + c->regions->num_regions++;
> + c->regions->max_region_id = i;
> + }
> + c->memory = calloc(c->regions->max_region_id + 1, sizeof(*c->memory));
> + assert(c->memory);
> +
>   igt_drm_client_update(c, pid, name, info);
>  }
>  
> diff --git a/lib/igt_drm_clients.h b/lib/igt_drm_clients.h
> index ed795c193986..07bd236d43bf 100644
> --- a/lib/igt_drm_clients.h
> +++ b/lib/igt_drm_clients.h
> @@ -8,6 +8,8 @@
>  
>  #include 
>  
> +#include "lib/igt_drm_fdinfo.h"
> +
>  /**
>   * SECTION:igt_drm_clients
>   * @short_description: Parsing driver exposed fdinfo to track DRM clients
> @@ -39,12 +41,20 @@ struct igt_drm_client_engines {
>   char **names; /* Array of engine names, either auto-detected or from 
> the passed in engine map. */
>  };
>  
> +struct igt_drm_client_regions {
> + unsigned int num_regions; /* Number of discovered memory_regions. */
> + unsigned int max_region_id; /* Largest memory region index discovered.
> +(Can differ from num_regions - 1 when 
> using the region map facility.) */
> + char **names; /* Array of region names, either auto-detected or from 
> the passed in region map. */
> +};
> +
>  struct igt_drm_clients;
>  
>  struct igt_drm_client {
>   struct igt_drm_clients *clients; /* Owning list. */
>  
>   enum igt_drm_client_status status;
> + struct igt_drm_client_regions *regions; /* Memory regions present in 
> this client, to map with memory usage. */
>   struct igt_drm_client_engines *engines; /* Engines used by this client, 
> to map with busynees data. */
>   unsigned int id; /* DRM client id from fdinfo. */
>   unsigned int drm_minor; /* DRM minor of this client. */
> @@ -57,6 +67,7 @@ struct igt_drm_client {
>   unsigned long last_runtime; /* Aggregate busyness on all engines since 
> previous scan. */
>   unsigned long *val; /* Array of engine busyness data, relative to 
> previous scan. */
>   uint64_t *last; /* Array of engine 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Simplify shmem_create_from_object map_type selection

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/gt: Simplify 
shmem_create_from_object map_type selection
URL   : https://patchwork.freedesktop.org/series/121373/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13426 -> Patchwork_121373v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/index.html

Participating hosts (41 -> 41)
--

  Additional (1): bat-adlp-11 
  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_121373v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_auth@basic-auth:
- bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#8011])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-adlp-11/igt@core_a...@basic-auth.html

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-skl-6600u:   [PASS][2] -> [ABORT][3] ([i915#5122])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-dg2-9:  [PASS][4] -> [INCOMPLETE][5] ([i915#7793])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@i915_module_load@load:
- bat-adlp-11:NOTRUN -> [DMESG-WARN][6] ([i915#4423])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-adlp-11/igt@i915_module_l...@load.html

  * igt@i915_pm_rpm@basic-rte:
- fi-skl-guc: [PASS][7] -> [FAIL][8] ([i915#7940])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-skl-guc/igt@i915_pm_...@basic-rte.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/fi-skl-guc/igt@i915_pm_...@basic-rte.html

  * igt@i915_selftest@live@slpc:
- bat-mtlp-6: [PASS][9] -> [DMESG-WARN][10] ([i915#6367])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-mtlp-6/igt@i915_selftest@l...@slpc.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-mtlp-6/igt@i915_selftest@l...@slpc.html
- bat-rpls-2: NOTRUN -> [DMESG-WARN][11] ([i915#6367])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
- bat-rpls-1: NOTRUN -> [DMESG-WARN][12] ([i915#6367])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][13] ([i915#6687] / [i915#7978] / 
[i915#8668])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][14] ([i915#7828])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-jsl-3:  NOTRUN -> [SKIP][15] ([i915#7828])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-jsl-3/igt@kms_chamelium_...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][16] -> [ABORT][17] ([i915#8442] / [i915#8668])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-2: NOTRUN -> [SKIP][18] ([i915#1845])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-rpls-2/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3:  [ABORT][19] ([i915#5122]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_pm_rpm@basic-rte:
- fi-kbl-x1275:   [FAIL][21] ([i915#8843]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13426/fi-kbl-x1275/igt@i915_pm_...@basic-rte.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121373v1/fi-kbl-x1275/igt@i915_pm_...@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
- fi-rkl-11600:   [FAIL][23] ([i915#7940]) -> 

Re: [Intel-gfx] [PATCH 16/17] cgroup/drm: Expose memory stats

[Tvrtko Ursulin]

On 21/07/2023 23:21, Tejun Heo wrote:

On Wed, Jul 12, 2023 at 12:46:04PM +0100, Tvrtko Ursulin wrote:

   $ cat drm.memory.stat
   card0 region=system total=12898304 shared=0 active=0 resident=12111872 
purgeable=167936
   card0 region=stolen-system total=0 shared=0 active=0 resident=0 purgeable=0

Data is generated on demand for simplicty of implementation ie. no running
totals are kept or accounted during migrations and such. Various
optimisations such as cheaper collection of data are possible but
deliberately left out for now.

Overall, the feature is deemed to be useful to container orchestration
software (and manual management).

Limits, either soft or hard, are not envisaged to be implemented on top of
this approach due on demand nature of collecting the stats.


So, yeah, if you want to add memory controls, we better think through how
the fd ownership migration should work.


It would be quite easy to make the implicit migration fail - just the 
matter of failing the first ioctl, which is what triggers the migration, 
after the file descriptor access from a new owner.


But I don't think I can really add that in the RFC given I have no hard 
controls or anything like that.


With GPU usage throttling it doesn't really apply, at least I don't 
think it does, since even when migrated to a lower budget group it would 
just get immediately de-prioritized.


I don't think hard GPU time limits are feasible in general, and while 
soft might be, again I don't see that any limiting would necessarily 
have to run immediately on implicit migration.


Second part of the story are hypothetical/future memory controls.

I think first thing to say is that implicit migration is important, but 
it is not really established to use the file descriptor from two places 
or to migrate more than once. It is simply fresh fd which gets sent to 
clients from Xorg, which is one of the legacy ways of doing things.


So we probably can just ignore that given no significant amount of 
memory ownership would be getting migrated.


And for drm.memory.stat I think what I have is good enough - both 
private and shared data get accounted, for any clients that have handles 
to particular buffers.


Maarten was working on memory controls so maybe he would have more 
thoughts on memory ownership and implicit migration.


But I don't think there is anything incompatible with that and 
drm.memory.stats as proposed here, given how the categories reported are 
the established ones from the DRM fdinfo spec, and it is fact of the 
matter that we can have multiple memory regions per driver.


The main thing that would change between this RFC and future memory 
controls in the area of drm.memory.stat is the implementation - it would 
have to get changed under the hood from "collect on query" to "account 
at allocation/free/etc". But that is just implementation details.


Regards,

Tvrtko

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Simplify shmem_create_from_object map_type selection

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/gt: Simplify 
shmem_create_from_object map_type selection
URL   : https://patchwork.freedesktop.org/series/121373/
State : warning

== Summary ==

Error: dim checkpatch failed
dd84f9f99c63 drm/i915/gt: Simplify shmem_create_from_object map_type selection
bf170c1d59f6 drm/i915: Make i915_coherent_map_type GT-centric
-:216: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#216: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1195:
+
intel_gt_coherent_map_type(ce->engine->gt,
ce->state->obj,

-:250: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#250: FILE: drivers/gpu/drm/i915/gt/selftest_context.c:92:
+
intel_gt_coherent_map_type(engine->gt,

ce->state->obj, false));

-:285: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#285: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:1296:
+  
intel_gt_coherent_map_type(engine->gt,
  
ce->state->obj,

-:319: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#319: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.c:796:
+
intel_gt_coherent_map_type(guc_to_gt(guc),

vma->obj, true));

-:402: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#402: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_tee.c:249:
+   cmd = i915_gem_object_pin_map_unlocked(obj, 
intel_gt_coherent_map_type(pxp->ctrl_gt, obj, true));

total: 0 errors, 1 warnings, 4 checks, 290 lines checked
8f99ef785777 drm/i915/gt: Apply workaround 22016122933 correctly

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/gt: Simplify shmem_create_from_object map_type selection

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/gt: Simplify 
shmem_create_from_object map_type selection
URL   : https://patchwork.freedesktop.org/series/121373/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Invalidate secondary IOMMU TLB on permission upgrade

[Patchwork]

== Series Details ==

Series: Invalidate secondary IOMMU TLB on permission upgrade
URL   : https://patchwork.freedesktop.org/series/121355/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/121355/revisions/1/mbox/ not 
applied
Applying: arm64/smmu: Use TLBI ASID when invalidating entire range
Applying: mmu_notifiers: Fixup comment in mmu_interval_read_begin()
Applying: mmu_notifiers: Call invalidate_range() when invalidating TLBs
error: short object ID b466172 is ambiguous
hint: The candidates are:
hint:   b46617207c93 blob
hint:   b466172eec25 blob
error: sha1 information is lacking or useless (include/asm-generic/tlb.h).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0003 mmu_notifiers: Call invalidate_range() when invalidating 
TLBs
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Regression in linux-next

[Patchwork]

== Series Details ==

Series: Regression in linux-next
URL   : https://patchwork.freedesktop.org/series/121356/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/121356/revisions/1/mbox/ not 
applied
Applying: Regression in linux-next
Using index info to reconstruct a base tree...
M   mm/mmu_notifier.c
Falling back to patching base and 3-way merge...
Auto-merging mm/mmu_notifier.c
CONFLICT (content): Merge conflict in mm/mmu_notifier.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 Regression in linux-next
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

[Intel-gfx] [PATCH 2/3] drm/i915: Make i915_coherent_map_type GT-centric

[Jonathan Cavitt]

Refactor i915_coherent_map_type to be GT-centric rather than
device-centric.  Each GT may require different coherency
handling due to hardware workarounds.

Since the function now takes a GT instead of the i915, the function is
renamed and moved to the gt folder.

Suggested-by: Matt Roper 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c |  3 ++-
 drivers/gpu/drm/i915/gem/i915_gem_object.h|  4 
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 15 ---
 .../gpu/drm/i915/gem/selftests/i915_gem_migrate.c | 12 ++--
 drivers/gpu/drm/i915/gt/intel_engine_pm.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c| 15 +++
 drivers/gpu/drm/i915/gt/intel_gt.h|  3 +++
 drivers/gpu/drm/i915/gt/intel_gtt.c   |  4 ++--
 drivers/gpu/drm/i915/gt/intel_lrc.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_ring.c  |  3 ++-
 drivers/gpu/drm/i915/gt/selftest_context.c|  2 +-
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |  4 ++--
 drivers/gpu/drm/i915/gt/selftest_lrc.c|  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c |  3 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  3 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  3 ++-
 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c|  3 ++-
 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c  |  3 ++-
 drivers/gpu/drm/i915/selftests/igt_spinner.c  |  2 +-
 20 files changed, 46 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c 
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index ad0405375881..d753db3eef15 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -6,6 +6,7 @@
 #include 
 
 #include "gem/i915_gem_region.h"
+#include "gt/intel_gt.h"
 #include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"
 #include "i915_drv.h"
 #include "i915_utils.h"
@@ -632,7 +633,7 @@ static int intel_hdcp_gsc_initialize_message(struct 
drm_i915_private *i915,
return PTR_ERR(obj);
}
 
-   cmd_in = i915_gem_object_pin_map_unlocked(obj, 
i915_coherent_map_type(i915, obj, true));
+   cmd_in = i915_gem_object_pin_map_unlocked(obj, 
intel_gt_coherent_map_type(gt, obj, true));
if (IS_ERR(cmd_in)) {
drm_err(>drm, "Failed to map gsc message page!\n");
err = PTR_ERR(cmd_in);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 884a17275b3a..0c695b4c129f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -716,10 +716,6 @@ void *__must_check i915_gem_object_pin_map(struct 
drm_i915_gem_object *obj,
 void *__must_check i915_gem_object_pin_map_unlocked(struct drm_i915_gem_object 
*obj,
enum i915_map_type type);
 
-enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
- struct drm_i915_gem_object *obj,
- bool always_coherent);
-
 void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
 unsigned long offset,
 unsigned long size);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c 
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 89fc8ea6bcfc..6d262d269c71 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -465,21 +465,6 @@ void *i915_gem_object_pin_map_unlocked(struct 
drm_i915_gem_object *obj,
return ret;
 }
 
-enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
- struct drm_i915_gem_object *obj,
- bool always_coherent)
-{
-   /*
-* Wa_22016122933: always return I915_MAP_WC for MTL
-*/
-   if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
-   return I915_MAP_WC;
-   if (HAS_LLC(i915) || always_coherent)
-   return I915_MAP_WB;
-   else
-   return I915_MAP_WC;
-}
-
 void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
 unsigned long offset,
 unsigned long size)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
index a93a90b15907..d8f4a10d71de 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
@@ -13,12 +13,12 @@
 #include "selftests/igt_spinner.h"
 
 static int igt_fill_check_buffer(struct drm_i915_gem_object *obj,
+struct intel_gt *gt,
 bool 

[Intel-gfx] [PATCH 3/3] drm/i915/gt: Apply workaround 22016122933 correctly

[Jonathan Cavitt]

WA_22016122933 was recently applied to all MeteorLake engines, which is
simultaneously too broad (should only apply to Media engines) and too
specific (should apply to all platforms that use the same media engine
as MeteorLake).  Correct this in cases where coherency settings are
modified.

There were also two additional places where the workaround was applied
unconditionally.  The change was confirmed as necessary for all
platforms, so the workaround label was removed.

Signed-off-by: Jonathan Cavitt 
Suggested-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_gt.c| 5 +++--
 drivers/gpu/drm/i915/gt/intel_gt.h| 6 ++
 drivers/gpu/drm/i915/gt/intel_lrc.c   | 7 ---
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 4 
 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 7 ---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 
 6 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 62eda0ab9bfc..b0f029f2380d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1139,9 +1139,10 @@ enum i915_map_type intel_gt_coherent_map_type(struct 
intel_gt *gt,
  bool always_coherent)
 {
/*
-* Wa_22016122933: always return I915_MAP_WC for MTL
+* Wa_22016122933: always return I915_MAP_WC for Media
+* version 13.0 when the object is on the Media GT
 */
-   if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(gt->i915))
+   if (i915_gem_object_is_lmem(obj) || intel_gt_needs_wa_22016122933(gt))
return I915_MAP_WC;
if (HAS_LLC(gt->i915) || always_coherent)
return I915_MAP_WB;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index adb442aaa522..2444ceb42b1b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -6,6 +6,7 @@
 #ifndef __INTEL_GT__
 #define __INTEL_GT__
 
+#include "i915_drv.h"
 #include "intel_engine_types.h"
 #include "intel_gt_types.h"
 #include "intel_reset.h"
@@ -24,6 +25,11 @@ static inline bool gt_is_root(struct intel_gt *gt)
return !gt->info.id;
 }
 
+static inline bool intel_gt_needs_wa_22016122933(struct intel_gt *gt)
+{
+   return MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && gt->type == 
GT_MEDIA;
+}
+
 static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
 {
return container_of(uc, struct intel_gt, uc);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 1897cb5aa2a2..1c43276ae4b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1095,10 +1095,11 @@ __lrc_alloc_state(struct intel_context *ce, struct 
intel_engine_cs *engine)
if (IS_ERR(obj)) {
obj = i915_gem_object_create_shmem(engine->i915, context_size);
/*
-* Wa_22016122933: For MTL the shared memory needs to be mapped
-* as WC on CPU side and UC (PAT index 2) on GPU side
+* Wa_22016122933: For Media version 13.0, all Media GT shared
+* memory needs to be mapped as WC on CPU side and UC (PAT
+* index 2) on GPU side.
 */
-   if (IS_METEORLAKE(engine->i915))
+   if (intel_gt_needs_wa_22016122933(engine->gt))
i915_gem_object_set_cache_coherency(obj, 
I915_CACHE_NONE);
}
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index 6efb86c93bfc..52652a0350c6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -284,10 +284,6 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
memcpy_toio(gsc->local_vaddr, src, gsc->fw.size);
memset_io(gsc->local_vaddr + gsc->fw.size, 0, gsc->local->size - 
gsc->fw.size);
 
-   /*
-* Wa_22016122933: Making sure the data in dst is
-* visible to GSC right away
-*/
intel_guc_write_barrier(>uc.guc);
 
i915_gem_object_unpin_map(gsc->fw.obj);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index c0fa9d232205..63bdc000d76b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -745,10 +745,11 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc 
*guc, u32 size)
return ERR_CAST(obj);
 
/*
-* Wa_22016122933: For MTL the shared memory needs to be mapped
-* as WC on CPU side and UC (PAT index 2) on GPU side
+* Wa_22016122933: For Media version 13.0, all Media GT shared
+* memory needs to be mapped as WC on CPU side and UC (PAT
+* index 2) on GPU side.
 */
-   if (IS_METEORLAKE(gt->i915))
+   if 

[Intel-gfx] [PATCH 1/3] drm/i915/gt: Simplify shmem_create_from_object map_type selection

[Jonathan Cavitt]

The object pin created for shmem_create_from_object is just a
single use mapping with the sole purpose of reading the contents
of the whole object in bulk. And the whole source object is also
even a throw-away.  Ergo, the additional logic required by
i915_coherent_map_type can be safely dropped and simplified.

Signed-off-by: Jonathan Cavitt 
Suggested-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gt/shmem_utils.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c 
b/drivers/gpu/drm/i915/gt/shmem_utils.c
index 449c9ed44382..bccc3a1200bc 100644
--- a/drivers/gpu/drm/i915/gt/shmem_utils.c
+++ b/drivers/gpu/drm/i915/gt/shmem_utils.c
@@ -33,7 +33,6 @@ struct file *shmem_create_from_data(const char *name, void 
*data, size_t len)
 
 struct file *shmem_create_from_object(struct drm_i915_gem_object *obj)
 {
-   struct drm_i915_private *i915 = to_i915(obj->base.dev);
enum i915_map_type map_type;
struct file *file;
void *ptr;
@@ -44,7 +43,7 @@ struct file *shmem_create_from_object(struct 
drm_i915_gem_object *obj)
return file;
}
 
-   map_type = i915_coherent_map_type(i915, obj, true);
+   map_type = i915_gem_object_is_lmem(obj) ? I915_MAP_WC : I915_MAP_WB;
ptr = i915_gem_object_pin_map_unlocked(obj, map_type);
if (IS_ERR(ptr))
return ERR_CAST(ptr);
-- 
2.25.1

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Add getter/setter for i915_gem_object->frontbuffer

[Nirmoy Das]

Hi Jouni,

On 5/29/2023 8:27 AM, Jouni Högander wrote:

Add getter/setter for i915_gem_object->frontbuffer and use it instead of
directly touching i915_gem_object->frontbuffer frontbuffer pointer.

Signed-off-by: Jouni Högander 
---
  .../gpu/drm/i915/display/intel_frontbuffer.c  | 18 ++---
  .../gpu/drm/i915/display/intel_frontbuffer.h  | 27 ---
  drivers/gpu/drm/i915/gem/i915_gem_object.c| 70 ++-
  drivers/gpu/drm/i915/gem/i915_gem_object.h|  6 ++
  drivers/gpu/drm/i915/i915_vma.c   |  2 +-
  5 files changed, 81 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c 
b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 3ce0436a0c7d..41ac65c98720 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -237,7 +237,7 @@ static void frontbuffer_release(struct kref *ref)
}
spin_unlock(>vma.lock);
  
-	RCU_INIT_POINTER(obj->frontbuffer, NULL);

+   i915_gem_object_set_frontbuffer(obj, NULL);
spin_unlock(_bo_to_i915(obj)->display.fb_tracking.lock);
  
  	i915_active_fini(>write);

@@ -250,9 +250,9 @@ struct intel_frontbuffer *
  intel_frontbuffer_get(struct drm_i915_gem_object *obj)
  {
struct drm_i915_private *i915 = intel_bo_to_i915(obj);
-   struct intel_frontbuffer *front;
+   struct intel_frontbuffer *front, *front_ret;
  
-	front = __intel_frontbuffer_get(obj);

+   front = i915_gem_object_get_frontbuffer(obj);
if (front)
return front;
  
@@ -269,16 +269,10 @@ intel_frontbuffer_get(struct drm_i915_gem_object *obj)

 I915_ACTIVE_RETIRE_SLEEPS);
  
  	spin_lock(>display.fb_tracking.lock);

-   if (rcu_access_pointer(obj->frontbuffer)) {
-   kfree(front);
-   front = rcu_dereference_protected(obj->frontbuffer, true);
-   kref_get(>ref);
-   } else {
-   i915_gem_object_get(obj);
-   rcu_assign_pointer(obj->frontbuffer, front);
-   }
+   front_ret = i915_gem_object_set_frontbuffer(obj, front);
spin_unlock(>display.fb_tracking.lock);
-
+   if (front_ret != front)
+   kfree(front);
return front;



Should be "return front_ret" here or better s/front_ret/cur/


  }
  
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.h b/drivers/gpu/drm/i915/display/intel_frontbuffer.h

index 3c474ed937fb..eeccc847331d 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.h
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.h
@@ -75,33 +75,6 @@ void intel_frontbuffer_flip(struct drm_i915_private *i915,
  
  void intel_frontbuffer_put(struct intel_frontbuffer *front);
  
-static inline struct intel_frontbuffer *

-__intel_frontbuffer_get(const struct drm_i915_gem_object *obj)
-{
-   struct intel_frontbuffer *front;
-
-   if (likely(!rcu_access_pointer(obj->frontbuffer)))
-   return NULL;
-
-   rcu_read_lock();
-   do {
-   front = rcu_dereference(obj->frontbuffer);
-   if (!front)
-   break;
-
-   if (unlikely(!kref_get_unless_zero(>ref)))
-   continue;
-
-   if (likely(front == rcu_access_pointer(obj->frontbuffer)))
-   break;
-
-   intel_frontbuffer_put(front);
-   } while (1);
-   rcu_read_unlock();
-
-   return front;
-}
-
  struct intel_frontbuffer *
  intel_frontbuffer_get(struct drm_i915_gem_object *obj);
  
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c

index 46a19b099ec8..6945e903e106 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -463,7 +463,7 @@ void __i915_gem_object_flush_frontbuffer(struct 
drm_i915_gem_object *obj,
  {
struct intel_frontbuffer *front;
  
-	front = __intel_frontbuffer_get(obj);

+   front = i915_gem_object_get_frontbuffer(obj);
if (front) {
intel_frontbuffer_flush(front, origin);
intel_frontbuffer_put(front);
@@ -475,7 +475,7 @@ void __i915_gem_object_invalidate_frontbuffer(struct 
drm_i915_gem_object *obj,
  {
struct intel_frontbuffer *front;
  
-	front = __intel_frontbuffer_get(obj);

+   front = i915_gem_object_get_frontbuffer(obj);
if (front) {
intel_frontbuffer_invalidate(front, origin);
intel_frontbuffer_put(front);
@@ -952,6 +952,72 @@ bool i915_gem_object_has_unknown_state(struct 
drm_i915_gem_object *obj)
return obj->mm.unknown_state;
  }
  
+/**

+ * i915_gem_object_get_frontbuffer - Get the object's frontbuffer
+ * @obj: The object whose frontbuffer to get.
+ *
+ * Get pointer to object's frontbuffer if such exists. Please note that RCU
+ * mechanism is used to handle e.g. ongoing removal of frontbuffer pointer.
+ *
+ * Return: pointer to 

Re: [Intel-gfx] [PATCH v15 00/26] Add vfio_device cdev for iommufd support

[Jason Gunthorpe]

On Tue, Jul 25, 2023 at 12:00:09PM -0600, Alex Williamson wrote:
> On Mon, 24 Jul 2023 13:09:22 -0600
> Alex Williamson  wrote:
> 
> > On Tue, 18 Jul 2023 13:57:46 -0300
> > Jason Gunthorpe  wrote:
> > 
> > > On Tue, Jul 18, 2023 at 06:55:25AM -0700, Yi Liu wrote:  
> > > > Existing VFIO provides group-centric user APIs for userspace. Userspace
> > > > opens the /dev/vfio/$group_id first before getting device fd and hence
> > > > getting access to device. This is not the desired model for iommufd. Per
> > > > the conclusion of community discussion[1], iommufd provides 
> > > > device-centric
> > > > kAPIs and requires its consumer (like VFIO) to be device-centric user
> > > > APIs. Such user APIs are used to associate device with iommufd and also
> > > > the I/O address spaces managed by the iommufd.
> > > > 
> > > > This series first introduces a per device file structure to be prepared
> > > > for further enhancement and refactors the kvm-vfio code to be prepared
> > > > for accepting device file from userspace. After this, adds a mechanism 
> > > > for
> > > > blocking device access before iommufd bind. Then refactors the vfio to 
> > > > be
> > > > able to handle cdev paths (e.g. iommufd binding, no-iommufd, [de]attach 
> > > > ioas).
> > > > This refactor includes making the device_open exclusive between the 
> > > > group
> > > > and the cdev path, only allow single device open in cdev path; 
> > > > vfio-iommufd
> > > > code is also refactored to support cdev. e.g. split the 
> > > > vfio_iommufd_bind()
> > > > into two steps. Eventually, adds the cdev support for vfio device and 
> > > > the
> > > > new ioctls, then makes group infrastructure optional as it is not needed
> > > > when vfio device cdev is compiled.
> > > > 
> > > > This series is based on some preparation works done to vfio emulated 
> > > > devices[2]
> > > > and vfio pci hot reset enhancements[3]. Per discussion[4], this series 
> > > > does not
> > > > support cdev for physical devices that do not have IOMMU. Such devices 
> > > > only
> > > > have group-centric user APIs.
> > > > 
> > > > This series is a prerequisite for iommu nesting for vfio device[5] [6].
> > > > 
> > > > The complete code can be found in below branch, simple tests done to the
> > > > legacy group path and the cdev path. QEMU changes are in upstreaming[7]
> > > > and the complete code can be found at[8]
> > > > 
> > > > https://github.com/yiliu1765/iommufd/tree/vfio_device_cdev_v15
> > > > (config CONFIG_IOMMUFD=y CONFIG_VFIO_DEVICE_CDEV=y)
> > > 
> > > Alex, if you are still good with this lets make this into a shared
> > > branch, do you want to do it or would you like a PR from me?  
> > 
> > Sorry, was out much of last week.  Yes, my intent would be to put this
> > both in a shared branch and my next branch for v6.6.  Given this is
> > mostly vfio, it seems like it'd make sense for me to provide that
> > branch but I may not get to it until tomorrow.  Thanks,
> 
> Both series are applied to my next branch for v6.6 and I've also
> published them to the v6.6/vfio/cdev branch[1].  Thanks for all the
> work and collaboration on this effort!

Great, I pulled it and merged the next series

Thanks,
Jason

Re: [Intel-gfx] [PATCH] drm/i915: Do not disable preemption for resets

[Sebastian Andrzej Siewior]

On 2023-07-05 10:30:25 [+0100], Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Commit ade8a0f59844 ("drm/i915: Make all GPU resets atomic") added a
> preempt disable section over the hardware reset callback to prepare the
> driver for being able to reset from atomic contexts.
> 
…

This looks like what I tested previously. So

Acked-by: Sebastian Andrzej Siewior 

Thank you.

> Signed-off-by: Tvrtko Ursulin 
> Cc: Chris Wilson 
> Cc: Paul Gortmaker 
> Cc: Sebastian Andrzej Siewior 

Sebastian

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use the i915_vma_flush_writes helper (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Use the i915_vma_flush_writes helper (rev6)
URL   : https://patchwork.freedesktop.org/series/121122/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13423_full -> Patchwork_121122v6_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_121122v6_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_fdinfo@virtual-busy-hang-all:
- shard-mtlp: NOTRUN -> [SKIP][1] ([i915#8414])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-mtlp-2/igt@drm_fdi...@virtual-busy-hang-all.html

  * igt@gem_ccs@block-copy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][2] ([i915#5325])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-mtlp-6/igt@gem_...@block-copy-compressed.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-dg1:  [PASS][3] -> [FAIL][4] ([fdo#103375]) +3 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-dg1-13/igt@gem_ctx_isolation@preservation...@vcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-dg1-13/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-snb1/igt@gem_ctx_persiste...@legacy-engines-queued.html

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-mtlp: [PASS][6] -> [ABORT][7] ([i915#7941])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-mtlp-3/igt@gem_...@in-flight-contexts-10ms.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-mtlp-5/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_eio@unwedge-stress:
- shard-dg2:  [PASS][8] -> [FAIL][9] ([i915#5784])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-dg2-5/igt@gem_...@unwedge-stress.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-dg2-5/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl:  [PASS][10] -> [FAIL][11] ([i915#2842]) +3 similar 
issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-rkl-1/igt@gem_exec_fair@basic-n...@bcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-rkl-7/igt@gem_exec_fair@basic-n...@bcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#3281])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-mtlp-6/igt@gem_exec_re...@basic-gtt-cpu-noreloc.html

  * igt@gem_exec_schedule@preempt-queue-chain:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#4812]) +1 similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-mtlp-7/igt@gem_exec_sched...@preempt-queue-chain.html

  * igt@gem_lmem_swapping@parallel-multi:
- shard-glk:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-glk8/igt@gem_lmem_swapp...@parallel-multi.html

  * igt@gem_lmem_swapping@random-engines:
- shard-mtlp: NOTRUN -> [SKIP][16] ([i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-mtlp-2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_mmap_gtt@coherency:
- shard-mtlp: NOTRUN -> [SKIP][17] ([i915#4077]) +2 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-mtlp-6/igt@gem_mmap_...@coherency.html

  * igt@gem_pread@exhaustion:
- shard-glk:  NOTRUN -> [WARN][18] ([i915#2658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-glk8/igt@gem_pr...@exhaustion.html

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-mtlp: NOTRUN -> [SKIP][19] ([i915#4270])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-mtlp-6/igt@gem_...@protected-encrypted-src-copy-not-readible.html

  * igt@gem_readwrite@new-obj:
- shard-mtlp: NOTRUN -> [SKIP][20] ([i915#3282])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/shard-mtlp-6/igt@gem_readwr...@new-obj.html

  * igt@gen9_exec_parse@bb-oversize:
- shard-dg2:  NOTRUN -> [SKIP][21] ([i915#2856])
   [21]: 

[Intel-gfx] [PATCH v4 1/5] arm64/smmu: Use TLBI ASID when invalidating entire range

[Alistair Popple]

The ARM SMMU has a specific command for invalidating the TLB for an
entire ASID. Currently this is used for the IO_PGTABLE API but not for
ATS when called from the MMU notifier.

The current implementation of notifiers does not attempt to invalidate
such a large address range, instead walking each VMA and invalidating
each range individually during mmap removal. However in future SMMU
TLB invalidations are going to be sent as part of the normal
flush_tlb_*() kernel calls. To better deal with that add handling to
use TLBI ASID when invalidating the entire address space.

Signed-off-by: Alistair Popple 
Reviewed-by: Jason Gunthorpe 
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c 
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
index a5a63b1..2a19784 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
@@ -200,10 +200,20 @@ static void arm_smmu_mm_invalidate_range(struct 
mmu_notifier *mn,
 * range. So do a simple translation here by calculating size correctly.
 */
size = end - start;
+   if (size == ULONG_MAX)
+   size = 0;
+
+   if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM)) {
+   if (!size)
+   arm_smmu_tlb_inv_asid(smmu_domain->smmu,
+ smmu_mn->cd->asid);
+   else
+   arm_smmu_tlb_inv_range_asid(start, size,
+   smmu_mn->cd->asid,
+   PAGE_SIZE, false,
+   smmu_domain);
+   }
 
-   if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM))
-   arm_smmu_tlb_inv_range_asid(start, size, smmu_mn->cd->asid,
-   PAGE_SIZE, false, smmu_domain);
arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, start, size);
 }
 
-- 
git-series 0.9.1

[Intel-gfx] [PATCH v4 2/5] mmu_notifiers: Fixup comment in mmu_interval_read_begin()

[Alistair Popple]

The comment in mmu_interval_read_begin() refers to a function that
doesn't exist and uses the wrong call-back name. The op for mmu
interval notifiers is mmu_interval_notifier_ops->invalidate() so fix
the comment up to reflect that.

Signed-off-by: Alistair Popple 
Reviewed-by: Jason Gunthorpe 
---
 mm/mmu_notifier.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
index 50c0dde..b7ad155 100644
--- a/mm/mmu_notifier.c
+++ b/mm/mmu_notifier.c
@@ -199,7 +199,7 @@ mmu_interval_read_begin(struct mmu_interval_notifier 
*interval_sub)
 * invalidate_start/end and is colliding.
 *
 * The locking looks broadly like this:
-*   mn_tree_invalidate_start():  mmu_interval_read_begin():
+*   mn_itree_inv_start(): mmu_interval_read_begin():
 * spin_lock
 *  seq = 
READ_ONCE(interval_sub->invalidate_seq);
 *  seq == subs->invalidate_seq
@@ -207,7 +207,7 @@ mmu_interval_read_begin(struct mmu_interval_notifier 
*interval_sub)
 *spin_lock
 * seq = ++subscriptions->invalidate_seq
 *spin_unlock
-* op->invalidate_range():
+* op->invalidate():
 *   user_lock
 *mmu_interval_set_seq()
 * interval_sub->invalidate_seq = seq
-- 
git-series 0.9.1

[Intel-gfx] [PATCH v4 5/5] mmu_notifiers: Rename invalidate_range notifier

[Alistair Popple]

There are two main use cases for mmu notifiers. One is by KVM which
uses mmu_notifier_invalidate_range_start()/end() to manage a software
TLB.

The other is to manage hardware TLBs which need to use the
invalidate_range() callback because HW can establish new TLB entries
at any time. Hence using start/end() can lead to memory corruption as
these callbacks happen too soon/late during page unmap.

mmu notifier users should therefore either use the start()/end()
callbacks or the invalidate_range() callbacks. To make this usage
clearer rename the invalidate_range() callback to
arch_invalidate_secondary_tlbs() and update documention.

Signed-off-by: Alistair Popple 
Suggested-by: Jason Gunthorpe 
Acked-by: Catalin Marinas 
Reviewed-by: Jason Gunthorpe 
---
 arch/arm64/include/asm/tlbflush.h   |  6 +-
 arch/powerpc/mm/book3s64/radix_hugetlbpage.c|  2 +-
 arch/powerpc/mm/book3s64/radix_tlb.c|  8 +--
 arch/x86/include/asm/tlbflush.h |  2 +-
 arch/x86/mm/tlb.c   |  2 +-
 drivers/iommu/amd/iommu_v2.c| 10 ++--
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 13 ++---
 drivers/iommu/intel/svm.c   |  8 +--
 drivers/misc/ocxl/link.c|  8 +--
 include/linux/mmu_notifier.h| 48 +-
 mm/huge_memory.c|  4 +-
 mm/hugetlb.c|  7 +--
 mm/mmu_notifier.c   | 21 ++--
 13 files changed, 76 insertions(+), 63 deletions(-)

diff --git a/arch/arm64/include/asm/tlbflush.h 
b/arch/arm64/include/asm/tlbflush.h
index a99349d..84a05a0 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -253,7 +253,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
__tlbi(aside1is, asid);
__tlbi_user(aside1is, asid);
dsb(ish);
-   mmu_notifier_invalidate_range(mm, 0, -1UL);
+   mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);
 }
 
 static inline void __flush_tlb_page_nosync(struct mm_struct *mm,
@@ -265,7 +265,7 @@ static inline void __flush_tlb_page_nosync(struct mm_struct 
*mm,
addr = __TLBI_VADDR(uaddr, ASID(mm));
__tlbi(vale1is, addr);
__tlbi_user(vale1is, addr);
-   mmu_notifier_invalidate_range(mm, uaddr & PAGE_MASK,
+   mmu_notifier_arch_invalidate_secondary_tlbs(mm, uaddr & PAGE_MASK,
(uaddr & PAGE_MASK) + 
PAGE_SIZE);
 }
 
@@ -400,7 +400,7 @@ static inline void __flush_tlb_range(struct vm_area_struct 
*vma,
scale++;
}
dsb(ish);
-   mmu_notifier_invalidate_range(vma->vm_mm, start, end);
+   mmu_notifier_arch_invalidate_secondary_tlbs(vma->vm_mm, start, end);
 }
 
 static inline void flush_tlb_range(struct vm_area_struct *vma,
diff --git a/arch/powerpc/mm/book3s64/radix_hugetlbpage.c 
b/arch/powerpc/mm/book3s64/radix_hugetlbpage.c
index f3fb49f..17075c7 100644
--- a/arch/powerpc/mm/book3s64/radix_hugetlbpage.c
+++ b/arch/powerpc/mm/book3s64/radix_hugetlbpage.c
@@ -39,7 +39,7 @@ void radix__flush_hugetlb_tlb_range(struct vm_area_struct 
*vma, unsigned long st
radix__flush_tlb_pwc_range_psize(vma->vm_mm, start, end, psize);
else
radix__flush_tlb_range_psize(vma->vm_mm, start, end, psize);
-   mmu_notifier_invalidate_range(vma->vm_mm, start, end);
+   mmu_notifier_arch_invalidate_secondary_tlbs(vma->vm_mm, start, end);
 }
 
 void radix__huge_ptep_modify_prot_commit(struct vm_area_struct *vma,
diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c 
b/arch/powerpc/mm/book3s64/radix_tlb.c
index 4d44902..06e647e 100644
--- a/arch/powerpc/mm/book3s64/radix_tlb.c
+++ b/arch/powerpc/mm/book3s64/radix_tlb.c
@@ -987,7 +987,7 @@ void radix__flush_tlb_mm(struct mm_struct *mm)
}
}
preempt_enable();
-   mmu_notifier_invalidate_range(mm, 0, -1UL);
+   mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);
 }
 EXPORT_SYMBOL(radix__flush_tlb_mm);
 
@@ -1021,7 +1021,7 @@ static void __flush_all_mm(struct mm_struct *mm, bool 
fullmm)
_tlbiel_pid_multicast(mm, pid, RIC_FLUSH_ALL);
}
preempt_enable();
-   mmu_notifier_invalidate_range(mm, 0, -1UL);
+   mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);
 }
 
 void radix__flush_all_mm(struct mm_struct *mm)
@@ -1230,7 +1230,7 @@ static inline void __radix__flush_tlb_range(struct 
mm_struct *mm,
}
 out:
preempt_enable();
-   mmu_notifier_invalidate_range(mm, start, end);
+   mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, end);
 }
 
 void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
@@ -1395,7 +1395,7 @@ static void __radix__flush_tlb_range_psize(struct 
mm_struct *mm,
}
 out:
preempt_enable();
-   mmu_notifier_invalidate_range(mm, start, 

Re: [Intel-gfx] [PATCH v2] drm/i915/tv: avoid possible division by zero

[Su Hui]

On 2023/7/25 13:51, Dan Carpenter wrote:

The reason why the first five attempts had bugs is because we are
trying to write it in the most complicated way possible, shifting by
logical not what?

Wonderful! Should I add your name as signed-of-by?
I will send a v3 patch later.
Really thanks for your help!

Su Hui


regards,
dan carpenter

diff --git a/drivers/gpu/drm/i915/display/intel_tv.c 
b/drivers/gpu/drm/i915/display/intel_tv.c
index 36b479b46b60..6997b6cb1df2 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -988,7 +988,13 @@ intel_tv_mode_to_mode(struct drm_display_mode *mode,
  const struct tv_mode *tv_mode,
  int clock)
  {
-   mode->clock = clock / (tv_mode->oversample >> !tv_mode->progressive);
+   int div = tv_mode->oversample;
+
+   if (!tv_mode->progressive)
+   div >>= 1;
+   if (div == 0)
+   div = 1;
+   mode->clock = clock / div;
  
  	/*

 * tv_mode horizontal timings:
@@ -1135,6 +1141,8 @@ intel_tv_get_config(struct intel_encoder *encoder,
break;
default:
tv_mode.oversample = 1;
+   WARN_ON_ONCE(!tv_mode.progressive);
+   tv_mode.progressive = true;
break;
}
  

Re: [Intel-gfx] Regression in linux-next

[Alistair Popple]

Thanks Chaitanya for the detailed report. Dan Carpenter also reported a
Smatch warning for this:

https://lore.kernel.org/linux-mm/38ed0627-1283-4da2-827a-e90484d7bd7d@moroto.mountain/

The below should fix the problem, will respin the series to include the
fix.

---

diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
index 63c8eb740af7..ec3b068cbbe6 100644
--- a/mm/mmu_notifier.c
+++ b/mm/mmu_notifier.c
@@ -621,9 +621,10 @@ int __mmu_notifier_register(struct mmu_notifier 
*subscription,
 * Subsystems should only register for invalidate_secondary_tlbs() or
 * invalidate_range_start()/end() callbacks, not both.
 */
-   if (WARN_ON_ONCE(subscription->ops->arch_invalidate_secondary_tlbs &&
-   (subscription->ops->invalidate_range_start ||
-   subscription->ops->invalidate_range_end)))
+   if (WARN_ON_ONCE(subscription &&
+(subscription->ops->arch_invalidate_secondary_tlbs &&
+(subscription->ops->invalidate_range_start ||
+ subscription->ops->invalidate_range_end
return -EINVAL;
 
if (!mm->notifier_subscriptions) {


"Borah, Chaitanya Kumar"  writes:

> Hello Alistair,
>
> Hope you are doing well. I am Chaitanya from the linux graphics team in Intel.
>  
> This mail is regarding a regression we are seeing in our CI runs[1] on 
> linux-next
> repository.
>  
> On next-20230720 [2], we are seeing the following error
>
> <4>[   76.189375] Hardware name: Intel Corporation Meteor Lake Client 
> Platform/MTL-P DDR5 SODIMM SBS RVP, BIOS MTLPFWI1.R00.3271.D81.2307101805 
> 07/10/2023
> <4>[   76.202534] RIP: 0010:__mmu_notifier_register+0x40/0x210
> <4>[ 76.207804] Code: 1a 71 5a 01 85 c0 0f 85 ec 00 00 00 48 8b 85 30
> 01 00 00 48 85 c0 0f 84 04 01 00 00 8b 85 cc 00 00 00 85 c0 0f 8e bb
> 01 00 00 <49> 8b 44 24 10 48 83 78 38 00 74 1a 48 83 78 28 00 74 0c 0f
> 0b b8
> <4>[   76.226368] RSP: 0018:c900019d7ca8 EFLAGS: 00010202
> <4>[   76.231549] RAX: 0001 RBX: 1000 RCX: 
> 0001
> <4>[   76.238613] RDX:  RSI: 823ceb7b RDI: 
> 823ee12d
> <4>[   76.245680] RBP: 888102ec9b40 R08:  R09: 
> 0001
> <4>[   76.252747] R10: 0001 R11: 8881157cd2c0 R12: 
> 
> <4>[   76.259811] R13: 888102ec9c70 R14: a07de500 R15: 
> 888102ec9ce0
> <4>[   76.266875] FS:  7fbcabe11c00() GS:88846ec0() 
> knlGS:
> <4>[   76.274884] CS:  0010 DS:  ES:  CR0: 80050033
> <4>[   76.280578] CR2: 0010 CR3: 00010d4c2005 CR4: 
> 00f70ee0
> <4>[   76.287643] DR0:  DR1:  DR2: 
> 
> <4>[   76.294711] DR3:  DR6: 07f0 DR7: 
> 0400
> <4>[   76.301775] PKRU: 5554
> <4>[   76.304463] Call Trace:
> <4>[   76.306893]  
> <4>[   76.308983]  ? __die_body+0x1a/0x60
> <4>[   76.312444]  ? page_fault_oops+0x156/0x450
> <4>[   76.316510]  ? do_user_addr_fault+0x65/0x980
> <4>[   76.320747]  ? exc_page_fault+0x68/0x1a0
> <4>[   76.324643]  ? asm_exc_page_fault+0x26/0x30
> <4>[   76.328796]  ? __mmu_notifier_register+0x40/0x210
> <4>[   76.333460]  ? __mmu_notifier_register+0x11c/0x210
> <4>[   76.338206]  ? preempt_count_add+0x4c/0xa0
> <4>[   76.342273]  mmu_notifier_register+0x30/0xe0
> <4>[   76.346509]  mmu_interval_notifier_insert+0x74/0xb0
> <4>[   76.351344]  i915_gem_userptr_ioctl+0x21a/0x320 [i915]
> <4>[   76.356565]  ? __pfx_i915_gem_userptr_ioctl+0x10/0x10 [i915]
> <4>[   76.362271]  drm_ioctl_kernel+0xb4/0x150
> <4>[   76.366159]  drm_ioctl+0x21d/0x420
> <4>[   76.369537]  ? __pfx_i915_gem_userptr_ioctl+0x10/0x10 [i915]
> <4>[   76.375242]  ? find_held_lock+0x2b/0x80
> <4>[   76.379046]  __x64_sys_ioctl+0x79/0xb0
> <4>[   76.382766]  do_syscall_64+0x3c/0x90
> <4>[   76.386312]  entry_SYSCALL_64_after_hwframe+0x6e/0xd8
> <4>[   76.391317] RIP: 0033:0x7fbcae63f3ab
>
> Details log can be found in [3].
>
> After bisecting the tree, the following patch seems to be causing the
> regression.
>
> commit 828fe4085cae77acb3abf7dd3d25b3ed6c560edf
> Author: Alistair Popple apop...@nvidia.com
> Date:   Wed Jul 19 22:18:46 2023 +1000
>
> mmu_notifiers: rename invalidate_range notifier
>
> There are two main use cases for mmu notifiers.  One is by KVM which uses
> mmu_notifier_invalidate_range_start()/end() to manage a software TLB.
>
> The other is to manage hardware TLBs which need to use the
> invalidate_range() callback because HW can establish new TLB entries at
> any time.  Hence using start/end() can lead to memory corruption as these
> callbacks happen too soon/late during page unmap.
>
> mmu notifier users should therefore either use the start()/end() callbacks
> or the invalidate_range() callbacks.  To make this usage clearer 

Re: [Intel-gfx] [PATCH v2] drm/i915/tv: avoid possible division by zero

[Su Hui]

On 2023/7/25 01:35, Andi Shyti wrote:

On Tue, Jul 18, 2023 at 09:32:17AM +0800, Su Hui wrote:

Clang warning: drivers/gpu/drm/i915/display/intel_tv.c:
line 991, column 22 Division by zero.
Assuming tv_mode->oversample=1 and (!tv_mode->progressive)=1,
then division by zero will happen.

Fixes: 1bba5543e4fe ("drm/i915: Fix TV encoder clock computation")
Signed-off-by: Su Hui 
---
  drivers/gpu/drm/i915/display/intel_tv.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_tv.c 
b/drivers/gpu/drm/i915/display/intel_tv.c
index 36b479b46b60..f59553f7c132 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -988,7 +988,7 @@ intel_tv_mode_to_mode(struct drm_display_mode *mode,
  const struct tv_mode *tv_mode,
  int clock)
  {
-   mode->clock = clock / (tv_mode->oversample >> !tv_mode->progressive);
+   mode->clock = clock / tv_mode->oversample << !tv_mode->progressive;

but this does not provide the same value. Try with:

8 / (2 >> 1)

and

8 / 2 << 1

They are definitely different.

The real check could be:

if (!(tv_mode->oversample >> 1))
return ...

But first I would check if that's actually possible.


Oh, I have a v3 patch, like this:

-   mode->clock = clock / (tv_mode->oversample >> 
!tv_mode->progressive);

+   mode->clock = clock;
+   if (tv_mode->oversample >> !tv_mode->progressive)
+   mode->clock /= tv_mode->oversample >> 1;

But I'm not sure does it need to print some error messages or do some 
things  when

"tv_mode->oversample << !tv_mode->progressive" is zero?
If all right , I will send this v3 patch.

Su Hui


Andi

[Intel-gfx] [PATCH v4 0/5] Invalidate secondary IOMMU TLB on permission upgrade

[Alistair Popple]

The main change is to move secondary TLB invalidation mmu notifier
callbacks into the architecture specific TLB flushing functions. This
makes secondary TLB invalidation mostly match CPU invalidation while
still allowing efficient range based invalidations based on the
existing TLB batching code.

Changes for v4:

 - Fixed a NULL pointer dereference when registering the first
   notifier with mmu_interval_notifier_insert() instead of
   mmu_notifier_register() - Thanks Dan and Chaitanya for the bug
   reports.

 - Collected Acked/Reviewed tags.

 - Don't call the notifier from radix__local_flush_tlb_page() on
   PowerPC.

Changes for v3:

 - On x86 call the invalidation when adding pending TLB invalidates
   rather than when flushing the batch. This is because the mm is
   required. It also matches what happens on ARM64. Fixes a bug
   reported by SeongJae Park (thanks!)

Changes for v2:

 - Rebased on linux-next commit 906fa30154ef ("mm/rmap: correct stale
   comment of rmap_walk_anon and rmap_walk_file") to fix a minor
   integration conflict with "arm64: support batched/deferred tlb
   shootdown during page reclamation/migration". This series will need
   to be applied after the conflicting patch.

 - Reordered the function rename until the end of the series as many
   places that were getting renamed ended up being removed anyway.

 - Fixed a couple of build issues which broke bisection.

 - Added a minor patch to fix up a stale/incorrect comment.

==
Background
==

The arm64 architecture specifies TLB permission bits may be cached and
therefore the TLB must be invalidated during permission upgrades. For
the CPU this currently occurs in the architecture specific
ptep_set_access_flags() routine.

Secondary TLBs such as implemented by the SMMU IOMMU match the CPU
architecture specification and may also cache permission bits and
require the same TLB invalidations. This may be achieved in one of two
ways.

Some SMMU implementations implement broadcast TLB maintenance
(BTM). This snoops CPU TLB invalidates and will invalidate any
secondary TLB at the same time as the CPU. However implementations are
not required to implement BTM.

Implementations without BTM rely on mmu notifier callbacks to send
explicit TLB invalidation commands to invalidate SMMU TLB. Therefore
either generic kernel code or architecture specific code needs to call
the mmu notifier on permission upgrade.

Currently that doesn't happen so devices will fault indefinitely when
writing to a PTE that was previously read-only as nothing invalidates
the SMMU TLB.


Solution


To fix this the series first renames the .invalidate_range() callback
to .arch_invalidate_secondary_tlbs() as suggested by Jason and Sean to
make it clear this callback is only used for secondary TLBs. That was
made possible thanks to Sean's series [1] to remove KVM's incorrect
usage.

Based on feedback from Jason [2] the proposed solution to the bug is
to move the calls to mmu_notifier_arch_invalidate_secondary_tlbs()
closer to the architecture specific TLB invalidation code. This
ensures the secondary TLB won't miss invalidations, including the
existing invalidation in the ARM64 code to deal with permission
upgrade.

Currently only ARM64, PowerPC and x86 have IOMMU with secondary TLBs
requiring SW invalidation so the notifier is only called for those
architectures. It is also not called for invalidation of kernel
mappings as no secondary IOMMU implementations can access those and
hence it is not required.

[1] - https://lore.kernel.org/all/20230602011518.787006-1-sea...@google.com/
[2] - https://lore.kernel.org/linux-mm/zjmr5bw8l+bbz...@ziepe.ca/

Alistair Popple (5):
  arm64/smmu: Use TLBI ASID when invalidating entire range
  mmu_notifiers: Fixup comment in mmu_interval_read_begin()
  mmu_notifiers: Call invalidate_range() when invalidating TLBs
  mmu_notifiers: Don't invalidate secondary TLBs as part of 
mmu_notifier_invalidate_range_end()
  mmu_notifiers: Rename invalidate_range notifier

 arch/arm64/include/asm/tlbflush.h   |   5 +-
 arch/powerpc/include/asm/book3s/64/tlbflush.h   |   1 +-
 arch/powerpc/mm/book3s64/radix_hugetlbpage.c|   1 +-
 arch/powerpc/mm/book3s64/radix_tlb.c|   4 +-
 arch/x86/include/asm/tlbflush.h |   2 +-
 arch/x86/mm/tlb.c   |   2 +-
 drivers/iommu/amd/iommu_v2.c|  10 +-
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c |  29 +++--
 drivers/iommu/intel/svm.c   |   8 +-
 drivers/misc/ocxl/link.c|   8 +-
 include/asm-generic/tlb.h   |   1 +-
 include/linux/mmu_notifier.h| 104 -
 kernel/events/uprobes.c |   2 +-
 mm/huge_memory.c|  29 +
 mm/hugetlb.c|   8 +-
 mm/memory.c |   8 +-
 

[Intel-gfx] [PATCH v4 4/5] mmu_notifiers: Don't invalidate secondary TLBs as part of mmu_notifier_invalidate_range_end()

[Alistair Popple]

Secondary TLBs are now invalidated from the architecture specific TLB
invalidation functions. Therefore there is no need to explicitly
notify or invalidate as part of the range end functions. This means we
can remove mmu_notifier_invalidate_range_end_only() and some of the
ptep_*_notify() functions.

Signed-off-by: Alistair Popple 
Reviewed-by: Jason Gunthorpe 
---
 include/linux/mmu_notifier.h | 56 +
 kernel/events/uprobes.c  |  2 +-
 mm/huge_memory.c | 25 ++---
 mm/hugetlb.c |  1 +-
 mm/memory.c  |  8 +
 mm/migrate_device.c  |  9 +-
 mm/mmu_notifier.c| 25 ++---
 mm/rmap.c| 40 +--
 8 files changed, 14 insertions(+), 152 deletions(-)

diff --git a/include/linux/mmu_notifier.h b/include/linux/mmu_notifier.h
index 64a3e05..f2e9edc 100644
--- a/include/linux/mmu_notifier.h
+++ b/include/linux/mmu_notifier.h
@@ -395,8 +395,7 @@ extern int __mmu_notifier_test_young(struct mm_struct *mm,
 extern void __mmu_notifier_change_pte(struct mm_struct *mm,
  unsigned long address, pte_t pte);
 extern int __mmu_notifier_invalidate_range_start(struct mmu_notifier_range *r);
-extern void __mmu_notifier_invalidate_range_end(struct mmu_notifier_range *r,
- bool only_end);
+extern void __mmu_notifier_invalidate_range_end(struct mmu_notifier_range *r);
 extern void __mmu_notifier_invalidate_range(struct mm_struct *mm,
  unsigned long start, unsigned long end);
 extern bool
@@ -481,14 +480,7 @@ mmu_notifier_invalidate_range_end(struct 
mmu_notifier_range *range)
might_sleep();
 
if (mm_has_notifiers(range->mm))
-   __mmu_notifier_invalidate_range_end(range, false);
-}
-
-static inline void
-mmu_notifier_invalidate_range_only_end(struct mmu_notifier_range *range)
-{
-   if (mm_has_notifiers(range->mm))
-   __mmu_notifier_invalidate_range_end(range, true);
+   __mmu_notifier_invalidate_range_end(range);
 }
 
 static inline void mmu_notifier_invalidate_range(struct mm_struct *mm,
@@ -582,45 +574,6 @@ static inline void mmu_notifier_range_init_owner(
__young;\
 })
 
-#defineptep_clear_flush_notify(__vma, __address, __ptep)   
\
-({ \
-   unsigned long ___addr = __address & PAGE_MASK;  \
-   struct mm_struct *___mm = (__vma)->vm_mm;   \
-   pte_t ___pte;   \
-   \
-   ___pte = ptep_clear_flush(__vma, __address, __ptep);\
-   mmu_notifier_invalidate_range(___mm, ___addr,   \
-   ___addr + PAGE_SIZE);   \
-   \
-   ___pte; \
-})
-
-#define pmdp_huge_clear_flush_notify(__vma, __haddr, __pmd)\
-({ \
-   unsigned long ___haddr = __haddr & HPAGE_PMD_MASK;  \
-   struct mm_struct *___mm = (__vma)->vm_mm;   \
-   pmd_t ___pmd;   \
-   \
-   ___pmd = pmdp_huge_clear_flush(__vma, __haddr, __pmd);  \
-   mmu_notifier_invalidate_range(___mm, ___haddr,  \
- ___haddr + HPAGE_PMD_SIZE);   \
-   \
-   ___pmd; \
-})
-
-#define pudp_huge_clear_flush_notify(__vma, __haddr, __pud)\
-({ \
-   unsigned long ___haddr = __haddr & HPAGE_PUD_MASK;  \
-   struct mm_struct *___mm = (__vma)->vm_mm;   \
-   pud_t ___pud;   \
-   \
-   ___pud = pudp_huge_clear_flush(__vma, __haddr, __pud);  \
-   mmu_notifier_invalidate_range(___mm, ___haddr,  \
- ___haddr + HPAGE_PUD_SIZE);   \
-   \
-   ___pud; \
-})
-
 /*
  * set_pte_at_notify() sets the pte _after_ running the notifier.
  * This is safe to start by updating the secondary MMUs, because the 

Re: [Intel-gfx] [PATCH v6 3/4] drm: Expand max DRM device number to full MINORBITS

[James Zhu]

On 2023-07-24 17:14, Michał Winiarski wrote:

Having a limit of 64 DRM devices is not good enough for modern world
where we have multi-GPU servers, SR-IOV virtual functions and virtual
devices used for testing.
Let's utilize full minor range for DRM devices.
To avoid regressing the existing userspace, we're still maintaining the
numbering scheme where 0-63 is used for primary, 64-127 is reserved
(formerly for control) and 128-191 is used for render.
For minors >= 192, we're allocating minors dynamically on a first-come,
first-served basis.


[JZ] Hello Michal,

Do you have libdrm patches for review together with this change?

Especially to support static int drmGetMinorType(int major, int minor).

Thanks and Best Regards!

James Zhu



Signed-off-by: Michał Winiarski
---
  drivers/gpu/drm/drm_drv.c | 12 
  1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 34b60196c443..c2c6e80e6b31 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -121,10 +121,19 @@ static void drm_minor_alloc_release(struct drm_device 
*dev, void *data)
xa_erase(drm_minor_get_xa(minor->type), minor->index);
  }
  
+/*

+ * DRM used to support 64 devices, for backwards compatibility we need to 
maintain the
+ * minor allocation scheme where minors 0-63 are primary nodes, 64-127 are 
control nodes,
+ * and 128-191 are render nodes.
+ * After reaching the limit, we're allocating minors dynamically - first-come, 
first-serve.
+ * Accel nodes are using a distinct major, so the minors are allocated in 
continuous 0-MAX
+ * range.
+ */
  #define DRM_MINOR_LIMIT(t) ({ \
typeof(t) _t = (t); \
_t == DRM_MINOR_ACCEL ? XA_LIMIT(0, ACCEL_MAX_MINORS) : XA_LIMIT(64 * 
_t, 64 * _t + 63); \
  })
+#define DRM_EXTENDED_MINOR_LIMIT XA_LIMIT(192, (1 << MINORBITS) - 1)
  
  static int drm_minor_alloc(struct drm_device *dev, enum drm_minor_type type)

  {
@@ -140,6 +149,9 @@ static int drm_minor_alloc(struct drm_device *dev, enum 
drm_minor_type type)
  
  	r = xa_alloc(drm_minor_get_xa(type), >index,

 NULL, DRM_MINOR_LIMIT(type), GFP_KERNEL);
+   if (r == -EBUSY && (type == DRM_MINOR_PRIMARY || type == 
DRM_MINOR_RENDER))
+   r = xa_alloc(_minors_xa, >index,
+NULL, DRM_EXTENDED_MINOR_LIMIT, GFP_KERNEL);
if (r < 0)
return r;
  

[Intel-gfx] [PATCH v4 3/5] mmu_notifiers: Call invalidate_range() when invalidating TLBs

[Alistair Popple]

The invalidate_range() is going to become an architecture specific mmu
notifier used to keep the TLB of secondary MMUs such as an IOMMU in
sync with the CPU page tables. Currently it is called from separate
code paths to the main CPU TLB invalidations. This can lead to a
secondary TLB not getting invalidated when required and makes it hard
to reason about when exactly the secondary TLB is invalidated.

To fix this move the notifier call to the architecture specific TLB
maintenance functions for architectures that have secondary MMUs
requiring explicit software invalidations.

This fixes a SMMU bug on ARM64. On ARM64 PTE permission upgrades
require a TLB invalidation. This invalidation is done by the
architecture specific ptep_set_access_flags() which calls
flush_tlb_page() if required. However this doesn't call the notifier
resulting in infinite faults being generated by devices using the SMMU
if it has previously cached a read-only PTE in it's TLB.

Moving the invalidations into the TLB invalidation functions ensures
all invalidations happen at the same time as the CPU invalidation. The
architecture specific flush_tlb_all() routines do not call the
notifier as none of the IOMMUs require this.

Signed-off-by: Alistair Popple 
Suggested-by: Jason Gunthorpe 
Tested-by: SeongJae Park 
Acked-by: Catalin Marinas 
Reviewed-by: Jason Gunthorpe 
---
 arch/arm64/include/asm/tlbflush.h | 5 +
 arch/powerpc/include/asm/book3s/64/tlbflush.h | 1 +
 arch/powerpc/mm/book3s64/radix_hugetlbpage.c  | 1 +
 arch/powerpc/mm/book3s64/radix_tlb.c  | 4 
 arch/x86/include/asm/tlbflush.h   | 2 ++
 arch/x86/mm/tlb.c | 2 ++
 include/asm-generic/tlb.h | 1 -
 7 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/tlbflush.h 
b/arch/arm64/include/asm/tlbflush.h
index 3456866..a99349d 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -252,6 +253,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
__tlbi(aside1is, asid);
__tlbi_user(aside1is, asid);
dsb(ish);
+   mmu_notifier_invalidate_range(mm, 0, -1UL);
 }
 
 static inline void __flush_tlb_page_nosync(struct mm_struct *mm,
@@ -263,6 +265,8 @@ static inline void __flush_tlb_page_nosync(struct mm_struct 
*mm,
addr = __TLBI_VADDR(uaddr, ASID(mm));
__tlbi(vale1is, addr);
__tlbi_user(vale1is, addr);
+   mmu_notifier_invalidate_range(mm, uaddr & PAGE_MASK,
+   (uaddr & PAGE_MASK) + 
PAGE_SIZE);
 }
 
 static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
@@ -396,6 +400,7 @@ static inline void __flush_tlb_range(struct vm_area_struct 
*vma,
scale++;
}
dsb(ish);
+   mmu_notifier_invalidate_range(vma->vm_mm, start, end);
 }
 
 static inline void flush_tlb_range(struct vm_area_struct *vma,
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h 
b/arch/powerpc/include/asm/book3s/64/tlbflush.h
index 0d0c144..dca0477 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h
@@ -5,6 +5,7 @@
 #define MMU_NO_CONTEXT ~0UL
 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/arch/powerpc/mm/book3s64/radix_hugetlbpage.c 
b/arch/powerpc/mm/book3s64/radix_hugetlbpage.c
index 5e31955..f3fb49f 100644
--- a/arch/powerpc/mm/book3s64/radix_hugetlbpage.c
+++ b/arch/powerpc/mm/book3s64/radix_hugetlbpage.c
@@ -39,6 +39,7 @@ void radix__flush_hugetlb_tlb_range(struct vm_area_struct 
*vma, unsigned long st
radix__flush_tlb_pwc_range_psize(vma->vm_mm, start, end, psize);
else
radix__flush_tlb_range_psize(vma->vm_mm, start, end, psize);
+   mmu_notifier_invalidate_range(vma->vm_mm, start, end);
 }
 
 void radix__huge_ptep_modify_prot_commit(struct vm_area_struct *vma,
diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c 
b/arch/powerpc/mm/book3s64/radix_tlb.c
index 0bd4866..4d44902 100644
--- a/arch/powerpc/mm/book3s64/radix_tlb.c
+++ b/arch/powerpc/mm/book3s64/radix_tlb.c
@@ -987,6 +987,7 @@ void radix__flush_tlb_mm(struct mm_struct *mm)
}
}
preempt_enable();
+   mmu_notifier_invalidate_range(mm, 0, -1UL);
 }
 EXPORT_SYMBOL(radix__flush_tlb_mm);
 
@@ -1020,6 +1021,7 @@ static void __flush_all_mm(struct mm_struct *mm, bool 
fullmm)
_tlbiel_pid_multicast(mm, pid, RIC_FLUSH_ALL);
}
preempt_enable();
+   mmu_notifier_invalidate_range(mm, 0, -1UL);
 }
 
 void radix__flush_all_mm(struct mm_struct *mm)
@@ -1228,6 +1230,7 @@ static inline void __radix__flush_tlb_range(struct 
mm_struct *mm,
}
 out:
preempt_enable();
+   mmu_notifier_invalidate_range(mm, start, end);
 }
 
 void radix__flush_tlb_range(struct vm_area_struct *vma, 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use the i915_vma_flush_writes helper (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Use the i915_vma_flush_writes helper (rev6)
URL   : https://patchwork.freedesktop.org/series/121122/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13423 -> Patchwork_121122v6


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/index.html

Participating hosts (43 -> 42)
--

  Additional (1): fi-kbl-soraka 
  Missing(2): bat-dg1-7 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_121122v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-cfl-8109u:   [PASS][3] -> [FAIL][4] ([i915#7940])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-cfl-8109u/igt@i915_pm_...@basic-pci-d3-state.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/fi-cfl-8109u/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
- fi-kbl-x1275:   [PASS][5] -> [FAIL][6] ([i915#8843])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-kbl-x1275/igt@i915_pm_...@basic-rte.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/fi-kbl-x1275/igt@i915_pm_...@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
- fi-rkl-11600:   [PASS][7] -> [FAIL][8] ([i915#7940])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-rkl-11600/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/fi-rkl-11600/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][9] -> [ABORT][10] ([i915#7911] / [i915#7913])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_mocs:
- bat-mtlp-8: [PASS][11] -> [DMESG-FAIL][12] ([i915#7059])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][13] ([i915#1886] / [i915#7913])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@migrate:
- bat-dg2-11: NOTRUN -> [DMESG-WARN][14] ([i915#7699])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/bat-dg2-11/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][15] ([i915#6367])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/bat-rpls-2/igt@i915_selftest@l...@slpc.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][16] ([i915#7828])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#7828])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][18] ([fdo#109271]) +15 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#1845] / [i915#5354]) +3 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-2: NOTRUN -> [SKIP][20] ([i915#1845])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v6/bat-rpls-2/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8700k:   [FAIL][21] ([i915#7940]) -> [PASS][22]
   [21]: 

Re: [Intel-gfx] [PATCH 16/17] cgroup/drm: Expose memory stats

[Tvrtko Ursulin]

On 26/07/2023 11:14, Maarten Lankhorst wrote:

Hey,

On 2023-07-22 00:21, Tejun Heo wrote:

On Wed, Jul 12, 2023 at 12:46:04PM +0100, Tvrtko Ursulin wrote:

   $ cat drm.memory.stat
   card0 region=system total=12898304 shared=0 active=0 
resident=12111872 purgeable=167936
   card0 region=stolen-system total=0 shared=0 active=0 resident=0 
purgeable=0


Data is generated on demand for simplicty of implementation ie. no 
running

totals are kept or accounted during migrations and such. Various
optimisations such as cheaper collection of data are possible but
deliberately left out for now.

Overall, the feature is deemed to be useful to container orchestration
software (and manual management).

Limits, either soft or hard, are not envisaged to be implemented on 
top of

this approach due on demand nature of collecting the stats.


So, yeah, if you want to add memory controls, we better think through how
the fd ownership migration should work.
I've taken a look at the series, since I have been working on cgroup 
memory eviction.


The scheduling stuff will work for i915, since it has a purely software 
execlist scheduler, but I don't think it will work for GuC (firmware) 
scheduling or other drivers that use the generic drm scheduler.


It actually works - I used to have a blurb in the cover letter about it 
but apparently I dropped it. Just a bit less well with many clients, 
since there are fewer priority levels.


All that the design requires from the invididual drivers is some way to 
react to the "you are over budget by this much" signal. The rest is 
driver and backend specific.


For something like this,  you would probably want it to work inside the 
drm scheduler first. Presumably, this can be done by setting a weight on 
each runqueue, and perhaps adding a callback to update one for a running 
queue. Calculating the weights hierarchically might be fun..


It is not needed to work in drm scheduler first. In fact drm scheduler 
based drivers can plug into what I have since it already has the notion 
of scheduling priorities.


They would only need to implement a hook which allow the cgroup 
controller to query client GPU utilisation and another to received the 
over budget signal.


Amdgpu and msm AFAIK could be easy candidates because they both support 
per client utilisation and priorities.


Looks like I need to put all this info back into the cover letter.

Also, hierarchic weights and time budgets are all already there. What 
could be done later is make this all smarter and respect the time budget 
with more precision. That would however, in many cases including Intel, 
require co-operation with the firmware. In any case it is only work in 
the implementation, while the cgroup control interface remains the same.


I have taken a look at how the rest of cgroup controllers change 
ownership when moved to a different cgroup, and the answer was: not at 
all. If we attempt to create the scheduler controls only on the first 
time the fd is used, you could probably get rid of all the tracking.


Can you send a CPU file descriptor from process A to process B and have 
CPU usage belonging to process B show up in process' A cgroup, or 
vice-versa? Nope, I am not making any sense, am I? My point being it is 
not like-to-like, model is different.


No ownership transfer would mean in wide deployments all GPU utilisation 
would be assigned to Xorg and so there is no point to any of this. No 
way to throttle a cgroup with un-important GPU clients for instance.



This can be done very easily with the drm scheduler.

WRT memory, I think the consensus is to track system memory like normal 
memory. Stolen memory doesn't need to be tracked. It's kernel only 
memory, used for internal bookkeeping  only.


The only time userspace can directly manipulate stolen memory, is by 
mapping the pinned initial framebuffer to its own address space. The 
only allocation it can do is when a framebuffer is displayed, and 
framebuffer compression creates some stolen memory. Userspace is not

aware of this though, and has no way to manipulate those contents.


Stolen memory is irrelevant and not something cgroup controller knows 
about. Point is drivers say which memory regions they have and their 
utilisation.


Imagine instead of stolen it said vram0, or on Intel multi-tile it shows 
local0 and local1. People working with containers are interested to see 
this breakdown. I guess the parallel and use case here is closer to 
memory.numa_stat.


Regards,

Tvrtko

[Intel-gfx] ✗ Fi.CI.IGT: failure for Update AUX invalidation sequence (rev13)

[Patchwork]

== Series Details ==

Series: Update AUX invalidation sequence (rev13)
URL   : https://patchwork.freedesktop.org/series/119798/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13423_full -> Patchwork_119798v13_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_119798v13_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_119798v13_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_119798v13_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl:  [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-apl4/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-apl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html

  
Known issues


  Here are the changes found in Patchwork_119798v13_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_fdinfo@virtual-busy-hang-all:
- shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8414])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-mtlp-2/igt@drm_fdi...@virtual-busy-hang-all.html

  * igt@gem_ccs@block-copy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#5325])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-mtlp-1/igt@gem_...@block-copy-compressed.html

  * igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-mtlp: [PASS][6] -> [ABORT][7] ([i915#7941])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-mtlp-3/igt@gem_...@in-flight-contexts-10ms.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-mtlp-6/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_exec_await@wide-contexts:
- shard-dg2:  [PASS][8] -> [FAIL][9] ([i915#5892])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-dg2-8/igt@gem_exec_aw...@wide-contexts.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-dg2-8/igt@gem_exec_aw...@wide-contexts.html

  * igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl:  [PASS][10] -> [FAIL][11] ([i915#2842]) +4 similar 
issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-rkl-1/igt@gem_exec_fair@basic-n...@bcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-rkl-1/igt@gem_exec_fair@basic-n...@bcs0.html

  * igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][12] ([i915#3281])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-mtlp-1/igt@gem_exec_re...@basic-gtt-cpu-noreloc.html

  * igt@gem_exec_schedule@preempt-queue-chain:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#4812]) +1 similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-mtlp-5/igt@gem_exec_sched...@preempt-queue-chain.html

  * igt@gem_exec_schedule@wide@rcs0:
- shard-apl:  [PASS][14] -> [FAIL][15] ([i915#6659])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-apl4/igt@gem_exec_schedule@w...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-apl1/igt@gem_exec_schedule@w...@rcs0.html

  * igt@gem_lmem_swapping@random-engines:
- shard-mtlp: NOTRUN -> [SKIP][16] ([i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-mtlp-2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_mmap_gtt@coherency:
- shard-mtlp: NOTRUN -> [SKIP][17] ([i915#4077]) +2 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-mtlp-1/igt@gem_mmap_...@coherency.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
- shard-snb:  [PASS][18] -> [ABORT][19] ([i915#5161])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/shard-snb5/igt@gem_mmap_...@fault-concurrent-y.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/shard-snb5/igt@gem_mmap_...@fault-concurrent-y.html

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-mtlp: NOTRUN -> [SKIP][20] ([i915#4270])

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use the i915_vma_flush_writes helper (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Use the i915_vma_flush_writes helper (rev5)
URL   : https://patchwork.freedesktop.org/series/121122/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13423 -> Patchwork_121122v5


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_121122v5 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_121122v5, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/index.html

Participating hosts (43 -> 42)
--

  Additional (1): fi-kbl-soraka 
  Missing(2): bat-dg1-7 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_121122v5:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/fi-kbl-soraka/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html

  
Known issues


  Here are the changes found in Patchwork_121122v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-n3050:   [PASS][4] -> [DMESG-WARN][5] ([i915#1982])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
- fi-kbl-7567u:   [PASS][6] -> [FAIL][7] ([i915#7940])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-kbl-7567u/igt@i915_pm_...@basic-rte.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/fi-kbl-7567u/igt@i915_pm_...@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
- fi-rkl-11600:   [PASS][8] -> [FAIL][9] ([i915#7940])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-rkl-11600/igt@i915_pm_...@module-reload.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/fi-rkl-11600/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][10] -> [ABORT][11] ([i915#7911] / [i915#7913])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][12] -> [DMESG-FAIL][13] ([i915#5334])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_mocs:
- bat-mtlp-8: [PASS][14] -> [DMESG-FAIL][15] ([i915#7059])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
- bat-mtlp-6: [PASS][16] -> [DMESG-FAIL][17] ([i915#7059])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][18] ([i915#1886] / [i915#7913])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][19] ([i915#6367])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/bat-rpls-2/igt@i915_selftest@l...@slpc.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][20] ([i915#7828])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v5/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-dg2-11: 

Re: [Intel-gfx] [PATCH 16/17] cgroup/drm: Expose memory stats

[Maarten Lankhorst]

Hey,

On 2023-07-22 00:21, Tejun Heo wrote:

On Wed, Jul 12, 2023 at 12:46:04PM +0100, Tvrtko Ursulin wrote:

   $ cat drm.memory.stat
   card0 region=system total=12898304 shared=0 active=0 resident=12111872 
purgeable=167936
   card0 region=stolen-system total=0 shared=0 active=0 resident=0 purgeable=0

Data is generated on demand for simplicty of implementation ie. no running
totals are kept or accounted during migrations and such. Various
optimisations such as cheaper collection of data are possible but
deliberately left out for now.

Overall, the feature is deemed to be useful to container orchestration
software (and manual management).

Limits, either soft or hard, are not envisaged to be implemented on top of
this approach due on demand nature of collecting the stats.


So, yeah, if you want to add memory controls, we better think through how
the fd ownership migration should work.
I've taken a look at the series, since I have been working on cgroup 
memory eviction.


The scheduling stuff will work for i915, since it has a purely software 
execlist scheduler, but I don't think it will work for GuC (firmware) 
scheduling or other drivers that use the generic drm scheduler.


For something like this,  you would probably want it to work inside the 
drm scheduler first. Presumably, this can be done by setting a weight on 
each runqueue, and perhaps adding a callback to update one for a running 
queue. Calculating the weights hierarchically might be fun..


I have taken a look at how the rest of cgroup controllers change 
ownership when moved to a different cgroup, and the answer was: not at 
all. If we attempt to create the scheduler controls only on the first 
time the fd is used, you could probably get rid of all the tracking.

This can be done very easily with the drm scheduler.

WRT memory, I think the consensus is to track system memory like normal 
memory. Stolen memory doesn't need to be tracked. It's kernel only 
memory, used for internal bookkeeping  only.


The only time userspace can directly manipulate stolen memory, is by 
mapping the pinned initial framebuffer to its own address space. The 
only allocation it can do is when a framebuffer is displayed, and 
framebuffer compression creates some stolen memory. Userspace is not

aware of this though, and has no way to manipulate those contents.

Cheers,
~Maarten

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use the i915_vma_flush_writes helper (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Use the i915_vma_flush_writes helper (rev4)
URL   : https://patchwork.freedesktop.org/series/121122/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13423 -> Patchwork_121122v4


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_121122v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_121122v4, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/index.html

Participating hosts (43 -> 41)
--

  Missing(2): bat-dg1-7 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_121122v4:

### IGT changes ###

 Possible regressions 

  * igt@kms_force_connector_basic@force-edid:
- bat-adlm-1: [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-adlm-1/igt@kms_force_connector_ba...@force-edid.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/bat-adlm-1/igt@kms_force_connector_ba...@force-edid.html

  
 Warnings 

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-rpls-2: [SKIP][3] ([i915#4613]) -> [ABORT][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-rpls-2/igt@gem_lmem_swapp...@parallel-random-engines.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/bat-rpls-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  
Known issues


  Here are the changes found in Patchwork_121122v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@basic-rte:
- fi-tgl-1115g4:  [PASS][5] -> [FAIL][6] ([i915#7940])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-tgl-1115g4/igt@i915_pm_...@basic-rte.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/fi-tgl-1115g4/igt@i915_pm_...@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
- fi-rkl-11600:   [PASS][7] -> [FAIL][8] ([i915#7940])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-rkl-11600/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/fi-rkl-11600/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@dmabuf:
- bat-mtlp-6: [PASS][9] -> [DMESG-FAIL][10] ([i915#8558])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-mtlp-6/igt@i915_selftest@l...@dmabuf.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/bat-mtlp-6/igt@i915_selftest@l...@dmabuf.html

  * igt@i915_selftest@live@gt_mocs:
- bat-mtlp-6: [PASS][11] -> [DMESG-FAIL][12] ([i915#7059])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#7828])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html

  * igt@kms_psr@sprite_plane_onoff:
- bat-rplp-1: NOTRUN -> [ABORT][14] ([i915#8442] / [i915#8668] / 
[i915#8712])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@i915_pm_rpm@basic-rte:
- fi-cfl-guc: [FAIL][15] ([i915#7940]) -> [PASS][16] +1 similar 
issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-cfl-guc/igt@i915_pm_...@basic-rte.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/fi-cfl-guc/igt@i915_pm_...@basic-rte.html

  * igt@i915_selftest@live@gt_lrc:
- bat-dg2-11: [INCOMPLETE][17] ([i915#7609] / [i915#7913]) -> 
[PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@requests:
- bat-mtlp-6: [DMESG-FAIL][19] ([i915#8497]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-mtlp-6/igt@i915_selftest@l...@requests.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121122v4/bat-mtlp-6/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@slpc:
- bat-mtlp-6: [DMESG-WARN][21] ([i915#6367]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-mtlp-6/igt@i915_selftest@l...@slpc.html
   [22]: 

Re: [Intel-gfx] [PATCH dii-client 1/2] drm/i915: Make i915_coherent_map_type GT-centric

[Tvrtko Ursulin]

On 25/07/2023 18:39, Cavitt, Jonathan wrote:

-Original Message-
From: Tvrtko Ursulin 
Sent: Tuesday, July 25, 2023 9:23 AM
To: Cavitt, Jonathan ; 
intel-gfx@lists.freedesktop.org
Cc: Shyti, Andi ; Roper, Matthew D ; 
chris.p.wil...@linux.intel.com; Das, Nirmoy 
Subject: Re: [Intel-gfx] [PATCH dii-client 1/2] drm/i915: Make 
i915_coherent_map_type GT-centric



On 25/07/2023 17:01, Jonathan Cavitt wrote:

Refactor i915_coherent_map_type to be GT-centric rather than
device-centric.  Each GT may require different coherency
handling due to hardware workarounds.

Since the function now takes a GT instead of the i915, the function is
renamed and moved to the gt folder.


What about the issue of fake gt passed to shmem_create_from_object I raised?



The function is, presently, only called in __engines_record_defaults, as a part 
of
intel_gt_init.  shmem_create_from_object uses i915_coherent_map_type to 
determine
the map_type to pass to i915_gem_object_pin_map_unlocked.  This creates a 
pointer
that we pass to shmem_create_from_data.  Aside from an i915_gem_object_is_shmem
check at the start, the function is otherwise just calling 
shmem_create_from_data...
which, itself, is only called by shmem_create_from_object.

I'd argue that any additional changes to shmem_create_from_object are 
unnecessary
as the function is only called from __engines_record_defaults.  Additionally, 
the function
is a part of the gt library (shmem_utils.h is in the gt folder), so taking a gt 
argument should
be expected.  However, if you still disagree, here's a few options for how we 
can rectify
this issue:


Looking at the content of shmem_utils.c it does seem wholly misplaced in 
gt/. I would say we could move it (and should really, just no need in 
scope of this series).



Debatably, we could just delete shmem_create_from_object and use the full 
expansion
in __engines_record_defaults.  Though this may come with some additional 
complications,
such as the lost helper function being desirable in the future and needing to 
expand the
definition of shmem_create_from_data to include an object pinning requirement.

The second option is that we pass the map_type to the shmem_create_from_object 
function
instead of the GT, bypassing the need for i915_coherent_map_type in the 
function by breaking
it out as a part of __engines_record_defaults.  I'll leave it to your judgement 
whether this would
be more or less confusing than just passing the GT.

Thirdly, we could just hard-code a specific map_type to use, though that seems 
ill-advised.


Does the helper even need the coherent mapping if it is not setting up 
shared access? AFAICS it is just a single use mapping with the sole 
purpose to read the content of the whole object in bulk. And the whole 
source object is also even a throw-away.


So in fact yes, why not just hardcode to something like:

type = i915_gem_object_is_lmem(obj) : I915_MMAP_WC : I915_MMAP_WB;

?

Regards,

Tvrtko



The last option is to rename the function to something more representative. 
Here's a few ideas
I can think of off the top of my head:

shmem_create
shmem_create_on_gt
shmem_create_from_gt
shmem_create_from_object_on_gt
intel_gt_create_shmem_from_object

If I had to recommend one approach over the rest, it would probably be the 
second option,
followed by the fourth.

-Jonathan Cavitt




Regards,

Tvrtko

P.S. See if you can drop the dii-client part from the subject line going
forward.



Suggested-by: Matt Roper 
Signed-off-by: Jonathan Cavitt 
---
   drivers/gpu/drm/i915/display/intel_hdcp_gsc.c   |  3 ++-
   drivers/gpu/drm/i915/gem/i915_gem_object.h  |  4 
   drivers/gpu/drm/i915/gem/i915_gem_pages.c   | 15 ---
   .../drm/i915/gem/selftests/i915_gem_migrate.c   | 12 ++--
   drivers/gpu/drm/i915/gt/intel_engine_pm.c   |  2 +-
   drivers/gpu/drm/i915/gt/intel_gt.c  | 17 -
   drivers/gpu/drm/i915/gt/intel_gt.h  |  3 +++
   drivers/gpu/drm/i915/gt/intel_gtt.c |  4 ++--
   drivers/gpu/drm/i915/gt/intel_lrc.c |  2 +-
   drivers/gpu/drm/i915/gt/intel_ring.c|  3 ++-
   drivers/gpu/drm/i915/gt/selftest_context.c  |  2 +-
   drivers/gpu/drm/i915/gt/selftest_hangcheck.c|  4 ++--
   drivers/gpu/drm/i915/gt/selftest_lrc.c  |  2 +-
   drivers/gpu/drm/i915/gt/shmem_utils.c   |  7 ---
   drivers/gpu/drm/i915/gt/shmem_utils.h   |  4 +++-
   drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c   |  3 +--
   drivers/gpu/drm/i915/gt/uc/intel_guc.c  |  2 +-
   drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c   |  3 +--
   drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c|  3 ++-
   drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c  |  2 +-
   drivers/gpu/drm/i915/pxp/intel_pxp_tee.c|  3 ++-
   drivers/gpu/drm/i915/selftests/igt_spinner.c|  2 +-
   22 files changed, 53 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c 

[Intel-gfx] ✓ Fi.CI.BAT: success for Update AUX invalidation sequence (rev13)

[Patchwork]

== Series Details ==

Series: Update AUX invalidation sequence (rev13)
URL   : https://patchwork.freedesktop.org/series/119798/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13423 -> Patchwork_119798v13


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/index.html

Participating hosts (43 -> 42)
--

  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_119798v13 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3:  [PASS][1] -> [ABORT][2] ([i915#5122])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- bat-dg1-7:  [PASS][3] -> [FAIL][4] ([i915#7691])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-dg1-7/igt@i915_pm_...@basic-pci-d3-state.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/bat-dg1-7/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
- fi-rkl-11600:   [PASS][5] -> [FAIL][6] ([i915#7940])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-rkl-11600/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/fi-rkl-11600/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_mocs:
- bat-mtlp-8: [PASS][9] -> [DMESG-FAIL][10] ([i915#7059])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
- bat-mtlp-6: [PASS][11] -> [DMESG-FAIL][12] ([i915#7059])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@requests:
- bat-rpls-2: [PASS][13] -> [ABORT][14] ([i915#4983] / [i915#7913])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-rpls-2/igt@i915_selftest@l...@requests.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/bat-rpls-2/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3:  [PASS][15] -> [FAIL][16] ([fdo#103375])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#7828])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][18] -> [ABORT][19] ([i915#8442] / [i915#8668])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html

  
 Possible fixes 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-cfl-8700k:   [FAIL][20] ([i915#7940]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/fi-cfl-8700k/igt@i915_pm_...@basic-pci-d3-state.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/fi-cfl-8700k/igt@i915_pm_...@basic-pci-d3-state.html
- bat-adlp-9: [FAIL][22] ([i915#7940]) -> [PASS][23]
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-adlp-9/igt@i915_pm_...@basic-pci-d3-state.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119798v13/bat-adlp-9/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_selftest@live@gt_lrc:
- bat-dg2-11: [INCOMPLETE][24] ([i915#7609] / [i915#7913]) -> 
[PASS][25]
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13423/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
   [25]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update AUX invalidation sequence (rev13)

[Patchwork]

== Series Details ==

Series: Update AUX invalidation sequence (rev13)
URL   : https://patchwork.freedesktop.org/series/119798/
State : warning

== Summary ==

Error: dim checkpatch failed
83c202cba4ad drm/i915/gt: Cleanup aux invalidation registers
24756b4dcb54 drm/i915: Add the gen12_needs_ccs_aux_inv helper
7aa919db5903 drm/i915/gt: Ensure memory quiesced before invalidation
5240b3ba01d3 drm/i915/gt: Rename flags with bit_group_X according to the 
datasheet
6fce0e157344 drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control and in 
the CS
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#15: 
Requires: 8da173db894a ("drm/i915/gt: Rename flags with bit_group_X according 
to the datasheet")

-:61: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#61: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:302:
+#define   PIPE_CONTROL_CCS_FLUSH   (1<<13) /* MTL+ */
  ^

total: 0 errors, 1 warnings, 1 checks, 30 lines checked
0231f7fc45ff drm/i915/gt: Poll aux invalidation register bit on invalidation
478e4e207bb7 drm/i915/gt: Support aux invalidation on all engines

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Update AUX invalidation sequence (rev13)

[Patchwork]

== Series Details ==

Series: Update AUX invalidation sequence (rev13)
URL   : https://patchwork.freedesktop.org/series/119798/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'

Re: [Intel-gfx] [PATCH dii-client 2/2] drm/i915/gt: Apply workaround 22016122933 correctly

[Yang, Fei]

> Subject: [PATCH dii-client 2/2] drm/i915/gt: Apply workaround 22016122933 
> correctly

Remove dii-client from the subject.
Otherwise LGTM.

Acked-by: Fei Yang 

> WA_22016122933 was recently applied to all MeteorLake engines,
> which is simultaneously too broad (should only apply to Media
> engines) and too specific (should apply to all platforms that
> use the same media engine as MeteorLake). Correct this in cases
> where coherency settings are modified.
>
> There were also two additional places where the workaround was
> applied unconditionally. The change was confirmed as necessary
> for all platforms, so the workaround label was removed.
>
> Signed-off-by: Jonathan Cavitt 
> Suggested-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c| 5 +++--
>  drivers/gpu/drm/i915/gt/intel_gt.h| 6 ++
>  drivers/gpu/drm/i915/gt/intel_lrc.c   | 7 ---
>  drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 4 
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c| 7 ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 
>  6 files changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 6faf1dae965f..207bfc0ff939 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -1139,9 +1139,10 @@ enum i915_map_type intel_gt_coherent_map_type(struct 
> intel_gt *gt,
> bool always_coherent)
>  {
>   /*
> -  * Wa_22016122933: always return I915_MAP_WC for MTL
> +  * Wa_22016122933: always return I915_MAP_WC for Media
> +  * version 13.0 when the object is on the Media GT
>*/
> - if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(gt->i915))
> + if (i915_gem_object_is_lmem(obj) || intel_gt_needs_wa_22016122933(gt))
>   return I915_MAP_WC;
>   if (HAS_LLC(gt->i915) || always_coherent)
>   return I915_MAP_WB;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index adb442aaa522..2444ceb42b1b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -6,6 +6,7 @@
>  #ifndef __INTEL_GT__
>  #define __INTEL_GT__
>
> +#include "i915_drv.h"
>  #include "intel_engine_types.h"
>  #include "intel_gt_types.h"
>  #include "intel_reset.h"
> @@ -24,6 +25,11 @@ static inline bool gt_is_root(struct intel_gt *gt)
>   return !gt->info.id;
>  }
>
> +static inline bool intel_gt_needs_wa_22016122933(struct intel_gt *gt) {
> + return MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && gt->type ==
> +GT_MEDIA; }
> +
>  static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)  {
>   return container_of(uc, struct intel_gt, uc); diff --git 
> a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index e5a83d4932c8..9f0a2d828a2a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1095,10 +1095,11 @@ __lrc_alloc_state(struct intel_context *ce, struct 
> intel_engine_cs *engine)
>   if (IS_ERR(obj)) {
>   obj = i915_gem_object_create_shmem(engine->i915, context_size);
>   /*
> -  * Wa_22016122933: For MTL the shared memory needs to be mapped
> -  * as WC on CPU side and UC (PAT index 2) on GPU side
> +  * Wa_22016122933: For Media version 13.0, all Media GT shared
> +  * memory needs to be mapped as WC on CPU side and UC (PAT
> +  * index 2) on GPU side.
>*/
> - if (IS_METEORLAKE(engine->i915))
> + if (intel_gt_needs_wa_22016122933(engine->gt))
>   i915_gem_object_set_cache_coherency(obj, 
> I915_CACHE_NONE);
>   }
>   if (IS_ERR(obj))
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> index 6efb86c93bfc..52652a0350c6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
> @@ -284,10 +284,6 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
>   memcpy_toio(gsc->local_vaddr, src, gsc->fw.size);
>   memset_io(gsc->local_vaddr + gsc->fw.size, 0, gsc->local->size - 
> gsc->fw.size);
>
> - /*
> -  * Wa_22016122933: Making sure the data in dst is
> -  * visible to GSC right away
> -  */
>   intel_guc_write_barrier(>uc.guc);
>
>   i915_gem_object_unpin_map(gsc->fw.obj);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index c0fa9d232205..63bdc000d76b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -745,10 +745,11 @@ struct i915_vma *intel_guc_allocate_vma(struct 
> intel_guc *guc, u32 size)
>   return ERR_CAST(obj);
>
>   /*
> -  * Wa_22016122933: For MTL the shared memory needs to be mapped
> -  * as WC on CPU side 

Re: [Intel-gfx] [PATCH dii-client 1/2] drm/i915: Make i915_coherent_map_type GT-centric

[Yang, Fei]

> Refactor i915_coherent_map_type to be GT-centric rather than
> device-centric.  Each GT may require different coherency handling
> due to hardware workarounds.
>
> Since the function now takes a GT instead of the i915, the function
> is renamed and moved to the gt folder.

Remove dii-client in the title. Also need to fix the check-patch warnings.
Otherwise the patch looks good to me.

assume you address the above issues,
Acked-by: Fei Yang 

> Suggested-by: Matt Roper 
> Signed-off-by: Jonathan Cavitt 
> ---
>  drivers/gpu/drm/i915/display/intel_hdcp_gsc.c   |  3 ++-
>  drivers/gpu/drm/i915/gem/i915_gem_object.h  |  4 
>  drivers/gpu/drm/i915/gem/i915_gem_pages.c   | 15 ---
>  .../drm/i915/gem/selftests/i915_gem_migrate.c   | 12 ++--
>  drivers/gpu/drm/i915/gt/intel_engine_pm.c   |  2 +-
>  drivers/gpu/drm/i915/gt/intel_gt.c  | 17 -
>  drivers/gpu/drm/i915/gt/intel_gt.h  |  3 +++
>  drivers/gpu/drm/i915/gt/intel_gtt.c |  4 ++--
>  drivers/gpu/drm/i915/gt/intel_lrc.c |  2 +-
>  drivers/gpu/drm/i915/gt/intel_ring.c|  3 ++-
>  drivers/gpu/drm/i915/gt/selftest_context.c  |  2 +-
>  drivers/gpu/drm/i915/gt/selftest_hangcheck.c|  4 ++--
>  drivers/gpu/drm/i915/gt/selftest_lrc.c  |  2 +-
>  drivers/gpu/drm/i915/gt/shmem_utils.c   |  7 ---
>  drivers/gpu/drm/i915/gt/shmem_utils.h   |  4 +++-
>  drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c   |  3 +--
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c  |  2 +-
>  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c   |  3 +--
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c|  3 ++-
>  drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c  |  2 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp_tee.c|  3 ++-
>  drivers/gpu/drm/i915/selftests/igt_spinner.c|  2 +-
>  22 files changed, 53 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c 
> b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
> index ad0405375881..d753db3eef15 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
> @@ -6,6 +6,7 @@
>  #include 
>
>  #include "gem/i915_gem_region.h"
> +#include "gt/intel_gt.h"
>  #include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"
>  #include "i915_drv.h"
>  #include "i915_utils.h"
> @@ -632,7 +633,7 @@ static int intel_hdcp_gsc_initialize_message(struct 
> drm_i915_private *i915,
>   return PTR_ERR(obj);
>   }
>
> - cmd_in = i915_gem_object_pin_map_unlocked(obj, 
> i915_coherent_map_type(i915, obj, true));
> + cmd_in = i915_gem_object_pin_map_unlocked(obj,
> +intel_gt_coherent_map_type(gt, obj, true));
>   if (IS_ERR(cmd_in)) {
>   drm_err(>drm, "Failed to map gsc message page!\n");
>   err = PTR_ERR(cmd_in);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index 884a17275b3a..0c695b4c129f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> @@ -716,10 +716,6 @@ void *__must_check i915_gem_object_pin_map(struct 
> drm_i915_gem_object *obj,
>  void *__must_check i915_gem_object_pin_map_unlocked(struct 
> drm_i915_gem_object *obj,
>   enum i915_map_type type);
>
> -enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
> -   struct drm_i915_gem_object *obj,
> -   bool always_coherent);
> -
>  void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
>unsigned long offset,
>unsigned long size);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> index 89fc8ea6bcfc..6d262d269c71 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -465,21 +465,6 @@ void *i915_gem_object_pin_map_unlocked(struct 
> drm_i915_gem_object *obj,
>   return ret;
>  }
>
> -enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
> -   struct drm_i915_gem_object *obj,
> -   bool always_coherent)
> -{
> - /*
> -  * Wa_22016122933: always return I915_MAP_WC for MTL
> -  */
> - if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
> - return I915_MAP_WC;
> - if (HAS_LLC(i915) || always_coherent)
> - return I915_MAP_WB;
> - else
> - return I915_MAP_WC;
> -}
> -
>  void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
>unsigned long offset,
>unsigned long size)
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c 
> 

[Intel-gfx] ✓ Fi.CI.IGT: success for MTL Degamma implementation (rev3)

[Patchwork]

== Series Details ==

Series: MTL Degamma implementation (rev3)
URL   : https://patchwork.freedesktop.org/series/119844/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13419_full -> Patchwork_119844v3_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_119844v3_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-dg1:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [FAIL][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50]) ([i915#8614])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-12/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-12/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-12/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-12/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-13/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-14/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-15/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-15/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-15/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-16/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-16/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-16/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-16/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-17/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-17/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-17/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-17/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-18/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-18/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-18/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-18/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-19/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-19/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-19/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-19/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-19/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-19/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-19/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-18/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-18/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-18/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-17/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-17/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-17/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-16/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-16/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-16/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-15/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-15/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-15/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-14/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-14/boot.html
   

Re: [Intel-gfx] [PATCH] drm/i915/hotplug: Reduce SHPD_FILTER to 250us

[Shankar, Uma]

> -Original Message-
> From: Intel-gfx  On Behalf Of 
> Shankar,
> Uma
> Sent: Thursday, July 20, 2023 3:41 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/hotplug: Reduce SHPD_FILTER to 250us
> 
> 
> 
> > -Original Message-
> > From: Kandpal, Suraj 
> > Sent: Monday, July 17, 2023 2:54 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Kandpal, Suraj ; Shankar, Uma
> > ; Ville Syrjala 
> > Subject: [PATCH] drm/i915/hotplug: Reduce SHPD_FILTER to 250us
> >
> > On TGP, the RTC (always running) was reduced from 3MHz to 32KHz.
> > As a result of this change, when HPD active going low pulse or HPD IRQ
> > is presented and the refclk (19.2MHz) is not toggling already
> > toggling, there is a 60 to 90us synchronization delay which
> > effectively reduces the duration of the IRQ pulse to less than the 
> > programmed
> 500us filter value and the hot plug interrupt is NOT registered.
> > Solution was to Reduce SHPD_FILTER to 250us for ADL and above.
> > This solution was derived when the below patch was floated.
> > [1]https://patchwork.freedesktop.org/patch/532187
> > and after some internal discussion Ville's suggestion made sense.
> 
> Looks Good to me. Just add also a Suggested-By tag mentioning Ville.
> Reviewed-by: Uma Shankar 

Pushed to drm-intel-next. Thanks for the change.

Regards,
Uma Shankar

> > Bspec: 68970
> >
> > Cc: Uma Shankar 
> > Cc: Ville Syrjala 
> > Signed-off-by: Suraj Kandpal 
> > ---
> >  drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 4 +++-
> >  drivers/gpu/drm/i915/i915_reg.h  | 1 +
> >  2 files changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > index f95fa793fabb..95a7ea94f417 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > @@ -842,6 +842,8 @@ static void icp_hpd_irq_setup(struct
> > drm_i915_private
> > *dev_priv)
> >
> > if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
> > intel_uncore_write(_priv->uncore, SHPD_FILTER_CNT,
> > SHPD_FILTER_CNT_500_ADJ);
> > +   else
> > +   intel_uncore_write(_priv->uncore, SHPD_FILTER_CNT,
> > +SHPD_FILTER_CNT_250);
> >
> > ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> >
> > @@ -1049,7 +1051,7 @@ static void mtp_hpd_irq_setup(struct
> > drm_i915_private
> > *i915)
> > enabled_irqs = intel_hpd_enabled_irqs(i915, 
> > i915->display.hotplug.pch_hpd);
> > hotplug_irqs = intel_hpd_hotplug_irqs(i915,
> > i915->display.hotplug.pch_hpd);
> >
> > -   intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
> > +   intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
> >
> > mtp_hpd_invert(i915);
> > ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs); diff
> > --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index dcf64e32cd54..aefad14ab27a
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4939,6 +4939,7 @@
> >
> >  #define SHPD_FILTER_CNT_MMIO(0xc4038)
> >  #define   SHPD_FILTER_CNT_500_ADJ  0x001D9
> > +#define   SHPD_FILTER_CNT_250  0x000F8
> >
> >  #define _PCH_DPLL_A  0xc6014
> >  #define _PCH_DPLL_B  0xc6018
> > --
> > 2.25.1

[Intel-gfx] ✗ Fi.CI.IGT: failure for MTL Degamma implementation (rev3)

[Patchwork]

== Series Details ==

Series: MTL Degamma implementation (rev3)
URL   : https://patchwork.freedesktop.org/series/119844/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13419_full -> Patchwork_119844v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_119844v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_119844v3_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_119844v3_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_flip@flip-vs-modeset-vs-hang@b-vga1:
- shard-snb:  [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-snb7/igt@kms_flip@flip-vs-modeset-vs-h...@b-vga1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-snb7/igt@kms_flip@flip-vs-modeset-vs-h...@b-vga1.html

  
Known issues


  Here are the changes found in Patchwork_119844v3_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-dg1:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [FAIL][47], [PASS][48], 
[PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#8614])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-12/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-12/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-12/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-12/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-13/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-14/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-15/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-15/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-15/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-16/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-16/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-16/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-16/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-17/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-17/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-17/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-17/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-18/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-18/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-18/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-18/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-19/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-19/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-19/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13419/shard-dg1-19/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-19/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-19/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-19/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-18/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-18/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-18/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119844v3/shard-dg1-17/boot.html
   [35]: