[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display/lspcon: Increase LSPCON mode settle timeout (rev4)
== Series Details == Series: drm/i915/display/lspcon: Increase LSPCON mode settle timeout (rev4) URL : https://patchwork.freedesktop.org/series/108735/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/lspcon: Increase LSPCON mode settle timeout (rev4)
== Series Details == Series: drm/i915/display/lspcon: Increase LSPCON mode settle timeout (rev4) URL : https://patchwork.freedesktop.org/series/108735/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Eliminate has_4tile feature flag
On 8/11/2023 5:16 AM, Matt Roper wrote:
We don't really need a feature flag for has_4tile since there's a
well-defined cutover point (DG2) at which all new platforms started
using Tile4 as their Y-major tiling layout. The GT side of the code
already handles Tile4 vs legacy TileY with checks on the IP version
rather than looking at the feature flag, and we can simplify the display
code similarly (which will also make it more self-contained for re-use
in the Xe driver).
Hi Matt,
Looks good to me.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h| 1 -
4 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 215e682bd8b7..eb630a946343 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -32,6 +32,7 @@ struct drm_printer;
func(overlay_needs_physical); \
func(supports_tv);
+#define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
is this tab space aligned with below lines ?
#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
#define HAS_CDCLK_SQUASH(i915)
(DISPLAY_INFO(i915)->has_cdclk_squash)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a8ce7239bc9..4c6852f0a61c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -737,7 +737,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
-#define HAS_4TILE(i915)(INTEL_INFO(i915)->has_4tile)
#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
#define HAS_EDRAM(i915) ((i915)->edram_size_mb)
#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fcacdc21643c..df7c261410f7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -713,7 +713,6 @@ static const struct intel_device_info adl_p_info = {
.has_3d_pipeline = 1, \
.has_64bit_reloc = 1, \
.has_flat_ccs = 1, \
- .has_4tile = 1, \
.has_global_mocs = 1, \
.has_gt_uc = 1, \
.has_llc = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index dbfe6443457b..19d120728ff1 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -150,7 +150,6 @@ enum intel_ppgtt_type {
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_3d_pipeline); \
- func(has_4tile); \
func(has_flat_ccs); \
func(has_global_mocs); \
func(has_gmd_id); \
--
Regards,
Haridhar Kalvala
Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftest: Simplify Y-major tiling in blit selftest
On 8/11/2023 5:16 AM, Matt Roper wrote:
Rather than picking random tiling formats from a pool that contains both
TileY and Tile4 and then trying to replace one with the other depending
on the platform, it's simpler to just use a single enum value that
represents whatever the platform-appropriate Y-major tiling format is
(i.e., Tile4 on Xe_HP and beyond, legacy TileY on earlier platforms).
Signed-off-by: Matt Roper
---
.../i915/gem/selftests/i915_gem_client_blt.c | 39 +++
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ff81af4c8202..10a7847f1b04 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -83,8 +83,7 @@ static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride,
int bpp)
enum client_tiling {
CLIENT_TILING_LINEAR,
CLIENT_TILING_X,
- CLIENT_TILING_Y,
- CLIENT_TILING_4,
+ CLIENT_TILING_Y, /* Y-major, either Tile4 (Xe_HP and beyond) or legacy
TileY */
CLIENT_NUM_TILING_TYPES
};
@@ -165,11 +164,10 @@ static int prepare_blit(const struct tiled_blits *t,
BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
src_pitch = t->width; /* in dwords */
- if (src->tiling == CLIENT_TILING_4) {
- src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
- src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
- } else if (src->tiling == CLIENT_TILING_Y) {
+ if (src->tiling == CLIENT_TILING_Y) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >=
IP_VER(12, 50))
+ src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
} else if (src->tiling == CLIENT_TILING_X) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
} else {
@@ -177,11 +175,10 @@ static int prepare_blit(const struct tiled_blits *t,
}
dst_pitch = t->width; /* in dwords */
- if (dst->tiling == CLIENT_TILING_4) {
- dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
- dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
- } else if (dst->tiling == CLIENT_TILING_Y) {
+ if (dst->tiling == CLIENT_TILING_Y) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >=
IP_VER(12, 50))
+ dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
} else if (dst->tiling == CLIENT_TILING_X) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
} else {
@@ -326,12 +323,6 @@ static int tiled_blits_create_buffers(struct tiled_blits
*t,
t->buffers[i].vma = vma;
t->buffers[i].tiling =
i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES,
prng);
-
- /* Platforms support either TileY or Tile4, not both */
- if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
- t->buffers[i].tiling = CLIENT_TILING_4;
- else if (!HAS_4TILE(i915) && t->buffers[i].tiling ==
CLIENT_TILING_4)
- t->buffers[i].tiling = CLIENT_TILING_Y;
}
return 0;
@@ -367,18 +358,19 @@ static u64 tiled_offset(const struct intel_gt *gt,
y = div64_u64_rem(v, stride, &x);
- if (tiling == CLIENT_TILING_4) {
- v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
-
- /* no swizzling for f-tiling */
- swizzle = I915_BIT_6_SWIZZLE_NONE;
- } else if (tiling == CLIENT_TILING_X) {
+ if (tiling == CLIENT_TILING_X) {
v = div64_u64_rem(y, 8, &y) * stride * 8;
v += y * 512;
v += div64_u64_rem(x, 512, &x) << 12;
v += x;
swizzle = gt->ggtt->bit_6_swizzle_x;
+ } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+ /* Y-major tiling layout is Tile4 for Xe_HP and beyond */
+ v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
+
+ /* no swizzling for f-tiling */
+ swizzle = I915_BIT_6_SWIZZLE_NONE;
} else {
const unsigned int ytile_span = 16;
const unsigned int ytile_height = 512;
@@ -414,8 +406,7 @@ static const char *repr_tiling(enum client_tiling tiling)
switch (tiling) {
case CLIENT_TILING_LINEAR: return "linear";
case CLIENT_TILING_X: return "X";
- case CLIENT_TILING_Y: return "Y";
- case CLIENT_TILING_4: return "F";
+ case CLIENT_TILING_Y: return "Y / 4";
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Force a reset on internal GuC error (rev2)
== Series Details == Series: drm/i915/guc: Force a reset on internal GuC error (rev2) URL : https://patchwork.freedesktop.org/series/118890/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13524_full -> Patchwork_118890v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_118890v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118890v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_118890v2_full: ### IGT changes ### Possible regressions * igt@kms_draw_crc@draw-method-blt@xrgb-ytiled: - shard-glk: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-glk8/igt@kms_draw_crc@draw-method-...@xrgb-ytiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-glk7/igt@kms_draw_crc@draw-method-...@xrgb-ytiled.html Known issues Here are the changes found in Patchwork_118890v2_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414]) +20 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-dg2-6/igt@drm_fdinfo@busy-h...@bcs0.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][4] -> [FAIL][5] ([i915#7742]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-rkl-4/igt@drm_fdinfo@most-busy-check-...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@feature_discovery@chamelium: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#4854]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-dg2-6/igt@feature_discov...@chamelium.html * igt@gem_close_race@multigpu-basic-threads: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#7697]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-dg2-6/igt@gem_close_r...@multigpu-basic-threads.html * igt@gem_ctx_persistence@heartbeat-hang: - shard-dg2: NOTRUN -> [SKIP][8] ([i915#8555]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-dg2-6/igt@gem_ctx_persiste...@heartbeat-hang.html * igt@gem_ctx_persistence@hostile: - shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-snb4/igt@gem_ctx_persiste...@hostile.html * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#5882]) +9 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-dg2-6/igt@gem_ctx_persistence@saturated-hostile-nopree...@ccs0.html * igt@gem_exec_balancer@bonded-pair: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#4771]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-dg2-6/igt@gem_exec_balan...@bonded-pair.html * igt@gem_exec_capture@pi@vcs0: - shard-mtlp: [PASS][12] -> [FAIL][13] ([i915#4475]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-mtlp-5/igt@gem_exec_capture@p...@vcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-mtlp-7/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_endless@dispatch@rcs0: - shard-dg2: [PASS][14] -> [TIMEOUT][15] ([i915#3778] / [i915#7016] / [i915#7921]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-dg2-12/igt@gem_exec_endless@dispa...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-dg2-12/igt@gem_exec_endless@dispa...@rcs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglu: [PASS][16] -> [FAIL][17] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-tglu-8/igt@gem_exec_fair@basic-f...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-tglu-5/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-rkl: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-rkl-7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/shard-rkl-1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exe
Re: [Intel-gfx] [PATCH] drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI
> On Mon, 07 Aug 2023, Suraj Kandpal wrote: > > Assign explicit value of 12 at 8bpp as per Table E2 of DSC 1.1 for DSI > > panels even though we already use calculations from CModel for > > first_line_bpg_offset. > > The reason being some DSI monitors may have not have added the change > > in errata for the calculation of first_line_bpg_offset. > > > > Signed-off-by: Suraj Kandpal > > --- > > drivers/gpu/drm/i915/display/icl_dsi.c | 5 + > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > > b/drivers/gpu/drm/i915/display/icl_dsi.c > > index f7ebc146f96d..2376d5000d78 100644 > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > > @@ -1585,6 +1585,11 @@ static int gen11_dsi_dsc_compute_config(struct > intel_encoder *encoder, > > if (ret) > > return ret; > > > > + /* From Table E-2 in DSC 1.1*/ > > + if (vdsc_cfg->dsc_version_minor == 1 && > > + vdsc_cfg->bits_per_pixel == 128) > Hi Jani, Thanks for the review > So, vdsc_cfg->bits_per_pixel has 4 fractional bits, and that's 8 bpp > compressed? > > Better describe it that way, instead of as 128. > Yes would be better to right shift (vdsc_cfg->bits_per_pixel) by 4 then compare with 8 to avoid confusion. > But... looking around, in intel_vdsc.c we set: > > pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); > > and we have: > > #define DSC_BPP(bpp)((bpp) << 4) > > however, when reading it back in intel_dsc_get_config(), it's just > directly: > > vdsc_cfg->bits_per_pixel = pps1; > > Are we always sending x16 bpp in PPS? Yes we are always sending bpp x16 considering the fractional bits also in intel_vdsc_regs.h We have #define DSC_BPP(bpp) ((bpp) << 0) Which in hindsight can be renamed as it has the same name as the one in drm_dsc_helper.c But then again the DSC_BPP macro there is more local to that file. Moreover vdsc_cfg->bits_per_pixel is being set in intel_dsc_compute_params(among other places but is still being set x16 the value). vdsc_cfg->bits_per_pixel = compressed_bpp << 4; Regards, Suraj Kandpal > > > BR, > Jani. > > > > > + vdsc_cfg->first_line_bpg_offset = 12; > > + > > /* DSI specific sanity checks on the common code */ > > drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); > > drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); > > -- > Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v3] drm/i915/display/lspcon: Increase LSPCON mode settle timeout
This is to eliminate all cases of "*ERROR* LSPCON mode hasn't settled",
followed by link training errors. Intel engineers recommended increasing
this timeout and that does resolve the issue.
On some CometLake-based device designs the Parade PS175 takes more than
400ms to settle in PCON mode. 100 reboot trials on one device resulted
in a median settle time of 440ms and a maximum of 444ms. Even after
increasing the timeout to 500ms, 2% of devices still had this error. So
this increases the timeout to 800ms.
Signed-off-by: Pablo Ceballos
---
V2: Added more details in the commit message
V3: Only apply the increased timeout if the vendor is Parade
drivers/gpu/drm/i915/display/intel_lspcon.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index bb3b5355a0d9..b07eab84cc63 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -153,6 +153,24 @@ static enum drm_lspcon_mode lspcon_get_current_mode(struct
intel_lspcon *lspcon)
return current_mode;
}
+static u32 lspcon_get_mode_settle_timeout(struct intel_lspcon *lspcon)
+{
+ u32 timeout_ms = 400;
+
+ /*
+* On some CometLake-based device designs the Parade PS175 takes more
+* than 400ms to settle in PCON mode. 100 reboot trials on one device
+* resulted in a median settle time of 440ms and a maximum of 444ms.
+* Even after increasing the timeout to 500ms, 2% of devices still had
+* this error. So this sets the timeout to 800ms.
+*/
+ if (lspcon->vendor == LSPCON_VENDOR_PARADE)
+ timeout_ms = 800;
+
+ return timeout_ms;
+}
+
+
static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon,
enum drm_lspcon_mode mode)
{
@@ -167,7 +185,8 @@ static enum drm_lspcon_mode lspcon_wait_mode(struct
intel_lspcon *lspcon,
drm_dbg_kms(&i915->drm, "Waiting for LSPCON mode %s to settle\n",
lspcon_mode_name(mode));
- wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400);
+ wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode,
+lspcon_get_mode_settle_timeout(lspcon));
if (current_mode != mode)
drm_err(&i915->drm, "LSPCON mode hasn't settled\n");
--
2.39.2
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec
== Series Details == Series: drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec URL : https://patchwork.freedesktop.org/series/122479/ State : success == Summary == CI Bug Log - changes from CI_DRM_13524_full -> Patchwork_122479v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_122479v1_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][1] ([i915#8414]) +10 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-dg2-1/igt@drm_fdinfo@busy-h...@bcs0.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][2] -> [FAIL][3] ([i915#7742]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-rkl-4/igt@drm_fdinfo@most-busy-check-...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@drm_fdinfo@virtual-busy-idle-all: - shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8414]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-mtlp-6/igt@drm_fdi...@virtual-busy-idle-all.html * igt@feature_discovery@chamelium: - shard-dg2: NOTRUN -> [SKIP][5] ([i915#4854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-dg2-1/igt@feature_discov...@chamelium.html * igt@gem_close_race@multigpu-basic-threads: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#7697]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-dg2-1/igt@gem_close_r...@multigpu-basic-threads.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#8562]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-dg2-12/igt@gem_cre...@create-ext-set-pat.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-dg2: [PASS][8] -> [FAIL][9] ([fdo#103375]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-dg2-6/igt@gem_ctx_isolation@preservation...@vcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-dg2-11/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@heartbeat-hang: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#8555]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-dg2-2/igt@gem_ctx_persiste...@heartbeat-hang.html * igt@gem_ctx_persistence@hostile: - shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1099]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-snb2/igt@gem_ctx_persiste...@hostile.html * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0: - shard-dg2: NOTRUN -> [SKIP][12] ([i915#5882]) +9 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-dg2-1/igt@gem_ctx_persistence@saturated-hostile-nopree...@ccs0.html * igt@gem_eio@hibernate: - shard-dg2: NOTRUN -> [ABORT][13] ([i915#7975] / [i915#8213]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-dg2-12/igt@gem_...@hibernate.html * igt@gem_eio@in-flight-contexts-immediate: - shard-mtlp: [PASS][14] -> [ABORT][15] ([i915#8503]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-mtlp-7/igt@gem_...@in-flight-contexts-immediate.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-mtlp-1/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_exec_balancer@bonded-pair: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#4771]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-dg2-1/igt@gem_exec_balan...@bonded-pair.html * igt@gem_exec_capture@pi@vcs1: - shard-mtlp: [PASS][17] -> [FAIL][18] ([i915#4475] / [i915#7765]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-mtlp-5/igt@gem_exec_capture@p...@vcs1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-mtlp-3/igt@gem_exec_capture@p...@vcs1.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#2846]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-glk1/igt@gem_exec_f...@basic-deadline.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/shard-glk5/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-rkl: [PASS][21] -> [FAIL][22] ([i915#2842]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/shard-rkl-7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [22]: htt
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Force a reset on internal GuC error (rev2)
== Series Details == Series: drm/i915/guc: Force a reset on internal GuC error (rev2) URL : https://patchwork.freedesktop.org/series/118890/ State : success == Summary == CI Bug Log - changes from CI_DRM_13524 -> Patchwork_118890v2 Summary --- **WARNING** Minor unknown changes coming with Patchwork_118890v2 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118890v2, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/index.html Participating hosts (40 -> 39) -- Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_118890v2: ### IGT changes ### Warnings * igt@i915_module_load@load: - bat-adlp-11:[ABORT][1] ([i915#4423]) -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-adlp-11/igt@i915_module_l...@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-adlp-11/igt@i915_module_l...@load.html Known issues Here are the changes found in Patchwork_118890v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-adlp-11:NOTRUN -> [SKIP][3] ([i915#7456]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-adlp-11/igt@debugfs_t...@basic-hwmon.html * igt@gem_tiled_pread_basic: - bat-adlp-11:NOTRUN -> [SKIP][4] ([i915#3282]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-adlp-11/igt@gem_tiled_pread_basic.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [PASS][5] -> [DMESG-FAIL][6] ([i915#7059]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][7] -> [ABORT][8] ([i915#4983] / [i915#7911] / [i915#7920]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-rpls-1/igt@i915_selftest@l...@requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-rpls-1/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@slpc: - bat-mtlp-8: NOTRUN -> [DMESG-WARN][9] ([i915#6367]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-mtlp-8/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#6645]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium_frames@hdmi-crc-fast: - bat-adlp-11:NOTRUN -> [SKIP][11] ([i915#7828]) +7 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-adlp-11/igt@kms_chamelium_fra...@hdmi-crc-fast.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#7828]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-mtlp-8/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-adlp-11:NOTRUN -> [ABORT][13] ([i915#4423]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-adlp-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html Possible fixes * igt@i915_selftest@live@slpc: - bat-mtlp-6: [DMESG-WARN][14] ([i915#6367]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-mtlp-6/igt@i915_selftest@l...@slpc.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-mtlp-6/igt@i915_selftest@l...@slpc.html Warnings * igt@i915_selftest@live@requests: - bat-mtlp-8: [ABORT][16] ([i915#7982]) -> [DMESG-FAIL][17] ([i915#8497]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-mtlp-8/igt@i915_selftest@l...@requests.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@reset: - bat-rpls-2: [ABORT][18] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347]) -> [ABORT][19] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#7981] / [i915#8347]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-rpls-2/igt@i915_selftest@l...@reset.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v2/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@kms_psr@primary_page_flip:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Force a reset on internal GuC error (rev2)
== Series Details == Series: drm/i915/guc: Force a reset on internal GuC error (rev2) URL : https://patchwork.freedesktop.org/series/118890/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Force a reset on internal GuC error (rev2)
== Series Details == Series: drm/i915/guc: Force a reset on internal GuC error (rev2) URL : https://patchwork.freedesktop.org/series/118890/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] [PATCH v2] drm/i915/guc: Force a reset on internal GuC error
From: John Harrison
If GuC hits an internal error (and survives long enough to report it
to the KMD), it is basically toast and will stop until a GT reset and
subsequent GuC reload is performed. Previously, the KMD just printed
an error message and then waited for the heartbeat to eventually kick
in and trigger a reset (assuming the heartbeat had not been disabled).
Instead, force the reset immediately to guarantee that it happens and
to eliminate the very long heartbeat delay. The captured error state
is also more likely to be useful if captured at the time of the error
rather than many seconds later.
Note that it is not possible to trigger a reset from with the G2H
handler itself. The reset prepare process involves flushing
outstanding G2H contents. So a deadlock could result. Instead, the G2H
handler queues a worker thread to do the reset asynchronously.
v2: Flush the worker on suspend and shutdown. Add rate limiting to
prevent spam from a totally dead system (review feedback from Daniele).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 38 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 15 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +---
3 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 569b5fe94c416..12a817b762334 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -159,6 +159,21 @@ static void gen11_disable_guc_interrupts(struct intel_guc
*guc)
gen11_reset_guc_interrupts(guc);
}
+static void guc_dead_worker_func(struct work_struct *w)
+{
+ struct intel_guc *guc = container_of(w, struct intel_guc,
dead_guc_worker);
+ struct intel_gt *gt = guc_to_gt(guc);
+ unsigned long last = guc->last_dead_guc_jiffies;
+ unsigned long delta = jiffies_to_msecs(jiffies - last);
+
+ if (delta < 500) {
+ intel_gt_set_wedged(gt);
+ } else {
+ intel_gt_handle_error(gt, ALL_ENGINES, I915_ERROR_CAPTURE,
"dead GuC");
+ guc->last_dead_guc_jiffies = jiffies;
+ }
+}
+
void intel_guc_init_early(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -171,6 +186,8 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_slpc_init_early(&guc->slpc);
intel_guc_rc_init_early(guc);
+ INIT_WORK(&guc->dead_guc_worker, guc_dead_worker_func);
+
mutex_init(&guc->send_mutex);
spin_lock_init(&guc->irq_lock);
if (GRAPHICS_VER(i915) >= 11) {
@@ -461,6 +478,8 @@ void intel_guc_fini(struct intel_guc *guc)
if (!intel_uc_fw_is_loadable(&guc->fw))
return;
+ flush_work(&guc->dead_guc_worker);
+
if (intel_guc_slpc_is_used(guc))
intel_guc_slpc_fini(&guc->slpc);
@@ -585,6 +604,20 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
return ret;
}
+int intel_guc_crash_process_msg(struct intel_guc *guc, u32 action)
+{
+ if (action == INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED)
+ guc_err(guc, "Crash dump notification\n");
+ else if (action == INTEL_GUC_ACTION_NOTIFY_EXCEPTION)
+ guc_err(guc, "Exception notification\n");
+ else
+ guc_err(guc, "Unknown crash notification: 0x%04X\n", action);
+
+ queue_work(system_unbound_wq, &guc->dead_guc_worker);
+
+ return 0;
+}
+
int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
const u32 *payload, u32 len)
{
@@ -601,6 +634,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
*guc,
if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
guc_err(guc, "Received early exception notification!\n");
+ if (msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
INTEL_GUC_RECV_MSG_EXCEPTION))
+ queue_work(system_unbound_wq, &guc->dead_guc_worker);
+
return 0;
}
@@ -640,6 +676,8 @@ int intel_guc_suspend(struct intel_guc *guc)
return 0;
if (intel_guc_submission_is_used(guc)) {
+ flush_work(&guc->dead_guc_worker);
+
/*
* This H2G MMIO command tears down the GuC in two steps. First
it will
* generate a G2H CTB for every active context indicating a
reset. In
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 8dc291ff00935..6c392bad29c19 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -266,6 +266,20 @@ struct intel_guc {
unsigned long last_stat_jiffies;
} timestamp;
+ /**
+* @dead_guc_worker: Asynchronous worker thread for forcing a GuC reset.
+* Specifically used when the G2H handler wants to issue a reset. Resets
+* require flushing the G2H queue.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec
== Series Details == Series: drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec URL : https://patchwork.freedesktop.org/series/122479/ State : success == Summary == CI Bug Log - changes from CI_DRM_13524 -> Patchwork_122479v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/index.html Participating hosts (40 -> 39) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_122479v1 that come from known issues: ### IGT changes ### Issues hit * igt@core_auth@basic-auth: - bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#8011]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-adlp-11/igt@core_a...@basic-auth.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-6: [PASS][2] -> [DMESG-FAIL][3] ([i915#7059]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][4] -> [ABORT][5] ([i915#4983] / [i915#7461] / [i915#8347] / [i915#8384]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-rpls-1/igt@i915_selftest@l...@reset.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#6645]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#7828]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-mtlp-8/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html Possible fixes * igt@i915_selftest@live@requests: - bat-mtlp-8: [ABORT][9] ([i915#7982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-mtlp-8/igt@i915_selftest@l...@requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@slpc: - bat-mtlp-6: [DMESG-WARN][11] ([i915#6367]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-mtlp-6/igt@i915_selftest@l...@slpc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-mtlp-6/igt@i915_selftest@l...@slpc.html Warnings * igt@i915_module_load@load: - bat-adlp-11:[ABORT][13] ([i915#4423]) -> [DMESG-WARN][14] ([i915#4423]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-adlp-11/igt@i915_module_l...@load.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-adlp-11/igt@i915_module_l...@load.html * igt@i915_selftest@live@reset: - bat-rpls-2: [ABORT][15] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347]) -> [ABORT][16] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#7981] / [i915#8347]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-rpls-2/igt@i915_selftest@l...@reset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@kms_psr@cursor_plane_move: - bat-rplp-1: [SKIP][17] ([i915#1072]) -> [ABORT][18] ([i915#8469] / [i915#8668]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13524/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122479v1/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645 [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059 [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7981]: https://gitlab.free
Re: [Intel-gfx] [PATCH] drm/i915/display: Remove unused POWER_DOMAIN_MASK
On Tue, Aug 15, 2023 at 05:13:44PM -0300, Gustavo Sousa wrote:
> That macro became unused with commit 323286c81245 ("drm/i915: Move the
> power domain->well mappings to intel_display_power_map.c").
>
> Signed-off-by: Gustavo Sousa
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 9e01054c2430..71d70bd9fd82 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -338,8 +338,6 @@ void intel_display_power_set_target_dc_state(struct
> drm_i915_private *dev_priv,
> mutex_unlock(&power_domains->lock);
> }
>
> -#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
> -
> static void __async_put_domains_mask(struct i915_power_domains
> *power_domains,
>struct intel_power_domain_mask *mask)
> {
> --
> 2.41.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec
== Series Details == Series: drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec URL : https://patchwork.freedesktop.org/series/122479/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec
== Series Details == Series: drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec URL : https://patchwork.freedesktop.org/series/122479/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Remove unused POWER_DOMAIN_MASK
== Series Details == Series: drm/i915/display: Remove unused POWER_DOMAIN_MASK URL : https://patchwork.freedesktop.org/series/122478/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13523 -> Patchwork_122478v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122478v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122478v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/index.html Participating hosts (41 -> 40) -- Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122478v1: ### IGT changes ### Possible regressions * igt@gem_busy@busy@all-engines: - bat-mtlp-8: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13523/bat-mtlp-8/igt@gem_busy@b...@all-engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/bat-mtlp-8/igt@gem_busy@b...@all-engines.html Known issues Here are the changes found in Patchwork_122478v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-glk-j4005: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13523/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [PASS][7] -> [DMESG-FAIL][8] ([i915#7059]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13523/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#7913]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][10] -> [DMESG-FAIL][11] ([i915#8497]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13523/bat-mtlp-8/igt@i915_selftest@l...@requests.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@slpc: - bat-rpls-2: NOTRUN -> [DMESG-WARN][12] ([i915#6367]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html - bat-mtlp-8: [PASS][13] -> [DMESG-WARN][14] ([i915#6367]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13523/bat-mtlp-8/igt@i915_selftest@l...@slpc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/bat-mtlp-8/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_frames@hdmi-crc-fast: - fi-kbl-soraka: NOTRUN -> [SKIP][15] ([fdo#109271]) +15 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-rpls-2: NOTRUN -> [SKIP][16] ([i915#7828]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#1845] / [i915#5354]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-rpls-2: NOTRUN -> [SKIP][18] ([i915#1845]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122478v1/bat-rpls-2/igt@kms_pipe_crc_ba...@suspend-read-crc.html Possible fixes * igt@fbdev@eof: - fi-kbl-soraka: [ABORT][19] -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13523/fi-kbl-soraka/igt@fb...@eof.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1224
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Remove Wa_15010599737
On Mon, Aug 14, 2023 at 08:04:54AM -0700, Matt Roper wrote: > On Mon, Aug 14, 2023 at 08:32:15PM +0530, Shekhar Chauhan wrote: > > Since this Wa is specific to DirectX, this is not required on Linux. > > > > Signed-off-by: Shekhar Chauhan > > Reviewed-by: Matt Roper > > Too bad the hardware teams didn't do a better job of documenting this so > that we would have known earlier. Applied to drm-intel-gt-next. Thanks for the patch. Matt > > > Matt > > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 --- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 --- > > 2 files changed, 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 718cb2c80f79..15b82d37486b 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -412,9 +412,6 @@ > > > > #define XEHP_CULLBIT1 MCR_REG(0x6100) > > > > -#define CHICKEN_RASTER_1 MCR_REG(0x6204) > > -#define DIS_SF_ROUND_NEAREST_EVENREG_BIT(8) > > - > > #define CHICKEN_RASTER_2 MCR_REG(0x6208) > > #define TBIMR_FAST_CLIP REG_BIT(5) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 01807a7dd2c1..5aa0d3f23c6b 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -805,9 +805,6 @@ static void dg2_ctx_workarounds_init(struct > > intel_engine_cs *engine, > > IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > > wa_mcr_masked_en(wal, XEHP_PSS_MODE2, > > SCOREBOARD_STALL_FLUSH_CONTROL); > > > > - /* Wa_15010599737:dg2 */ > > - wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > > - > > /* Wa_18019271663:dg2 */ > > wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); > > } > > -- > > 2.34.1 > > > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Remove unused POWER_DOMAIN_MASK
== Series Details == Series: drm/i915/display: Remove unused POWER_DOMAIN_MASK URL : https://patchwork.freedesktop.org/series/122478/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Remove unused POWER_DOMAIN_MASK
== Series Details == Series: drm/i915/display: Remove unused POWER_DOMAIN_MASK URL : https://patchwork.freedesktop.org/series/122478/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/pxp/mtl: Update pxp-firmware response timeout
On Tue, 2023-08-15 at 13:29 -0700, Teres Alexis, Alan Previn wrote:
> Update the max GSC-fw response time to match updated internal
> fw specs. Because this response time is an SLA on the firmware,
> not inclusive of i915->GuC->HW handoff latency, when submitting
> requests to the GSC fw via intel_gsc_uc_heci_cmd_submit_nonpriv,
> start the count after the request hits the GSC command streamer.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 3 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h| 6 +++---
> 2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> index 89ed5ee9cded..ae45855594ac 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> @@ -186,6 +186,9 @@ intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc
> *gsc,
> i915_request_add(rq);
>
> if (!err) {
> + if (wait_for(i915_request_started(rq), 200))
> + drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm,
> + "Delay in gsc-heci-non-priv submission to
> gsccs-hw");
alan: offline discussion with Daniele, Daniele provided the following review
comments:
We should add this wait-check for both priv and non-priv but we should increase
the
timeout to be more than the guaranteed fw response time of 1 other message
(since we
have a total of 2 contexts that could be sending messages concurrently at any
time
including this one)... so maybe timeout of the new GSC_REPLY_LATENCY_MS + 150.
More importantly, he highlighted the fact that we should wait for the
request-started
AND ensure there as no error in request status.
[snip]
[Intel-gfx] [PATCH v3 1/3] drm/i915/pxp/mtl: Update pxp-firmware response timeout
Update the max GSC-fw response time to match updated internal
fw specs. Because this response time is an SLA on the firmware,
not inclusive of i915->GuC->HW handoff latency, when submitting
requests to the GSC fw via intel_gsc_uc_heci_cmd_submit_nonpriv,
start the count after the request hits the GSC command streamer.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h| 6 +++---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
index 89ed5ee9cded..ae45855594ac 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
@@ -186,6 +186,9 @@ intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc
*gsc,
i915_request_add(rq);
if (!err) {
+ if (wait_for(i915_request_started(rq), 200))
+ drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm,
+ "Delay in gsc-heci-non-priv submission to
gsccs-hw");
if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
msecs_to_jiffies(timeout_ms)) < 0)
err = -ETIME;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
index 298ad38e6c7d..4368f010bbd3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
@@ -10,10 +10,10 @@
struct intel_pxp;
-#define GSC_REPLY_LATENCY_MS 210
+#define GSC_REPLY_LATENCY_MS 350
/*
- * Max FW response time is 200ms, to which we add 10ms to account for overhead
- * such as request preparation, GuC submission to hw and pipeline completion
times.
+ * Max FW response time is 350ms, but this should be counted from the time the
+ * command has hit the GSC-CS hardware, not the preceding handoff to GuC CTB.
*/
#define GSC_PENDING_RETRY_MAXCOUNT 40
#define GSC_PENDING_RETRY_PAUSE_MS 50
--
2.39.0
[Intel-gfx] [PATCH v3 3/3] drm/i915/gt/pxp: User PXP contexts requires runalone bit in lrc
On Meteorlake onwards, HW specs require that all user contexts that
run on render or compute engines and require PXP must enforce
run-alone bit in lrc. Add this enforcement for protected contexts.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 957d0aeb0c02..c7cab1c727ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -845,6 +845,29 @@ lrc_setup_indirect_ctx(u32 *regs,
lrc_ring_indirect_offset_default(engine) << 6;
}
+static bool ctx_needs_runalone(const struct intel_context *ce)
+{
+ struct i915_gem_context *gem_ctx;
+ bool ctx_is_protected = false;
+
+ /*
+* On MTL and newer platforms, protected contexts require setting
+* the LRC run-alone bit or else the encryption will not happen.
+*/
+ if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) &&
+ (ce->engine->class == COMPUTE_CLASS || ce->engine->class ==
RENDER_CLASS)) {
+ rcu_read_lock();
+ gem_ctx = rcu_dereference(ce->gem_context);
+ if (gem_ctx)
+ ctx_is_protected = gem_ctx->uses_protected_content;
+ rcu_read_unlock();
+ if (ctx_is_protected)
+ return true;
+ }
+
+ return false;
+}
+
static void init_common_regs(u32 * const regs,
const struct intel_context *ce,
const struct intel_engine_cs *engine,
@@ -860,6 +883,8 @@ static void init_common_regs(u32 * const regs,
if (GRAPHICS_VER(engine->i915) < 11)
ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
CTX_CTRL_RS_CTX_ENABLE);
+ if (ctx_needs_runalone(ce))
+ ctl |= _MASKED_BIT_ENABLE(BIT(7));
regs[CTX_CONTEXT_CONTROL] = ctl;
regs[CTX_TIMESTAMP] = ce->stats.runtime.last;
--
2.39.0
[Intel-gfx] [PATCH v3 2/3] drm/i915/pxp/mtl: Update pxp-firmware packet size
Update the GSC-fw input/output HECI packet size to match updated internal fw specs. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h index 0165d38fbead..fa460491ce42 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h @@ -15,7 +15,7 @@ #define PXP43_CMDID_INIT_SESSION 0x0036 /* PXP-Packet sizes for MTL's GSCCS-HECI instruction */ -#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K) +#define PXP43_MAX_HECI_INOUT_SIZE (SZ_64K) /* PXP-Packet size for MTL's NEW_HUC_AUTH instruction */ #define PXP43_HUC_AUTH_INOUT_SIZE (SZ_4K) -- 2.39.0
[Intel-gfx] [PATCH v3 0/3] drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec
For MTL, update the GSC-HECI packet size and the max firmware response timeout to match internal fw specs. Enforce setting run-alone bit in LRC for protected contexts. Changes from prio revs: v2: - Patch #3: fix sparse warning reported by kernel test robot. v1: - N/A (Re-test) Signed-off-by: Alan Previn Alan Previn (3): drm/i915/pxp/mtl: Update pxp-firmware response timeout drm/i915/pxp/mtl: Update pxp-firmware packet size drm/i915/gt/pxp: User PXP contexts requires runalone bit in lrc drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +++ .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 3 +++ .../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h| 6 ++--- 4 files changed, 32 insertions(+), 4 deletions(-) base-commit: 85f20fb339f05ec4221bb295c13e46061c5c566f -- 2.39.0
[Intel-gfx] [PATCH] drm/i915/display: Remove unused POWER_DOMAIN_MASK
That macro became unused with commit 323286c81245 ("drm/i915: Move the
power domain->well mappings to intel_display_power_map.c").
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9e01054c2430..71d70bd9fd82 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -338,8 +338,6 @@ void intel_display_power_set_target_dc_state(struct
drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
}
-#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
-
static void __async_put_domains_mask(struct i915_power_domains *power_domains,
struct intel_power_domain_mask *mask)
{
--
2.41.0
Re: [Intel-gfx] [PATCH] drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI
On Mon, 07 Aug 2023, Suraj Kandpal wrote: > Assign explicit value of 12 at 8bpp as per Table E2 of DSC 1.1 for DSI > panels even though we already use calculations from CModel for > first_line_bpg_offset. > The reason being some DSI monitors may have not have added the > change in errata for the calculation of first_line_bpg_offset. > > Signed-off-by: Suraj Kandpal > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index f7ebc146f96d..2376d5000d78 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1585,6 +1585,11 @@ static int gen11_dsi_dsc_compute_config(struct > intel_encoder *encoder, > if (ret) > return ret; > > + /* From Table E-2 in DSC 1.1*/ > + if (vdsc_cfg->dsc_version_minor == 1 && > + vdsc_cfg->bits_per_pixel == 128) So, vdsc_cfg->bits_per_pixel has 4 fractional bits, and that's 8 bpp compressed? Better describe it that way, instead of as 128. But... looking around, in intel_vdsc.c we set: pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); and we have: #define DSC_BPP(bpp)((bpp) << 4) however, when reading it back in intel_dsc_get_config(), it's just directly: vdsc_cfg->bits_per_pixel = pps1; Are we always sending x16 bpp in PPS? BR, Jani. > + vdsc_cfg->first_line_bpg_offset = 12; > + > /* DSI specific sanity checks on the common code */ > drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); > drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Align igt_spinner_create_request with hangcheck
On Tue, Aug 15, 2023 at 09:53:44AM -0700, Jonathan Cavitt wrote: > Align igt_spinner_create_request with the hang_create_request > implementation in selftest_hangcheck.c. > > Signed-off-by: Jonathan Cavitt Reviewed-by: Matt Roper For the second patch in the series, the general direction looks good to me, but I'm not familiar enough with the spinner implementation and context handling to do a detailed review there. Hopefully someone more familiar with that code can take a look. Matt > --- > drivers/gpu/drm/i915/selftests/igt_spinner.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c > b/drivers/gpu/drm/i915/selftests/igt_spinner.c > index 0f064930ef11..8c3e1f20e5a1 100644 > --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c > +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c > @@ -179,6 +179,9 @@ igt_spinner_create_request(struct igt_spinner *spin, > > *batch++ = arbitration_command; > > + memset32(batch, MI_NOOP, 128); > + batch += 128; > + > if (GRAPHICS_VER(rq->i915) >= 8) > *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1; > else if (IS_HASWELL(rq->i915)) > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
[Intel-gfx] ✗ Fi.CI.BAT: failure for Drop support for pre-production DG2 hardware
== Series Details == Series: Drop support for pre-production DG2 hardware URL : https://patchwork.freedesktop.org/series/122469/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13520 -> Patchwork_122469v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122469v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122469v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/index.html Participating hosts (39 -> 39) -- Additional (1): bat-rpls-2 Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122469v1: ### IGT changes ### Possible regressions * igt@i915_module_load@load: - fi-apl-guc: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-apl-guc/igt@i915_module_l...@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/fi-apl-guc/igt@i915_module_l...@load.html Known issues Here are the changes found in Patchwork_122469v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rpls-2: NOTRUN -> [SKIP][3] ([i915#7456]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-rpls-2: NOTRUN -> [SKIP][4] ([i915#1849] / [i915#2582]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@fb...@info.html * igt@fbdev@read: - bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#2582]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@fb...@read.html * igt@gem_lmem_swapping@verify-random: - bat-rpls-2: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_tiled_pread_basic: - bat-rpls-2: NOTRUN -> [SKIP][7] ([i915#3282]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-rpls-2: NOTRUN -> [SKIP][8] ([i915#7561]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-rpls-2: NOTRUN -> [SKIP][9] ([i915#6621]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [PASS][10] -> [DMESG-FAIL][11] ([i915#7059]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@gt_pm: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][12] ([i915#4258] / [i915#7913]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@slpc: - bat-rpls-2: NOTRUN -> [DMESG-WARN][13] ([i915#6367]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html - bat-rpls-1: [PASS][14] -> [DMESG-WARN][15] ([i915#6367]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/bat-rpls-1/igt@i915_selftest@l...@slpc.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-2: NOTRUN -> [ABORT][16] ([i915#6687] / [i915#7978] / [i915#8668]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_busy@basic: - bat-rpls-2: NOTRUN -> [SKIP][17] ([i915#1845]) +15 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@kms_b...@basic.html * igt@kms_chamelium_edid@hdmi-edid-read: - bat-rpls-2: NOTRUN -> [SKIP][18] ([i915#7828]) +7 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@kms_chamelium_e...@hdmi-edid-read.html * igt@kms_flip@basic-flip-vs-dpms: - bat-rpls-2: NOTRUN -> [SKIP][19] ([i915#3637]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122469v1/bat-rpls-2/igt@kms_f...@basic-flip-vs-dpms.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Drop support for pre-production DG2 hardware
== Series Details == Series: Drop support for pre-production DG2 hardware URL : https://patchwork.freedesktop.org/series/122469/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Drop support for pre-production DG2 hardware
== Series Details == Series: Drop support for pre-production DG2 hardware URL : https://patchwork.freedesktop.org/series/122469/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/guc: Close deregister-context race against CT-loss
On Tue, 2023-08-15 at 09:56 -0400, Vivi, Rodrigo wrote:
> On Mon, Aug 14, 2023 at 06:12:09PM -0700, Alan Previn wrote:
> > If we are at the end of suspend or very early in resume
> > its possible an async fence signal could lead us to the
> > execution of the context destruction worker (after the
> > prior worker flush).
[snip]
>
> > @@ -3199,10 +3206,20 @@ static inline void guc_lrc_desc_unpin(struct
> > intel_context *ce)
> > if (unlikely(disabled)) {
> > release_guc_id(guc, ce);
> > __guc_context_destroy(ce);
> > - return;
> > + return 0;
> > + }
> > +
> > + if (deregister_context(ce, ce->guc_id.id)) {
> > + /* Seal race with concurrent suspend by unrolling */
> > + spin_lock_irqsave(&ce->guc_state.lock, flags);
> > + set_context_registered(ce);
> > + clr_context_destroyed(ce);
> > + intel_gt_pm_put(gt);
>
> how sure we are this is not calling unbalanced puts?
alan: in this function (guc_lrc_desc_unpin), the summarized flow is:
check-status-stuff
if guc-is-not-disabled, take-pm, change ctx-state-bits
[implied else] if guc-is-disabled, scub-ctx and return
thus derigster_context is only called if we didnt exit, i.e. when
guc-is-not-disabled, i.e. after the pm was taken.
> could we wrap this in some existent function to make this clear?
alan: yeah - not so readible as it now - let me tweak this function and make it
cleaner
>
> > + spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> > + return -ENODEV;
> > }
> >
> > - deregister_context(ce, ce->guc_id.id);
> > + return 0;
> > }
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/gt: Timeout when waiting for idle in suspending
Thanks Rodrigo - agreed on everything below - will re-rev.
On Tue, 2023-08-15 at 09:51 -0400, Vivi, Rodrigo wrote:
> On Mon, Aug 14, 2023 at 06:12:10PM -0700, Alan Previn wrote:
> > When suspending, add a timeout when calling
> > intel_gt_pm_wait_for_idle else if we have a lost
> > G2H event that holds a wakeref (which would be
> >
[snip]
> > @@ -301,7 +303,10 @@ static void wait_for_suspend(struct intel_gt *gt)
> > intel_gt_retire_requests(gt);
> > }
> >
> > - intel_gt_pm_wait_for_idle(gt);
> > + /* we are suspending, so we shouldn't be waiting forever */
> > + if (intel_gt_pm_wait_timeout_for_idle(gt, timeout_ms) == -ETIME)
>
> you forgot to change the error code here..^
>
> but maybe we don't even need this here and a simple
> if (intel_gt_pm_wait_timeout_for_idle(gt, timeout_ms)) should be enough
> since the error from the killable one is unlikely and the only place
> I error I could check on that path would be a catastrophic -ERESTARTSYS.
>
> but up to you.
alan: my bad - I'll fix it - but i agree with not needing to check the failure
type.
and I'll keep the error the same ("bailing from...")
[snip]
> > +static inline int intel_gt_pm_wait_timeout_for_idle(struct intel_gt *gt,
> > int timeout_ms)
> > +{
> > + return intel_wakeref_wait_for_idle(>->wakeref, timeout_ms);
> > }
>
> I was going to ask why you created a single use function here, but then I
> noticed the above one. So it makes sense.
> Then I was going to ask why in here you didn't use the same change of
> timeout = 0 in the existent function like you used below, but then I
> noticed that the above function is called in multiple places and the
> patch with this change is much cleaner and the function is static inline
> so your approach was good here.
alan: yes that was my exact reason - thus no impact across other callers.
[snip]
> Please add a documentation for this function making sure you have the
> following
> mentions:
alan: good catch -will do.
>
> /**
> [snip]
> * @timeout_ms: Timeout in ums, 0 means never timeout.
> *
> * Returns 0 on success, -ETIMEDOUT upon a timeout, or the unlikely
> * error propagation from wait_var_event_killable if timeout_ms is 0.
> */
>
> with the return error fixed above and the documentation in place:
>
> Reviewed-by: Rodrigo Vivi
>
> > -int intel_wakeref_wait_for_idle(struct intel_wakeref *wf)
> > +int intel_wakeref_wait_for_idle(struct intel_wakeref *wf, int timeout_ms)
> > {
> > - int err;
> >
[snip]
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Align igt_spinner_create_request with hangcheck
== Series Details == Series: drm/i915/selftests: Align igt_spinner_create_request with hangcheck URL : https://patchwork.freedesktop.org/series/122462/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13520 -> Patchwork_122462v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122462v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122462v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/index.html Participating hosts (39 -> 38) -- Additional (1): bat-rpls-2 Missing(2): fi-snb-2520m fi-pnv-d510 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122462v1: ### IGT changes ### Possible regressions * igt@gem_busy@busy@all-engines: - bat-mtlp-8: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/bat-mtlp-8/igt@gem_busy@b...@all-engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/bat-mtlp-8/igt@gem_busy@b...@all-engines.html * igt@i915_selftest@live@hangcheck: - fi-cfl-guc: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-cfl-guc/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/fi-cfl-guc/igt@i915_selftest@l...@hangcheck.html - bat-jsl-3: [PASS][5] -> [ABORT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/bat-jsl-3/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/bat-jsl-3/igt@i915_selftest@l...@hangcheck.html - fi-kbl-x1275: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-kbl-x1275/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/fi-kbl-x1275/igt@i915_selftest@l...@hangcheck.html - fi-hsw-4770:[PASS][9] -> [ABORT][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html - fi-cfl-8109u: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-cfl-8109u/igt@i915_selftest@l...@hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/fi-cfl-8109u/igt@i915_selftest@l...@hangcheck.html - fi-kbl-8809g: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-kbl-8809g/igt@i915_selftest@l...@hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/fi-kbl-8809g/igt@i915_selftest@l...@hangcheck.html - bat-mtlp-8: [PASS][15] -> [ABORT][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/bat-mtlp-8/igt@i915_selftest@l...@hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/bat-mtlp-8/igt@i915_selftest@l...@hangcheck.html - fi-kbl-guc: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-kbl-guc/igt@i915_selftest@l...@hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/fi-kbl-guc/igt@i915_selftest@l...@hangcheck.html - bat-jsl-1: [PASS][19] -> [ABORT][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/bat-jsl-1/igt@i915_selftest@l...@hangcheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/bat-jsl-1/igt@i915_selftest@l...@hangcheck.html - fi-tgl-1115g4: [PASS][21] -> [ABORT][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-tgl-1115g4/igt@i915_selftest@l...@hangcheck.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/fi-tgl-1115g4/igt@i915_selftest@l...@hangcheck.html - bat-mtlp-6: [PASS][23] -> [ABORT][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/bat-mtlp-6/igt@i915_selftest@l...@hangcheck.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/bat-mtlp-6/igt@i915_selftest@l...@hangcheck.html - fi-skl-6600u: [PASS][25] -> [ABORT][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-skl-6600u/igt@i915_selftest@l...@hangcheck.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122462v1/fi-skl-6600u/igt@i915_selftest@l...@hangcheck.html - fi-apl-guc: [PASS][27] -> [ABORT][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13520/fi-apl-guc/igt@i91
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/selftests: Align igt_spinner_create_request with hangcheck
== Series Details == Series: drm/i915/selftests: Align igt_spinner_create_request with hangcheck URL : https://patchwork.freedesktop.org/series/122462/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Align igt_spinner_create_request with hangcheck
== Series Details == Series: drm/i915/selftests: Align igt_spinner_create_request with hangcheck URL : https://patchwork.freedesktop.org/series/122462/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH v3] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset
On Mon, 14 Aug 2023, Manasi Navare wrote:
> Dual refresh rate (DRR) fastset seamlessly lets refresh rate
> throttle without needing a full modeset.
Is this something different from DRRS, or Dynamic Refresh Rate
Switching?
> However with the recent VRR fastset patches that got merged this
> logic was broken.
Which commits exactly? "recent patches" is a bit vague.
Is there a gitlab issue for this? Is it [1] or is that different?
[1] https://gitlab.freedesktop.org/drm/intel/-/issues/8851
> This is broken because now with VRR fastset
> VRR parameters are calculated by default at the nominal refresh rate say
> 120Hz.
> Now when DRR throttle happens to switch refresh rate to 60Hz, crtc clock
> changes and this throws a mismatch in VRR parameters and fastset logic
> for DRR gets thrown off and full modeset is indicated.
>
> This patch fixes this by ignoring the pipe mismatch for VRR parameters
> in the case of DRR and when VRR is not enabled. With this fix, DRR
> will still throttle seamlessly as long as VRR is not enabled.
>
> This will still need a full modeset for both DRR and VRR operating together
> during the refresh rate throttle and then enabling VRR since now VRR
> parameters need to be recomputed with new crtc clock and written to HW.
>
> This DRR + VRR fastset in conjunction needs more work in the driver and
> will be fixed in later patches.
I admit I have a hard time wrapping my head around the above explanation
with the code changes. :/
I'm hoping describing the "what broke" along with a regressing commit
would help it.
BR,
Jani.
>
> v3:
> Compute new VRR params whenever there is fastset and its non DRRS.
> This will ensure it computes while switching to a fixed RR (Mitul)
>
> v2:
> Check for pipe config mismatch in crtc clock whenever VRR is enabled
>
> Cc: Drew Davenport
> Cc: Ville Syrjälä
> Cc: Sean Paul
> Cc: Mitul Golani
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 763ab569d8f3..2cf3b22adaf7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5352,7 +5352,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
>
> - if (!fastset || !pipe_config->seamless_m_n) {
> + if (!fastset || !pipe_config->seamless_m_n || pipe_config->vrr.enable) {
> PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> }
> @@ -5387,11 +5387,13 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> if (!fastset)
> PIPE_CONF_CHECK_BOOL(vrr.enable);
> - PIPE_CONF_CHECK_I(vrr.vmin);
> - PIPE_CONF_CHECK_I(vrr.vmax);
> - PIPE_CONF_CHECK_I(vrr.flipline);
> - PIPE_CONF_CHECK_I(vrr.pipeline_full);
> - PIPE_CONF_CHECK_I(vrr.guardband);
> + if ((fastset && !pipe_config->seamless_m_n) || pipe_config->vrr.enable)
> {
> + PIPE_CONF_CHECK_I(vrr.vmin);
> + PIPE_CONF_CHECK_I(vrr.vmax);
> + PIPE_CONF_CHECK_I(vrr.flipline);
> + PIPE_CONF_CHECK_I(vrr.pipeline_full);
> + PIPE_CONF_CHECK_I(vrr.guardband);
> + }
>
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dg2: Drop pre-production GT workarounds
On Tue, 15 Aug 2023 10:36:15 -0700, Matt Roper wrote:
>
Hi Matt,
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 04bc1f4a1115..eadbfd2fb9e5 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -3381,25 +3381,6 @@ static int i915_oa_stream_init(struct i915_perf_stream
> *stream,
> intel_engine_pm_get(stream->engine);
> intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
>
> - /*
> - * Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes
> - * OA to lose the configuration state. Prevent this by overriding GUCRC
> - * mode.
> - */
> - if (intel_uc_uses_guc_rc(>->uc) &&
> - (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
> - IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) {
> - ret = intel_guc_slpc_override_gucrc_mode(>->uc.guc.slpc,
> -
> SLPC_GUCRC_MODE_GUCRC_NO_RC6);
> - if (ret) {
> - drm_dbg(&stream->perf->i915->drm,
> - "Unable to override gucrc mode\n");
> - goto err_gucrc;
> - }
> -
> - stream->override_gucrc = true;
> - }
> -
> ret = alloc_oa_buffer(stream);
> if (ret)
> goto err_oa_buf_alloc;
> @@ -3439,7 +3420,6 @@ static int i915_oa_stream_init(struct i915_perf_stream
> *stream,
> if (stream->override_gucrc)
> intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc);
>
> -err_gucrc:
> intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
> intel_engine_pm_put(stream->engine);
>
If we are deleting this, let's basically remove all references to "gucrc"
in this file and includes. So:
* clean up the error path
* Remove stream->override_gucrc
* clean up i915_oa_stream_destroy
Maybe the functions intel_guc_slpc_unset_gucrc_mode and
intel_guc_slpc_override_gucrc_mode can also be removed.
Let's wait to hear from Umesh/Vinay (Cc'd) who implemented this stuff.
Thanks.
--
Ashutosh
[Intel-gfx] [PATCH 3/4] drm/i915/dg2: Drop pre-production GT workarounds
DG2 first production steppings were C0 (for DG2-G10), B1 (for DG2-G11),
and A1 (for DG2-G12). Several workarounds that apply onto to
pre-production hardware can be dropped. Furthermore, several
workarounds that apply to all production steppings can have their
conditions simplified to no longer check the GT stepping. Finally, the
now-unused IS_DG2_GRAPHICS_STEP macro can be dropped.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +---
drivers/gpu/drm/i915/gt/intel_mocs.c| 21 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 6 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 211 +---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 20 +-
drivers/gpu/drm/i915/i915_drv.h | 19 --
drivers/gpu/drm/i915/i915_perf.c| 20 --
drivers/gpu/drm/i915/intel_clock_gating.c | 8 -
8 files changed, 21 insertions(+), 318 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 957d0aeb0c02..bc7ce2c2b959 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1315,29 +1315,6 @@ gen12_emit_cmd_buf_wa(const struct intel_context *ce,
u32 *cs)
return cs;
}
-/*
- * On DG2 during context restore of a preempted context in GPGPU mode,
- * RCS restore hang is detected. This is extremely timing dependent.
- * To address this below sw wabb is implemented for DG2 A steppings.
- */
-static u32 *
-dg2_emit_rcs_hang_wabb(const struct intel_context *ce, u32 *cs)
-{
- *cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ =
i915_mmio_reg_offset(GEN12_STATE_ACK_DEBUG(ce->engine->mmio_base));
- *cs++ = 0x21;
-
- *cs++ = MI_LOAD_REGISTER_REG;
- *cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base));
- *cs++ = i915_mmio_reg_offset(XEHP_CULLBIT1);
-
- *cs++ = MI_LOAD_REGISTER_REG;
- *cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base));
- *cs++ = i915_mmio_reg_offset(XEHP_CULLBIT2);
-
- return cs;
-}
-
/*
* The bspec's tuning guide asks us to program a vertical watermark value of
* 0x3FF. However this register is not saved/restored properly by the
@@ -1362,14 +1339,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
*ce, u32 *cs)
cs = gen12_emit_cmd_buf_wa(ce, cs);
cs = gen12_emit_restore_scratch(ce, cs);
- /* Wa_22011450934:dg2 */
- if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_A0, STEP_B0) ||
- IS_DG2_GRAPHICS_STEP(ce->engine->i915, G11, STEP_A0, STEP_B0))
- cs = dg2_emit_rcs_hang_wabb(ce, cs);
-
/* Wa_16013000631:dg2 */
- if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||
- IS_DG2_G11(ce->engine->i915))
+ if (IS_DG2_G11(ce->engine->i915))
cs = gen8_emit_pipe_control(cs,
PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);
cs = gen12_emit_aux_table_inv(ce->engine, cs);
@@ -1390,8 +1361,7 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context
*ce, u32 *cs)
cs = gen12_emit_restore_scratch(ce, cs);
/* Wa_16013000631:dg2 */
- if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||
- IS_DG2_G11(ce->engine->i915))
+ if (IS_DG2_G11(ce->engine->i915))
if (ce->engine->class == COMPUTE_CLASS)
cs = gen8_emit_pipe_control(cs,
PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 2c014407225c..bf8b42d2d327 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -404,18 +404,6 @@ static const struct drm_i915_mocs_entry dg2_mocs_table[] =
{
MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
};
-static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
- /* Wa_14011441408: Set Go to Memory for MOCS#0 */
- MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
- /* UC - Coherent; GO:Memory */
- MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
- /* UC - Non-Coherent; GO:Memory */
- MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
-
- /* WB - LC */
- MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
-};
-
static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
/* Error */
MOCS_ENTRY(0, 0, L3_3_WB),
@@ -521,13 +509,8 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
table->wb_index = 2;
table->unused_entries_index = 2;
} else if (IS_DG2(i915)) {
- if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
- table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
- table->table = dg2_mocs_table_g10_ax;
- } else {
- table->size = ARRAY_SIZE(dg2_mocs_table);
-
[Intel-gfx] [PATCH 2/4] drm/i915/dg2: Drop pre-production display workarounds
All production DG2 cards have display stepping C0 or later. We can drop Wa_14013215631 (only applies to pre-C0) and make Wa_14010547955 unconditional (applies to everything B0 and beyond). Also drop the now-unused IS_DG2_DISPLAY_STEP macro. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 drivers/gpu/drm/i915/i915_drv.h| 4 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 763ab569d8f3..8c81206ce90d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -726,7 +726,7 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; /* Wa_14010547955:dg2 */ - if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) + if (IS_DG2(dev_priv)) tmp |= DG2_RENDER_CCSTAG_4_3_EN; intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index ffc15d278a39..a408ec2d3958 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2203,10 +2203,6 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) return false; - /* Wa_14013215631 */ - if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) - return false; - return plane_id < PLANE_SPRITE4; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7a8ce7239bc9..7f8fa0eb9dc6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -689,10 +689,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ IS_GRAPHICS_STEP(__i915, since, until)) -#define IS_DG2_DISPLAY_STEP(__i915, since, until) \ - (IS_DG2(__i915) && \ -IS_DISPLAY_STEP(__i915, since, until)) - #define IS_PVC_BD_STEP(__i915, since, until) \ (IS_PONTEVECCHIO(__i915) && \ IS_BASEDIE_STEP(__i915, since, until)) -- 2.41.0
[Intel-gfx] [PATCH 1/4] drm/i915/dg2: Recognize pre-production hardware
The first production SoC steppings for DG2 were C0 (for G10), B1 (for
G11), and A1 (for G12). This corresponds to PCI revision IDs 0x8, 0x5,
and 0x1 respectively. Add this information to the driver's
pre-production detection.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_driver.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index b870c0df081a..0201115746a7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -183,6 +183,9 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
+ pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;
+ pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;
+ pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
if (pre) {
drm_err(&dev_priv->drm, "This is a pre-production stepping. "
--
2.41.0
[Intel-gfx] [PATCH 0/4] Drop support for pre-production DG2 hardware
We generally only keep support for pre-production steppings and workarounds around in the driver until the next major platform is implemented. Now that MTL is in good shape in i915 (and subsequent platforms like LNL are being implemented solely on the Xe driver) it's time to drop the DG2 pre-production hardware support. DG2 production hardware always has display stepping C0 or later. On the GT side, production hardware starts with C0 (for DG2-G10), B1 (for DG2-G11), and A1 (for DG2-G12). This means we can drop quite a few pre-production workarounds, and simplify the handling of several others. Matt Roper (4): drm/i915/dg2: Recognize pre-production hardware drm/i915/dg2: Drop pre-production display workarounds drm/i915/dg2: Drop pre-production GT workarounds drm/i915: Tidy workaround definitions drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/skl_universal_plane.c| 4 - drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 21 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 6 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 301 +++--- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 20 +- drivers/gpu/drm/i915/i915_driver.c| 3 + drivers/gpu/drm/i915/i915_drv.h | 23 -- drivers/gpu/drm/i915/i915_perf.c | 20 -- drivers/gpu/drm/i915/intel_clock_gating.c | 8 - 11 files changed, 66 insertions(+), 376 deletions(-) -- 2.41.0
[Intel-gfx] [PATCH 4/4] drm/i915: Tidy workaround definitions
Removal of the DG2 pre-production workarounds has left duplicate
condition blocks in a couple places, as well as some inconsistent
platform ordering. Reshuffle and consolidate some of the workarounds to
reduce the number of condition blocks and to more consistently follow
the "newest platform first" convention. Code movement only; no
functional change.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 100 +---
1 file changed, 46 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 7b426f3015b3..69973dc51828 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2337,6 +2337,19 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
true);
}
+ if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
+ IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /*
+* Wa_1606700617:tgl,dg1,adl-p
+* Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
+* Wa_14010826681:tgl,dg1,rkl,adl-p
+* Wa_18019627453:dg2
+*/
+ wa_masked_en(wal,
+GEN9_CS_DEBUG_MODE1,
+FF_DOP_CLOCK_GATE_DISABLE);
+ }
+
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
@@ -2350,19 +2363,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
*/
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
- }
- if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) ||
- IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
- /*
-* Wa_1606700617:tgl,dg1,adl-p
-* Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
-* Wa_14010826681:tgl,dg1,rkl,adl-p
-* Wa_18019627453:dg2
-*/
- wa_masked_en(wal,
-GEN9_CS_DEBUG_MODE1,
-FF_DOP_CLOCK_GATE_DISABLE);
+ /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
+ wa_mcr_masked_en(wal,
+GEN10_SAMPLER_MODE,
+ENABLE_SMALLPL);
}
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
@@ -2389,14 +2394,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
- if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) ||
- IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
- /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
- wa_mcr_masked_en(wal,
-GEN10_SAMPLER_MODE,
-ENABLE_SMALLPL);
- }
-
if (GRAPHICS_VER(i915) == 11) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
@@ -2877,6 +2874,9 @@ general_render_compute_wa_init(struct intel_engine_cs
*engine, struct i915_wa_li
/* Wa_22013037850 */
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
DISABLE_128B_EVICTION_COMMAND_UDW);
+
+ /* Wa_18017747507 */
+ wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
POLYGON_TRIFAN_LINELOOP_DISABLE);
}
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
@@ -2887,11 +2887,20 @@ general_render_compute_wa_init(struct intel_engine_cs
*engine, struct i915_wa_li
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
DISABLE_D8_D16_COASLESCE);
}
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
- IS_DG2(i915)) {
- /* Wa_18017747507 */
- wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
POLYGON_TRIFAN_LINELOOP_DISABLE);
+ if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) {
+ /* Wa_14015227452:dg2,pvc */
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
+
+ /* Wa_16015675438:dg2,pvc */
+ wa_masked_en(wal, FF_SLICE_CS_CHICKEN2,
GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
+ }
+
+ if (IS_DG2(i915)) {
+ /*
+* Wa_16011620976:dg2_g11
+* Wa_22015475538:dg2
+*/
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
}
if (IS_DG2_G11(i915)) {
@@ -2906,6 +2915,18 @@ general_render_compute_wa_init(struct intel_engine_cs
*e
Re: [Intel-gfx] [PATCH v2 4/4] drm/915/display: configure SDP split for DP-MST
On Tue, 15 Aug 2023, Vinod Govindapillai wrote: > Extend the SDP split audio config for DP-MST > > Signed-off-by: Vinod Govindapillai > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > drivers/gpu/drm/i915/display/intel_dp.h | 4 > drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++ > 3 files changed, 8 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 0eb072a78d44..269828e22437 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2233,7 +2233,7 @@ intel_dp_compute_output_format(struct intel_encoder > *encoder, > return ret; > } > > -static void > +void > intel_dp_audio_compute_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config, > struct drm_connector_state *conn_state, > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h > b/drivers/gpu/drm/i915/display/intel_dp.h > index e7b515b685ac..b8516a34cfaf 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -65,6 +65,10 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > struct link_config_limits *limits, > int timeslots, > bool recompute_pipe_bpp); > +void intel_dp_audio_compute_config(struct intel_encoder *encoder, > +struct intel_crtc_state *pipe_config, > +struct drm_connector_state *conn_state, > +struct intel_dp *intel_dp); > bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); > bool intel_dp_is_edp(struct intel_dp *intel_dp); > bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 8881cfd41ee7..05228c006a1b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -309,10 +309,6 @@ static int intel_dp_mst_compute_config(struct > intel_encoder *encoder, > pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; > pipe_config->has_pch_encoder = false; > > - pipe_config->has_audio = > - intel_dp_has_audio(encoder, conn_state, intel_dp) && > - intel_audio_compute_config(encoder, pipe_config, conn_state); Yeah, so there shouldn't be an intemediate step where you call intel_dp_has_audio() directly from mst code. You just switch from the current code to calling intel_dp_audio_compute_config(). BR, Jani. > - > /* >* for MST we always configure max link bw - the spec doesn't >* seem to suggest we should do otherwise. > @@ -375,6 +371,7 @@ static int intel_dp_mst_compute_config(struct > intel_encoder *encoder, > pipe_config->lane_lat_optim_mask = > > bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); > > + intel_dp_audio_compute_config(encoder, pipe_config, conn_state, > intel_dp); > intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); > > return 0; > @@ -779,6 +776,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state > *state, > intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, >FECSTALL_DIS_DPTSTREAM_DPTTG); > > + intel_audio_sdp_split_update(pipe_config); > + > intel_enable_transcoder(pipe_config); > > intel_crtc_vblank_on(pipe_config); -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/display: combine DP audio compute config steps
On Tue, 15 Aug 2023, Vinod Govindapillai wrote:
> Combine all DP audio configs into a single function
This should've been the first step.
>
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 97a14afbcfe8..0eb072a78d44 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2236,11 +2236,16 @@ intel_dp_compute_output_format(struct intel_encoder
> *encoder,
> static void
> intel_dp_audio_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> - struct drm_connector_state *conn_state)
> + struct drm_connector_state *conn_state,
> + struct intel_dp *intel_dp)
No need to pass intel_dp around. And usually if it's necessary, it's the
kind of context parameter that should be one of the first parameters.
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct drm_connector *connector = conn_state->connector;
>
> + pipe_config->has_audio =
> + intel_dp_has_audio(encoder, conn_state, intel_dp) &&
> + intel_audio_compute_config(encoder, pipe_config, conn_state);
> +
> pipe_config->sdp_split_enable = pipe_config->has_audio &&
> intel_dp_is_uhbr(pipe_config);
>
> @@ -2264,10 +2269,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port !=
> PORT_A)
> pipe_config->has_pch_encoder = true;
>
> - pipe_config->has_audio =
> - intel_dp_has_audio(encoder, conn_state, intel_dp) &&
> - intel_audio_compute_config(encoder, pipe_config, conn_state);
> -
> fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
> if (intel_dp_is_edp(intel_dp) && fixed_mode) {
> ret = intel_panel_compute_config(connector, adjusted_mode);
> @@ -2334,7 +2335,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> adjusted_mode->crtc_clock /= n;
> }
>
> - intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
> + intel_dp_audio_compute_config(encoder, pipe_config, conn_state,
> intel_dp);
>
> intel_link_compute_m_n(output_bpp,
> pipe_config->lane_count,
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/display: combine has_audio check for DP and DP-MST
On Tue, 15 Aug 2023, Vinod Govindapillai wrote:
> Combine has_audio check for both DP and DP-MST into a single
> function.
I tried to explain the first step should be combining these two steps in
intel_dp_compute_config():
1)
pipe_config->has_audio =
intel_dp_has_audio(encoder, conn_state) &&
intel_audio_compute_config(encoder, pipe_config, conn_state);
2)
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
The latter function should include step 1.
Simplify first, only add the MST complication afterwards. Not vice
versa.
>
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 +--
> 3 files changed, 13 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 12bd2f322e62..97a14afbcfe8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2170,16 +2170,17 @@ intel_dp_drrs_compute_config(struct intel_connector
> *connector,
> pipe_config->dp_m2_n2.data_m *=
> pipe_config->splitter.link_count;
> }
>
> -static bool intel_dp_has_audio(struct intel_encoder *encoder,
> -const struct drm_connector_state *conn_state)
> +bool intel_dp_has_audio(struct intel_encoder *encoder,
Now you've created an intermediate step that requires this to be
non-static, but you also don't add static back afterwards.
> + const struct drm_connector_state *conn_state,
> + struct intel_dp *intel_dp)
There should be no need to pass intel_dp as parameter.
BR,
Jani.
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> - struct intel_connector *connector = intel_dp->attached_connector;
> const struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> + struct intel_connector *connector =
> + to_intel_connector(conn_state->connector);
>
> - if (!intel_dp_port_has_audio(i915, encoder->port))
> + if (!intel_dp->is_mst && !intel_dp_port_has_audio(i915, encoder->port))
> return false;
>
> if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
> @@ -2240,9 +2241,8 @@ intel_dp_audio_compute_config(struct intel_encoder
> *encoder,
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct drm_connector *connector = conn_state->connector;
>
> - pipe_config->sdp_split_enable =
> - intel_dp_has_audio(encoder, conn_state) &&
> - intel_dp_is_uhbr(pipe_config);
> + pipe_config->sdp_split_enable = pipe_config->has_audio &&
> + intel_dp_is_uhbr(pipe_config);
>
> drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
> connector->base.id, connector->name,
> @@ -2265,7 +2265,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> pipe_config->has_pch_encoder = true;
>
> pipe_config->has_audio =
> - intel_dp_has_audio(encoder, conn_state) &&
> + intel_dp_has_audio(encoder, conn_state, intel_dp) &&
> intel_audio_compute_config(encoder, pipe_config, conn_state);
>
> fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 22099de3ca45..e7b515b685ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -69,6 +69,9 @@ bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
> bool intel_dp_is_edp(struct intel_dp *intel_dp);
> bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
> bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
> +bool intel_dp_has_audio(struct intel_encoder *encoder,
> + const struct drm_connector_state *conn_state,
> + struct intel_dp *intel_dp);
> enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
> bool long_hpd);
> void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index e3f176a093d2..8881cfd41ee7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -290,19 +290,6 @@ static int intel_dp_mst_update_slots(struct
> intel_encoder *encoder,
> return 0;
> }
>
> -static bool intel_dp_mst_has_audio(const struct drm_connector_state
> *conn_state)
> -{
> - const struct intel
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/display: remove redundant parameter from sdp split update
On Tue, 15 Aug 2023, Vinod Govindapillai wrote:
> The needed functionality can be performed using crtc_state here.
>
> Signed-off-by: Vinod Govindapillai
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_audio.h | 3 +--
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> 3 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 3d9c9b4f27f8..19605264a35c 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -759,10 +759,10 @@ static void ibx_audio_codec_enable(struct intel_encoder
> *encoder,
> mutex_unlock(&i915->display.audio.mutex);
> }
>
> -void intel_audio_sdp_split_update(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state)
> +void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> enum transcoder trans = crtc_state->cpu_transcoder;
>
> if (HAS_DP20(i915))
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.h
> b/drivers/gpu/drm/i915/display/intel_audio.h
> index 07d034a981e9..9327954b801e 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.h
> +++ b/drivers/gpu/drm/i915/display/intel_audio.h
> @@ -29,7 +29,6 @@ void intel_audio_cdclk_change_pre(struct drm_i915_private
> *dev_priv);
> void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv);
> void intel_audio_init(struct drm_i915_private *dev_priv);
> void intel_audio_deinit(struct drm_i915_private *dev_priv);
> -void intel_audio_sdp_split_update(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state);
> +void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_AUDIO_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 84bbf854337a..b7f4281b8658 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3248,7 +3248,7 @@ static void intel_enable_ddi(struct intel_atomic_state
> *state,
> intel_ddi_enable_transcoder_func(encoder, crtc_state);
>
> /* Enable/Disable DP2.0 SDP split config before transcoder */
> - intel_audio_sdp_split_update(encoder, crtc_state);
> + intel_audio_sdp_split_update(crtc_state);
>
> intel_enable_transcoder(crtc_state);
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 0/2] drm/i915/selftests: Align igt_spinner_create_request with hangcheck
Align igt_spinner_create_request with the hang_create_request implementation in selftest_hangcheck.c, since they perform the same actions. Additionally, refactor the hangcheck live selftest to use igt_spinner functions and structures instead of those internally declared for the same reason. v2: - Refactor hangcheck selftest to use igt_spinner. Signed-off-by: Jonathan Cavitt CC: Chris Wilson CC: Saurabhg Gupta CC: Andi Shyti CC: Stuart Summers CC: Nirmoy Das CC: Vinay Belgaumkar CC: Michal Winiarski CC: Matt Roper Jonathan Cavitt (2): drm/i915/selftests: Align igt_spinner_create_request with hangcheck drm/i915/gt: Refactor hangcheck selftest to use igt_spinner drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 457 ++- drivers/gpu/drm/i915/selftests/igt_spinner.c | 18 +- drivers/gpu/drm/i915/selftests/igt_spinner.h | 9 + 3 files changed, 158 insertions(+), 326 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Align igt_spinner_create_request with hangcheck
Align igt_spinner_create_request with the hang_create_request implementation in selftest_hangcheck.c. Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/selftests/igt_spinner.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c index 0f064930ef11..8c3e1f20e5a1 100644 --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c @@ -179,6 +179,9 @@ igt_spinner_create_request(struct igt_spinner *spin, *batch++ = arbitration_command; + memset32(batch, MI_NOOP, 128); + batch += 128; + if (GRAPHICS_VER(rq->i915) >= 8) *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1; else if (IS_HASWELL(rq->i915)) -- 2.25.1
[Intel-gfx] [PATCH 2/2] drm/i915/gt: Refactor hangcheck selftest to use igt_spinner
The hangcheck live selftest contains duplicate declarations of some
functions that already exist in igt_spinner.c, such as the creation and
deconstruction of a spinning batch buffer (spinner) that hangs an engine.
It's undesireable to have such code duplicated, as the requirements for
the spinner may change with hardware updates, necessitating both
execution paths be updated. To avoid this, have the hangcheck live
selftest use the declaration from igt_spinner. This eliminates the need
for the declarations in the selftest itself, as well as the associated
local helper structures, so we can erase those.
Suggested-by: Matt Roper
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 457 ++-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 15 +-
drivers/gpu/drm/i915/selftests/igt_spinner.h | 9 +
3 files changed, 155 insertions(+), 326 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 0dd4d00ee894..36376a4ade8e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -29,281 +29,40 @@
#define IGT_IDLE_TIMEOUT 50 /* ms; time to wait after flushing between tests */
-struct hang {
- struct intel_gt *gt;
- struct drm_i915_gem_object *hws;
- struct drm_i915_gem_object *obj;
- struct i915_gem_context *ctx;
- u32 *seqno;
- u32 *batch;
-};
-
-static int hang_init(struct hang *h, struct intel_gt *gt)
-{
- void *vaddr;
- int err;
-
- memset(h, 0, sizeof(*h));
- h->gt = gt;
-
- h->ctx = kernel_context(gt->i915, NULL);
- if (IS_ERR(h->ctx))
- return PTR_ERR(h->ctx);
-
- GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx));
-
- h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
- if (IS_ERR(h->hws)) {
- err = PTR_ERR(h->hws);
- goto err_ctx;
- }
-
- h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
- if (IS_ERR(h->obj)) {
- err = PTR_ERR(h->obj);
- goto err_hws;
- }
-
- i915_gem_object_set_cache_coherency(h->hws, I915_CACHE_LLC);
- vaddr = i915_gem_object_pin_map_unlocked(h->hws, I915_MAP_WB);
- if (IS_ERR(vaddr)) {
- err = PTR_ERR(vaddr);
- goto err_obj;
- }
- h->seqno = memset(vaddr, 0xff, PAGE_SIZE);
-
- vaddr = i915_gem_object_pin_map_unlocked(h->obj,
-intel_gt_coherent_map_type(gt,
h->obj, false));
- if (IS_ERR(vaddr)) {
- err = PTR_ERR(vaddr);
- goto err_unpin_hws;
- }
- h->batch = vaddr;
-
- return 0;
-
-err_unpin_hws:
- i915_gem_object_unpin_map(h->hws);
-err_obj:
- i915_gem_object_put(h->obj);
-err_hws:
- i915_gem_object_put(h->hws);
-err_ctx:
- kernel_context_close(h->ctx);
- return err;
-}
-
-static u64 hws_address(const struct i915_vma *hws,
- const struct i915_request *rq)
-{
- return i915_vma_offset(hws) +
- offset_in_page(sizeof(u32) * rq->fence.context);
-}
-
-static struct i915_request *
-hang_create_request(struct hang *h, struct intel_engine_cs *engine)
-{
- struct intel_gt *gt = h->gt;
- struct i915_address_space *vm = i915_gem_context_get_eb_vm(h->ctx);
- struct drm_i915_gem_object *obj;
- struct i915_request *rq = NULL;
- struct i915_vma *hws, *vma;
- unsigned int flags;
- void *vaddr;
- u32 *batch;
- int err;
-
- obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
- if (IS_ERR(obj)) {
- i915_vm_put(vm);
- return ERR_CAST(obj);
- }
-
- vaddr = i915_gem_object_pin_map_unlocked(obj,
intel_gt_coherent_map_type(gt, obj, false));
- if (IS_ERR(vaddr)) {
- i915_gem_object_put(obj);
- i915_vm_put(vm);
- return ERR_CAST(vaddr);
- }
-
- i915_gem_object_unpin_map(h->obj);
- i915_gem_object_put(h->obj);
-
- h->obj = obj;
- h->batch = vaddr;
-
- vma = i915_vma_instance(h->obj, vm, NULL);
- if (IS_ERR(vma)) {
- i915_vm_put(vm);
- return ERR_CAST(vma);
- }
-
- hws = i915_vma_instance(h->hws, vm, NULL);
- if (IS_ERR(hws)) {
- i915_vm_put(vm);
- return ERR_CAST(hws);
- }
-
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
- if (err) {
- i915_vm_put(vm);
- return ERR_PTR(err);
- }
-
- err = i915_vma_pin(hws, 0, 0, PIN_USER);
- if (err)
- goto unpin_vma;
-
- rq = igt_request_alloc(h->ctx, engine);
- if (IS_ERR(rq)) {
- err = PTR_ERR(rq);
- goto unpin_hws;
- }
-
- err = igt_vma_move_to_active_unlocked(vma, rq,
[Intel-gfx] ✓ Fi.CI.IGT: success for SDP split for DP-MST
== Series Details == Series: SDP split for DP-MST URL : https://patchwork.freedesktop.org/series/122460/ State : success == Summary == CI Bug Log - changes from CI_DRM_13519_full -> Patchwork_122460v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_122460v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_bad_reloc@negative-reloc: - shard-mtlp: NOTRUN -> [SKIP][1] ([i915#3281]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-mtlp-3/igt@gem_bad_re...@negative-reloc.html * igt@gem_ctx_persistence@processes: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-snb4/igt@gem_ctx_persiste...@processes.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-rkl: [PASS][3] -> [FAIL][4] ([i915#2842]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/shard-rkl-2/igt@gem_exec_fair@basic-f...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-rkl-4/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_schedule@preempt-queue-contexts: - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#4812]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-mtlp-6/igt@gem_exec_sched...@preempt-queue-contexts.html * igt@gem_lmem_swapping@verify-random-ccs: - shard-mtlp: NOTRUN -> [SKIP][6] ([i915#4613]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-mtlp-3/igt@gem_lmem_swapp...@verify-random-ccs.html * igt@gem_madvise@dontneed-before-exec: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#3282]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-dg2-12/igt@gem_madv...@dontneed-before-exec.html * igt@gem_mmap_gtt@basic-small-bo-tiledx: - shard-mtlp: NOTRUN -> [SKIP][8] ([i915#4077]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-mtlp-3/igt@gem_mmap_...@basic-small-bo-tiledx.html * igt@gem_pxp@verify-pxp-execution-after-suspend-resume: - shard-mtlp: NOTRUN -> [SKIP][9] ([i915#4270]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-mtlp-3/igt@gem_...@verify-pxp-execution-after-suspend-resume.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled: - shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8428]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-mtlp-3/igt@gem_render_c...@yf-tiled-mc-ccs-to-vebox-y-tiled.html * igt@gem_set_tiling_vs_pwrite: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#4079]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-dg2-12/igt@gem_set_tiling_vs_pwrite.html * igt@gen9_exec_parse@allowed-all: - shard-apl: [PASS][12] -> [ABORT][13] ([i915#5566]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/shard-apl1/igt@gen9_exec_pa...@allowed-all.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-apl2/igt@gen9_exec_pa...@allowed-all.html * igt@gen9_exec_parse@bb-start-far: - shard-mtlp: NOTRUN -> [SKIP][14] ([i915#2856]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-mtlp-3/igt@gen9_exec_pa...@bb-start-far.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a: - shard-dg2: NOTRUN -> [SKIP][15] ([i915#1937]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-dg2-6/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-dg1: [PASS][16] -> [FAIL][17] ([i915#3591]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-i...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-i...@rcs0.html * igt@i915_pm_rpm@dpms-mode-unset-lpsp: - shard-dg1: [PASS][18] -> [SKIP][19] ([i915#1397]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/shard-dg1-19/igt@i915_pm_...@dpms-mode-unset-lpsp.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-dg1-14/igt@i915_pm_...@dpms-mode-unset-lpsp.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-mtlp: NOTRUN -> [SKIP][20] ([fdo#109293]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/shard-mtlp-4/igt@i915_pm_...@modeset-pc8-residency-stress.html * igt@i915_pm_rps@reset: - shard-snb: [PASS][21] -> [INCOMPLETE][22]
[Intel-gfx] ✓ Fi.CI.BAT: success for SDP split for DP-MST
== Series Details == Series: SDP split for DP-MST URL : https://patchwork.freedesktop.org/series/122460/ State : success == Summary == CI Bug Log - changes from CI_DRM_13519 -> Patchwork_122460v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/index.html Participating hosts (41 -> 39) -- Missing(2): fi-snb-2520m fi-pnv-d510 Known issues Here are the changes found in Patchwork_122460v1 that come from known issues: ### IGT changes ### Issues hit * igt@core_auth@basic-auth: - bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#8011]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-adlp-11/igt@core_a...@basic-auth.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-8809g: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334] / [i915#7872]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/fi-kbl-8809g/igt@i915_selftest@live@gt_heartbeat.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/fi-kbl-8809g/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-6: [PASS][4] -> [DMESG-FAIL][5] ([i915#7059]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@guc: - bat-rpls-1: [PASS][6] -> [DMESG-WARN][7] ([i915#7852]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/bat-rpls-1/igt@i915_selftest@l...@guc.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-rpls-1/igt@i915_selftest@l...@guc.html * igt@i915_selftest@live@slpc: - bat-rpls-2: NOTRUN -> [DMESG-WARN][8] ([i915#6367]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s3-without-i915: - bat-dg2-11: NOTRUN -> [INCOMPLETE][9] ([i915#4817]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-dg2-11/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-rpls-2: NOTRUN -> [SKIP][10] ([i915#7828]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-rpls-2/igt@kms_chamelium_...@common-hpd-after-suspend.html - bat-jsl-3: NOTRUN -> [SKIP][11] ([i915#7828]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-jsl-3/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-rpls-2: NOTRUN -> [SKIP][12] ([i915#1845]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-rpls-2/igt@kms_pipe_crc_ba...@suspend-read-crc.html Possible fixes * igt@gem_exec_suspend@basic-s0@smem: - bat-jsl-3: [ABORT][13] ([i915#5122]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][15] ([i915#5334] / [i915#7872]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html - fi-apl-guc: [DMESG-FAIL][17] ([i915#5334]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_lrc: - bat-dg2-11: [INCOMPLETE][19] ([i915#7609] / [i915#7913]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [DMESG-FAIL][21] ([i915#7059]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@reset: - bat-rpls-2: [ABORT][23] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13519/bat-rpls-2/igt@i915_selftest@l...@reset.html [24]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SDP split for DP-MST
== Series Details == Series: SDP split for DP-MST URL : https://patchwork.freedesktop.org/series/122460/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for SDP split for DP-MST
== Series Details == Series: SDP split for DP-MST URL : https://patchwork.freedesktop.org/series/122460/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] [PATCH v2 4/4] drm/915/display: configure SDP split for DP-MST
Extend the SDP split audio config for DP-MST Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.h | 4 drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++ 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0eb072a78d44..269828e22437 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2233,7 +2233,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, return ret; } -static void +void intel_dp_audio_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index e7b515b685ac..b8516a34cfaf 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -65,6 +65,10 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct link_config_limits *limits, int timeslots, bool recompute_pipe_bpp); +void intel_dp_audio_compute_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct intel_dp *intel_dp); bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 8881cfd41ee7..05228c006a1b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -309,10 +309,6 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->has_pch_encoder = false; - pipe_config->has_audio = - intel_dp_has_audio(encoder, conn_state, intel_dp) && - intel_audio_compute_config(encoder, pipe_config, conn_state); - /* * for MST we always configure max link bw - the spec doesn't * seem to suggest we should do otherwise. @@ -375,6 +371,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, pipe_config->lane_lat_optim_mask = bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); + intel_dp_audio_compute_config(encoder, pipe_config, conn_state, intel_dp); intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); return 0; @@ -779,6 +776,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, FECSTALL_DIS_DPTSTREAM_DPTTG); + intel_audio_sdp_split_update(pipe_config); + intel_enable_transcoder(pipe_config); intel_crtc_vblank_on(pipe_config); -- 2.34.1
[Intel-gfx] [PATCH v2 3/4] drm/i915/display: combine DP audio compute config steps
Combine all DP audio configs into a single function
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 97a14afbcfe8..0eb072a78d44 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2236,11 +2236,16 @@ intel_dp_compute_output_format(struct intel_encoder
*encoder,
static void
intel_dp_audio_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
- struct drm_connector_state *conn_state)
+ struct drm_connector_state *conn_state,
+ struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_connector *connector = conn_state->connector;
+ pipe_config->has_audio =
+ intel_dp_has_audio(encoder, conn_state, intel_dp) &&
+ intel_audio_compute_config(encoder, pipe_config, conn_state);
+
pipe_config->sdp_split_enable = pipe_config->has_audio &&
intel_dp_is_uhbr(pipe_config);
@@ -2264,10 +2269,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port !=
PORT_A)
pipe_config->has_pch_encoder = true;
- pipe_config->has_audio =
- intel_dp_has_audio(encoder, conn_state, intel_dp) &&
- intel_audio_compute_config(encoder, pipe_config, conn_state);
-
fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
if (intel_dp_is_edp(intel_dp) && fixed_mode) {
ret = intel_panel_compute_config(connector, adjusted_mode);
@@ -2334,7 +2335,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock /= n;
}
- intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
+ intel_dp_audio_compute_config(encoder, pipe_config, conn_state,
intel_dp);
intel_link_compute_m_n(output_bpp,
pipe_config->lane_count,
--
2.34.1
[Intel-gfx] [PATCH v2 2/4] drm/i915/display: combine has_audio check for DP and DP-MST
Combine has_audio check for both DP and DP-MST into a single
function.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 +--
3 files changed, 13 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 12bd2f322e62..97a14afbcfe8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2170,16 +2170,17 @@ intel_dp_drrs_compute_config(struct intel_connector
*connector,
pipe_config->dp_m2_n2.data_m *=
pipe_config->splitter.link_count;
}
-static bool intel_dp_has_audio(struct intel_encoder *encoder,
- const struct drm_connector_state *conn_state)
+bool intel_dp_has_audio(struct intel_encoder *encoder,
+ const struct drm_connector_state *conn_state,
+ struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- struct intel_connector *connector = intel_dp->attached_connector;
const struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
+ struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
- if (!intel_dp_port_has_audio(i915, encoder->port))
+ if (!intel_dp->is_mst && !intel_dp_port_has_audio(i915, encoder->port))
return false;
if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
@@ -2240,9 +2241,8 @@ intel_dp_audio_compute_config(struct intel_encoder
*encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_connector *connector = conn_state->connector;
- pipe_config->sdp_split_enable =
- intel_dp_has_audio(encoder, conn_state) &&
- intel_dp_is_uhbr(pipe_config);
+ pipe_config->sdp_split_enable = pipe_config->has_audio &&
+ intel_dp_is_uhbr(pipe_config);
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
connector->base.id, connector->name,
@@ -2265,7 +2265,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_pch_encoder = true;
pipe_config->has_audio =
- intel_dp_has_audio(encoder, conn_state) &&
+ intel_dp_has_audio(encoder, conn_state, intel_dp) &&
intel_audio_compute_config(encoder, pipe_config, conn_state);
fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 22099de3ca45..e7b515b685ac 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -69,6 +69,9 @@ bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
bool intel_dp_is_edp(struct intel_dp *intel_dp);
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
+bool intel_dp_has_audio(struct intel_encoder *encoder,
+ const struct drm_connector_state *conn_state,
+ struct intel_dp *intel_dp);
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
bool long_hpd);
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e3f176a093d2..8881cfd41ee7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -290,19 +290,6 @@ static int intel_dp_mst_update_slots(struct intel_encoder
*encoder,
return 0;
}
-static bool intel_dp_mst_has_audio(const struct drm_connector_state
*conn_state)
-{
- const struct intel_digital_connector_state *intel_conn_state =
- to_intel_digital_connector_state(conn_state);
- struct intel_connector *connector =
- to_intel_connector(conn_state->connector);
-
- if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
- return connector->base.display_info.has_audio;
- else
- return intel_conn_state->force_audio == HDMI_AUDIO_ON;
-}
-
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -323,7 +310,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder
*encoder,
pipe_config->has_pch_encoder = false;
pipe_config->has_audio =
[Intel-gfx] [PATCH v2 1/4] drm/i915/display: remove redundant parameter from sdp split update
The needed functionality can be performed using crtc_state here.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_audio.c | 6 +++---
drivers/gpu/drm/i915/display/intel_audio.h | 3 +--
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 3d9c9b4f27f8..19605264a35c 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -759,10 +759,10 @@ static void ibx_audio_codec_enable(struct intel_encoder
*encoder,
mutex_unlock(&i915->display.audio.mutex);
}
-void intel_audio_sdp_split_update(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum transcoder trans = crtc_state->cpu_transcoder;
if (HAS_DP20(i915))
diff --git a/drivers/gpu/drm/i915/display/intel_audio.h
b/drivers/gpu/drm/i915/display/intel_audio.h
index 07d034a981e9..9327954b801e 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.h
+++ b/drivers/gpu/drm/i915/display/intel_audio.h
@@ -29,7 +29,6 @@ void intel_audio_cdclk_change_pre(struct drm_i915_private
*dev_priv);
void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv);
void intel_audio_init(struct drm_i915_private *dev_priv);
void intel_audio_deinit(struct drm_i915_private *dev_priv);
-void intel_audio_sdp_split_update(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
+void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_AUDIO_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 84bbf854337a..b7f4281b8658 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3248,7 +3248,7 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
intel_ddi_enable_transcoder_func(encoder, crtc_state);
/* Enable/Disable DP2.0 SDP split config before transcoder */
- intel_audio_sdp_split_update(encoder, crtc_state);
+ intel_audio_sdp_split_update(crtc_state);
intel_enable_transcoder(crtc_state);
--
2.34.1
[Intel-gfx] [PATCH v2 0/4] SDP split for DP-MST
SDP split config for DP-MST v2: Style changes and patch splits (Jani Nikula) Vinod Govindapillai (4): drm/i915/display: remove redundant parameter from sdp split update drm/i915/display: combine has_audio check for DP and DP-MST drm/i915/display: combine DP audio compute config steps drm/915/display: configure SDP split for DP-MST drivers/gpu/drm/i915/display/intel_audio.c | 6 ++-- drivers/gpu/drm/i915/display/intel_audio.h | 3 +- drivers/gpu/drm/i915/display/intel_ddi.c| 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 31 +++-- drivers/gpu/drm/i915/display/intel_dp.h | 7 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 ++--- 6 files changed, 31 insertions(+), 38 deletions(-) -- 2.34.1
Re: [Intel-gfx] [PATCH] drm/i915/dgfx: Enable d3cold at s2idle
On Tue, Aug 15, 2023 at 03:29:12AM -0400, Gupta, Anshuman wrote:
>
>
> > -Original Message-
> > From: Vivi, Rodrigo
> > Sent: Monday, August 14, 2023 9:33 PM
> > To: Gupta, Anshuman
> > Cc: intel-gfx@lists.freedesktop.org; Nilawar, Badal
> > ; Tauro, Riana
> > Subject: Re: [PATCH] drm/i915/dgfx: Enable d3cold at s2idle
> >
> > On Mon, Aug 14, 2023 at 04:34:18PM +0530, Anshuman Gupta wrote:
> > > System wide suspend already has support for lmem save/restore during
> > > suspend therefore enabling d3cold for s2idle and keepng it disable for
> > > runtime PM.(Refer below commit for d3cold runtime PM disable
> > > justification) 'commit 66eb93e71a7a ("drm/i915/dgfx: Keep PCI
> > > autosuspend control 'on' by default on all dGPU")'
> > >
> > > It will reduce the DG2 Card power consumption to ~0 Watt for s2idle
> > > power KPI.
> > >
> > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8755
> > > Cc: Rodrigo Vivi
> > > Signed-off-by: Anshuman Gupta
> >
> > Reviewed-by: Rodrigo Vivi
> Hi Rodrigo,
> Thanks for review, will this be good candidate for Linux stable tree ?
Yes, I think so.
do we have a good commit to mark for 'Fixes:'?
but we can add the cc: stable even without the Fixes already in
advance anyway.
otherwise we need to wait for this to land in Linus tree and then
send directly again to the stable mailing list.
> Thanks,
> Anshuman Gupta.
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_driver.c | 33
> > > --
> > > 1 file changed, 18 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > > b/drivers/gpu/drm/i915/i915_driver.c
> > > index b870c0df081a..ec4d26b3c17c 100644
> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > @@ -443,7 +443,6 @@ static int i915_pcode_init(struct drm_i915_private
> > > *i915) static int i915_driver_hw_probe(struct drm_i915_private
> > > *dev_priv) {
> > > struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > > - struct pci_dev *root_pdev;
> > > int ret;
> > >
> > > if (i915_inject_probe_failure(dev_priv))
> > > @@ -557,15 +556,6 @@ static int i915_driver_hw_probe(struct
> > > drm_i915_private *dev_priv)
> > >
> > > intel_bw_init_hw(dev_priv);
> > >
> > > - /*
> > > - * FIXME: Temporary hammer to avoid freezing the machine on our
> > DGFX
> > > - * This should be totally removed when we handle the pci states
> > properly
> > > - * on runtime PM and on s2idle cases.
> > > - */
> > > - root_pdev = pcie_find_root_port(pdev);
> > > - if (root_pdev)
> > > - pci_d3cold_disable(root_pdev);
> > > -
> > > return 0;
> > >
> > > err_opregion:
> > > @@ -591,7 +581,6 @@ static int i915_driver_hw_probe(struct
> > > drm_i915_private *dev_priv) static void i915_driver_hw_remove(struct
> > > drm_i915_private *dev_priv) {
> > > struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > > - struct pci_dev *root_pdev;
> > >
> > > i915_perf_fini(dev_priv);
> > >
> > > @@ -599,10 +588,6 @@ static void i915_driver_hw_remove(struct
> > > drm_i915_private *dev_priv)
> > >
> > > if (pdev->msi_enabled)
> > > pci_disable_msi(pdev);
> > > -
> > > - root_pdev = pcie_find_root_port(pdev);
> > > - if (root_pdev)
> > > - pci_d3cold_enable(root_pdev);
> > > }
> > >
> > > /**
> > > @@ -1519,6 +1504,8 @@ static int intel_runtime_suspend(struct device
> > > *kdev) {
> > > struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > > struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
> > > + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > > + struct pci_dev *root_pdev;
> > > struct intel_gt *gt;
> > > int ret, i;
> > >
> > > @@ -1570,6 +1557,15 @@ static int intel_runtime_suspend(struct device
> > *kdev)
> > > drm_err(&dev_priv->drm,
> > > "Unclaimed access detected prior to suspending\n");
> > >
> > > + /*
> > > + * FIXME: Temporary hammer to avoid freezing the machine on our
> > DGFX
> > > + * This should be totally removed when we handle the pci states
> > properly
> > > + * on runtime PM.
> > > + */
> > > + root_pdev = pcie_find_root_port(pdev);
> > > + if (root_pdev)
> > > + pci_d3cold_disable(root_pdev);
> > > +
> > > rpm->suspended = true;
> > >
> > > /*
> > > @@ -1608,6 +1604,8 @@ static int intel_runtime_resume(struct device
> > > *kdev) {
> > > struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > > struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
> > > + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > > + struct pci_dev *root_pdev;
> > > struct intel_gt *gt;
> > > int ret, i;
> > >
> > > @@ -1621,6 +1619,11 @@ static int intel_runtime_resume(struct device
> > > *kdev)
> > >
> > > intel_opregion_notify_adapter(dev_priv, PCI_D0);
> > > rpm->suspended = false;
> > > +
> > > + root_pdev = pcie_find_root_port(pdev);
> > > + if (root_pdev)
> > > + pci_d3cold_enable(root_pdev);
> > > +
> > > if (int
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/guc: Close deregister-context race against CT-loss
On Mon, Aug 14, 2023 at 06:12:09PM -0700, Alan Previn wrote:
> If we are at the end of suspend or very early in resume
> its possible an async fence signal could lead us to the
> execution of the context destruction worker (after the
> prior worker flush).
>
> Even if checking that the CT is enabled before calling
> destroyed_worker_func, guc_lrc_desc_unpin may still fail
> because in corner cases, as we traverse the GuC's
> context-destroy list, the CT could get disabled in the mid
> of it right before calling the GuC's CT send function.
>
> We've witnessed this race condition once every ~6000-8000
> suspend-resume cycles while ensuring workloads that render
> something onscreen is continuously started just before
> we suspend (and the workload is small enough to complete
> and trigger the queued engine/context free-up either very
> late in suspend or very early in resume).
>
> In such a case, we need to unroll the unpin process because
> guc-lrc-unpin takes a gt wakeref which only gets released in
> the G2H IRQ reply that never comes through in this corner
> case. That will cascade into a kernel hang later at the tail
> end of suspend in this function:
>
>intel_wakeref_wait_for_idle(>->wakeref)
>(called by) - intel_gt_pm_wait_for_idle
>(called by) - wait_for_suspend
>
> Doing this unroll and keeping the context in the GuC's
> destroy-list will allow the context to get picked up on
> the next destroy worker invocation or purged as part of a
> major GuC sanitization or reset flow.
>
> Signed-off-by: Alan Previn
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 40 +--
> 1 file changed, 36 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 050572bb8dbe..ddb4ee4c4e51 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -235,6 +235,13 @@ set_context_destroyed(struct intel_context *ce)
> ce->guc_state.sched_state |= SCHED_STATE_DESTROYED;
> }
>
> +static inline void
> +clr_context_destroyed(struct intel_context *ce)
> +{
> + lockdep_assert_held(&ce->guc_state.lock);
> + ce->guc_state.sched_state &= ~SCHED_STATE_DESTROYED;
> +}
> +
> static inline bool context_pending_disable(struct intel_context *ce)
> {
> return ce->guc_state.sched_state & SCHED_STATE_PENDING_DISABLE;
> @@ -3175,7 +3182,7 @@ static void guc_context_close(struct intel_context *ce)
> spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> }
>
> -static inline void guc_lrc_desc_unpin(struct intel_context *ce)
> +static inline int guc_lrc_desc_unpin(struct intel_context *ce)
> {
> struct intel_guc *guc = ce_to_guc(ce);
> struct intel_gt *gt = guc_to_gt(guc);
> @@ -3199,10 +3206,20 @@ static inline void guc_lrc_desc_unpin(struct
> intel_context *ce)
> if (unlikely(disabled)) {
> release_guc_id(guc, ce);
> __guc_context_destroy(ce);
> - return;
> + return 0;
> + }
> +
> + if (deregister_context(ce, ce->guc_id.id)) {
> + /* Seal race with concurrent suspend by unrolling */
> + spin_lock_irqsave(&ce->guc_state.lock, flags);
> + set_context_registered(ce);
> + clr_context_destroyed(ce);
> + intel_gt_pm_put(gt);
how sure we are this is not calling unbalanced puts?
could we wrap this in some existent function to make this clear?
> + spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> + return -ENODEV;
> }
>
> - deregister_context(ce, ce->guc_id.id);
> + return 0;
> }
>
> static void __guc_context_destroy(struct intel_context *ce)
> @@ -3270,7 +3287,22 @@ static void deregister_destroyed_contexts(struct
> intel_guc *guc)
> if (!ce)
> break;
>
> - guc_lrc_desc_unpin(ce);
> + if (guc_lrc_desc_unpin(ce)) {
> + /*
> + * This means GuC's CT link severed mid-way which could
> happen
> + * in suspend-resume corner cases. In this case, put the
> + * context back into the destroyed_contexts list which
> will
> + * get picked up on the next context deregistration
> event or
> + * purged in a GuC sanitization event
> (reset/unload/wedged/...).
> + */
> + spin_lock_irqsave(&guc->submission_state.lock, flags);
> + list_add_tail(&ce->destroyed_link,
> +
> &guc->submission_state.destroyed_contexts);
> + spin_unlock_irqrestore(&guc->submission_state.lock,
> flags);
> + /* Bail now since the list might never be emptied if
> h2gs fail */
> + break;
> + }
> +
> }
> }
>
>
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/guc: Flush context destruction worker at suspend
On Mon, Aug 14, 2023 at 06:12:08PM -0700, Alan Previn wrote:
> When suspending, flush the context-guc-id
> deregistration worker at the final stages of
> intel_gt_suspend_late when we finally call gt_sanitize
> that eventually leads down to __uc_sanitize so that
> the deregistration worker doesn't fire off later as
> we reset the GuC microcontroller.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 5 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 ++
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 ++
> 3 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index a0e3ef1c65d2..050572bb8dbe 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1578,6 +1578,11 @@ static void guc_flush_submissions(struct intel_guc
> *guc)
> spin_unlock_irqrestore(&sched_engine->lock, flags);
> }
>
> +void intel_guc_submission_flush_work(struct intel_guc *guc)
> +{
> + flush_work(&guc->submission_state.destroyed_worker);
> +}
> +
> static void guc_flush_destroyed_contexts(struct intel_guc *guc);
>
> void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
> index c57b29cdb1a6..b6df75622d3b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
> @@ -38,6 +38,8 @@ int intel_guc_wait_for_pending_msg(struct intel_guc *guc,
> bool interruptible,
> long timeout);
>
> +void intel_guc_submission_flush_work(struct intel_guc *guc);
> +
> static inline bool intel_guc_submission_is_supported(struct intel_guc *guc)
> {
> return guc->submission_supported;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 98b103375b7a..eb3554cb5ea4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -693,6 +693,8 @@ void intel_uc_suspend(struct intel_uc *uc)
> return;
> }
>
> + intel_guc_submission_flush_work(guc);
> +
what happens if a new job comes exactly here?
This still sounds a bit racy, although this already looks
much cleaner than the previous version.
> with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref) {
> err = intel_guc_suspend(guc);
> if (err)
> --
> 2.39.0
>
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/gt: Timeout when waiting for idle in suspending
On Mon, Aug 14, 2023 at 06:12:10PM -0700, Alan Previn wrote:
> When suspending, add a timeout when calling
> intel_gt_pm_wait_for_idle else if we have a lost
> G2H event that holds a wakeref (which would be
> indicative of a bug elsewhere in the driver),
> driver will at least complete the suspend-resume
> cycle, (albeit not hitting all the targets for
> low power hw counters), instead of hanging in the kernel.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 7 ++-
> drivers/gpu/drm/i915/gt/intel_gt_pm.h | 7 ++-
> drivers/gpu/drm/i915/intel_wakeref.c | 14 ++
> drivers/gpu/drm/i915/intel_wakeref.h | 5 +++--
> 5 files changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index ee15486fed0d..090438eb8682 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -688,7 +688,7 @@ void intel_engines_release(struct intel_gt *gt)
> if (!engine->release)
> continue;
>
> - intel_wakeref_wait_for_idle(&engine->wakeref);
> + intel_wakeref_wait_for_idle(&engine->wakeref, 0);
> GEM_BUG_ON(intel_engine_pm_is_awake(engine));
>
> engine->release(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index 5a942af0a14e..e8b006c3ef29 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -289,6 +289,8 @@ int intel_gt_resume(struct intel_gt *gt)
>
> static void wait_for_suspend(struct intel_gt *gt)
> {
> + int timeout_ms = CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT ? : 1;
> +
> if (!intel_gt_pm_is_awake(gt))
> return;
>
> @@ -301,7 +303,10 @@ static void wait_for_suspend(struct intel_gt *gt)
> intel_gt_retire_requests(gt);
> }
>
> - intel_gt_pm_wait_for_idle(gt);
> + /* we are suspending, so we shouldn't be waiting forever */
> + if (intel_gt_pm_wait_timeout_for_idle(gt, timeout_ms) == -ETIME)
you forgot to change the error code here..^
but maybe we don't even need this here and a simple
if (intel_gt_pm_wait_timeout_for_idle(gt, timeout_ms)) should be enough
since the error from the killable one is unlikely and the only place
I error I could check on that path would be a catastrophic -ERESTARTSYS.
but up to you.
> + gt_warn(gt, "bailing from %s after %d milisec timeout\n",
> + __func__, timeout_ms);
> }
>
> void intel_gt_suspend_prepare(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> index 6c9a46452364..5358acc2b5b1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
> @@ -68,7 +68,12 @@ static inline void intel_gt_pm_might_put(struct intel_gt
> *gt)
>
> static inline int intel_gt_pm_wait_for_idle(struct intel_gt *gt)
> {
> - return intel_wakeref_wait_for_idle(>->wakeref);
> + return intel_wakeref_wait_for_idle(>->wakeref, 0);
> +}
> +
> +static inline int intel_gt_pm_wait_timeout_for_idle(struct intel_gt *gt, int
> timeout_ms)
> +{
> + return intel_wakeref_wait_for_idle(>->wakeref, timeout_ms);
> }
I was going to ask why you created a single use function here, but then I
noticed the above one. So it makes sense.
Then I was going to ask why in here you didn't use the same change of
timeout = 0 in the existent function like you used below, but then I
noticed that the above function is called in multiple places and the
patch with this change is much cleaner and the function is static inline
so your approach was good here.
>
> void intel_gt_pm_init_early(struct intel_gt *gt);
> diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
> b/drivers/gpu/drm/i915/intel_wakeref.c
> index 718f2f1b6174..383a37521415 100644
> --- a/drivers/gpu/drm/i915/intel_wakeref.c
> +++ b/drivers/gpu/drm/i915/intel_wakeref.c
> @@ -111,14 +111,20 @@ void __intel_wakeref_init(struct intel_wakeref *wf,
>"wakeref.work", &key->work, 0);
> }
>
Please add a documentation for this function making sure you have the following
mentions:
/**
[snip]
* @timeout_ms: Timeout in ums, 0 means never timeout.
*
* Returns 0 on success, -ETIMEDOUT upon a timeout, or the unlikely
* error propagation from wait_var_event_killable if timeout_ms is 0.
*/
with the return error fixed above and the documentation in place:
Reviewed-by: Rodrigo Vivi
> -int intel_wakeref_wait_for_idle(struct intel_wakeref *wf)
> +int intel_wakeref_wait_for_idle(struct intel_wakeref *wf, int timeout_ms)
> {
> - int err;
> + int err = 0;
>
> might_sleep();
>
> - err = wait_var_event_killable(&wf->wakeref,
> -
[Intel-gfx] ✓ Fi.CI.IGT: success for Revert "drm/edid: Fix csync detailed mode parsing"
== Series Details == Series: Revert "drm/edid: Fix csync detailed mode parsing" URL : https://patchwork.freedesktop.org/series/122455/ State : success == Summary == CI Bug Log - changes from CI_DRM_13518_full -> Patchwork_122455v1_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_122455v1_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122455v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122455v1_full: ### IGT changes ### Warnings * igt@kms_cursor_crc@cursor-sliding-64x64@pipe-a-edp-1: - shard-mtlp: [DMESG-WARN][1] ([i915#1982] / [i915#2017]) -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/shard-mtlp-2/igt@kms_cursor_crc@cursor-sliding-64...@pipe-a-edp-1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-mtlp-7/igt@kms_cursor_crc@cursor-sliding-64...@pipe-a-edp-1.html Known issues Here are the changes found in Patchwork_122455v1_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@virtual-busy-idle-all: - shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8414]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-mtlp-2/igt@drm_fdi...@virtual-busy-idle-all.html * igt@gem_busy@close-race: - shard-rkl: [PASS][4] -> [ABORT][5] ([i915#6016]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/shard-rkl-7/igt@gem_b...@close-race.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-rkl-2/igt@gem_b...@close-race.html * igt@gem_ctx_persistence@engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-snb4/igt@gem_ctx_persiste...@engines-mixed-process.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#8555]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-dg2-12/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_sseu@invalid-sseu: - shard-dg2: NOTRUN -> [SKIP][8] ([i915#280]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-dg2-11/igt@gem_ctx_s...@invalid-sseu.html * igt@gem_eio@in-flight-contexts-immediate: - shard-mtlp: [PASS][9] -> [ABORT][10] ([i915#8503]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/shard-mtlp-3/igt@gem_...@in-flight-contexts-immediate.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-mtlp-8/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_exec_fair@basic-pace: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#3539]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-dg2-11/igt@gem_exec_f...@basic-pace.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglu: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/shard-tglu-9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-tglu-7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-rkl: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/shard-rkl-4/igt@gem_exec_fair@basic-p...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-rkl-4/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_flush@basic-wb-rw-before-default: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#3539] / [i915#4852]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-dg2-10/igt@gem_exec_fl...@basic-wb-rw-before-default.html * igt@gem_exec_reloc@basic-cpu-wc-active: - shard-mtlp: NOTRUN -> [SKIP][17] ([i915#3281]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-mtlp-2/igt@gem_exec_re...@basic-cpu-wc-active.html * igt@gem_exec_reloc@basic-range: - shard-dg2: NOTRUN -> [SKIP][18] ([i915#3281]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/shard-dg2-11/igt@gem_exec_re...@basic-range.html * igt@gem_exec_suspend@basic-s4-devices@lmem0: - shard-dg2: NOTRUN -> [ABORT][19] ([i915#7975] / [i915#8213]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/edid: Fix csync detailed mode parsing"
== Series Details == Series: Revert "drm/edid: Fix csync detailed mode parsing" URL : https://patchwork.freedesktop.org/series/122455/ State : success == Summary == CI Bug Log - changes from CI_DRM_13518 -> Patchwork_122455v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/index.html Participating hosts (41 -> 39) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_122455v1 that come from known issues: ### IGT changes ### Issues hit * igt@core_auth@basic-auth: - bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#8011]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-adlp-11/igt@core_a...@basic-auth.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][2] -> [ABORT][3] ([i915#4983] / [i915#7911] / [i915#7920]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/bat-rpls-1/igt@i915_selftest@l...@requests.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-rpls-1/igt@i915_selftest@l...@requests.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-jsl-3: NOTRUN -> [SKIP][4] ([i915#7828]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-jsl-3/igt@kms_chamelium_...@common-hpd-after-suspend.html Possible fixes * igt@gem_exec_suspend@basic-s0@smem: - bat-jsl-3: [ABORT][5] ([i915#5122]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-6: [DMESG-FAIL][7] ([i915#7059]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][9] ([i915#7699]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/bat-dg2-11/igt@i915_selftest@l...@migrate.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_suspend@basic-s3-without-i915: - bat-jsl-3: [FAIL][11] ([fdo#103375]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html Warnings * igt@i915_module_load@load: - bat-adlp-11:[ABORT][13] ([i915#4423]) -> [DMESG-WARN][14] ([i915#4423]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/bat-adlp-11/igt@i915_module_l...@load.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-adlp-11/igt@i915_module_l...@load.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [DMESG-FAIL][15] ([i915#8497]) -> [ABORT][16] ([i915#7982] / [i915#8865]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/bat-mtlp-8/igt@i915_selftest@l...@requests.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@kms_psr@cursor_plane_move: - bat-rplp-1: [SKIP][17] ([i915#1072]) -> [ABORT][18] ([i915#8469] / [i915#8668]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13518/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v1/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122 [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920 [i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982 [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011 [i915#8469]: https://gitlab.freedesktop.org/drm/intel/issues/8469 [i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i9
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Revert "drm/edid: Fix csync detailed mode parsing"
== Series Details == Series: Revert "drm/edid: Fix csync detailed mode parsing" URL : https://patchwork.freedesktop.org/series/122455/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "drm/edid: Fix csync detailed mode parsing"
== Series Details == Series: Revert "drm/edid: Fix csync detailed mode parsing" URL : https://patchwork.freedesktop.org/series/122455/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] [PATCH] Revert "drm/edid: Fix csync detailed mode parsing"
This reverts commit ca62297b2085b5b3168bd891ca24862242c635a1.
Commit ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") fixed
EDID detailed mode sync parsing. Unfortunately, there are quite a few
displays out there that have bogus (zero) sync field that are broken by
the change. Zero means analog composite sync, which is not right for
digital displays, and the modes get rejected. Regardless, it used to
work, and it needs to continue to work. Revert the change.
Rejecting modes with analog composite sync was the part that fixed the
gitlab issue 8146 [1]. We'll need to get back to the drawing board with
that.
[1] https://gitlab.freedesktop.org/drm/intel/-/issues/8146
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8789
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8930
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9044
Fixes: ca62297b2085 ("drm/edid: Fix csync detailed mode parsing")
Cc: Ville Syrjälä
Cc: dri-de...@lists.freedesktop.org
Cc: # v6.4+
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 29 -
include/drm/drm_edid.h | 12 +++-
2 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f95152fac427..340da8257b51 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3457,6 +3457,10 @@ static struct drm_display_mode *drm_mode_detailed(struct
drm_connector *connecto
connector->base.id, connector->name);
return NULL;
}
+ if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
+ drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not
supported\n",
+ connector->base.id, connector->name);
+ }
/* it is incorrect if hsync/vsync width is zero */
if (!hsync_pulse_width || !vsync_pulse_width) {
@@ -3503,27 +3507,10 @@ static struct drm_display_mode
*drm_mode_detailed(struct drm_connector *connecto
if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
} else {
- switch (pt->misc & DRM_EDID_PT_SYNC_MASK) {
- case DRM_EDID_PT_ANALOG_CSYNC:
- case DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC:
- drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Analog composite
sync!\n",
- connector->base.id, connector->name);
- mode->flags |= DRM_MODE_FLAG_CSYNC |
DRM_MODE_FLAG_NCSYNC;
- break;
- case DRM_EDID_PT_DIGITAL_CSYNC:
- drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Digital composite
sync!\n",
- connector->base.id, connector->name);
- mode->flags |= DRM_MODE_FLAG_CSYNC;
- mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
- DRM_MODE_FLAG_PCSYNC : DRM_MODE_FLAG_NCSYNC;
- break;
- case DRM_EDID_PT_DIGITAL_SEPARATE_SYNC:
- mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
- DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
- mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
- DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
- break;
- }
+ mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
+ DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
+ mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
+ DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
}
set_size:
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 169755d3de19..48e93f909ef6 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -61,15 +61,9 @@ struct std_timing {
u8 vfreq_aspect;
} __attribute__((packed));
-#define DRM_EDID_PT_SYNC_MASK (3 << 3)
-# define DRM_EDID_PT_ANALOG_CSYNC (0 << 3)
-# define DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC (1 << 3)
-# define DRM_EDID_PT_DIGITAL_CSYNC (2 << 3)
-# define DRM_EDID_PT_CSYNC_ON_RGB (1 << 1) /* analog csync only */
-# define DRM_EDID_PT_CSYNC_SERRATE(1 << 2)
-# define DRM_EDID_PT_DIGITAL_SEPARATE_SYNC (3 << 3)
-# define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) /* also digital csync */
-# define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
+#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
+#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
+#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
#define DRM_EDID_PT_STEREO (1 << 5)
#define DRM_EDID_PT_INTERLACED (1 << 7)
--
2.39.2
Re: [Intel-gfx] [PATCH v2 2/5] drm: Add an HPD poll helper to reschedule the poll work
On Thu, 20 Jul 2023 at 15:54, Imre Deak wrote: > > Add a helper to reschedule drm_mode_config::output_poll_work after > polling has been enabled for a connector (and needing a reschedule, > since previously polling was disabled for all connectors and hence > output_poll_work was not running). > > This is needed by the next patch fixing HPD polling on i915. > > Cc: Dmitry Baryshkov > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Imre Deak Reviewed-by: Dmitry Baryshkov > --- > drivers/gpu/drm/drm_probe_helper.c | 68 -- > include/drm/drm_probe_helper.h | 1 + > 2 files changed, 47 insertions(+), 22 deletions(-) I support merging these patches through drm-intel rather than drm-misc. -- With best wishes Dmitry
Re: [Intel-gfx] [REGRESSION] HDMI connector detection broken in 6.3 on Intel(R) Celeron(R) N3060 integrated graphics
On Mon, 14 Aug 2023, Imre Deak wrote: > On Sun, Aug 13, 2023 at 03:41:30PM +0200, Linux regression tracking (Thorsten > Leemhuis) wrote: > Hi, > >> On 11.08.23 20:10, Mikhail Rudenko wrote: >> > On 2023-08-11 at 08:45 +02, Thorsten Leemhuis >> > wrote: >> >> On 10.08.23 21:33, Mikhail Rudenko wrote: >> >>> The following is a copy an issue I posted to drm/i915 gitlab [1] two >> >>> months ago. I repost it to the mailing lists in hope that it will help >> >>> the right people pay attention to it. >> >> >> >> Thx for your report. Wonder why Dmitry (who authored a4e771729a51) or >> >> Thomas (who committed it) it didn't look into this, but maybe the i915 >> >> devs didn't forward the report to them. >> >> For the record: they did, and Jani mentioned already. Sorry, should have >> phrased this differently. >> >> >> Let's see if these mails help. Just wondering: does reverting >> >> a4e771729a51 from 6.5-rc5 or drm-tip help as well? >> > >> > I've redone my tests with 6.5-rc5, and here are the results: >> > (1) 6.5-rc5 -> still affected >> > (2) 6.5-rc5 + revert a4e771729a51 -> not affected >> > (3) 6.5-rc5 + two patches [1][2] suggested on i915 gitlab by @ideak -> not >> > affected (!) >> > >> > Should we somehow tell regzbot about (3)? >> >> That's good to know, thx. But the more important things are: >> >> * When will those be merged? They are not yet in next yet afaics, so it >> might take some time to mainline them, especially at this point of the >> devel cycle. Imre, could you try to prod the right people so that these >> are ideally upstreamed rather sooner than later, as they fix a regression? > > I think the patches ([1] and [2]) could be merged via the drm-intel-next > (drm-intel-fixes) tree Cc'ing also stable. Jani, is this ok? It's fine by me, but need drm-misc maintainer ack to merge [1] via drm-intel. BR, Jani. > >> * They if possible ideally should be tagged for backporting to 6.4, as >> this is a regression from the 6.3 cycle. >> >> But yes, let's tell regzbot that fixes are available, too: >> >> #regzbot fix: drm/i915: Fix HPD polling, reenabling the output poll work >> as needed >> >> (for the record: that's the second of two patches apparently needed) >> >> Ciao, Thorsten (wearing his 'the Linux kernel's regression tracker' hat) >> -- >> Everything you wanna know about Linux kernel regression tracking: >> https://linux-regtracking.leemhuis.info/about/#tldr >> If I did something stupid, please tell me, as explained on that page. >> >> >> BTW, there was an earlier report about a problem with a4e771729a51 that >> >> afaics was never addressed, but it might be unrelated. >> >> https://lore.kernel.org/all/20230328023129.3596968-1-zhouzong...@kylinos.cn/ >> > [1] https://patchwork.freedesktop.org/patch/548590/?series=121050&rev=1 >> > [2] https://patchwork.freedesktop.org/patch/548591/?series=121050&rev=1 >> -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/dgfx: Enable d3cold at s2idle
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Monday, August 14, 2023 9:33 PM
> To: Gupta, Anshuman
> Cc: intel-gfx@lists.freedesktop.org; Nilawar, Badal
> ; Tauro, Riana
> Subject: Re: [PATCH] drm/i915/dgfx: Enable d3cold at s2idle
>
> On Mon, Aug 14, 2023 at 04:34:18PM +0530, Anshuman Gupta wrote:
> > System wide suspend already has support for lmem save/restore during
> > suspend therefore enabling d3cold for s2idle and keepng it disable for
> > runtime PM.(Refer below commit for d3cold runtime PM disable
> > justification) 'commit 66eb93e71a7a ("drm/i915/dgfx: Keep PCI
> > autosuspend control 'on' by default on all dGPU")'
> >
> > It will reduce the DG2 Card power consumption to ~0 Watt for s2idle
> > power KPI.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8755
> > Cc: Rodrigo Vivi
> > Signed-off-by: Anshuman Gupta
>
> Reviewed-by: Rodrigo Vivi
Hi Rodrigo,
Thanks for review, will this be good candidate for Linux stable tree ?
Thanks,
Anshuman Gupta.
>
> > ---
> > drivers/gpu/drm/i915/i915_driver.c | 33
> > --
> > 1 file changed, 18 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index b870c0df081a..ec4d26b3c17c 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -443,7 +443,6 @@ static int i915_pcode_init(struct drm_i915_private
> > *i915) static int i915_driver_hw_probe(struct drm_i915_private
> > *dev_priv) {
> > struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > - struct pci_dev *root_pdev;
> > int ret;
> >
> > if (i915_inject_probe_failure(dev_priv))
> > @@ -557,15 +556,6 @@ static int i915_driver_hw_probe(struct
> > drm_i915_private *dev_priv)
> >
> > intel_bw_init_hw(dev_priv);
> >
> > - /*
> > -* FIXME: Temporary hammer to avoid freezing the machine on our
> DGFX
> > -* This should be totally removed when we handle the pci states
> properly
> > -* on runtime PM and on s2idle cases.
> > -*/
> > - root_pdev = pcie_find_root_port(pdev);
> > - if (root_pdev)
> > - pci_d3cold_disable(root_pdev);
> > -
> > return 0;
> >
> > err_opregion:
> > @@ -591,7 +581,6 @@ static int i915_driver_hw_probe(struct
> > drm_i915_private *dev_priv) static void i915_driver_hw_remove(struct
> > drm_i915_private *dev_priv) {
> > struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > - struct pci_dev *root_pdev;
> >
> > i915_perf_fini(dev_priv);
> >
> > @@ -599,10 +588,6 @@ static void i915_driver_hw_remove(struct
> > drm_i915_private *dev_priv)
> >
> > if (pdev->msi_enabled)
> > pci_disable_msi(pdev);
> > -
> > - root_pdev = pcie_find_root_port(pdev);
> > - if (root_pdev)
> > - pci_d3cold_enable(root_pdev);
> > }
> >
> > /**
> > @@ -1519,6 +1504,8 @@ static int intel_runtime_suspend(struct device
> > *kdev) {
> > struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
> > + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > + struct pci_dev *root_pdev;
> > struct intel_gt *gt;
> > int ret, i;
> >
> > @@ -1570,6 +1557,15 @@ static int intel_runtime_suspend(struct device
> *kdev)
> > drm_err(&dev_priv->drm,
> > "Unclaimed access detected prior to suspending\n");
> >
> > + /*
> > +* FIXME: Temporary hammer to avoid freezing the machine on our
> DGFX
> > +* This should be totally removed when we handle the pci states
> properly
> > +* on runtime PM.
> > +*/
> > + root_pdev = pcie_find_root_port(pdev);
> > + if (root_pdev)
> > + pci_d3cold_disable(root_pdev);
> > +
> > rpm->suspended = true;
> >
> > /*
> > @@ -1608,6 +1604,8 @@ static int intel_runtime_resume(struct device
> > *kdev) {
> > struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
> > + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > + struct pci_dev *root_pdev;
> > struct intel_gt *gt;
> > int ret, i;
> >
> > @@ -1621,6 +1619,11 @@ static int intel_runtime_resume(struct device
> > *kdev)
> >
> > intel_opregion_notify_adapter(dev_priv, PCI_D0);
> > rpm->suspended = false;
> > +
> > + root_pdev = pcie_find_root_port(pdev);
> > + if (root_pdev)
> > + pci_d3cold_enable(root_pdev);
> > +
> > if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
> > drm_dbg(&dev_priv->drm,
> > "Unclaimed access during suspend, bios?\n");
> > --
> > 2.25.1
> >
