[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Add new DG2 PCI IDs

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Add new DG2 PCI IDs
URL   : https://patchwork.freedesktop.org/series/124937/
State : failure

== Summary ==

Error: make failed
  CALLscripts/checksyscalls.sh
  DESCEND objtool
  INSTALL libsubcmd_headers
  CC  arch/x86/kernel/early-quirks.o
In file included from arch/x86/kernel/early-quirks.c:21:
./include/drm/i915_pciids.h:695:2: error: expected ‘;’ before ‘extern’
  695 | h
  |  ^
  |  ;
make[4]: *** [scripts/Makefile.build:243: arch/x86/kernel/early-quirks.o] Error 
1
make[3]: *** [scripts/Makefile.build:480: arch/x86/kernel] Error 2
make[2]: *** [scripts/Makefile.build:480: arch/x86] Error 2
make[1]: *** [/home/kbuild/kernel/Makefile:1913: .] Error 2
make: *** [Makefile:234: __sub-make] Error 2
Build failed, no error log produced

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/lnl: Remove watchdog timers for PSR (rev3)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915/lnl: Remove watchdog timers for PSR (rev3)
URL   : https://patchwork.freedesktop.org/series/124715/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13735_full -> Patchwork_124715v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_124715v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_124715v3_full, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_124715v3_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_rotation_crc@bad-pixel-format:
- shard-rkl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13735/shard-rkl-1/igt@kms_rotation_...@bad-pixel-format.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-rkl-1/igt@kms_rotation_...@bad-pixel-format.html

  
New tests
-

  New tests have been introduced between CI_DRM_13735_full and 
Patchwork_124715v3_full:

### New IGT tests (1) ###

  * igt@kms_content_protection@srm@pipe-a-dp-4:
- Statuses : 1 timeout(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_124715v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@blit-reloc-keep-cache:
- shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8411])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-mtlp-7/igt@api_intel...@blit-reloc-keep-cache.html

  * igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg2:  NOTRUN -> [SKIP][4] ([i915#8411])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-dg2-7/igt@api_intel...@object-reloc-purge-cache.html

  * igt@device_reset@cold-reset-bound:
- shard-mtlp: NOTRUN -> [SKIP][5] ([i915#7701])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-mtlp-7/igt@device_re...@cold-reset-bound.html

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl:  [PASS][6] -> [FAIL][7] ([i915#7742])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13735/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-rkl-3/igt@drm_fdinfo@most-busy-check-...@rcs0.html

  * igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
- shard-dg2:  NOTRUN -> [SKIP][8] ([i915#8414]) +21 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-dg2-11/igt@drm_fdinfo@most-busy-idle-check-...@vecs1.html

  * igt@drm_fdinfo@virtual-busy-hang-all:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#8414])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-mtlp-8/igt@drm_fdi...@virtual-busy-hang-all.html

  * igt@gem_close_race@multigpu-basic-process:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#7697])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-mtlp-8/igt@gem_close_r...@multigpu-basic-process.html

  * igt@gem_ctx_isolation@preservation-s3@vcs1:
- shard-mtlp: [PASS][11] -> [ABORT][12] ([i915#9262])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13735/shard-mtlp-3/igt@gem_ctx_isolation@preservation...@vcs1.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-mtlp-4/igt@gem_ctx_isolation@preservation...@vcs1.html

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-mtlp: [PASS][13] -> [DMESG-WARN][14] ([i915#9262])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13735/shard-mtlp-3/igt@gem_ctx_isolation@preservation...@vecs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-mtlp-4/igt@gem_ctx_isolation@preservation...@vecs0.html

  * igt@gem_ctx_persistence@legacy-engines-cleanup:
- shard-snb:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1099])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-cleanup.html

  * igt@gem_eio@hibernate:
- shard-dg2:  NOTRUN -> [ABORT][16] ([i915#7975] / [i915#8213])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-dg2-1/igt@gem_...@hibernate.html

  * igt@gem_eio@kms:
- shard-dg2:  [PASS][17] -> [FAIL][18] ([i915#5784])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13735/shard-dg2-7/igt@gem_...@kms.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/shard-dg2-3/

Re: [Intel-gfx] [PATCH 1/4] drm/i915/gvt: remove unused to_gvt() and reduce includes

2023-10-10 Thread Zhenyu Wang 
On 2023.10.04 15:54:11 +0300, Jani Nikula wrote:
> On Tue, 26 Sep 2023, Jani Nikula  wrote:
> > gvt.h has no need to include i915_drv.h once the unused to_gvt() has
> > been removed.
> >
> > Signed-off-by: Jani Nikula 
> 
> Zhenyu, Zhi, ping?
> 

Sorry for late reply, as last week was full holiday here.

Reviewed-by: Zhenyu Wang 

I don't think I need to do extra pick and pull request for this or
let me know if you has question.

Thanks!

> 
> 
> 
> > ---
> >  drivers/gpu/drm/i915/gvt/gvt.h | 7 +--
> >  1 file changed, 1 insertion(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
> > index 53a0a42a50db..3a0624fe63bf 100644
> > --- a/drivers/gpu/drm/i915/gvt/gvt.h
> > +++ b/drivers/gpu/drm/i915/gvt/gvt.h
> > @@ -39,7 +39,7 @@
> >  
> >  #include 
> >  
> > -#include "i915_drv.h"
> > +#include "gt/intel_gt.h"
> >  #include "intel_gvt.h"
> >  
> >  #include "debug.h"
> > @@ -368,11 +368,6 @@ struct intel_gvt {
> > struct dentry *debugfs_root;
> >  };
> >  
> > -static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
> > -{
> > -   return i915->gvt;
> > -}
> > -
> >  enum {
> > /* Scheduling trigger by timer */
> > INTEL_GVT_REQUEST_SCHED = 0,
> 
> -- 
> Jani Nikula, Intel


signature.asc
Description: PGP signature

[Intel-gfx] [PATCH] drm/i915: Add new DG2 PCI IDs

2023-10-10 Thread Shekhar Chauhan 
Add new PCI IDs which are recently added.

BSpec: 44477
Signed-off-by: Shekhar Chauhan 
---
 include/drm/i915_pciids.h | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 1256770d3827..deb2eb0b4979 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -692,7 +692,7 @@
INTEL_VGA_DEVICE(0xA7A9, info), \
INTEL_VGA_DEVICE(0xA7AC, info), \
INTEL_VGA_DEVICE(0xA7AD, info)
-
+h
 /* RPL-P */
 #define INTEL_RPLP_IDS(info) \
INTEL_RPLU_IDS(info), \
@@ -718,7 +718,11 @@
INTEL_VGA_DEVICE(0x56A5, info), \
INTEL_VGA_DEVICE(0x56A6, info), \
INTEL_VGA_DEVICE(0x56B0, info), \
-   INTEL_VGA_DEVICE(0x56B1, info)
+   INTEL_VGA_DEVICE(0x56B1, info), \
+   INTEL_VGA_DEVICE(0x56BA, info), \
+   INTEL_VGA_DEVICE(0x56BB, info), \
+   INTEL_VGA_DEVICE(0x56BC, info), \
+   INTEL_VGA_DEVICE(0x56BD, info)
 
 #define INTEL_DG2_G12_IDS(info) \
INTEL_VGA_DEVICE(0x5696, info), \
-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines
URL   : https://patchwork.freedesktop.org/series/124932/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13737 -> Patchwork_124932v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124932v1/index.html

Participating hosts (37 -> 37)
--

  Additional (1): fi-kbl-soraka 
  Missing(1): bat-dg2-9 

Known issues


  Here are the changes found in Patchwork_124932v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124932v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124932v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][3] ([i915#1886])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124932v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_dsc@dsc-basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +9 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124932v1/fi-kbl-soraka/igt@kms_...@dsc-basic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#1845]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124932v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613


Build changes
-

  * Linux: CI_DRM_13737 -> Patchwork_124932v1

  CI-20190529: 20190529
  CI_DRM_13737: c768959add20d28639e5bfa4cea2544aab51879e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7527: 46f98a3041f73a1d6ee7ec3ace6eba79b15369c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_124932v1: c768959add20d28639e5bfa4cea2544aab51879e @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

9c2d2f05c582 drm/i915: Enable GuC TLB invalidations for MTL
f663fd7b9b34 drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
baa79c5c2bfd drm/i915: No TLB invalidation on wedged GT
aecc6bc57042 drm/i915: No TLB invalidation on suspended GT
fde005228698 drm/i915: Define and use GuC and CTB TLB invalidation routines
80c7acef2d00 drm/i915/guc: Add CT size delay helper
d14d76eb585b drm/i915: Add GuC TLB Invalidation device info flags

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124932v1/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines
URL   : https://patchwork.freedesktop.org/series/124932/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines
URL   : https://patchwork.freedesktop.org/series/124932/
State : warning

== Summary ==

Error: dim checkpatch failed
3f043e9037de drm/i915: Add GuC TLB Invalidation device info flags
dcdab6a3e4e0 drm/i915/guc: Add CT size delay helper
1248f130a3fd drm/i915: Define and use GuC and CTB TLB invalidation routines
-:429: WARNING:MEMORY_BARRIER: memory barrier without comment
#429: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4729:
+   smp_store_mb(wq_entry->flags, wq_entry->flags & ~WQ_FLAG_WOKEN);

total: 0 errors, 1 warnings, 0 checks, 426 lines checked
6e7fd44a6545 drm/i915: No TLB invalidation on suspended GT
b8fe58e9fa02 drm/i915: No TLB invalidation on wedged GT
d7d906e001d1 drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
-:30: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see 
Documentation/timers/timers-howto.rst
#30: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:146:
+   msleep(10);

total: 0 errors, 1 warnings, 0 checks, 17 lines checked
5b7f6c362b58 drm/i915: Enable GuC TLB invalidations for MTL

Re: [Intel-gfx] Regression in linux-next

2023-10-10 Thread Borah, Chaitanya Kumar 
Hello Rafael,

> -Original Message-
> From: Wysocki, Rafael J 
> Sent: Tuesday, October 10, 2023 12:54 AM
> To: Borah, Chaitanya Kumar 
> Cc: intel-gfx@lists.freedesktop.org; Kurmi, Suresh Kumar
> ; Saarinen, Jani 
> Subject: Re: Regression in linux-next
> 
> Hi,
> 
> On 10/9/2023 7:10 AM, Borah, Chaitanya Kumar wrote:
> > Hello Rafael
> >
> >> Thanks for the report, I think that this is a lockdep assertion failing.
> >> If that is correct, it should be straightforward to fix.
> >> I'll take care of this early next week.
> >> Thanks!
> > Thank you for your response.  Please let us know when a fix is available.
> 
> It should be fixed in linux-next from today, by this commit:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-
> pm.git/commit/?h=linux-
> next&id=b4027ce7714f309e96b804b7fb088a40d708
> 
> Thanks!

Thanks a lot for the fix. This seems to have fixed the issue in most of the 
machines but we are still seeing a similar problem in few of the machines.

This has a different call stack but seems to be from the same thermal 
subsystem. Full logs in [1]

<4>[4.392015] WARNING: CPU: 1 PID: 306 at 
drivers/thermal/thermal_trip.c:178 thermal_zone_trip_id+0x61/0x70
<4>[4.392022] Modules linked in: x86_pkg_temp_thermal coretemp kvm_intel 
mei_pxp mei_hdcp wmi_bmof kvm e1000e irqbypass crct10dif_pclmul video ptp 
crc32_pclmul ghash_clmulni_intel i2c_i801 mei_me pps_core mei i2c_smbus wmi
<4>[4.392057] CPU: 1 PID: 306 Comm: thermald Not tainted 
6.6.0-rc5-next-20231010-next-20231010-gc0a6edb636cb+ #1
<4>[4.392061] Hardware name: System manufacturer System Product 
Name/Z170M-PLUS, BIOS 3610 03/29/2018
<4>[4.392063] RIP: 0010:thermal_zone_trip_id+0x61/0x70
<4>[4.392066] Code: 74 0c 83 c0 01 39 c8 75 f0 b8 c3 ff ff ff 5b 5d c3 cc 
cc cc cc 48 8d bf f0 05 00 00 be ff ff ff ff e8 63 a4 2d 00 85 c0 75 b5 <0f> 0b 
eb b1 66 2e 0f 1f 84 00 00 00 00 00 90 90 90 90 90 90 90 90
<4>[4.392069] RSP: 0018:c9000156bda8 EFLAGS: 00010246
<4>[4.392073] RAX:  RBX: 888103828ae8 RCX: 
0001
<4>[4.392075] RDX: 8000 RSI: 823de5ab RDI: 
823fdfba
<4>[4.392078] RBP: 888103a88800 R08: 888103828ae8 R09: 
0001
<4>[4.392080] R10: 0001 R11: 88811494d3c0 R12: 
888103a88818
<4>[4.392082] R13: 8881108bfa00 R14: 888103794408 R15: 
0001
<4>[4.392084] FS:  7f1f0d6d28c0() GS:88822e68() 
knlGS:
<4>[4.392087] CS:  0010 DS:  ES:  CR0: 80050033
<4>[4.392089] CR2: 55857c50b750 CR3: 000111efa005 CR4: 
003706f0
<4>[4.392091] DR0:  DR1:  DR2: 

<4>[4.392093] DR3:  DR6: fffe0ff0 DR7: 
0400
<4>[4.392095] Call Trace:
<4>[4.392097]  
<4>[4.392100]  ? __warn+0x7f/0x170
<4>[4.392104]  ? thermal_zone_trip_id+0x61/0x70
<4>[4.392109]  ? report_bug+0x1f8/0x200
<4>[4.392116]  ? handle_bug+0x3c/0x70
<4>[4.392119]  ? exc_invalid_op+0x18/0x70
<4>[4.392123]  ? asm_exc_invalid_op+0x1a/0x20
<4>[4.392133]  ? thermal_zone_trip_id+0x61/0x70
<4>[4.392137]  ? thermal_zone_trip_id+0x5d/0x70
<4>[4.392141]  trip_point_show+0x18/0x40
<4>[4.392145]  dev_attr_show+0x15/0x60
<4>[4.392149]  sysfs_kf_seq_show+0xb5/0x100
<4>[4.392154]  seq_read_iter+0x111/0x450
<4>[4.392158]  ? check_object+0x133/0x320
<4>[4.392164]  vfs_read+0x20d/0x300
<4>[4.392175]  ksys_read+0x64/0xe0
<4>[4.392180]  do_syscall_64+0x3c/0x90
<4>[4.392183]  entry_SYSCALL_64_after_hwframe+0x6e/0xd8
<4>[4.392187] RIP: 0033:0x7f1f0e193392

Can you please check what could be the reason for this issue?

[1] 
https://intel-gfx-ci.01.org/tree/linux-next/next-20231010/fi-kbl-guc/boot0.txt

Regards

Chaitanya




> 
> 
> > From: Wysocki, Rafael J 
> > Sent: Saturday, October 7, 2023 2:01 AM
> > To: Borah, Chaitanya Kumar 
> > Cc: intel-gfx@lists.freedesktop.org; Kurmi, Suresh Kumar
> > ; Saarinen, Jani
> > 
> > Subject: Re: Regression in linux-next
> >
> > Hi,
> > On 10/5/2023 5:58 PM, Borah, Chaitanya Kumar wrote:
> > Hello Rafael,
> >
> > Hope you are doing well. I am Chaitanya from the linux graphics team in
> Intel.
> > This mail is regarding a regression we are seeing in our CI runs[1] on 
> > linux-
> next repository.
> >
> > Thanks for the report, I think that this is a lockdep assertion failing.
> > If that is corre

[Intel-gfx] ✓ Fi.CI.BAT: success for Use intel_crtc_destroy state

2023-10-10 Thread Patchwork 
== Series Details ==

Series: Use intel_crtc_destroy state
URL   : https://patchwork.freedesktop.org/series/124919/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13737 -> Patchwork_124919v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124919v1/index.html

Participating hosts (37 -> 36)
--

  Missing(1): bat-dg2-9 

Known issues


  Here are the changes found in Patchwork_124919v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gt_mocs:
- bat-dg2-11: [PASS][1] -> [INCOMPLETE][2] ([i915#9253])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13737/bat-dg2-11/igt@i915_selftest@live@gt_mocs.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124919v1/bat-dg2-11/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][3] -> [ABORT][4] ([i915#9414])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13737/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124919v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  
  [i915#9253]: https://gitlab.freedesktop.org/drm/intel/issues/9253
  [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414


Build changes
-

  * Linux: CI_DRM_13737 -> Patchwork_124919v1

  CI-20190529: 20190529
  CI_DRM_13737: c768959add20d28639e5bfa4cea2544aab51879e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7527: 46f98a3041f73a1d6ee7ec3ace6eba79b15369c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_124919v1: c768959add20d28639e5bfa4cea2544aab51879e @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

3631e060174a drm/i915/display: Use correct method to free crtc_state
2b1fad8fd49c drm/i915/display: Use intel_crtc_destroy_state instead kfree

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124919v1/index.html

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Implement range-based TLB

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Implement range-based TLB
URL   : https://patchwork.freedesktop.org/series/124922/
State : failure

== Summary ==

Error: make failed
  CALLscripts/checksyscalls.sh
  DESCEND objtool
  INSTALL libsubcmd_headers
  CC [M]  drivers/gpu/drm/i915/i915_vma.o
drivers/gpu/drm/i915/i915_vma.c:1343:4: error: expected ‘;’, ‘,’ or ‘)’ before 
‘u64’
 1343 |u64 start, u64 size)
  |^~~
make[6]: *** [scripts/Makefile.build:243: drivers/gpu/drm/i915/i915_vma.o] 
Error 1
make[5]: *** [scripts/Makefile.build:480: drivers/gpu/drm/i915] Error 2
make[4]: *** [scripts/Makefile.build:480: drivers/gpu/drm] Error 2
make[3]: *** [scripts/Makefile.build:480: drivers/gpu] Error 2
make[2]: *** [scripts/Makefile.build:480: drivers] Error 2
make[1]: *** [/home/kbuild/kernel/Makefile:1913: .] Error 2
make: *** [Makefile:234: __sub-make] Error 2
Build failed, no error log produced

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use intel_crtc_destroy state

2023-10-10 Thread Patchwork 
== Series Details ==

Series: Use intel_crtc_destroy state
URL   : https://patchwork.freedesktop.org/series/124919/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy 
expression type 31
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced 
symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced 
symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: un

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/1] drm/i915/pxp: Add drm_dbgs for critical PXP events. (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: series starting with [v2,1/1] drm/i915/pxp: Add drm_dbgs for critical 
PXP events. (rev2)
URL   : https://patchwork.freedesktop.org/series/123656/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13737 -> Patchwork_123656v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v2/index.html

Participating hosts (37 -> 36)
--

  Missing(1): fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_123656v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-bsw-n3050:   [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13737/fi-bsw-n3050/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v2/fi-bsw-n3050/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13737/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][5] -> [ABORT][6] ([i915#9414])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13737/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@lmem0:
- bat-dg2-9:  [INCOMPLETE][7] ([i915#9275]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13737/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v2/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html

  
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
  [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414


Build changes
-

  * Linux: CI_DRM_13737 -> Patchwork_123656v2

  CI-20190529: 20190529
  CI_DRM_13737: c768959add20d28639e5bfa4cea2544aab51879e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7527: 46f98a3041f73a1d6ee7ec3ace6eba79b15369c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_123656v2: c768959add20d28639e5bfa4cea2544aab51879e @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

3fb92abb05cf drm/i915/pxp: Add drm_dbgs for critical PXP events.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v2/index.html

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/1] drm/i915/pxp: Add drm_dbgs for critical PXP events. (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: series starting with [v2,1/1] drm/i915/pxp: Add drm_dbgs for critical 
PXP events. (rev2)
URL   : https://patchwork.freedesktop.org/series/123656/
State : warning

== Summary ==

Error: dim checkpatch failed
afd41e939c6c drm/i915/pxp: Add drm_dbgs for critical PXP events.
-:93: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#93: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_irq.c:43:
+   pxp->session_events |= PXP_TERMINATION_REQUEST | 
PXP_INVAL_REQUIRED | PXP_EVENT_TYPE_IRQ;

total: 0 errors, 1 warnings, 0 checks, 95 lines checked

Re: [Intel-gfx] [PATCH dii-client 1/2] drm/i915: Add generic interface for tlb invalidation

2023-10-10 Thread kernel test robot 
Hi Jonathan,

kernel test robot noticed the following build errors:

[auto build test ERROR on drm-tip/drm-tip]

url:
https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cavitt/drm-i915-Use-selective-tlb-invalidations-where-supported/20231011-034501
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:
https://lore.kernel.org/r/20231010184423.2118908-3-jonathan.cavitt%40intel.com
patch subject: [Intel-gfx] [PATCH dii-client 1/2] drm/i915: Add generic 
interface for tlb invalidation
config: x86_64-randconfig-001-20231011 
(https://download.01.org/0day-ci/archive/20231011/202310110932.rz34wr7w-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build): 
(https://download.01.org/0day-ci/archive/20231011/202310110932.rz34wr7w-...@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot 
| Closes: 
https://lore.kernel.org/oe-kbuild-all/202310110932.rz34wr7w-...@intel.com/

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/gt/intel_tlb.c: In function 
'intel_gt_invalidate_tlb_full':
   drivers/gpu/drm/i915/gt/intel_tlb.c:141:7: error: implicit declaration of 
function 'intel_guc_invalidate_tlb_full'; did you mean 
'intel_gt_invalidate_tlb_full'? [-Werror=implicit-function-declaration]
 141 |   if (intel_guc_invalidate_tlb_full(guc, 
INTEL_GUC_TLB_INVAL_MODE_HEAVY) < 0)
 |   ^
 |   intel_gt_invalidate_tlb_full
   drivers/gpu/drm/i915/gt/intel_tlb.c:141:42: error: 
'INTEL_GUC_TLB_INVAL_MODE_HEAVY' undeclared (first use in this function)
 141 |   if (intel_guc_invalidate_tlb_full(guc, 
INTEL_GUC_TLB_INVAL_MODE_HEAVY) < 0)
 |  
^~
   drivers/gpu/drm/i915/gt/intel_tlb.c:141:42: note: each undeclared identifier 
is reported only once for each function it appears in
   In file included from include/linux/bits.h:6,
from include/linux/ratelimit_types.h:5,
from include/linux/printk.h:9,
from include/asm-generic/bug.h:22,
from arch/x86/include/asm/bug.h:87,
from include/linux/plist.h:80,
from include/linux/pm_qos.h:15,
from drivers/gpu/drm/i915/i915_drv.h:35,
from drivers/gpu/drm/i915/gt/intel_tlb.c:6:
   drivers/gpu/drm/i915/gt/intel_tlb.c: In function 
'intel_gt_invalidate_tlb_range':
   drivers/gpu/drm/i915/gt/intel_tlb.c:190:41: error: 'const struct 
intel_device_info' has no member named 'ppgtt_size'
 190 |  vm_total = BIT_ULL(INTEL_INFO(gt->i915)->ppgtt_size);
 | ^~
   include/vdso/bits.h:8:34: note: in definition of macro 'BIT_ULL'
   8 | #define BIT_ULL(nr)  (ULL(1) << (nr))
 |  ^~
   drivers/gpu/drm/i915/gt/intel_tlb.c:195:9: error: implicit declaration of 
function 'intel_guc_invalidate_tlb_page_selective' 
[-Werror=implicit-function-declaration]
 195 |   ret = intel_guc_invalidate_tlb_page_selective(guc,
 | ^~~
   drivers/gpu/drm/i915/gt/intel_tlb.c:196:14: error: 
'INTEL_GUC_TLB_INVAL_MODE_HEAVY' undeclared (first use in this function)
 196 |  INTEL_GUC_TLB_INVAL_MODE_HEAVY,
 |  ^~
   In file included from drivers/gpu/drm/i915/gt/intel_tlb.c:214:
   drivers/gpu/drm/i915/gt/selftest_tlb.c: In function 'pte_tlbinv':
>> drivers/gpu/drm/i915/gt/selftest_tlb.c:161:1: error: version control 
>> conflict marker in file
 161 | <<< HEAD
 | ^~~
   drivers/gpu/drm/i915/gt/selftest_tlb.c:163:1: error: version control 
conflict marker in file
 163 | ===
 | ^~~
   drivers/gpu/drm/i915/gt/selftest_tlb.c:165:1: error: version control 
conflict marker in file
 165 | >>> 774058193c61b... INTEL_DII: drm/i915/xehpsdv: Add generic 
interface for tlb invalidation
 | ^~~
>> drivers/gpu/drm/i915/gt/selftest_tlb.c:165:9: error: invalid suffix 
>> "c61b..." on integer constant
 165 | >>> 774058193c61b... INTEL_DII: drm/i915/xehpsdv: Add generic 
interface for tlb invalidation
 | ^~~~
>> drivers/gpu/drm/i915/gt/selftest_tlb.c:150:28: warning: unused variable 
>> 'vb_res' [-Wunused-variable]
 150 |   struct i915_vma_resource vb_res = {
 |^~
>> drivers/gpu/drm/i915/gt/selftest_tlb.c:40:21: warning: unused variable 
>> 'pat_index' [-Wunused-variable]
  40 |  const unsigned int pat_index =
 | ^
   cc1: some warnings being treated as errors


vim +161 drivers/gpu/drm/i915/gt/selftest_tlb.c

30  
31  static int
32  pte_tlbinv(struct intel_contex

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines
URL   : https://patchwork.freedesktop.org/series/124917/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13737 -> Patchwork_124917v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124917v1/index.html

Participating hosts (37 -> 35)
--

  Missing(2): fi-hsw-4770 fi-bsw-n3050 

Known issues


  Here are the changes found in Patchwork_124917v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][1] -> [DMESG-FAIL][2] ([i915#7699])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13737/bat-dg2-11/igt@i915_selftest@l...@migrate.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124917v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html

  
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699


Build changes
-

  * Linux: CI_DRM_13737 -> Patchwork_124917v1

  CI-20190529: 20190529
  CI_DRM_13737: c768959add20d28639e5bfa4cea2544aab51879e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7527: 46f98a3041f73a1d6ee7ec3ace6eba79b15369c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_124917v1: c768959add20d28639e5bfa4cea2544aab51879e @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

0bf641461201 drm/i915: Enable GuC TLB invalidations for MTL
c08e9df848d3 drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
e5ca4f66491a drm/i915: No TLB invalidation on wedged GT
77d3a86daa4a drm/i915: No TLB invalidation on suspended GT
e61bb57a019e drm/i915: Define and use GuC and CTB TLB invalidation routines
c54bc97db213 drm/i915/guc: Add CT size delay helper
bbc80bca21a6 drm/i915: Add GuC TLB Invalidation device info flags

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124917v1/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines
URL   : https://patchwork.freedesktop.org/series/124917/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH v11 2/7] drm/i915/guc: Add CT size delay helper

2023-10-10 Thread Jonathan Cavitt 
Add a helper function to the GuC CT buffer that reports the expected
time to process all outstanding requests.  As of now, there is no
functionality to check number of requests in the buffer, so the helper
function just reports 2 seconds, or 1ms per request up to the maximum
number of requests the CT buffer can store.

Suggested-by: John Harrison 
Signed-off-by: Jonathan Cavitt 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 27 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  2 ++
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index c33210ead1ef7..03b616ba4ebb7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -103,6 +103,33 @@ enum { CTB_SEND = 0, CTB_RECV = 1 };
 
 enum { CTB_OWNER_HOST = 0 };
 
+/*
+ * Some H2G commands involve a synchronous response that the driver needs
+ * to wait for. In such cases, a timeout is required to prevent the driver
+ * from waiting forever in the case of an error (either no error response
+ * is defined in the protocol or something has died and requires a reset).
+ * The specific command may be defined as having a time bound response but
+ * the CT is a queue and that time guarantee only starts from the point
+ * when the command reaches the head of the queue and is processed by GuC.
+ *
+ * Ideally there would be a helper to report the progress of a given
+ * command through the CT. However, that would require a significant
+ * amount of work in the CT layer. In the meantime, provide a reasonable
+ * estimation of the worst case latency it should take for the entire
+ * queue to drain. And therefore, how long a caller should wait before
+ * giving up on their request. The current estimate is based on empirical
+ * measurement of a test that fills the buffer with context creation and
+ * destruction requests as they seem to be the slowest operation.
+ */
+long intel_guc_ct_max_queue_time_jiffies(void)
+{
+   /*
+* A 4KB buffer full of context destroy commands takes a little
+* over a second to process so bump that to 2s to be super safe.
+*/
+   return (CTB_H2G_BUFFER_SIZE * HZ) / SZ_2K;
+}
+
 static void ct_receive_tasklet_func(struct tasklet_struct *t);
 static void ct_incoming_request_worker_func(struct work_struct *w);
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 58e42901ff498..2c4bb9a941be6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -104,6 +104,8 @@ struct intel_guc_ct {
 #endif
 };
 
+long intel_guc_ct_max_queue_time_jiffies(void);
+
 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
 int intel_guc_ct_init(struct intel_guc_ct *ct);
 void intel_guc_ct_fini(struct intel_guc_ct *ct);
-- 
2.25.1

[Intel-gfx] [PATCH v11 5/7] drm/i915: No TLB invalidation on wedged GT

2023-10-10 Thread Jonathan Cavitt 
It is not an error for GuC TLB invalidations to fail when the GT is
wedged or disabled, so do not process a wait failure as one in
guc_send_invalidate_tlb.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
Reviewed-by: Andi Shyti 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c  | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9d5f8cccaa592..1914cba5f48dd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -32,6 +32,7 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "i915_irq.h"
 #include "i915_trace.h"
 
 /**
@@ -1941,6 +1942,12 @@ void intel_guc_submission_cancel_requests(struct 
intel_guc *guc)
 
/* GuC is blown away, drop all references to contexts */
xa_destroy(&guc->context_lookup);
+
+   /*
+* Wedged GT won't respond to any TLB invalidation request. Simply
+* release all the blocked waiters.
+*/
+   wake_up_all_tlb_invalidate(guc);
 }
 
 void intel_guc_submission_reset_finish(struct intel_guc *guc)
@@ -4740,6 +4747,14 @@ static long must_wait_woken(struct wait_queue_entry 
*wq_entry, long timeout)
return timeout;
 }
 
+static bool intel_gt_is_enabled(const struct intel_gt *gt)
+{
+   /* Check if GT is wedged or suspended */
+   if (intel_gt_is_wedged(gt) || !intel_irqs_enabled(gt->i915))
+   return false;
+   return true;
+}
+
 static int guc_send_invalidate_tlb(struct intel_guc *guc,
   enum intel_guc_tlb_invalidation_type type)
 {
@@ -4789,7 +4804,8 @@ static int guc_send_invalidate_tlb(struct intel_guc *guc,
if (err)
goto out;
 
-   if (!must_wait_woken(&wait, intel_guc_ct_max_queue_time_jiffies())) {
+   if (intel_gt_is_enabled(guc_to_gt(guc)) &&
+   !must_wait_woken(&wait, intel_guc_ct_max_queue_time_jiffies())) {
guc_err(guc,
"TLB invalidation response timed out for seqno %u\n", 
seqno);
err = -ETIME;
-- 
2.25.1

[Intel-gfx] [PATCH v11 1/7] drm/i915: Add GuC TLB Invalidation device info flags

2023-10-10 Thread Jonathan Cavitt 
Add device info flags for if GuC TLB Invalidation is enabled.

Signed-off-by: Jonathan Cavitt 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb60fc9cf8737..6a2a78c61f212 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,6 +794,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_GUC_DEPRIVILEGE(i915) \
(INTEL_INFO(i915)->has_guc_deprivilege)
 
+#define HAS_GUC_TLB_INVALIDATION(i915) 
(INTEL_INFO(i915)->has_guc_tlb_invalidation)
+
 #define HAS_3D_PIPELINE(i915)  (INTEL_INFO(i915)->has_3d_pipeline)
 
 #define HAS_ONE_EU_PER_FUSE_BIT(i915)  
(INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 39817490b13fd..eba2f0b919c87 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
+   func(has_guc_tlb_invalidation); \
func(has_l3_ccs_read); \
func(has_l3_dpf); \
func(has_llc); \
-- 
2.25.1

[Intel-gfx] [PATCH v11 7/7] drm/i915: Enable GuC TLB invalidations for MTL

2023-10-10 Thread Jonathan Cavitt 
Enable GuC TLB invalidations for MTL.  Though more platforms than just
MTL support GuC TLB invalidations, MTL is presently the only platform
that requires it for any purpose, so only enable it there for now to
minimize cross-platform impact.

Signed-off-by: Jonathan Cavitt 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index df7c261410f79..d4b51ececbb12 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -829,6 +829,7 @@ static const struct intel_device_info mtl_info = {
.has_flat_ccs = 0,
.has_gmd_id = 1,
.has_guc_deprivilege = 1,
+   .has_guc_tlb_invalidation = 1,
.has_llc = 0,
.has_mslice_steering = 0,
.has_snoop = 1,
-- 
2.25.1

[Intel-gfx] [PATCH v11 6/7] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck

2023-10-10 Thread Jonathan Cavitt 
For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.

Signed-off-by: Jonathan Cavitt 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c 
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 7e41f69fc818f..00b872b6380b1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -136,8 +136,15 @@ pte_tlbinv(struct intel_context *ce,
i915_request_get(rq);
i915_request_add(rq);
 
-   /* Short sleep to sanitycheck the batch is spinning before we begin */
-   msleep(10);
+   /*
+* Short sleep to sanitycheck the batch is spinning before we begin.
+* FIXME: Why is GSC so slow?
+*/
+   if (ce->engine->class == OTHER_CLASS)
+   msleep(200);
+   else
+   msleep(10);
+
if (va == vb) {
if (!i915_request_completed(rq)) {
pr_err("%s(%s): Semaphore sanitycheck failed %llx, with 
alignment %llx, using PTE size %x (phys %x, sg %x)\n",
-- 
2.25.1

[Intel-gfx] [PATCH v11 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Jonathan Cavitt 
Implement GuC-based TLB invalidations and use them on MTL.

Some complexity in the implementation was introduced early on
and will be required for range-based TLB invalidations.
RFC: https://patchwork.freedesktop.org/series/124922/

v2:
- Add missing supporting patches.

v3:
- Split suspend/resume changes and multi-gt support into separate
  patches.
- Only perform GuC TLB invalidation functions when supported.
- Move intel_guc_is_enabled check function to usage location.
- Address comments.

v4:
- Change conditions for GuC-based tlb invalidation support
  to a pci tag that's only active for MTL.
- Address some FIXMEs and formatting issues.
- Move suspend/resume changes to helper functions in intel_gt.h
- Improve comment for ct_handle_event change.
- Use cleaner if-else conditions.
- Address comments.

v5:
- Reintroduce missing change to selftest msleep duration
- Move suspend/resume loops from intel_gt.h to intel_tlb.c,
  making them no longer static inlines.
- Remove superfluous blocking and error checks.
- Move ct_handle_event exception to general case in
  ct_process_request.
- Explain usage of xa_alloc_cyclic_irq.
- Modify explanation of purpose of
  OUTSTANDING_GUC_TIMEOUT_PERIOD macro.
- Explain purpose of performing tlb invalidation twice in
  intel_gt_tlb_resume_all.

v6:
- Add this cover letter.
- Fix explanation of purpose of
  OUTSTANDING_GUC_TIMEOUT_PERIOD macro again.
- s/pci tags/pci flags
- Enable GuC TLB Invalidations separately from adding the
  flags to do so.

v7:
- Eliminate pci terminology from patches.
- Order new device info flag correctly.
- Run gen8_ggtt_invalidate in more cases, specifically when
  GuC-based TLB invalidation is not supported.
- Use intel_uncore_write_fw instead of intel_uncore_write
  during guc_ggtt_invalidate.
- Remove duplicate request message clear in ct_process_request.
- Remove faulty tag from series.

v8:
- Simplify cover letter contents.
- Fix miscellaneous formatting and typos.
- Reorder device info flags and defines.
- Reword commit message.
- Rename TLB invalidation enums and functions.
- Add comments explaining confusing points.
- Add helper function getting expected delay of CT buffer.
- Simplify intel_guc_tlb_invalidation_done by passing computed
  values.
- Remove helper functions for tlb suspend and resume.
- Move tlb suspend and resume paths to uc.
- Split suspend/resume and wedged into two patches.
- Clarify purpose of sleep change in tlb selftest.

v9:
- Explain complexity of GuC TLB invalidations as required for
  range-based TLB invalidations, which will be platformed later.
- Fix CHECKPATCH issues.
- Explain intel_guc_is_ready tlb invalidation skip in
  intel_gt_invalidate_tlb_full.
- Reword comment for unlocked xa_for_each loop in
  intel_guc_submission_reset.
- Report all errors in init_tlb_lookup.
- Remove debug message from fini_tlb_lookup.
- Use standardized interface for
  intel_guc_tlb_invalidation_done
- Remove spurious changes.
- Move wake_up_all_tlb_invalidate on wedge to correct patch.

v10:
- Add lock to tlb_lookup on guc submission reset.
- Add comment about why timeout increased from 10 ms to 20 ms
  by default in gt_tlb selftest.
- Remove spurious changes.

v11:
- Update CT size delay helper to be clearer.
- Reorder some function declarations.
- Clarify some comments.
- Produce error message if attempting to free a busy wait
  during fini_tlb_lookup.
- Revert default sleep back to 10 ms.
- Link to RFC.

Jonathan Cavitt (6):
  drm/i915: Add GuC TLB Invalidation device info flags
  drm/i915/guc: Add CT size delay helper
  drm/i915: No TLB invalidation on suspended GT
  drm/i915: No TLB invalidation on wedged GT
  drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
  drm/i915: Enable GuC TLB invalidations for MTL

Prathap Kumar Valsan (1):
  drm/i915: Define and use GuC and CTB TLB invalidation routines

 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 ++-
 drivers/gpu/drm/i915/gt/intel_tlb.c   |  16 +-
 drivers/gpu/drm/i915/gt/selftest_tlb.c|  11 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  22 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  31 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 211 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |   7 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_pci.c   |   1 +
 drivers/gpu/drm/i915/intel_device_info.h  |   1 +
 13 files changed, 358 insertions(+), 14 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH v11 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Jonathan Cavitt 
From: Prathap Kumar Valsan 

The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation.  We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back to GT invalidation when the GuC is
disabled.
The invalidation is done by sending a request directly to the GuC
tlb_lookup that invalidates the table.  The invalidation is submitted as
a wait request and is performed in the CT event handler.  This means we
cannot perform this TLB invalidation path if the CT is not enabled.
If the request isn't fulfilled in two seconds, this would constitute
an error in the invalidation as that would constitute either a lost
request or a severe GuC overload.

With this new invalidation routine, we can perform GuC-based GGTT
invalidations.  GuC-based GGTT invalidation is incompatible with
MMIO invalidation so we should not perform MMIO invalidation when
GuC-based GGTT invalidation is expected.

The additional complexity incurred in this patch will be necessary for
range-based tlb invalidations, which will be platformed in the future.

Signed-off-by: Prathap Kumar Valsan 
Signed-off-by: Bruce Chang 
Signed-off-by: Chris Wilson 
Signed-off-by: Umesh Nerlige Ramappa 
Signed-off-by: Jonathan Cavitt 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Fei Yang 
CC: Andi Shyti 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 +++-
 drivers/gpu/drm/i915/gt/intel_tlb.c   |  16 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  21 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 186 +-
 7 files changed, 283 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 4d7d88b92632b..a1f7bdc602996 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -206,22 +206,38 @@ static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 }
 
+static void guc_ggtt_ct_invalidate(struct intel_gt *gt)
+{
+   struct intel_uncore *uncore = gt->uncore;
+   intel_wakeref_t wakeref;
+
+   with_intel_runtime_pm_if_active(uncore->rpm, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+}
+
 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
struct drm_i915_private *i915 = ggtt->vm.i915;
+   struct intel_gt *gt;
 
-   gen8_ggtt_invalidate(ggtt);
-
-   if (GRAPHICS_VER(i915) >= 12) {
-   struct intel_gt *gt;
+   if (!HAS_GUC_TLB_INVALIDATION(i915))
+   gen8_ggtt_invalidate(ggtt);
 
-   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link)
+   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link) {
+   if (HAS_GUC_TLB_INVALIDATION(i915) &&
+   intel_guc_is_ready(>->uc.guc)) {
+   guc_ggtt_ct_invalidate(gt);
+   } else if (GRAPHICS_VER(i915) >= 12) {
intel_uncore_write_fw(gt->uncore,
  GEN12_GUC_TLB_INV_CR,
  GEN12_GUC_TLB_INV_CR_INVALIDATE);
-   } else {
-   intel_uncore_write_fw(ggtt->vm.gt->uncore,
- GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   } else {
+   intel_uncore_write_fw(gt->uncore,
+ GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   }
}
 }
 
@@ -1243,7 +1259,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
}
 
-   if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
+   if (intel_uc_wants_guc_submission(&ggtt->vm.gt->uc))
ggtt->invalidate = guc_ggtt_invalidate;
else
ggtt->invalidate = gen8_ggtt_invalidate;
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index 139608c30d978..4bb13d1890e37 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -12,6 +12,7 @@
 #include "intel_gt_print.h"
 #include "intel_gt_regs.h"
 #include "intel_tlb.h"
+#include "uc/intel_guc.h"
 
 /*
  * HW architecture suggest typical invalidation time at 40us,
@@ -131,11 +132,24 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, 
u32 seqno)
return;
 
with_intel_gt_pm_if_awake(gt, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
mutex_lock(>->tlb.invalidate_lock);
if (tlb_seqno_passed(gt, seqno))

[Intel-gfx] [PATCH v11 4/7] drm/i915: No TLB invalidation on suspended GT

2023-10-10 Thread Jonathan Cavitt 
In case of GT is suspended, don't allow submission of new TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 21 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  7 +++
 3 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 6af65d44b1a02..9a743d7059628 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -536,4 +536,5 @@ int intel_guc_invalidate_tlb_engines(struct intel_guc *guc);
 int intel_guc_invalidate_tlb_guc(struct intel_guc *guc);
 int intel_guc_tlb_invalidation_done(struct intel_guc *guc,
const u32 *payload, u32 len);
+void wake_up_all_tlb_invalidate(struct intel_guc *guc);
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 8e5a79ecfc2a2..9d5f8cccaa592 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1796,13 +1796,25 @@ static void __guc_reset_context(struct intel_context 
*ce, intel_engine_mask_t st
intel_context_put(parent);
 }
 
-void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
+void wake_up_all_tlb_invalidate(struct intel_guc *guc)
 {
struct intel_guc_tlb_wait *wait;
+   unsigned long i;
+
+   if (!HAS_GUC_TLB_INVALIDATION(guc_to_gt(guc)->i915))
+   return;
+
+   xa_lock_irq(&guc->tlb_lookup);
+   xa_for_each(&guc->tlb_lookup, i, wait)
+   wake_up(&wait->wq);
+   xa_unlock_irq(&guc->tlb_lookup);
+}
+
+void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
+{
struct intel_context *ce;
unsigned long index;
unsigned long flags;
-   unsigned long i;
 
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
@@ -1833,10 +1845,7 @@ void intel_guc_submission_reset(struct intel_guc *guc, 
intel_engine_mask_t stall
 * The full GT reset will have cleared the TLB caches and flushed the
 * G2H message queue; we can release all the blocked waiters.
 */
-   xa_lock_irq(&guc->tlb_lookup);
-   xa_for_each(&guc->tlb_lookup, i, wait)
-   wake_up(&wait->wq);
-   xa_unlock_irq(&guc->tlb_lookup);
+   wake_up_all_tlb_invalidate(guc);
 }
 
 static void guc_cancel_context_requests(struct intel_context *ce)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 98b103375b7ab..750cb63503dd7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -688,6 +688,8 @@ void intel_uc_suspend(struct intel_uc *uc)
/* flush the GSC worker */
intel_gsc_uc_flush_work(&uc->gsc);
 
+   wake_up_all_tlb_invalidate(guc);
+
if (!intel_guc_is_ready(guc)) {
guc->interrupts.enabled = false;
return;
@@ -736,6 +738,11 @@ static int __uc_resume(struct intel_uc *uc, bool 
enable_communication)
 
intel_gsc_uc_resume(&uc->gsc);
 
+   if (HAS_GUC_TLB_INVALIDATION(gt->i915)) {
+   intel_guc_invalidate_tlb_engines(guc);
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+
return 0;
 }
 
-- 
2.25.1

Re: [Intel-gfx] [PATCH dii-client 1/2] drm/i915: Add generic interface for tlb invalidation

2023-10-10 Thread kernel test robot 
Hi Jonathan,

kernel test robot noticed the following build errors:

[auto build test ERROR on drm-tip/drm-tip]

url:
https://github.com/intel-lab-lkp/linux/commits/Jonathan-Cavitt/drm-i915-Use-selective-tlb-invalidations-where-supported/20231011-034501
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:
https://lore.kernel.org/r/20231010184423.2118908-3-jonathan.cavitt%40intel.com
patch subject: [Intel-gfx] [PATCH dii-client 1/2] drm/i915: Add generic 
interface for tlb invalidation
config: i386-buildonly-randconfig-002-20231011 
(https://download.01.org/0day-ci/archive/20231011/202310110727.6wnxzyai-...@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): 
(https://download.01.org/0day-ci/archive/20231011/202310110727.6wnxzyai-...@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot 
| Closes: 
https://lore.kernel.org/oe-kbuild-all/202310110727.6wnxzyai-...@intel.com/

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/gt/intel_tlb.c: In function 
'intel_gt_invalidate_tlb_full':
>> drivers/gpu/drm/i915/gt/intel_tlb.c:141:21: error: implicit declaration of 
>> function 'intel_guc_invalidate_tlb_full'; did you mean 
>> 'intel_gt_invalidate_tlb_full'? [-Werror=implicit-function-declaration]
 141 | if (intel_guc_invalidate_tlb_full(guc, 
INTEL_GUC_TLB_INVAL_MODE_HEAVY) < 0)
 | ^
 | intel_gt_invalidate_tlb_full
>> drivers/gpu/drm/i915/gt/intel_tlb.c:141:56: error: 
>> 'INTEL_GUC_TLB_INVAL_MODE_HEAVY' undeclared (first use in this function)
 141 | if (intel_guc_invalidate_tlb_full(guc, 
INTEL_GUC_TLB_INVAL_MODE_HEAVY) < 0)
 |
^~
   drivers/gpu/drm/i915/gt/intel_tlb.c:141:56: note: each undeclared identifier 
is reported only once for each function it appears in
   In file included from include/linux/bits.h:6,
from include/linux/ratelimit_types.h:5,
from include/linux/printk.h:9,
from include/asm-generic/bug.h:22,
from arch/x86/include/asm/bug.h:87,
from include/linux/plist.h:80,
from include/linux/pm_qos.h:15,
from drivers/gpu/drm/i915/i915_drv.h:35,
from drivers/gpu/drm/i915/gt/intel_tlb.c:6:
   drivers/gpu/drm/i915/gt/intel_tlb.c: In function 
'intel_gt_invalidate_tlb_range':
>> drivers/gpu/drm/i915/gt/intel_tlb.c:190:48: error: 'const struct 
>> intel_device_info' has no member named 'ppgtt_size'
 190 | vm_total = BIT_ULL(INTEL_INFO(gt->i915)->ppgtt_size);
 |^~
   include/vdso/bits.h:8:45: note: in definition of macro 'BIT_ULL'
   8 | #define BIT_ULL(nr) (ULL(1) << (nr))
 | ^~
>> drivers/gpu/drm/i915/gt/intel_tlb.c:195:23: error: implicit declaration of 
>> function 'intel_guc_invalidate_tlb_page_selective' 
>> [-Werror=implicit-function-declaration]
 195 | ret = intel_guc_invalidate_tlb_page_selective(guc,
 |   ^~~
   drivers/gpu/drm/i915/gt/intel_tlb.c:196:63: error: 
'INTEL_GUC_TLB_INVAL_MODE_HEAVY' undeclared (first use in this function)
 196 |   
INTEL_GUC_TLB_INVAL_MODE_HEAVY,
 |   
^~
   cc1: some warnings being treated as errors


vim +141 drivers/gpu/drm/i915/gt/intel_tlb.c

   120  
   121  void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno)
   122  {
   123  intel_wakeref_t wakeref;
   124  
   125  if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
   126  return;
   127  
   128  if (intel_gt_is_wedged(gt))
   129  return;
   130  
   131  if (tlb_seqno_passed(gt, seqno))
   132  return;
   133  
   134  with_intel_gt_pm_if_awake(gt, wakeref) {
   135  struct intel_guc *guc = >->uc.guc;
   136  
   137  mutex_lock(>->tlb.invalidate_lock);
   138  if (tlb_seqno_passed(gt, seqno))
   139  goto unlock;
   140  
 > 141  if (intel_guc_invalidate_tlb_full(guc, 
 > INTEL_GUC_TLB_INVAL_MODE_HEAVY) < 0)
   142  mmio_invalidate_full(gt);
   143  
   144  write_seqcount_invalidate(>->tlb.seqno);
   145  unlock:
   146  mutex_unlock(>->tlb.invalidate_lock);
   147  }
   148  }
   149  
   150  static u64 tlb_page_

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Temporarily force MTL into uncached mode (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915/gt: Temporarily force MTL into uncached mode (rev2)
URL   : https://patchwork.freedesktop.org/series/124866/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13736 -> Patchwork_124866v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/index.html

Participating hosts (36 -> 37)
--

  Additional (1): fi-hsw-4770 

Known issues


  Here are the changes found in Patchwork_124866v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-bsw-n3050:   [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-bsw-n3050/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-bsw-n3050/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#6645])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#5190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][7] -> [FAIL][8] ([IGT#3])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271]) +12 other tests 
skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-vga-1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-kbl-guc: NOTRUN -> [SKIP][10] ([fdo#109271])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-kbl-guc/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770:NOTRUN -> [DMESG-WARN][11] ([i915#8841]) +6 other 
tests dmesg-warn
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-vga-1.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1072]) +3 
other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@i915_selftest@live@requests:
- bat-mtlp-8: [ABORT][13] ([i915#9414]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-mtlp-6: [FAIL][15] ([fdo#103375]) -> [PASS][16] +2 other 
tests pass
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/bat-mtlp-6/igt@i915_susp...@basic-s2idle-without-i915.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/bat-mtlp-6/igt@i915_susp...@basic-s2idle-without-i915.html
- fi-apl-guc: [INCOMPLETE][17] ([i915#1982] / [i915#4528]) -> 
[PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-apl-guc/igt@i915_susp...@basic-s2idle-without-i915.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-apl-guc/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-guc: [ABORT][19] -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-kbl-guc/igt@i915_susp...@basic-s3-without-i915.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124866v2/fi-kbl-guc/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Temporarily force MTL into uncached mode (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915/gt: Temporarily force MTL into uncached mode (rev2)
URL   : https://patchwork.freedesktop.org/series/124866/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v10 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread John Harrison 

On 10/10/2023 15:30, Cavitt, Jonathan wrote:

-Original Message-
From: Harrison, John C 
Sent: Tuesday, October 10, 2023 2:51 PM
To: Cavitt, Jonathan ; 
intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; chris.p.wil...@linux.intel.com; Iddamsetty, Aravind 
; Yang, Fei ; Shyti, Andi ; 
Das, Nirmoy ; Krzysztofik, Janusz ; Roper, Matthew D 
; tvrtko.ursu...@linux.intel.com; jani.nik...@linux.intel.com
Subject: Re: [PATCH v10 3/7] drm/i915: Define and use GuC and CTB TLB 
invalidation routines

On 10/10/2023 08:02, Jonathan Cavitt wrote:

...

+static void fini_tlb_lookup(struct intel_guc *guc)
+{
+   struct intel_guc_tlb_wait *wait;
+
+   if (!HAS_GUC_TLB_INVALIDATION(guc_to_gt(guc)->i915))
+   return;
+
+   wait = xa_load(&guc->tlb_lookup, guc->serial_slot);
+   kfree(wait);

There was originally a error being printed if wait->busy was still set,
i.e. someone was still waiting on the object that is about to be
destroyed. There were review comments about that being broken in an
intermediate patch set. I don't recall seeing any explanation as to why
the error message should be completely removed.


The GEM_BUG_ON was downgraded to a debug message in an intermediate step
at the request of one of the reviewers (this was a version 8 change, IIRC).
We concluded that if the execution of the system was not impacted by the debug
path, we shouldn't bother with the debug message at all.  So we removed it.
I think it was Fei or Andi that suggested it?
-Jonathan Cavitt
I recall it was me that said it should be an error message rather than a 
BUG_ON. And my point is that I don't see how this is a 'debug path'. If 
a waiter is still waiting on the wait object that is about to be freed 
then that is a potential dangling pointer dereference. That totally has 
the possibility to impact execution of the system.


John.

[Intel-gfx] ✓ Fi.CI.BAT: success for Add drm_dbg_ratelimited()

2023-10-10 Thread Patchwork 
== Series Details ==

Series: Add drm_dbg_ratelimited()
URL   : https://patchwork.freedesktop.org/series/124894/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13736 -> Patchwork_124894v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/index.html

Participating hosts (36 -> 37)
--

  Additional (1): bat-dg2-8 

Known issues


  Here are the changes found in Patchwork_124894v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-9:  [PASS][1] -> [INCOMPLETE][2] ([i915#9275])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
- bat-mtlp-8: NOTRUN -> [FAIL][3] ([fdo#103375]) +6 other tests fail
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_mmap@basic:
- bat-dg2-8:  NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-8:  NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@gem_mmap_...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-8:  NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-8:  NOTRUN -> [SKIP][7] ([i915#6621])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@i915_pm_...@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#6645])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html
- bat-dg2-8:  NOTRUN -> [SKIP][9] ([i915#6645])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-8:  NOTRUN -> [SKIP][10] ([i915#5190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-8:  NOTRUN -> [SKIP][11] ([i915#4215] / [i915#5190])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-8:  NOTRUN -> [SKIP][12] ([i915#4212]) +6 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-8:  NOTRUN -> [SKIP][13] ([i915#4212] / [i915#5608])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-8:  NOTRUN -> [SKIP][14] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-8:  NOTRUN -> [SKIP][15] ([fdo#109285])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-8:  NOTRUN -> [SKIP][16] ([i915#5274])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/bat-dg2-8/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][17] -> [FAIL][18] ([IGT#3])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-kbl-guc: NOTRUN -> [SKIP][19] ([fdo#109271])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124894v1/fi-kbl-guc/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@cursor_plane_move:
- bat-dg2-8:  NOTRUN -> [SKIP][20] ([i915#1072]) +3 other tests skip
   [20]: 
https://int

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add drm_dbg_ratelimited()

2023-10-10 Thread Patchwork 
== Series Details ==

Series: Add drm_dbg_ratelimited()
URL   : https://patchwork.freedesktop.org/series/124894/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add drm_dbg_ratelimited()

2023-10-10 Thread Patchwork 
== Series Details ==

Series: Add drm_dbg_ratelimited()
URL   : https://patchwork.freedesktop.org/series/124894/
State : warning

== Summary ==

Error: dim checkpatch failed
b31dca360377 drm/print: Add drm_dbg_ratelimited
f2b0f288ffbb drm/i915: Ratelimit debug log in vm_fault_ttm
-:9: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'References:', use 
'Link:' or 'Closes:' instead
#9: 
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7038

total: 0 errors, 1 warnings, 0 checks, 11 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for Framework for display parameters (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: Framework for display parameters (rev2)
URL   : https://patchwork.freedesktop.org/series/124645/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13736 -> Patchwork_124645v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v2/index.html

Participating hosts (36 -> 37)
--

  Additional (1): fi-hsw-4770 

Known issues


  Here are the changes found in Patchwork_124645v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-hsw-4770:NOTRUN -> [FAIL][1] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v2/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@mman:
- bat-rpls-1: [PASS][2] -> [TIMEOUT][3] ([i915#6794] / [i915#7392])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/bat-rpls-1/igt@i915_selftest@l...@mman.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v2/bat-rpls-1/igt@i915_selftest@l...@mman.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-1: [PASS][4] -> [WARN][5] ([i915#8747])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v2/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][6] ([i915#3546]) +2 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v2/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-kbl-guc: NOTRUN -> [SKIP][7] ([fdo#109271])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v2/fi-kbl-guc/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  
 Possible fixes 

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-mtlp-6: [FAIL][8] ([fdo#103375]) -> [PASS][9] +2 other tests 
pass
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/bat-mtlp-6/igt@i915_susp...@basic-s2idle-without-i915.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v2/bat-mtlp-6/igt@i915_susp...@basic-s2idle-without-i915.html
- fi-apl-guc: [INCOMPLETE][10] ([i915#1982] / [i915#4528]) -> 
[PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-apl-guc/igt@i915_susp...@basic-s2idle-without-i915.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v2/fi-apl-guc/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-guc: [ABORT][12] -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-kbl-guc/igt@i915_susp...@basic-s3-without-i915.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v2/fi-kbl-guc/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
  [i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
  [i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#8747]: https://gitlab.freedesktop.org/drm/intel/issues/8747
  [i915#8981]: https://gitlab.freedesktop.org/drm/intel/issues/8981


Build changes
-

  * Linux: CI_DRM_13736 -> Patchwork_124645v2

  CI-20190529: 20190529
  CI_DRM_13736: 251e78c6b6f76712187d25034bc2ebed0eb33654 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7527: 46f98a3041f73a1d6ee7ec3ace6eba79b15369c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_124645v2: 251e78c6b6f76712187d25034bc2ebed0eb33654 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

d8ddae195a28 drm/i915/display: Use same permissions for enable_sagv as for rest
d27eb23603d4 drm/i915/display: Move enable_dp_mst under display
13f57f255bf7 drm/i915/display: Move nuclear_pageflip under display
48ba8d0e105e drm/i915/display: Move verbose_state_checks under display
64fdc54e5683 drm/i915/display: Use device parameters instead of module in 
I915_STATE_WARN
e5fcb32bf7d8 drm/i915/display: Move disable_display parameter under display
bd9d5d54b131 drm/i915/display: M

Re: [Intel-gfx] [PATCH v10 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Cavitt, Jonathan 
-Original Message-
From: Harrison, John C  
Sent: Tuesday, October 10, 2023 2:51 PM
To: Cavitt, Jonathan ; 
intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; chris.p.wil...@linux.intel.com; 
Iddamsetty, Aravind ; Yang, Fei 
; Shyti, Andi ; Das, Nirmoy 
; Krzysztofik, Janusz ; 
Roper, Matthew D ; tvrtko.ursu...@linux.intel.com; 
jani.nik...@linux.intel.com
Subject: Re: [PATCH v10 3/7] drm/i915: Define and use GuC and CTB TLB 
invalidation routines
> 
> On 10/10/2023 08:02, Jonathan Cavitt wrote:
> > From: Prathap Kumar Valsan 
> >
> > The GuC firmware had defined the interface for Translation Look-Aside
> > Buffer (TLB) invalidation.  We should use this interface when
> > invalidating the engine and GuC TLBs.
> > Add additional functionality to intel_gt_invalidate_tlb, invalidating
> > the GuC TLBs and falling back to GT invalidation when the GuC is
> > disabled.
> > The invalidation is done by sending a request directly to the GuC
> > tlb_lookup that invalidates the table.  The invalidation is submitted as
> > a wait request and is performed in the CT event handler.  This means we
> > cannot perform this TLB invalidation path if the CT is not enabled.
> > If the request isn't fulfilled in two seconds, this would constitute
> > an error in the invalidation as that would constitute either a lost
> > request or a severe GuC overload.
> >
> > With this new invalidation routine, we can perform GuC-based GGTT
> > invalidations.  GuC-based GGTT invalidation is incompatible with
> > MMIO invalidation so we should not perform MMIO invalidation when
> > GuC-based GGTT invalidation is expected.
> >
> > The additional complexity incurred in this patch will be necessary for
> > range-based tlb invalidations, which will be platformed in the future.
> >
> > Signed-off-by: Prathap Kumar Valsan 
> > Signed-off-by: Bruce Chang 
> > Signed-off-by: Chris Wilson 
> > Signed-off-by: Umesh Nerlige Ramappa 
> > Signed-off-by: Jonathan Cavitt 
> > Signed-off-by: Aravind Iddamsetty 
> > Signed-off-by: Fei Yang 
> > CC: Andi Shyti 
> > ---
> >   drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 +++-
> >   drivers/gpu/drm/i915/gt/intel_tlb.c   |  16 +-
> >   .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.h|  22 +++
> >   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
> >   drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 186 +-
> >   7 files changed, 284 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
> > b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > index 4d7d88b92632b..a1f7bdc602996 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > @@ -206,22 +206,38 @@ static void gen8_ggtt_invalidate(struct i915_ggtt 
> > *ggtt)
> > intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
> >   }
> >   
> > +static void guc_ggtt_ct_invalidate(struct intel_gt *gt)
> > +{
> > +   struct intel_uncore *uncore = gt->uncore;
> > +   intel_wakeref_t wakeref;
> > +
> > +   with_intel_runtime_pm_if_active(uncore->rpm, wakeref) {
> > +   struct intel_guc *guc = >->uc.guc;
> > +
> > +   intel_guc_invalidate_tlb_guc(guc);
> > +   }
> > +}
> > +
> >   static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
> >   {
> > struct drm_i915_private *i915 = ggtt->vm.i915;
> > +   struct intel_gt *gt;
> >   
> > -   gen8_ggtt_invalidate(ggtt);
> > -
> > -   if (GRAPHICS_VER(i915) >= 12) {
> > -   struct intel_gt *gt;
> > +   if (!HAS_GUC_TLB_INVALIDATION(i915))
> > +   gen8_ggtt_invalidate(ggtt);
> >   
> > -   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link)
> > +   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link) {
> > +   if (HAS_GUC_TLB_INVALIDATION(i915) &&
> > +   intel_guc_is_ready(>->uc.guc)) {
> > +   guc_ggtt_ct_invalidate(gt);
> > +   } else if (GRAPHICS_VER(i915) >= 12) {
> > intel_uncore_write_fw(gt->uncore,
> >   GEN12_GUC_TLB_INV_CR,
> >   GEN12_GUC_TLB_INV_CR_INVALIDATE);
> > -   } else {
> > -   intel_uncore_write_fw(ggtt->vm.gt->uncore,
> > - GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> > +   } else {
> > +   intel_uncore_write_fw(gt->uncore,
> > + GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> > +   }
> > }
> >   }
> >   
> > @@ -1243,7 +1259,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> > ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
> > }
> >   
> > -   if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
> > +   if (intel_uc_wants_guc_submission(&ggtt->vm.gt->uc))
> > ggtt->invalidate = guc_ggtt_invalidate;
> > else
> > ggtt->invalidate = gen8_gg

Re: [Intel-gfx] [PATCH v2 00/15] sysctl: Remove sentinel elements from drivers

2023-10-10 Thread Luis Chamberlain 
On Mon, Oct 02, 2023 at 10:55:17AM +0200, Joel Granados via B4 Relay wrote:
> Changes in v2:
> - Left the dangling comma in the ctl_table arrays.
> - Link to v1: 
> https://lore.kernel.org/r/20230928-jag-sysctl_remove_empty_elem_drivers-v1-0-e59120fca...@samsung.com

Thanks! Pushed onto sysctl-next for wider testing.

  Luis

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Framework for display parameters (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: Framework for display parameters (rev2)
URL   : https://patchwork.freedesktop.org/series/124645/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Framework for display parameters (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: Framework for display parameters (rev2)
URL   : https://patchwork.freedesktop.org/series/124645/
State : warning

== Summary ==

Error: dim checkpatch failed
6962346c45e5 drm/i915/display: Add framework to add parameters specific to 
display
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#79: 
new file mode 100644

-:207: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#207: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:124:
+intel_display_debugfs_create_int(const char *name, umode_t mode,
+   struct dentry *parent, int *value)

-:216: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#216: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:133:
+intel_display_debugfs_create_uint(const char *name, umode_t mode,
+struct dentry *parent, unsigned int *value)

-:223: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mode' - possible 
side-effects?
#223: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:140:
+#define _intel_display_param_create_file(parent, name, mode, valp) \
+   do {\
+   if (mode)   \
+   _Generic(valp,  \
+bool * : debugfs_create_bool,  \
+int * : intel_display_debugfs_create_int, \
+unsigned int * : 
intel_display_debugfs_create_uint, \
+unsigned long * : debugfs_create_ulong, \
+char ** : debugfs_create_str) \
+   (name, mode, parent, valp); \
+   } while (0)

-:223: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'valp' - possible 
side-effects?
#223: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:140:
+#define _intel_display_param_create_file(parent, name, mode, valp) \
+   do {\
+   if (mode)   \
+   _Generic(valp,  \
+bool * : debugfs_create_bool,  \
+int * : intel_display_debugfs_create_int, \
+unsigned int * : 
intel_display_debugfs_create_uint, \
+unsigned long * : debugfs_create_ulong, \
+char ** : debugfs_create_str) \
+   (name, mode, parent, valp); \
+   } while (0)

-:226: CHECK:CAMELCASE: Avoid CamelCase: <_Generic>
#226: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:143:
+   _Generic(valp,  \

-:231: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#231: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:148:
+char ** : debugfs_create_str) \
  ^

-:231: ERROR:SPACING: space prohibited after that '*' (ctx:OxW)
#231: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:148:
+char ** : debugfs_create_str) \
   ^

-:255: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#255: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:172:
+#define REGISTER(T, x, unused, mode, ...) _intel_display_param_create_file( \
+   dir, #x, mode, &i915->display.params.x);

-:332: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#332: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:9:
+#define intel_display_param_named(name, T, perm, desc) \
+   module_param_named(name, intel_display_modparams.name, T, perm); \
+   MODULE_PARM_DESC(name, desc)

-:335: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#335: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:12:
+#define intel_display_param_named_unsafe(name, T, perm, desc) \
+   module_param_named_unsafe(name, intel_display_modparams.name, T, perm); 
\
+   MODULE_PARM_DESC(name, desc)

-:344: CHECK:LINE_SPACING: Please use a blank line after 
functi

Re: [Intel-gfx] [PATCH v10 6/7] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck

2023-10-10 Thread John Harrison 

On 10/10/2023 08:02, Jonathan Cavitt wrote:

For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.

Additionally, increase the default timeout from 10 ms to 20 ms
because msleep < 20ms can sleep for up to 20ms.
I'm not seeing why that is a reason to make it always sleep for 20ms. 
msleep is not guaranteed to have any kind of high accuracy. It just 
vaguely guarantees to sleep for at least the time requested. The point 
of warning if used for small values is to check against the case where a 
larger sleep is a problem. E.g. if you must sleep for at least 1ms but 
no more than 5ms then you need to use a different function because 
msleep might violate that requirement. But if your requirement is simply 
to sleep for at least 10ms and who cares if it is longer (as 
demonstrated by the bump to 200ms for GSC), then it is fine to use 
msleep(10). Maybe it will waste time and sleep for 20ms, maybe it won't. 
But it's not a problem if it does. And if it doesn't then you haven't 
wasted the time.


John.



Signed-off-by: Jonathan Cavitt 
---
  drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +--
  1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c 
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 7e41f69fc818f..24beb94aa7a37 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -136,8 +136,15 @@ pte_tlbinv(struct intel_context *ce,
i915_request_get(rq);
i915_request_add(rq);
  
-	/* Short sleep to sanitycheck the batch is spinning before we begin */

-   msleep(10);
+   /*
+* Short sleep to sanitycheck the batch is spinning before we begin.
+* FIXME: Why is GSC so slow?
+*/
+   if (ce->engine->class == OTHER_CLASS)
+   msleep(200);
+   else
+   msleep(20);
+
if (va == vb) {
if (!i915_request_completed(rq)) {
pr_err("%s(%s): Semaphore sanitycheck failed %llx, with 
alignment %llx, using PTE size %x (phys %x, sg %x)\n",

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Store DSC DPCD capabilities in the connector (rev5)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Store DSC DPCD capabilities in the connector (rev5)
URL   : https://patchwork.freedesktop.org/series/124723/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13736 -> Patchwork_124723v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/index.html

Participating hosts (36 -> 38)
--

  Additional (2): fi-kbl-soraka fi-hsw-4770 

Known issues


  Here are the changes found in Patchwork_124723v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3:  [PASS][1] -> [INCOMPLETE][2] ([i915#9275])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][7] ([i915#1886])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3:  [PASS][8] -> [FAIL][9] ([fdo#103375])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#5190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_dsc@dsc-basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][11] ([fdo#109271]) +9 other tests 
skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-kbl-soraka/igt@kms_...@dsc-basic.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][12] -> [FAIL][13] ([IGT#3])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271]) +12 other tests 
skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-vga-1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][15] ([i915#3546]) +2 other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][16] -> [ABORT][17] ([i915#8668])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-kbl-guc: NOTRUN -> [SKIP][18] ([fdo#109271])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-kbl-guc/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770:NOTRUN -> [DMESG-WARN][19] ([i915#8841]) +6 other 
tests dmesg-warn
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-vga-1.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#1072]) +3 
other tests skip
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v5/fi-hsw-4770/igt@k

Re: [Intel-gfx] [PATCH v10 4/7] drm/i915: No TLB invalidation on suspended GT

2023-10-10 Thread Cavitt, Jonathan 
-Original Message-
From: Harrison, John C  
Sent: Tuesday, October 10, 2023 2:57 PM
To: Cavitt, Jonathan ; 
intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; chris.p.wil...@linux.intel.com; 
Iddamsetty, Aravind ; Yang, Fei 
; Shyti, Andi ; Das, Nirmoy 
; Krzysztofik, Janusz ; 
Roper, Matthew D ; tvrtko.ursu...@linux.intel.com; 
jani.nik...@linux.intel.com
Subject: Re: [PATCH v10 4/7] drm/i915: No TLB invalidation on suspended GT
> 
> On 10/10/2023 08:02, Jonathan Cavitt wrote:
> > In case of GT is suspended, don't allow submission of new TLB invalidation
> > request and cancel all pending requests. The TLB entries will be
> > invalidated either during GuC reload or on system resume.
> >
> > Signed-off-by: Fei Yang 
> > Signed-off-by: Jonathan Cavitt 
> > CC: John Harrison 
> > ---
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.h|  1 +
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 21 +--
> >   drivers/gpu/drm/i915/gt/uc/intel_uc.c |  7 +++
> >   3 files changed, 23 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > index 06c44f5c28776..ff7e7b90fd49b 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > @@ -536,4 +536,5 @@ void intel_guc_dump_time_info(struct intel_guc *guc, 
> > struct drm_printer *p);
> >   
> >   int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc);
> >   
> > +void wake_up_all_tlb_invalidate(struct intel_guc *guc);
> >   #endif
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index e9854652c2b52..b9c168ea57270 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1796,13 +1796,25 @@ static void __guc_reset_context(struct 
> > intel_context *ce, intel_engine_mask_t st
> > intel_context_put(parent);
> >   }
> >   
> > -void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
> > stalled)
> > +void wake_up_all_tlb_invalidate(struct intel_guc *guc)
> >   {
> > struct intel_guc_tlb_wait *wait;
> > +   unsigned long i;
> > +
> > +   if (!HAS_GUC_TLB_INVALIDATION(guc_to_gt(guc)->i915))
> > +   return;
> > +
> > +   xa_lock_irq(&guc->tlb_lookup);
> > +   xa_for_each(&guc->tlb_lookup, i, wait)
> > +   wake_up(&wait->wq);
> > +   xa_unlock_irq(&guc->tlb_lookup);
> > +}
> > +
> > +void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
> > stalled)
> What is changed on this line? Or is it just diff being confused and 
> seeing the move of the 'wait' declaration as being the anchor point 
> rather than the function declaration?

It's the latter, yes.  Diff is confused.
-Jonathan Cavitt

> 
> John.
> 
> 
> > +{
> > struct intel_context *ce;
> > unsigned long index;
> > unsigned long flags;
> > -   unsigned long i;
> >   
> > if (unlikely(!guc_submission_initialized(guc))) {
> > /* Reset called during driver load? GuC not yet initialised! */
> > @@ -1833,10 +1845,7 @@ void intel_guc_submission_reset(struct intel_guc 
> > *guc, intel_engine_mask_t stall
> >  * The full GT reset will have cleared the TLB caches and flushed the
> >  * G2H message queue; we can release all the blocked waiters.
> >  */
> > -   xa_lock_irq(&guc->tlb_lookup);
> > -   xa_for_each(&guc->tlb_lookup, i, wait)
> > -   wake_up(&wait->wq);
> > -   xa_unlock_irq(&guc->tlb_lookup);
> > +   wake_up_all_tlb_invalidate(guc);
> >   }
> >   
> >   static void guc_cancel_context_requests(struct intel_context *ce)
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
> > b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> > index 98b103375b7ab..750cb63503dd7 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> > @@ -688,6 +688,8 @@ void intel_uc_suspend(struct intel_uc *uc)
> > /* flush the GSC worker */
> > intel_gsc_uc_flush_work(&uc->gsc);
> >   
> > +   wake_up_all_tlb_invalidate(guc);
> > +
> > if (!intel_guc_is_ready(guc)) {
> > guc->interrupts.enabled = false;
> > return;
> > @@ -736,6 +738,11 @@ static int __uc_resume(struct intel_uc *uc, bool 
> > enable_communication)
> >   
> > intel_gsc_uc_resume(&uc->gsc);
> >   
> > +   if (HAS_GUC_TLB_INVALIDATION(gt->i915)) {
> > +   intel_guc_invalidate_tlb_engines(guc);
> > +   intel_guc_invalidate_tlb_guc(guc);
> > +   }
> > +
> > return 0;
> >   }
> >   
> 
>

Re: [Intel-gfx] [PATCH v10 4/7] drm/i915: No TLB invalidation on suspended GT

2023-10-10 Thread John Harrison 

On 10/10/2023 08:02, Jonathan Cavitt wrote:

In case of GT is suspended, don't allow submission of new TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
---
  drivers/gpu/drm/i915/gt/uc/intel_guc.h|  1 +
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 21 +--
  drivers/gpu/drm/i915/gt/uc/intel_uc.c |  7 +++
  3 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 06c44f5c28776..ff7e7b90fd49b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -536,4 +536,5 @@ void intel_guc_dump_time_info(struct intel_guc *guc, struct 
drm_printer *p);
  
  int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc);
  
+void wake_up_all_tlb_invalidate(struct intel_guc *guc);

  #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e9854652c2b52..b9c168ea57270 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1796,13 +1796,25 @@ static void __guc_reset_context(struct intel_context 
*ce, intel_engine_mask_t st
intel_context_put(parent);
  }
  
-void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled)

+void wake_up_all_tlb_invalidate(struct intel_guc *guc)
  {
struct intel_guc_tlb_wait *wait;
+   unsigned long i;
+
+   if (!HAS_GUC_TLB_INVALIDATION(guc_to_gt(guc)->i915))
+   return;
+
+   xa_lock_irq(&guc->tlb_lookup);
+   xa_for_each(&guc->tlb_lookup, i, wait)
+   wake_up(&wait->wq);
+   xa_unlock_irq(&guc->tlb_lookup);
+}
+
+void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
What is changed on this line? Or is it just diff being confused and 
seeing the move of the 'wait' declaration as being the anchor point 
rather than the function declaration?


John.



+{
struct intel_context *ce;
unsigned long index;
unsigned long flags;
-   unsigned long i;
  
  	if (unlikely(!guc_submission_initialized(guc))) {

/* Reset called during driver load? GuC not yet initialised! */
@@ -1833,10 +1845,7 @@ void intel_guc_submission_reset(struct intel_guc *guc, 
intel_engine_mask_t stall
 * The full GT reset will have cleared the TLB caches and flushed the
 * G2H message queue; we can release all the blocked waiters.
 */
-   xa_lock_irq(&guc->tlb_lookup);
-   xa_for_each(&guc->tlb_lookup, i, wait)
-   wake_up(&wait->wq);
-   xa_unlock_irq(&guc->tlb_lookup);
+   wake_up_all_tlb_invalidate(guc);
  }
  
  static void guc_cancel_context_requests(struct intel_context *ce)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 98b103375b7ab..750cb63503dd7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -688,6 +688,8 @@ void intel_uc_suspend(struct intel_uc *uc)
/* flush the GSC worker */
intel_gsc_uc_flush_work(&uc->gsc);
  
+	wake_up_all_tlb_invalidate(guc);

+
if (!intel_guc_is_ready(guc)) {
guc->interrupts.enabled = false;
return;
@@ -736,6 +738,11 @@ static int __uc_resume(struct intel_uc *uc, bool 
enable_communication)
  
  	intel_gsc_uc_resume(&uc->gsc);
  
+	if (HAS_GUC_TLB_INVALIDATION(gt->i915)) {

+   intel_guc_invalidate_tlb_engines(guc);
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+
return 0;
  }

Re: [Intel-gfx] [PATCH v10 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread John Harrison 

On 10/10/2023 08:02, Jonathan Cavitt wrote:

From: Prathap Kumar Valsan 

The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation.  We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back to GT invalidation when the GuC is
disabled.
The invalidation is done by sending a request directly to the GuC
tlb_lookup that invalidates the table.  The invalidation is submitted as
a wait request and is performed in the CT event handler.  This means we
cannot perform this TLB invalidation path if the CT is not enabled.
If the request isn't fulfilled in two seconds, this would constitute
an error in the invalidation as that would constitute either a lost
request or a severe GuC overload.

With this new invalidation routine, we can perform GuC-based GGTT
invalidations.  GuC-based GGTT invalidation is incompatible with
MMIO invalidation so we should not perform MMIO invalidation when
GuC-based GGTT invalidation is expected.

The additional complexity incurred in this patch will be necessary for
range-based tlb invalidations, which will be platformed in the future.

Signed-off-by: Prathap Kumar Valsan 
Signed-off-by: Bruce Chang 
Signed-off-by: Chris Wilson 
Signed-off-by: Umesh Nerlige Ramappa 
Signed-off-by: Jonathan Cavitt 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Fei Yang 
CC: Andi Shyti 
---
  drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 +++-
  drivers/gpu/drm/i915/gt/intel_tlb.c   |  16 +-
  .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 
  drivers/gpu/drm/i915/gt/uc/intel_guc.h|  22 +++
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 186 +-
  7 files changed, 284 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 4d7d88b92632b..a1f7bdc602996 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -206,22 +206,38 @@ static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
  }
  
+static void guc_ggtt_ct_invalidate(struct intel_gt *gt)

+{
+   struct intel_uncore *uncore = gt->uncore;
+   intel_wakeref_t wakeref;
+
+   with_intel_runtime_pm_if_active(uncore->rpm, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+}
+
  static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
  {
struct drm_i915_private *i915 = ggtt->vm.i915;
+   struct intel_gt *gt;
  
-	gen8_ggtt_invalidate(ggtt);

-
-   if (GRAPHICS_VER(i915) >= 12) {
-   struct intel_gt *gt;
+   if (!HAS_GUC_TLB_INVALIDATION(i915))
+   gen8_ggtt_invalidate(ggtt);
  
-		list_for_each_entry(gt, &ggtt->gt_list, ggtt_link)

+   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link) {
+   if (HAS_GUC_TLB_INVALIDATION(i915) &&
+   intel_guc_is_ready(>->uc.guc)) {
+   guc_ggtt_ct_invalidate(gt);
+   } else if (GRAPHICS_VER(i915) >= 12) {
intel_uncore_write_fw(gt->uncore,
  GEN12_GUC_TLB_INV_CR,
  GEN12_GUC_TLB_INV_CR_INVALIDATE);
-   } else {
-   intel_uncore_write_fw(ggtt->vm.gt->uncore,
- GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   } else {
+   intel_uncore_write_fw(gt->uncore,
+ GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   }
}
  }
  
@@ -1243,7 +1259,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)

ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
}
  
-	if (intel_uc_wants_guc(&ggtt->vm.gt->uc))

+   if (intel_uc_wants_guc_submission(&ggtt->vm.gt->uc))
ggtt->invalidate = guc_ggtt_invalidate;
else
ggtt->invalidate = gen8_ggtt_invalidate;
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index 139608c30d978..4bb13d1890e37 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -12,6 +12,7 @@
  #include "intel_gt_print.h"
  #include "intel_gt_regs.h"
  #include "intel_tlb.h"
+#include "uc/intel_guc.h"
  
  /*

   * HW architecture suggest typical invalidation time at 40us,
@@ -131,11 +132,24 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, 
u32 seqno)
return;
  
  	with_intel_gt_pm_if_awake(gt, wakeref) {

+   struct intel_guc *guc = >->uc.guc;
+
mutex_lock(>->tlb.invalidate_lock);
if (tlb_seqno_passed(gt, seqno))

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Store DSC DPCD capabilities in the connector (rev5)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Store DSC DPCD capabilities in the connector (rev5)
URL   : https://patchwork.freedesktop.org/series/124723/
State : warning

== Summary ==

Error: dim checkpatch failed
a9998de0514d drm/i915/dp: Sanitize DPCD revision check in 
intel_dp_get_dsc_sink_cap()
084a5d22e67b drm/i915/dp: Store DSC DPCD capabilities in the connector
4c9898f8ef1a drm/i915/dp_mst: Set connector DSC capabilities and decompression 
AUX
6253ceaca84b drm/i915/dp: Use i915/intel connector local variables in 
i915_dsc_fec_support_show()
5ece9e985289 drm/i915/dp: Use connector DSC DPCD in i915_dsc_fec_support_show()
-:40: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:1249:
+  
str_yes_no(drm_dp_sink_supports_fec(connector->dp.fec_capability)));

total: 0 errors, 1 warnings, 0 checks, 24 lines checked
c5ae10af3ff2 drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_compute_max_bpp()
aa1eb1172df1 drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_fec()
b656d0e3baf7 drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_dsc()
cb866f077227 drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_max_sink_compressed_bppx16()
28ed18aaf15f drm/i915/dp: Pass connector DSC DPCD to 
drm_dp_dsc_sink_supported_input_bpcs()
f46ee22472a3 drm/i915/dp: Pass only the required i915 to 
intel_dp_source_dsc_version_minor()
66131692fd55 drm/i915/dp: Pass only the required DSC DPCD to 
intel_dp_sink_dsc_version_minor()
07c88aede1d7 drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_compute_params()
779367d0f225 drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_supports_format()
82ee180ce7db drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_get_slice_count()
223d2d3478a5 drm/i915/dp: Use connector DSC DPCD in intel_dp_mode_valid()
06ea22c7d3a9 drm/i915/dp: Use connector DSC DPCD in 
intel_dp_dsc_compute_config()
b421faca8199 drm/i915/dp_mst: Use connector DSC DPCD in 
intel_dp_mst_mode_valid_ctx()
edabd32ab1cd drm/i915/dp: Remove unused DSC caps from intel_dp

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/print: Add drm_dbg_ratelimited (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: series starting with [1/2] drm/print: Add drm_dbg_ratelimited (rev2)
URL   : https://patchwork.freedesktop.org/series/112925/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13736 -> Patchwork_112925v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/index.html

Participating hosts (36 -> 37)
--

  Additional (2): bat-dg2-8 fi-hsw-4770 
  Missing(1): fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_112925v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-bsw-n3050:   [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-bsw-n3050/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/fi-bsw-n3050/boot.html
- fi-hsw-4770:NOTRUN -> [FAIL][3] ([i915#8293])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- bat-mtlp-8: NOTRUN -> [ABORT][4] ([i915#8213] / [i915#9262])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_mmap@basic:
- bat-dg2-8:  NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-8:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@gem_mmap_...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-8:  NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-8:  NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@i915_pm_...@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#6645])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html
- bat-dg2-8:  NOTRUN -> [SKIP][10] ([i915#6645])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-8:  NOTRUN -> [SKIP][11] ([i915#5190])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-8:  NOTRUN -> [SKIP][12] ([i915#4215] / [i915#5190])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-8:  NOTRUN -> [SKIP][13] ([i915#4212]) +6 other tests skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-8:  NOTRUN -> [SKIP][14] ([i915#4212] / [i915#5608])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-8:  NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-8:  NOTRUN -> [SKIP][16] ([fdo#109285])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-8:  NOTRUN -> [SKIP][17] ([i915#5274])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/bat-dg2-8/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][18] -> [FAIL][19] ([IGT#3])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13736/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-kbl-guc: NOTRUN -> [SKIP][20] ([fdo#109271])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112925v2/fi-kb

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/print: Add drm_dbg_ratelimited (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: series starting with [1/2] drm/print: Add drm_dbg_ratelimited (rev2)
URL   : https://patchwork.freedesktop.org/series/112925/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/print: Add drm_dbg_ratelimited (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: series starting with [1/2] drm/print: Add drm_dbg_ratelimited (rev2)
URL   : https://patchwork.freedesktop.org/series/112925/
State : warning

== Summary ==

Error: dim checkpatch failed
ada8428ec944 drm/print: Add drm_dbg_ratelimited
fbced019c190 drm/i915: Ratelimit debug log in vm_fault_ttm
-:9: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'References:', use 
'Link:' or 'Closes:' instead
#9: 
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7038

total: 0 errors, 1 warnings, 0 checks, 11 lines checked

Re: [Intel-gfx] [PATCH RESEND v2 1/2] drm/print: Add drm_dbg_ratelimited

2023-10-10 Thread Hamza Mahfooz 

On 10/10/23 08:15, Andi Shyti wrote:

From: Nirmoy Das 

Add a function for ratelimitted debug print.

Signed-off-by: Nirmoy Das 
Cc: Maarten Lankhorst 
Cc: Maxime Ripard 
Cc: Thomas Zimmermann 
Cc: David Airlie 
Cc: Daniel Vetter 
Reviewed-by: Matthew Auld 
Reviewed-by: Andrzej Hajda 
Reviewed-by: Andi Shyti 
Reviewed-by: Sam Ravnborg 
Signed-off-by: Andi Shyti 
---
  include/drm/drm_print.h | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index a93a387f8a1a..ad77ac4b6808 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -602,6 +602,9 @@ void __drm_err(const char *format, ...);
drm_dev_printk(drm_ ? drm_->dev : NULL, KERN_DEBUG, fmt, ## 
__VA_ARGS__);\
  })
  
+#define drm_dbg_ratelimited(drm, fmt, ...) \

+   __DRM_DEFINE_DBG_RATELIMITED(DRIVER, drm, fmt, ## __VA_ARGS__)
+


I guess since this was last sent drm_dbg_driver() was introduced,
with drm_dbg() only being grandfathered in since it's already
widely used, so it would probably be better to call this
drm_dbg_driver_ratelimited() instead.


  #define drm_dbg_kms_ratelimited(drm, fmt, ...) \
__DRM_DEFINE_DBG_RATELIMITED(KMS, drm, fmt, ## __VA_ARGS__)
  

--
Hamza

Re: [Intel-gfx] [PATCH RESEND v2 0/2] Add drm_dbg_ratelimited()

2023-10-10 Thread Andi Shyti 
Hi John,

On Tue, Oct 10, 2023 at 11:25:03AM -0700, John Harrison wrote:
> On 10/10/2023 05:15, Andi Shyti wrote:
> > Hi,
> > 
> > I might have picked up the wrong series and missed some reviews
> > and the extra patch from Nirmoy with a real use of the
> > drm_dbg_ratelimited() that John was looking for.
> > 
> > Thanks,
> > Andi
> I just found the original post of this from back in January
> (https://patchwork.freedesktop.org/series/112925/). Is there a reason why it
> was never merged? As noted, it appears to have a whole bunch of r-b's on it.

yes, the patch was widely appreciated by reviewers... but I think
somehow it was forgotten... that's why I am resending it :-)

Andi

Re: [Intel-gfx] [PATCH 2/2] drm/i915: More use of GT specific print helpers

2023-10-10 Thread Andi Shyti 
Hi John,

On Mon, Oct 09, 2023 at 12:57:55PM -0700, John Harrison wrote:
> On 10/9/2023 12:54, Andi Shyti wrote:
> > Hi John,
> > 
> > ...
> > 
> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > @@ -71,6 +71,7 @@
> > >   #include "gem/i915_gem_pm.h"
> > >   #include "gt/intel_gt.h"
> > >   #include "gt/intel_gt_pm.h"
> > > +#include "gt/intel_gt_print.h"
> > >   #include "gt/intel_rc6.h"
> > >   #include "pxp/intel_pxp.h"
> > > @@ -429,7 +430,7 @@ static int i915_pcode_init(struct drm_i915_private 
> > > *i915)
> > >   for_each_gt(gt, i915, id) {
> > >   ret = intel_pcode_init(gt->uncore);
> > >   if (ret) {
> > > - drm_err(>->i915->drm, "gt%d: intel_pcode_init failed 
> > > %d\n", id, ret);
> > > + gt_err(gt, "intel_pcode_init failed %d\n", ret);
> > using gt_*() print functions in the upper layers looks a bit
> > wrong to me. If we need GT printing, the prints need to be done
> > inside the function called, in this case would be
> > intel_pcode_init().
> It is less wrong that using gt->i915->drm as a parameter and 'gt%d' in the
> format string. That is the whole point of the helper. The code has access to
> a gt object so it should use the gt helper to make use of that object rather
> than unrolling it and diving in to the gt internals.

yes, it's an improvement

Reviewed-by: Andi Shyti  

> As for moving the error message inside the init function itself. That is
> maybe a valid change but that potentially counts as a functional change and
> should be done by someone who actually knows the code. All I'm doing is
> improving the code layering by using the correct helper to hide the internal
> details of an object this layer should not know about.

maybe one day we need to revisit all the gt dependency in the
higher levels and the i915 dependencies in gt.

Thanks,
Andi

Re: [Intel-gfx] [PATCH v10 2/7] drm/i915/guc: Add CT size delay helper

2023-10-10 Thread John Harrison 

On 10/10/2023 08:02, Jonathan Cavitt wrote:

Add a helper function to the GuC CT buffer that reports the expected
time to process all outstanding requests.  As of now, there is no
functionality to check number of requests in the buffer, so the helper
function just reports 2 seconds, or 1ms per request up to the maximum
number of requests the CT buffer can store.

Suggested-by: John Harrison
Signed-off-by: Jonathan Cavitt
---
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 13 +
  1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 58e42901ff498..36afc1ce9fabd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -120,6 +120,19 @@ static inline bool intel_guc_ct_enabled(struct 
intel_guc_ct *ct)
return ct->enabled;
  }
  
+/*

+ * GuC has a timeout of 1ms for a TLB invalidation response from GAM.  On a
+ * timeout GuC drops the request and has no mechanism to notify the host about
+ * the timeout.  There is also no mechanism for determining the number of
+ * outstanding requests in the CT buffer.  Ergo, keep a larger timeout that 
accounts
+ * for this individual timeout and the max number of outstanding requests that
+ * can be queued in CT buffer.
+ */
This feels like the wrong wording. TLB invalidations aren't even close 
to the slowest thing that goes through the CT buffer. And the 
description about dropping failed requests and such is irrelevant to the 
implementation/purpose of this helper. That is specific detail about one 
single use case of the helper. That might be the only user at this point 
but the intention is that other parts of the driver will be updated to 
call this as well rather than hard coding their own timeouts as they 
currently do.


I would suggest:

   Some H2G commands involve a synchronous response that the driver
   needs to wait for. In such cases, a timeout is required to prevent
   the driver from waiting forever in the case of an error (either no
   error response is defined in the protocol or something has died and
   requires a reset). The specific command may be defined as having a
   time bound response but the CT is a queue and that time guarantee
   only starts from the point when the command reaches the head of the
   queue and is processed by GuC.

   Ideally there would be a helper to report the progress of a given
   command through the CT. However, that would require a significant
   amount of work in the CT layer. In the meantime, provide a
   reasonable estimation of the worst case latency it should take for
   the entire queue to drain. And therefore, how long a caller should
   wait before giving up on their request. The current estimate is
   based on empirical measurement of a test that fills the buffer with
   context creation and destruction requests as they seem to be the
   slowest operation.



+static inline long intel_guc_ct_expected_delay(struct intel_guc_ct *ct)
This is not the 'expected' delay but the worst case maximum delay. Also, 
no need to force the callers to know about ct structures. They 
presumably have a intel_guc structure if they are sending H2G messages, 
and that is all you should need to know about. Having said that, the 
implementation isn't currently accessing any stored data, so why bother 
with a parameter at all?



+{
+   return HZ * 2;
Also, this needs to be based on the buffer size so that if the size were 
to increase then the time would as well.


My thought would be:

   long intel_guc_ct_max_queue_time_jiffies(void) {
    /*
     * A 4KB buffer full of context destroy commands takes a little
   over a second to process
 * so bump that to 2s to be super safe.
 */
    return (CTB_H2G_BUFFER_SIZE * HZ) / SZ_2K;
   }

John.



+}
+
  #define INTEL_GUC_CT_SEND_NB  BIT(31)
  #define INTEL_GUC_CT_SEND_G2H_DW_SHIFT0
  #define INTEL_GUC_CT_SEND_G2H_DW_MASK (0xff << INTEL_GUC_CT_SEND_G2H_DW_SHIFT)

Re: [Intel-gfx] [PATCH dii-client 2/2] drm/i915: Use selective tlb invalidations where supported

2023-10-10 Thread Cavitt, Jonathan 
Ignore this.  It's not a security hole: it's just a temporary patch I was 
using for rebasing purposes that got smuggled into this series
on accident.  It has a bad tag because of some stale gitconfig params
that I've since removed.
-Jonathan Cavitt

-Original Message-
From: Cavitt, Jonathan  
Sent: Tuesday, October 10, 2023 11:44 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; Cavitt, Jonathan 
; Das, Nirmoy ; Shyti, Andi 
; tvrtko.ursu...@linux.intel.com; Harrison, John C 

Subject: [PATCH dii-client 2/2] drm/i915: Use selective tlb invalidations where 
supported
> 
> For platforms supporting selective tlb invalidations, we don't need to
> do a full tlb invalidation. Rather do a range based tlb invalidation for
> every unbind of purged vma belongs to an active vm.
> 
> Signed-off-by: Prathap Kumar Valsan 
> Cc: Niranjana Vishwanathapura 
> Cc: Fei Yang 
> Signed-off-by: Mauro Carvalho Chehab 
> Signed-off-by: Jonathan Cavitt 
> ---
>  drivers/gpu/drm/i915/gt/intel_ppgtt.c |  2 +-
>  drivers/gpu/drm/i915/i915_vma.c   | 14 +-
>  drivers/gpu/drm/i915/i915_vma.h   |  3 ++-
>  3 files changed, 12 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c 
> b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index d07a4f97b9434..b43dae3cbd59f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
>   return;
>  
>   vm->clear_range(vm, vma_res->start, vma_res->vma_size);
> - vma_invalidate_tlb(vm, vma_res->tlb);
> + vma_invalidate_tlb(vm, vma_res->tlb, vma_res->start, vma_res->vma_size);
>  }
>  
>  static unsigned long pd_count(u64 size, int shift)
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index d09aad34ba37f..cb05d794f0d0f 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -1339,7 +1339,8 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct 
> i915_vma *vma)
>   return err;
>  }
>  
> -void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
> +void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb
> + u64 start, u64 size)
>  {
>   struct intel_gt *gt;
>   int id;
> @@ -1355,9 +1356,11 @@ void vma_invalidate_tlb(struct i915_address_space *vm, 
> u32 *tlb)
>* the most recent TLB invalidation seqno, and if we have not yet
>* flushed the TLBs upon release, perform a full invalidation.
>*/
> - for_each_gt(gt, vm->i915, id)
> - WRITE_ONCE(tlb[id],
> -intel_gt_next_invalidate_tlb_full(gt));
> + for_each_gt(gt, vm->i915, id) {
> + if (!intel_gt_invalidate_tlb_range(gt, start, size))
> + WRITE_ONCE(tlb[id],
> +intel_gt_next_invalidate_tlb_full(gt));
> + }
>  }
>  
>  static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
> @@ -2041,7 +2044,8 @@ struct dma_fence *__i915_vma_evict(struct i915_vma 
> *vma, bool async)
>   dma_fence_put(unbind_fence);
>   unbind_fence = NULL;
>   }
> - vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
> + vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb,
> +vma->node.start, vma->size);
>   }
>  
>   /*
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index e356dfb883d34..5a604aad55dfe 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -260,7 +260,8 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
>   u64 size, u64 alignment, u64 flags);
>  void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
>  void i915_vma_revoke_mmap(struct i915_vma *vma);
> -void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
> +void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
> + u64 start, u64 size);
>  struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
>  int __i915_vma_unbind(struct i915_vma *vma);
>  int __must_check i915_vma_unbind(struct i915_vma *vma);
> -- 
> 2.25.1
> 
>

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lnl: Remove watchdog timers for PSR (rev3)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915/lnl: Remove watchdog timers for PSR (rev3)
URL   : https://patchwork.freedesktop.org/series/124715/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13735 -> Patchwork_124715v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/index.html

Participating hosts (37 -> 36)
--

  Additional (1): bat-dg2-11 
  Missing(2): fi-kbl-soraka fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_124715v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- bat-mtlp-8: NOTRUN -> [ABORT][1] ([i915#8213] / [i915#9262])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#4083])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@gem_m...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#4077]) +2 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#6621])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hugepages:
- bat-mtlp-8: NOTRUN -> [DMESG-WARN][6] ([i915#8962])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#6645])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#4212]) +6 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#5190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#4215] / [i915#5190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#4212] / [i915#5608])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
- bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#3840])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-11: NOTRUN -> [SKIP][14] ([fdo#109285])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#5274])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-dg2-11/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][16] -> [FAIL][17] ([IGT#3])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13735/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][18] -> [ABORT][19] ([i915#8668])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13735/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124715v3/bat-rplp-1/igt@kms

[Intel-gfx] [RFC PATCH 00/10] drm/i915: Implement range-based TLB

2023-10-10 Thread Jonathan Cavitt 
Implement range-based TLB invalidations on top of GuC-based TLB
invalidations.  This is the future plan for GuC-based TLB
invalidations because it helps improve performance over performing
full tlb invalidations all the time.

Jonathan Cavitt (7):
  drm/i915: Add GuC TLB Invalidation device info flags
  drm/i915/guc: Add CT size delay helper
  drm/i915: No TLB invalidation on suspended GT
  drm/i915: No TLB invalidation on wedged GT
  drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
  drm/i915: Enable GuC TLB invalidations for MTL
  drm/i915: Use selective tlb invalidations where supported

Prathap Kumar Valsan (3):
  drm/i915: Define and use GuC and CTB TLB invalidation routines
  drm/i915: Define GuC Based TLB invalidation routines
  drm/i915: Add generic interface for tlb invalidation

 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 +-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |   8 +
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |   2 +-
 drivers/gpu/drm/i915/gt/intel_tlb.c   |  68 +++-
 drivers/gpu/drm/i915/gt/intel_tlb.h   |   1 +
 drivers/gpu/drm/i915/gt/selftest_tlb.c|  99 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  35 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  34 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  13 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 290 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |   7 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_pci.c   |   1 +
 drivers/gpu/drm/i915/i915_vma.c   |  14 +-
 drivers/gpu/drm/i915/i915_vma.h   |   3 +-
 drivers/gpu/drm/i915/intel_device_info.h  |   1 +
 .../drm/i915/selftests/i915_mock_selftests.h  |   1 +
 19 files changed, 597 insertions(+), 21 deletions(-)

-- 
2.25.1

[Intel-gfx] [RFC PATCH 03/10] drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Jonathan Cavitt 
From: Prathap Kumar Valsan 

The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation.  We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back to GT invalidation when the GuC is
disabled.
The invalidation is done by sending a request directly to the GuC
tlb_lookup that invalidates the table.  The invalidation is submitted as
a wait request and is performed in the CT event handler.  This means we
cannot perform this TLB invalidation path if the CT is not enabled.
If the request isn't fulfilled in two seconds, this would constitute
an error in the invalidation as that would constitute either a lost
request or a severe GuC overload.

With this new invalidation routine, we can perform GuC-based GGTT
invalidations.  GuC-based GGTT invalidation is incompatible with
MMIO invalidation so we should not perform MMIO invalidation when
GuC-based GGTT invalidation is expected.

The additional complexity incurred in this patch will be necessary for
range-based tlb invalidations, which will be platformed in the future.

Signed-off-by: Prathap Kumar Valsan 
Signed-off-by: Bruce Chang 
Signed-off-by: Chris Wilson 
Signed-off-by: Umesh Nerlige Ramappa 
Signed-off-by: Jonathan Cavitt 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Fei Yang 
CC: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 +++-
 drivers/gpu/drm/i915/gt/intel_tlb.c   |  16 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  22 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 186 +-
 7 files changed, 284 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 4d7d88b92632b..a1f7bdc602996 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -206,22 +206,38 @@ static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 }
 
+static void guc_ggtt_ct_invalidate(struct intel_gt *gt)
+{
+   struct intel_uncore *uncore = gt->uncore;
+   intel_wakeref_t wakeref;
+
+   with_intel_runtime_pm_if_active(uncore->rpm, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+}
+
 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
struct drm_i915_private *i915 = ggtt->vm.i915;
+   struct intel_gt *gt;
 
-   gen8_ggtt_invalidate(ggtt);
-
-   if (GRAPHICS_VER(i915) >= 12) {
-   struct intel_gt *gt;
+   if (!HAS_GUC_TLB_INVALIDATION(i915))
+   gen8_ggtt_invalidate(ggtt);
 
-   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link)
+   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link) {
+   if (HAS_GUC_TLB_INVALIDATION(i915) &&
+   intel_guc_is_ready(>->uc.guc)) {
+   guc_ggtt_ct_invalidate(gt);
+   } else if (GRAPHICS_VER(i915) >= 12) {
intel_uncore_write_fw(gt->uncore,
  GEN12_GUC_TLB_INV_CR,
  GEN12_GUC_TLB_INV_CR_INVALIDATE);
-   } else {
-   intel_uncore_write_fw(ggtt->vm.gt->uncore,
- GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   } else {
+   intel_uncore_write_fw(gt->uncore,
+ GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   }
}
 }
 
@@ -1243,7 +1259,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
}
 
-   if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
+   if (intel_uc_wants_guc_submission(&ggtt->vm.gt->uc))
ggtt->invalidate = guc_ggtt_invalidate;
else
ggtt->invalidate = gen8_ggtt_invalidate;
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index 139608c30d978..4bb13d1890e37 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -12,6 +12,7 @@
 #include "intel_gt_print.h"
 #include "intel_gt_regs.h"
 #include "intel_tlb.h"
+#include "uc/intel_guc.h"
 
 /*
  * HW architecture suggest typical invalidation time at 40us,
@@ -131,11 +132,24 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, 
u32 seqno)
return;
 
with_intel_gt_pm_if_awake(gt, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
mutex_lock(>->tlb.invalidate_lock);
if (tlb_seqno_passed(gt, seqno))
goto unlock;
 
-

[Intel-gfx] [RFC PATCH 09/10] drm/i915: Add generic interface for tlb invalidation

2023-10-10 Thread Jonathan Cavitt 
From: Prathap Kumar Valsan 

This supports selective and full tlb invalidations. When GuC is enabled
the tlb invalidations use guc ct otherwise use mmio interface.

Signed-off-by: Prathap Kumar Valsan 
CC: Niranjana Vishwanathapura 
CC: Fei Yang 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  8 ++
 drivers/gpu/drm/i915/gt/intel_tlb.c   | 52 +++
 drivers/gpu/drm/i915/gt/intel_tlb.h   |  1 +
 drivers/gpu/drm/i915/gt/selftest_tlb.c| 88 +++
 .../drm/i915/selftests/i915_mock_selftests.h  |  1 +
 5 files changed, 150 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index eecd0a87a6478..f2ca1c26ecde5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1124,6 +1124,14 @@
 
 #define GEN12_GAM_DONE _MMIO(0xcf68)
 
+#define XEHPSDV_TLB_INV_DESC0  _MMIO(0xcf7c)
+#define   XEHPSDV_TLB_INV_DESC0_ADDR_LOREG_GENMASK(31, 12)
+#define   XEHPSDV_TLB_INV_DESC0_ADDR_MASK  REG_GENMASK(8, 3)
+#define   XEHPSDV_TLB_INV_DESC0_G  REG_GENMASK(2, 1)
+#define   XEHPSDV_TLB_INV_DESC0_VALID  REG_BIT(0)
+#define XEHPSDV_TLB_INV_DESC1  _MMIO(0xcf80)
+#define   XEHPSDV_TLB_INV_DESC0_ADDR_HIREG_GENMASK(31, 0)
+
 #define GEN7_HALF_SLICE_CHICKEN1   _MMIO(0xe100) /* IVB GT1 + VLV 
*/
 #define GEN8_HALF_SLICE_CHICKEN1   MCR_REG(0xe100)
 #define   GEN7_MAX_PS_THREAD_DEP   (8 << 12)
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index 4bb13d1890e37..c31fd0875ac4f 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -157,6 +157,58 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 
seqno)
}
 }
 
+static u64 tlb_page_selective_size(u64 *addr, u64 length)
+{
+   const u64 end = *addr + length;
+   u64 start;
+
+   /*
+* Minimum invalidation size for a 2MB page that the hardware expects is
+* 16MB
+*/
+   length = max_t(u64, roundup_pow_of_two(length), SZ_4K);
+   if (length >= SZ_2M)
+   length = max_t(u64, SZ_16M, length);
+
+   /*
+* We need to invalidate a higher granularity if start address is not
+* aligned to length. When start is not aligned with length we need to
+* find the length large enough to create an address mask covering the
+* required range.
+*/
+   start = round_down(*addr, length);
+   while (start + length < end) {
+   length <<= 1;
+   start = round_down(*addr, length);
+   }
+
+   *addr = start;
+   return length;
+}
+
+bool intel_gt_invalidate_tlb_range(struct intel_gt *gt,
+  u64 start, u64 length)
+{
+   struct intel_guc *guc = >->uc.guc;
+   intel_wakeref_t wakeref;
+   u64 size, vm_total;
+   bool ret = true;
+
+   if (intel_gt_is_wedged(gt))
+   return true;
+
+   vm_total = BIT_ULL(RUNTIME_INFO(gt->i915)->ppgtt_size);
+   /* Align start and length */
+   size =  min_t(u64, vm_total, tlb_page_selective_size(&start, length));
+
+   with_intel_gt_pm_if_awake(gt, wakeref)
+   ret = intel_guc_invalidate_tlb_page_selective(guc,
+ 
INTEL_GUC_TLB_INVAL_MODE_HEAVY,
+ start, size) == 0;
+
+   return ret;
+}
+
 void intel_gt_init_tlb(struct intel_gt *gt)
 {
mutex_init(>->tlb.invalidate_lock);
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.h 
b/drivers/gpu/drm/i915/gt/intel_tlb.h
index 337327af92ac4..9e5fc40c2b08e 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.h
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.h
@@ -12,6 +12,7 @@
 #include "intel_gt_types.h"
 
 void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno);
+bool intel_gt_invalidate_tlb_range(struct intel_gt *gt, u64 start, u64 length);
 
 void intel_gt_init_tlb(struct intel_gt *gt);
 void intel_gt_fini_tlb(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c 
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 24beb94aa7a37..29f137a6e0362 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -382,10 +382,45 @@ static int invalidate_full(void *arg)
return err;
 }
 
+static void tlbinv_range(struct i915_address_space *vm, u64 addr, u64 length)
+{
+   if (!intel_gt_invalidate_tlb_range(vm->gt, addr, length))
+   pr_err("range invalidate failed\n");
+}
+
+static bool has_invalidate_range(struct intel_gt *gt)
+{
+   intel_wakeref_t wf;
+   bool result = false;
+
+   with_intel_gt_pm(gt, wf)
+   result = intel_gt_invalidate_tlb_range(gt, 0, gt->vm->total);
+
+

[Intel-gfx] [RFC PATCH 10/10] drm/i915: Use selective tlb invalidations where supported

2023-10-10 Thread Jonathan Cavitt 
For platforms supporting selective tlb invalidations, we don't need to
do a full tlb invalidation. Rather do a range based tlb invalidation for
every unbind of purged vma belongs to an active vm.

Signed-off-by: Prathap Kumar Valsan 
Cc: Niranjana Vishwanathapura 
Cc: Fei Yang 
Signed-off-by: Mauro Carvalho Chehab 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   | 14 +-
 drivers/gpu/drm/i915/i915_vma.h   |  3 ++-
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c 
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index d07a4f97b9434..b43dae3cbd59f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
return;
 
vm->clear_range(vm, vma_res->start, vma_res->vma_size);
-   vma_invalidate_tlb(vm, vma_res->tlb);
+   vma_invalidate_tlb(vm, vma_res->tlb, vma_res->start, vma_res->vma_size);
 }
 
 static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index d09aad34ba37f..cb05d794f0d0f 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1339,7 +1339,8 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct 
i915_vma *vma)
return err;
 }
 
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb
+   u64 start, u64 size)
 {
struct intel_gt *gt;
int id;
@@ -1355,9 +1356,11 @@ void vma_invalidate_tlb(struct i915_address_space *vm, 
u32 *tlb)
 * the most recent TLB invalidation seqno, and if we have not yet
 * flushed the TLBs upon release, perform a full invalidation.
 */
-   for_each_gt(gt, vm->i915, id)
-   WRITE_ONCE(tlb[id],
-  intel_gt_next_invalidate_tlb_full(gt));
+   for_each_gt(gt, vm->i915, id) {
+   if (!intel_gt_invalidate_tlb_range(gt, start, size))
+   WRITE_ONCE(tlb[id],
+  intel_gt_next_invalidate_tlb_full(gt));
+   }
 }
 
 static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
@@ -2041,7 +2044,8 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, 
bool async)
dma_fence_put(unbind_fence);
unbind_fence = NULL;
}
-   vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+   vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb,
+  vma->node.start, vma->size);
}
 
/*
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index e356dfb883d34..5a604aad55dfe 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -260,7 +260,8 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
u64 size, u64 alignment, u64 flags);
 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
 void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+   u64 start, u64 size);
 struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
 int __i915_vma_unbind(struct i915_vma *vma);
 int __must_check i915_vma_unbind(struct i915_vma *vma);
-- 
2.25.1

[Intel-gfx] [RFC PATCH 06/10] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck

2023-10-10 Thread Jonathan Cavitt 
For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.

Additionally, increase the default timeout from 10 ms to 20 ms
because msleep < 20ms can sleep for up to 20ms.

Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c 
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 7e41f69fc818f..24beb94aa7a37 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -136,8 +136,15 @@ pte_tlbinv(struct intel_context *ce,
i915_request_get(rq);
i915_request_add(rq);
 
-   /* Short sleep to sanitycheck the batch is spinning before we begin */
-   msleep(10);
+   /*
+* Short sleep to sanitycheck the batch is spinning before we begin.
+* FIXME: Why is GSC so slow?
+*/
+   if (ce->engine->class == OTHER_CLASS)
+   msleep(200);
+   else
+   msleep(20);
+
if (va == vb) {
if (!i915_request_completed(rq)) {
pr_err("%s(%s): Semaphore sanitycheck failed %llx, with 
alignment %llx, using PTE size %x (phys %x, sg %x)\n",
-- 
2.25.1

[Intel-gfx] [RFC PATCH 08/10] drm/i915: Define GuC Based TLB invalidation routines

2023-10-10 Thread Jonathan Cavitt 
From: Prathap Kumar Valsan 

The GuC firmware has defined the interface for selective TLB
invalidation support. This patch adds routines to interface with GuC.

Signed-off-by: Prathap Kumar Valsan 
CC: Matthew Brost 
---
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  11 ++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 105 +++---
 3 files changed, 105 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 33f253410d0c8..7bb710fcd9087 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -189,6 +189,8 @@ enum intel_guc_state_capture_event_status {
 
 enum intel_guc_tlb_invalidation_type {
INTEL_GUC_TLB_INVAL_ENGINES = 0x0,
+   INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1,
+   INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX = 0x2,
INTEL_GUC_TLB_INVAL_GUC = 0x3,
 };
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 3fbf4b33ce139..369fd2be1c725 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -431,6 +431,17 @@ int intel_guc_allocate_and_map_vma(struct intel_guc *guc, 
u32 size,
 int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value);
 int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value);
 
+int intel_guc_g2g_register(struct intel_guc *guc);
+
+int intel_guc_invalidate_tlb_full(struct intel_guc *guc);
+int intel_guc_invalidate_tlb_page_selective(struct intel_guc *guc,
+   enum intel_guc_tlb_inval_mode mode,
+   u64 start, u64 length);
+int intel_guc_invalidate_tlb_page_selective_ctx(struct intel_guc *guc,
+   enum intel_guc_tlb_inval_mode 
mode,
+   u64 start, u64 length, u32 
ctxid);
+int intel_guc_invalidate_tlb_guc(struct intel_guc *guc);
+
 static inline bool intel_guc_is_supported(struct intel_guc *guc)
 {
return intel_uc_fw_is_supported(&guc->fw);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c3c45d3b9e89b..8c31000525b59 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4753,22 +4753,12 @@ static bool intel_gt_is_enabled(const struct intel_gt 
*gt)
return true;
 }
 
-static int guc_send_invalidate_tlb(struct intel_guc *guc,
-  enum intel_guc_tlb_invalidation_type type)
+static int guc_send_invalidate_tlb(struct intel_guc *guc, u32 *action, u32 
size)
 {
struct intel_guc_tlb_wait _wq, *wq = &_wq;
DEFINE_WAIT_FUNC(wait, woken_wake_function);
int err;
u32 seqno;
-   u32 action[] = {
-   INTEL_GUC_ACTION_TLB_INVALIDATION,
-   0,
-   REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_TYPE_MASK, type) |
-   REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_MODE_MASK,
-  INTEL_GUC_TLB_INVAL_MODE_HEAVY) |
-   INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
-   };
-   u32 size = ARRAY_SIZE(action);
 
init_waitqueue_head(&_wq.wq);
 
@@ -4822,13 +4812,102 @@ static int guc_send_invalidate_tlb(struct intel_guc 
*guc,
 /* Full TLB invalidation */
 int intel_guc_invalidate_tlb_engines(struct intel_guc *guc)
 {
-   return guc_send_invalidate_tlb(guc, INTEL_GUC_TLB_INVAL_ENGINES);
+   u32 action[] = {
+   INTEL_GUC_ACTION_TLB_INVALIDATION,
+   0,
+   REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_TYPE_MASK,
+  INTEL_GUC_TLB_INVAL_ENGINES) |
+   REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_MODE_MASK,
+  INTEL_GUC_TLB_INVAL_MODE_HEAVY) |
+   INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
+   };
+   u32 size = ARRAY_SIZE(action);
+   return guc_send_invalidate_tlb(guc, action, size);
+}
+
+/*
+ * Selective TLB Invalidation for Address Range:
+ * TLB's in the Address Range is Invalidated across all engines.
+ */
+int intel_guc_invalidate_tlb_page_selective(struct intel_guc *guc,
+   enum intel_guc_tlb_inval_mode mode,
+   u64 start, u64 length)
+{
+   u64 vm_total = BIT_ULL(RUNTIME_INFO(guc_to_gt(guc)->i915)->ppgtt_size);
+
+   /*
+* For page selective invalidations, this specifies the number of 
contiguous
+* PPGTT pages that needs to be invalidated.
+*/
+   u32 address_mask = length >= vm_total ? 0 : ilog2(length) - 
ilog2(SZ_4K);
+   u32 action[] = {
+   INTEL_GUC_ACTION_TLB_INVALIDATION,
+   0,
+   REG_

[Intel-gfx] [RFC PATCH 07/10] drm/i915: Enable GuC TLB invalidations for MTL

2023-10-10 Thread Jonathan Cavitt 
Enable GuC TLB invalidations for MTL.  Though more platforms than just
MTL support GuC TLB invalidations, MTL is presently the only platform
that requires it for any purpose, so only enable it there for now to
minimize cross-platform impact.

Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index df7c261410f79..d4b51ececbb12 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -829,6 +829,7 @@ static const struct intel_device_info mtl_info = {
.has_flat_ccs = 0,
.has_gmd_id = 1,
.has_guc_deprivilege = 1,
+   .has_guc_tlb_invalidation = 1,
.has_llc = 0,
.has_mslice_steering = 0,
.has_snoop = 1,
-- 
2.25.1

[Intel-gfx] [RFC PATCH 05/10] drm/i915: No TLB invalidation on wedged GT

2023-10-10 Thread Jonathan Cavitt 
It is not an error for GuC TLB invalidations to fail when the GT is
wedged or disabled, so do not process a wait failure as one in
guc_send_invalidate_tlb.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c  | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b9c168ea57270..c3c45d3b9e89b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -32,6 +32,7 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "i915_irq.h"
 #include "i915_trace.h"
 
 /**
@@ -1941,6 +1942,12 @@ void intel_guc_submission_cancel_requests(struct 
intel_guc *guc)
 
/* GuC is blown away, drop all references to contexts */
xa_destroy(&guc->context_lookup);
+
+   /*
+* Wedged GT won't respond to any TLB invalidation request. Simply
+* release all the blocked waiters.
+*/
+   wake_up_all_tlb_invalidate(guc);
 }
 
 void intel_guc_submission_reset_finish(struct intel_guc *guc)
@@ -4738,6 +4745,14 @@ static long must_wait_woken(struct wait_queue_entry 
*wq_entry, long timeout)
return timeout;
 }
 
+static bool intel_gt_is_enabled(const struct intel_gt *gt)
+{
+   /* Check if GT is wedged or suspended */
+   if (intel_gt_is_wedged(gt) || !intel_irqs_enabled(gt->i915))
+   return false;
+   return true;
+}
+
 static int guc_send_invalidate_tlb(struct intel_guc *guc,
   enum intel_guc_tlb_invalidation_type type)
 {
@@ -4790,7 +4805,8 @@ static int guc_send_invalidate_tlb(struct intel_guc *guc,
if (err)
goto out;
 
-   if (!must_wait_woken(&wait, intel_guc_ct_expected_delay(&guc->ct))) {
+   if (intel_gt_is_enabled(guc_to_gt(guc)) &&
+   !must_wait_woken(&wait, intel_guc_ct_expected_delay(&guc->ct))) {
guc_err(guc,
"TLB invalidation response timed out for seqno %u\n", 
seqno);
err = -ETIME;
-- 
2.25.1

[Intel-gfx] [RFC PATCH 02/10] drm/i915/guc: Add CT size delay helper

2023-10-10 Thread Jonathan Cavitt 
Add a helper function to the GuC CT buffer that reports the expected
time to process all outstanding requests.  As of now, there is no
functionality to check number of requests in the buffer, so the helper
function just reports 2 seconds, or 1ms per request up to the maximum
number of requests the CT buffer can store.

Suggested-by: John Harrison 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 58e42901ff498..36afc1ce9fabd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -120,6 +120,19 @@ static inline bool intel_guc_ct_enabled(struct 
intel_guc_ct *ct)
return ct->enabled;
 }
 
+/*
+ * GuC has a timeout of 1ms for a TLB invalidation response from GAM.  On a
+ * timeout GuC drops the request and has no mechanism to notify the host about
+ * the timeout.  There is also no mechanism for determining the number of
+ * outstanding requests in the CT buffer.  Ergo, keep a larger timeout that 
accounts
+ * for this individual timeout and the max number of outstanding requests that
+ * can be queued in CT buffer.
+ */
+static inline long intel_guc_ct_expected_delay(struct intel_guc_ct *ct)
+{
+   return HZ * 2;
+}
+
 #define INTEL_GUC_CT_SEND_NB   BIT(31)
 #define INTEL_GUC_CT_SEND_G2H_DW_SHIFT 0
 #define INTEL_GUC_CT_SEND_G2H_DW_MASK  (0xff << INTEL_GUC_CT_SEND_G2H_DW_SHIFT)
-- 
2.25.1

[Intel-gfx] [RFC PATCH 04/10] drm/i915: No TLB invalidation on suspended GT

2023-10-10 Thread Jonathan Cavitt 
In case of GT is suspended, don't allow submission of new TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 21 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  7 +++
 3 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index f5ede14b18aae..3fbf4b33ce139 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -537,4 +537,5 @@ void intel_guc_dump_time_info(struct intel_guc *guc, struct 
drm_printer *p);
 
 int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc);
 
+void wake_up_all_tlb_invalidate(struct intel_guc *guc);
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e9854652c2b52..b9c168ea57270 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1796,13 +1796,25 @@ static void __guc_reset_context(struct intel_context 
*ce, intel_engine_mask_t st
intel_context_put(parent);
 }
 
-void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
+void wake_up_all_tlb_invalidate(struct intel_guc *guc)
 {
struct intel_guc_tlb_wait *wait;
+   unsigned long i;
+
+   if (!HAS_GUC_TLB_INVALIDATION(guc_to_gt(guc)->i915))
+   return;
+
+   xa_lock_irq(&guc->tlb_lookup);
+   xa_for_each(&guc->tlb_lookup, i, wait)
+   wake_up(&wait->wq);
+   xa_unlock_irq(&guc->tlb_lookup);
+}
+
+void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
+{
struct intel_context *ce;
unsigned long index;
unsigned long flags;
-   unsigned long i;
 
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
@@ -1833,10 +1845,7 @@ void intel_guc_submission_reset(struct intel_guc *guc, 
intel_engine_mask_t stall
 * The full GT reset will have cleared the TLB caches and flushed the
 * G2H message queue; we can release all the blocked waiters.
 */
-   xa_lock_irq(&guc->tlb_lookup);
-   xa_for_each(&guc->tlb_lookup, i, wait)
-   wake_up(&wait->wq);
-   xa_unlock_irq(&guc->tlb_lookup);
+   wake_up_all_tlb_invalidate(guc);
 }
 
 static void guc_cancel_context_requests(struct intel_context *ce)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 98b103375b7ab..750cb63503dd7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -688,6 +688,8 @@ void intel_uc_suspend(struct intel_uc *uc)
/* flush the GSC worker */
intel_gsc_uc_flush_work(&uc->gsc);
 
+   wake_up_all_tlb_invalidate(guc);
+
if (!intel_guc_is_ready(guc)) {
guc->interrupts.enabled = false;
return;
@@ -736,6 +738,11 @@ static int __uc_resume(struct intel_uc *uc, bool 
enable_communication)
 
intel_gsc_uc_resume(&uc->gsc);
 
+   if (HAS_GUC_TLB_INVALIDATION(gt->i915)) {
+   intel_guc_invalidate_tlb_engines(guc);
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+
return 0;
 }
 
-- 
2.25.1

[Intel-gfx] [RFC PATCH 01/10] drm/i915: Add GuC TLB Invalidation device info flags

2023-10-10 Thread Jonathan Cavitt 
Add device info flags for if GuC TLB Invalidation is enabled.

Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb60fc9cf8737..6a2a78c61f212 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,6 +794,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_GUC_DEPRIVILEGE(i915) \
(INTEL_INFO(i915)->has_guc_deprivilege)
 
+#define HAS_GUC_TLB_INVALIDATION(i915) 
(INTEL_INFO(i915)->has_guc_tlb_invalidation)
+
 #define HAS_3D_PIPELINE(i915)  (INTEL_INFO(i915)->has_3d_pipeline)
 
 #define HAS_ONE_EU_PER_FUSE_BIT(i915)  
(INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 39817490b13fd..eba2f0b919c87 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
+   func(has_guc_tlb_invalidation); \
func(has_l3_ccs_read); \
func(has_l3_dpf); \
func(has_llc); \
-- 
2.25.1

Re: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily force MTL into uncached mode

2023-10-10 Thread John Harrison 

On 10/10/2023 09:44, Matt Roper wrote:

On Tue, Oct 10, 2023 at 05:42:28PM +0100, Tvrtko Ursulin wrote:

On 10/10/2023 17:17, Andi Shyti wrote:

Hi Matt,


FIXME: CAT errors are cropping up on MTL.  This removes them,
but the real root cause must still be diagnosed.

Do you have a link to specific IGT test(s) that illustrate the CAT
errors so that we can ensure that they now appear fixed in CI?

this one:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124599v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html

Andi

Wait, now I'm confused.  That's a failure caused by a different patch
series (one that we won't be moving forward with).  The live@hugepages
test is always passing on drm-tip today:
https://intel-gfx-ci.01.org/tree/drm-tip/igt@i915_selftest@l...@hugepages.html

yes, true, but that patch allows us to move forward with the
testing and hit the CAT error.

(it was the most reachable link I found :))


Is there a test that's giving CAT errors on drm-tip itself (even
sporadically) that we can monitor to see the impact of Jonathan's patch
here?

Otherwise this one:

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13667/re-mtlp-3/igt@gem_exec_fe...@parallel.html#dmesg-warnings11

Parachuting in on a tangent - please do not mix CAT and CT errors. CAT, for me 
at least, associates with CATastrophic faults reported over CT channel, like 
GuC page faulting IIRC.

For CT errors maybe GuC folks can sched some light what they mean.

0x6000 is GUC_ACTION_GUC2HOST_NOTIFY_MEMORY_CAT_ERROR so this actually
is a CAT error, delivered via the CT channel.
The history is that catastrophic memory errors (CAT is an abbreviation 
not an acronym) are never meant to happen in the upstream driver because 
we map all invalid addresses to a scratch page and silently hide such 
accesses. Hence there has been push back on adding support for an error 
channel which is officially impossible to hit. The problem is that we 
keep hitting it due to hardware and/or software bugs.


Because there is no official support for handling this notification, the 
CT layer reports it as an unexpected notification and barfs. As far as 
the CT layer is concerned, it is a corrupted packet from GuC. And thus 
the error reporting looks totally weird for what is just an illegal 
address access from some random part of the GPU. And note that it is 
very unlikely that GuC itself caused the page fault. It is much more 
plausible to be coming from an engine/EU/batch buffer instruction. 
Although as noted, the fundamental cause is believed to be broken page 
table updates due to cache coherency issues.


John.




Matt


Regards,

Tvrtko

[Intel-gfx] [RFC PATCH 09/10] drm/i915: Add generic interface for tlb invalidation

2023-10-10 Thread Jonathan Cavitt 
From: Prathap Kumar Valsan 

This supports selective and full tlb invalidations. When GuC is enabled
the tlb invalidations use guc ct otherwise use mmio interface.

Signed-off-by: Prathap Kumar Valsan 
CC: Niranjana Vishwanathapura 
CC: Fei Yang 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  8 ++
 drivers/gpu/drm/i915/gt/intel_tlb.c   | 52 +++
 drivers/gpu/drm/i915/gt/intel_tlb.h   |  1 +
 drivers/gpu/drm/i915/gt/selftest_tlb.c| 88 +++
 .../drm/i915/selftests/i915_mock_selftests.h  |  1 +
 5 files changed, 150 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index eecd0a87a6478..f2ca1c26ecde5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1124,6 +1124,14 @@
 
 #define GEN12_GAM_DONE _MMIO(0xcf68)
 
+#define XEHPSDV_TLB_INV_DESC0  _MMIO(0xcf7c)
+#define   XEHPSDV_TLB_INV_DESC0_ADDR_LOREG_GENMASK(31, 12)
+#define   XEHPSDV_TLB_INV_DESC0_ADDR_MASK  REG_GENMASK(8, 3)
+#define   XEHPSDV_TLB_INV_DESC0_G  REG_GENMASK(2, 1)
+#define   XEHPSDV_TLB_INV_DESC0_VALID  REG_BIT(0)
+#define XEHPSDV_TLB_INV_DESC1  _MMIO(0xcf80)
+#define   XEHPSDV_TLB_INV_DESC0_ADDR_HIREG_GENMASK(31, 0)
+
 #define GEN7_HALF_SLICE_CHICKEN1   _MMIO(0xe100) /* IVB GT1 + VLV 
*/
 #define GEN8_HALF_SLICE_CHICKEN1   MCR_REG(0xe100)
 #define   GEN7_MAX_PS_THREAD_DEP   (8 << 12)
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index 4bb13d1890e37..c31fd0875ac4f 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -157,6 +157,58 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 
seqno)
}
 }
 
+static u64 tlb_page_selective_size(u64 *addr, u64 length)
+{
+   const u64 end = *addr + length;
+   u64 start;
+
+   /*
+* Minimum invalidation size for a 2MB page that the hardware expects is
+* 16MB
+*/
+   length = max_t(u64, roundup_pow_of_two(length), SZ_4K);
+   if (length >= SZ_2M)
+   length = max_t(u64, SZ_16M, length);
+
+   /*
+* We need to invalidate a higher granularity if start address is not
+* aligned to length. When start is not aligned with length we need to
+* find the length large enough to create an address mask covering the
+* required range.
+*/
+   start = round_down(*addr, length);
+   while (start + length < end) {
+   length <<= 1;
+   start = round_down(*addr, length);
+   }
+
+   *addr = start;
+   return length;
+}
+
+bool intel_gt_invalidate_tlb_range(struct intel_gt *gt,
+  u64 start, u64 length)
+{
+   struct intel_guc *guc = >->uc.guc;
+   intel_wakeref_t wakeref;
+   u64 size, vm_total;
+   bool ret = true;
+
+   if (intel_gt_is_wedged(gt))
+   return true;
+
+   vm_total = BIT_ULL(RUNTIME_INFO(gt->i915)->ppgtt_size);
+   /* Align start and length */
+   size =  min_t(u64, vm_total, tlb_page_selective_size(&start, length));
+
+   with_intel_gt_pm_if_awake(gt, wakeref)
+   ret = intel_guc_invalidate_tlb_page_selective(guc,
+ 
INTEL_GUC_TLB_INVAL_MODE_HEAVY,
+ start, size) == 0;
+
+   return ret;
+}
+
 void intel_gt_init_tlb(struct intel_gt *gt)
 {
mutex_init(>->tlb.invalidate_lock);
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.h 
b/drivers/gpu/drm/i915/gt/intel_tlb.h
index 337327af92ac4..9e5fc40c2b08e 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.h
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.h
@@ -12,6 +12,7 @@
 #include "intel_gt_types.h"
 
 void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno);
+bool intel_gt_invalidate_tlb_range(struct intel_gt *gt, u64 start, u64 length);
 
 void intel_gt_init_tlb(struct intel_gt *gt);
 void intel_gt_fini_tlb(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c 
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 24beb94aa7a37..29f137a6e0362 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -382,10 +382,45 @@ static int invalidate_full(void *arg)
return err;
 }
 
+static void tlbinv_range(struct i915_address_space *vm, u64 addr, u64 length)
+{
+   if (!intel_gt_invalidate_tlb_range(vm->gt, addr, length))
+   pr_err("range invalidate failed\n");
+}
+
+static bool has_invalidate_range(struct intel_gt *gt)
+{
+   intel_wakeref_t wf;
+   bool result = false;
+
+   with_intel_gt_pm(gt, wf)
+   result = intel_gt_invalidate_tlb_range(gt, 0, gt->vm->total);
+
+

Re: [Intel-gfx] [PATCH] drm/i915/display: Free crtc_state in verify_crtc_state

2023-10-10 Thread Ville Syrjälä 
On Tue, Oct 10, 2023 at 11:02:09AM +0530, Suraj Kandpal wrote:
> Free hw_crtc_state in verify_crtc_state after we are done using
> this or else it's just a resource leak.
> 
> Fixes: 2745bdda2095 ("drm/i915: Stop clobbering old crtc state during state 
> check")
> Signed-off-by: Suraj Kandpal 
> Reviewed-by: Ville Syrjälä 

Thanks. Pushed to din.

> ---
>  drivers/gpu/drm/i915/display/intel_modeset_verify.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c 
> b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index 303eb68fec11..5e1c2c780412 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -214,7 +214,7 @@ verify_crtc_state(struct intel_atomic_state *state,
>   }
>  
>   if (!sw_crtc_state->hw.active)
> - return;
> + goto destroy_state;
>  
>   intel_pipe_config_sanity_check(hw_crtc_state);
>  
> @@ -224,6 +224,9 @@ verify_crtc_state(struct intel_atomic_state *state,
>   intel_crtc_state_dump(hw_crtc_state, NULL, "hw state");
>   intel_crtc_state_dump(sw_crtc_state, NULL, "sw state");
>   }
> +
> +destroy_state:
> + intel_crtc_destroy_state(&crtc->base, &hw_crtc_state->uapi);
>  }
>  
>  void intel_modeset_verify_crtc(struct intel_atomic_state *state,
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

[Intel-gfx] [RFC PATCH 04/10] drm/i915: No TLB invalidation on suspended GT

2023-10-10 Thread Jonathan Cavitt 
In case of GT is suspended, don't allow submission of new TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 21 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  7 +++
 3 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index f5ede14b18aae..3fbf4b33ce139 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -537,4 +537,5 @@ void intel_guc_dump_time_info(struct intel_guc *guc, struct 
drm_printer *p);
 
 int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc);
 
+void wake_up_all_tlb_invalidate(struct intel_guc *guc);
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e9854652c2b52..b9c168ea57270 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1796,13 +1796,25 @@ static void __guc_reset_context(struct intel_context 
*ce, intel_engine_mask_t st
intel_context_put(parent);
 }
 
-void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
+void wake_up_all_tlb_invalidate(struct intel_guc *guc)
 {
struct intel_guc_tlb_wait *wait;
+   unsigned long i;
+
+   if (!HAS_GUC_TLB_INVALIDATION(guc_to_gt(guc)->i915))
+   return;
+
+   xa_lock_irq(&guc->tlb_lookup);
+   xa_for_each(&guc->tlb_lookup, i, wait)
+   wake_up(&wait->wq);
+   xa_unlock_irq(&guc->tlb_lookup);
+}
+
+void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
+{
struct intel_context *ce;
unsigned long index;
unsigned long flags;
-   unsigned long i;
 
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
@@ -1833,10 +1845,7 @@ void intel_guc_submission_reset(struct intel_guc *guc, 
intel_engine_mask_t stall
 * The full GT reset will have cleared the TLB caches and flushed the
 * G2H message queue; we can release all the blocked waiters.
 */
-   xa_lock_irq(&guc->tlb_lookup);
-   xa_for_each(&guc->tlb_lookup, i, wait)
-   wake_up(&wait->wq);
-   xa_unlock_irq(&guc->tlb_lookup);
+   wake_up_all_tlb_invalidate(guc);
 }
 
 static void guc_cancel_context_requests(struct intel_context *ce)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 98b103375b7ab..750cb63503dd7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -688,6 +688,8 @@ void intel_uc_suspend(struct intel_uc *uc)
/* flush the GSC worker */
intel_gsc_uc_flush_work(&uc->gsc);
 
+   wake_up_all_tlb_invalidate(guc);
+
if (!intel_guc_is_ready(guc)) {
guc->interrupts.enabled = false;
return;
@@ -736,6 +738,11 @@ static int __uc_resume(struct intel_uc *uc, bool 
enable_communication)
 
intel_gsc_uc_resume(&uc->gsc);
 
+   if (HAS_GUC_TLB_INVALIDATION(gt->i915)) {
+   intel_guc_invalidate_tlb_engines(guc);
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+
return 0;
 }
 
-- 
2.25.1

[Intel-gfx] [RFC PATCH 10/10] drm/i915: Use selective tlb invalidations where supported

2023-10-10 Thread Jonathan Cavitt 
For platforms supporting selective tlb invalidations, we don't need to
do a full tlb invalidation. Rather do a range based tlb invalidation for
every unbind of purged vma belongs to an active vm.

Signed-off-by: Prathap Kumar Valsan 
Cc: Niranjana Vishwanathapura 
Cc: Fei Yang 
Signed-off-by: Mauro Carvalho Chehab 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   | 14 +-
 drivers/gpu/drm/i915/i915_vma.h   |  3 ++-
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c 
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index d07a4f97b9434..b43dae3cbd59f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
return;
 
vm->clear_range(vm, vma_res->start, vma_res->vma_size);
-   vma_invalidate_tlb(vm, vma_res->tlb);
+   vma_invalidate_tlb(vm, vma_res->tlb, vma_res->start, vma_res->vma_size);
 }
 
 static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index d09aad34ba37f..cb05d794f0d0f 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1339,7 +1339,8 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct 
i915_vma *vma)
return err;
 }
 
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb
+   u64 start, u64 size)
 {
struct intel_gt *gt;
int id;
@@ -1355,9 +1356,11 @@ void vma_invalidate_tlb(struct i915_address_space *vm, 
u32 *tlb)
 * the most recent TLB invalidation seqno, and if we have not yet
 * flushed the TLBs upon release, perform a full invalidation.
 */
-   for_each_gt(gt, vm->i915, id)
-   WRITE_ONCE(tlb[id],
-  intel_gt_next_invalidate_tlb_full(gt));
+   for_each_gt(gt, vm->i915, id) {
+   if (!intel_gt_invalidate_tlb_range(gt, start, size))
+   WRITE_ONCE(tlb[id],
+  intel_gt_next_invalidate_tlb_full(gt));
+   }
 }
 
 static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
@@ -2041,7 +2044,8 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, 
bool async)
dma_fence_put(unbind_fence);
unbind_fence = NULL;
}
-   vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+   vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb,
+  vma->node.start, vma->size);
}
 
/*
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index e356dfb883d34..5a604aad55dfe 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -260,7 +260,8 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
u64 size, u64 alignment, u64 flags);
 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
 void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+   u64 start, u64 size);
 struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
 int __i915_vma_unbind(struct i915_vma *vma);
 int __must_check i915_vma_unbind(struct i915_vma *vma);
-- 
2.25.1

[Intel-gfx] [RFC PATCH 08/10] drm/i915: Define GuC Based TLB invalidation routines

2023-10-10 Thread Jonathan Cavitt 
From: Prathap Kumar Valsan 

The GuC firmware has defined the interface for selective TLB
invalidation support. This patch adds routines to interface with GuC.

Signed-off-by: Prathap Kumar Valsan 
CC: Matthew Brost 
---
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  11 ++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 105 +++---
 3 files changed, 105 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 33f253410d0c8..7bb710fcd9087 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -189,6 +189,8 @@ enum intel_guc_state_capture_event_status {
 
 enum intel_guc_tlb_invalidation_type {
INTEL_GUC_TLB_INVAL_ENGINES = 0x0,
+   INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1,
+   INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX = 0x2,
INTEL_GUC_TLB_INVAL_GUC = 0x3,
 };
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 3fbf4b33ce139..369fd2be1c725 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -431,6 +431,17 @@ int intel_guc_allocate_and_map_vma(struct intel_guc *guc, 
u32 size,
 int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value);
 int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value);
 
+int intel_guc_g2g_register(struct intel_guc *guc);
+
+int intel_guc_invalidate_tlb_full(struct intel_guc *guc);
+int intel_guc_invalidate_tlb_page_selective(struct intel_guc *guc,
+   enum intel_guc_tlb_inval_mode mode,
+   u64 start, u64 length);
+int intel_guc_invalidate_tlb_page_selective_ctx(struct intel_guc *guc,
+   enum intel_guc_tlb_inval_mode 
mode,
+   u64 start, u64 length, u32 
ctxid);
+int intel_guc_invalidate_tlb_guc(struct intel_guc *guc);
+
 static inline bool intel_guc_is_supported(struct intel_guc *guc)
 {
return intel_uc_fw_is_supported(&guc->fw);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c3c45d3b9e89b..8c31000525b59 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4753,22 +4753,12 @@ static bool intel_gt_is_enabled(const struct intel_gt 
*gt)
return true;
 }
 
-static int guc_send_invalidate_tlb(struct intel_guc *guc,
-  enum intel_guc_tlb_invalidation_type type)
+static int guc_send_invalidate_tlb(struct intel_guc *guc, u32 *action, u32 
size)
 {
struct intel_guc_tlb_wait _wq, *wq = &_wq;
DEFINE_WAIT_FUNC(wait, woken_wake_function);
int err;
u32 seqno;
-   u32 action[] = {
-   INTEL_GUC_ACTION_TLB_INVALIDATION,
-   0,
-   REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_TYPE_MASK, type) |
-   REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_MODE_MASK,
-  INTEL_GUC_TLB_INVAL_MODE_HEAVY) |
-   INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
-   };
-   u32 size = ARRAY_SIZE(action);
 
init_waitqueue_head(&_wq.wq);
 
@@ -4822,13 +4812,102 @@ static int guc_send_invalidate_tlb(struct intel_guc 
*guc,
 /* Full TLB invalidation */
 int intel_guc_invalidate_tlb_engines(struct intel_guc *guc)
 {
-   return guc_send_invalidate_tlb(guc, INTEL_GUC_TLB_INVAL_ENGINES);
+   u32 action[] = {
+   INTEL_GUC_ACTION_TLB_INVALIDATION,
+   0,
+   REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_TYPE_MASK,
+  INTEL_GUC_TLB_INVAL_ENGINES) |
+   REG_FIELD_PREP(INTEL_GUC_TLB_INVAL_MODE_MASK,
+  INTEL_GUC_TLB_INVAL_MODE_HEAVY) |
+   INTEL_GUC_TLB_INVAL_FLUSH_CACHE,
+   };
+   u32 size = ARRAY_SIZE(action);
+   return guc_send_invalidate_tlb(guc, action, size);
+}
+
+/*
+ * Selective TLB Invalidation for Address Range:
+ * TLB's in the Address Range is Invalidated across all engines.
+ */
+int intel_guc_invalidate_tlb_page_selective(struct intel_guc *guc,
+   enum intel_guc_tlb_inval_mode mode,
+   u64 start, u64 length)
+{
+   u64 vm_total = BIT_ULL(RUNTIME_INFO(guc_to_gt(guc)->i915)->ppgtt_size);
+
+   /*
+* For page selective invalidations, this specifies the number of 
contiguous
+* PPGTT pages that needs to be invalidated.
+*/
+   u32 address_mask = length >= vm_total ? 0 : ilog2(length) - 
ilog2(SZ_4K);
+   u32 action[] = {
+   INTEL_GUC_ACTION_TLB_INVALIDATION,
+   0,
+   REG_

[Intel-gfx] [RFC PATCH 07/10] drm/i915: Enable GuC TLB invalidations for MTL

2023-10-10 Thread Jonathan Cavitt 
Enable GuC TLB invalidations for MTL.  Though more platforms than just
MTL support GuC TLB invalidations, MTL is presently the only platform
that requires it for any purpose, so only enable it there for now to
minimize cross-platform impact.

Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index df7c261410f79..d4b51ececbb12 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -829,6 +829,7 @@ static const struct intel_device_info mtl_info = {
.has_flat_ccs = 0,
.has_gmd_id = 1,
.has_guc_deprivilege = 1,
+   .has_guc_tlb_invalidation = 1,
.has_llc = 0,
.has_mslice_steering = 0,
.has_snoop = 1,
-- 
2.25.1

[Intel-gfx] [RFC PATCH 03/10] drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Jonathan Cavitt 
From: Prathap Kumar Valsan 

The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation.  We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back to GT invalidation when the GuC is
disabled.
The invalidation is done by sending a request directly to the GuC
tlb_lookup that invalidates the table.  The invalidation is submitted as
a wait request and is performed in the CT event handler.  This means we
cannot perform this TLB invalidation path if the CT is not enabled.
If the request isn't fulfilled in two seconds, this would constitute
an error in the invalidation as that would constitute either a lost
request or a severe GuC overload.

With this new invalidation routine, we can perform GuC-based GGTT
invalidations.  GuC-based GGTT invalidation is incompatible with
MMIO invalidation so we should not perform MMIO invalidation when
GuC-based GGTT invalidation is expected.

The additional complexity incurred in this patch will be necessary for
range-based tlb invalidations, which will be platformed in the future.

Signed-off-by: Prathap Kumar Valsan 
Signed-off-by: Bruce Chang 
Signed-off-by: Chris Wilson 
Signed-off-by: Umesh Nerlige Ramappa 
Signed-off-by: Jonathan Cavitt 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Fei Yang 
CC: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 +++-
 drivers/gpu/drm/i915/gt/intel_tlb.c   |  16 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  22 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 186 +-
 7 files changed, 284 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 4d7d88b92632b..a1f7bdc602996 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -206,22 +206,38 @@ static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 }
 
+static void guc_ggtt_ct_invalidate(struct intel_gt *gt)
+{
+   struct intel_uncore *uncore = gt->uncore;
+   intel_wakeref_t wakeref;
+
+   with_intel_runtime_pm_if_active(uncore->rpm, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+}
+
 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
struct drm_i915_private *i915 = ggtt->vm.i915;
+   struct intel_gt *gt;
 
-   gen8_ggtt_invalidate(ggtt);
-
-   if (GRAPHICS_VER(i915) >= 12) {
-   struct intel_gt *gt;
+   if (!HAS_GUC_TLB_INVALIDATION(i915))
+   gen8_ggtt_invalidate(ggtt);
 
-   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link)
+   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link) {
+   if (HAS_GUC_TLB_INVALIDATION(i915) &&
+   intel_guc_is_ready(>->uc.guc)) {
+   guc_ggtt_ct_invalidate(gt);
+   } else if (GRAPHICS_VER(i915) >= 12) {
intel_uncore_write_fw(gt->uncore,
  GEN12_GUC_TLB_INV_CR,
  GEN12_GUC_TLB_INV_CR_INVALIDATE);
-   } else {
-   intel_uncore_write_fw(ggtt->vm.gt->uncore,
- GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   } else {
+   intel_uncore_write_fw(gt->uncore,
+ GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   }
}
 }
 
@@ -1243,7 +1259,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
}
 
-   if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
+   if (intel_uc_wants_guc_submission(&ggtt->vm.gt->uc))
ggtt->invalidate = guc_ggtt_invalidate;
else
ggtt->invalidate = gen8_ggtt_invalidate;
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index 139608c30d978..4bb13d1890e37 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -12,6 +12,7 @@
 #include "intel_gt_print.h"
 #include "intel_gt_regs.h"
 #include "intel_tlb.h"
+#include "uc/intel_guc.h"
 
 /*
  * HW architecture suggest typical invalidation time at 40us,
@@ -131,11 +132,24 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, 
u32 seqno)
return;
 
with_intel_gt_pm_if_awake(gt, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
mutex_lock(>->tlb.invalidate_lock);
if (tlb_seqno_passed(gt, seqno))
goto unlock;
 
-

[Intel-gfx] [RFC PATCH 02/10] drm/i915/guc: Add CT size delay helper

2023-10-10 Thread Jonathan Cavitt 
Add a helper function to the GuC CT buffer that reports the expected
time to process all outstanding requests.  As of now, there is no
functionality to check number of requests in the buffer, so the helper
function just reports 2 seconds, or 1ms per request up to the maximum
number of requests the CT buffer can store.

Suggested-by: John Harrison 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 58e42901ff498..36afc1ce9fabd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -120,6 +120,19 @@ static inline bool intel_guc_ct_enabled(struct 
intel_guc_ct *ct)
return ct->enabled;
 }
 
+/*
+ * GuC has a timeout of 1ms for a TLB invalidation response from GAM.  On a
+ * timeout GuC drops the request and has no mechanism to notify the host about
+ * the timeout.  There is also no mechanism for determining the number of
+ * outstanding requests in the CT buffer.  Ergo, keep a larger timeout that 
accounts
+ * for this individual timeout and the max number of outstanding requests that
+ * can be queued in CT buffer.
+ */
+static inline long intel_guc_ct_expected_delay(struct intel_guc_ct *ct)
+{
+   return HZ * 2;
+}
+
 #define INTEL_GUC_CT_SEND_NB   BIT(31)
 #define INTEL_GUC_CT_SEND_G2H_DW_SHIFT 0
 #define INTEL_GUC_CT_SEND_G2H_DW_MASK  (0xff << INTEL_GUC_CT_SEND_G2H_DW_SHIFT)
-- 
2.25.1

[Intel-gfx] [RFC PATCH 06/10] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck

2023-10-10 Thread Jonathan Cavitt 
For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.

Additionally, increase the default timeout from 10 ms to 20 ms
because msleep < 20ms can sleep for up to 20ms.

Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c 
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 7e41f69fc818f..24beb94aa7a37 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -136,8 +136,15 @@ pte_tlbinv(struct intel_context *ce,
i915_request_get(rq);
i915_request_add(rq);
 
-   /* Short sleep to sanitycheck the batch is spinning before we begin */
-   msleep(10);
+   /*
+* Short sleep to sanitycheck the batch is spinning before we begin.
+* FIXME: Why is GSC so slow?
+*/
+   if (ce->engine->class == OTHER_CLASS)
+   msleep(200);
+   else
+   msleep(20);
+
if (va == vb) {
if (!i915_request_completed(rq)) {
pr_err("%s(%s): Semaphore sanitycheck failed %llx, with 
alignment %llx, using PTE size %x (phys %x, sg %x)\n",
-- 
2.25.1

[Intel-gfx] [RFC PATCH 05/10] drm/i915: No TLB invalidation on wedged GT

2023-10-10 Thread Jonathan Cavitt 
It is not an error for GuC TLB invalidations to fail when the GT is
wedged or disabled, so do not process a wait failure as one in
guc_send_invalidate_tlb.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c  | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b9c168ea57270..c3c45d3b9e89b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -32,6 +32,7 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "i915_irq.h"
 #include "i915_trace.h"
 
 /**
@@ -1941,6 +1942,12 @@ void intel_guc_submission_cancel_requests(struct 
intel_guc *guc)
 
/* GuC is blown away, drop all references to contexts */
xa_destroy(&guc->context_lookup);
+
+   /*
+* Wedged GT won't respond to any TLB invalidation request. Simply
+* release all the blocked waiters.
+*/
+   wake_up_all_tlb_invalidate(guc);
 }
 
 void intel_guc_submission_reset_finish(struct intel_guc *guc)
@@ -4738,6 +4745,14 @@ static long must_wait_woken(struct wait_queue_entry 
*wq_entry, long timeout)
return timeout;
 }
 
+static bool intel_gt_is_enabled(const struct intel_gt *gt)
+{
+   /* Check if GT is wedged or suspended */
+   if (intel_gt_is_wedged(gt) || !intel_irqs_enabled(gt->i915))
+   return false;
+   return true;
+}
+
 static int guc_send_invalidate_tlb(struct intel_guc *guc,
   enum intel_guc_tlb_invalidation_type type)
 {
@@ -4790,7 +4805,8 @@ static int guc_send_invalidate_tlb(struct intel_guc *guc,
if (err)
goto out;
 
-   if (!must_wait_woken(&wait, intel_guc_ct_expected_delay(&guc->ct))) {
+   if (intel_gt_is_enabled(guc_to_gt(guc)) &&
+   !must_wait_woken(&wait, intel_guc_ct_expected_delay(&guc->ct))) {
guc_err(guc,
"TLB invalidation response timed out for seqno %u\n", 
seqno);
err = -ETIME;
-- 
2.25.1

[Intel-gfx] [PATCH dii-client 1/2] drm/i915: Add generic interface for tlb invalidation

2023-10-10 Thread Jonathan Cavitt 
From: Prathap Kumar Valsan 

This supports selective and full tlb invalidations. When GuC is enabled
the tlb invalidations use guc ct otherwise use mmio interface.

Signed-off-by: Prathap Kumar Valsan 
CC: Niranjana Vishwanathapura 
CC: Fei Yang 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  8 ++
 drivers/gpu/drm/i915/gt/intel_tlb.c   | 58 +++-
 drivers/gpu/drm/i915/gt/intel_tlb.h   |  1 +
 drivers/gpu/drm/i915/gt/selftest_tlb.c| 92 +++
 .../drm/i915/selftests/i915_mock_selftests.h  |  1 +
 5 files changed, 159 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index eecd0a87a6478..f2ca1c26ecde5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1124,6 +1124,14 @@
 
 #define GEN12_GAM_DONE _MMIO(0xcf68)
 
+#define XEHPSDV_TLB_INV_DESC0  _MMIO(0xcf7c)
+#define   XEHPSDV_TLB_INV_DESC0_ADDR_LOREG_GENMASK(31, 12)
+#define   XEHPSDV_TLB_INV_DESC0_ADDR_MASK  REG_GENMASK(8, 3)
+#define   XEHPSDV_TLB_INV_DESC0_G  REG_GENMASK(2, 1)
+#define   XEHPSDV_TLB_INV_DESC0_VALID  REG_BIT(0)
+#define XEHPSDV_TLB_INV_DESC1  _MMIO(0xcf80)
+#define   XEHPSDV_TLB_INV_DESC0_ADDR_HIREG_GENMASK(31, 0)
+
 #define GEN7_HALF_SLICE_CHICKEN1   _MMIO(0xe100) /* IVB GT1 + VLV 
*/
 #define GEN8_HALF_SLICE_CHICKEN1   MCR_REG(0xe100)
 #define   GEN7_MAX_PS_THREAD_DEP   (8 << 12)
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index 139608c30d978..92fb455299717 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -12,6 +12,7 @@
 #include "intel_gt_print.h"
 #include "intel_gt_regs.h"
 #include "intel_tlb.h"
+#include "uc/intel_guc.h"
 
 /*
  * HW architecture suggest typical invalidation time at 40us,
@@ -131,11 +132,14 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, 
u32 seqno)
return;
 
with_intel_gt_pm_if_awake(gt, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
mutex_lock(>->tlb.invalidate_lock);
if (tlb_seqno_passed(gt, seqno))
goto unlock;
 
-   mmio_invalidate_full(gt);
+   if (intel_guc_invalidate_tlb_full(guc, 
INTEL_GUC_TLB_INVAL_MODE_HEAVY) < 0)
+   mmio_invalidate_full(gt);
 
write_seqcount_invalidate(>->tlb.seqno);
 unlock:
@@ -143,6 +147,58 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 
seqno)
}
 }
 
+static u64 tlb_page_selective_size(u64 *addr, u64 length)
+{
+   const u64 end = *addr + length;
+   u64 start;
+
+   /*
+* Minimum invalidation size for a 2MB page that the hardware expects is
+* 16MB
+*/
+   length = max_t(u64, roundup_pow_of_two(length), SZ_4K);
+   if (length >= SZ_2M)
+   length = max_t(u64, SZ_16M, length);
+
+   /*
+* We need to invalidate a higher granularity if start address is not
+* aligned to length. When start is not aligned with length we need to
+* find the length large enough to create an address mask covering the
+* required range.
+*/
+   start = round_down(*addr, length);
+   while (start + length < end) {
+   length <<= 1;
+   start = round_down(*addr, length);
+   }
+
+   *addr = start;
+   return length;
+}
+
+bool intel_gt_invalidate_tlb_range(struct intel_gt *gt,
+  u64 start, u64 length)
+{
+   struct intel_guc *guc = >->uc.guc;
+   intel_wakeref_t wakeref;
+   u64 size, vm_total;
+   bool ret = true;
+
+   if (intel_gt_is_wedged(gt))
+   return true;
+
+   vm_total = BIT_ULL(INTEL_INFO(gt->i915)->ppgtt_size);
+   /* Align start and length */
+   size =  min_t(u64, vm_total, tlb_page_selective_size(&start, length));
+
+   with_intel_gt_pm_if_awake(gt, wakeref)
+   ret = intel_guc_invalidate_tlb_page_selective(guc,
+ 
INTEL_GUC_TLB_INVAL_MODE_HEAVY,
+ start, size) == 0;
+
+   return ret;
+}
+
 void intel_gt_init_tlb(struct intel_gt *gt)
 {
mutex_init(>->tlb.invalidate_lock);
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.h 
b/drivers/gpu/drm/i915/gt/intel_tlb.h
index 337327af92ac4..9e5fc40c2b08e 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.h
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.h
@@ -12,6 +12,7 @@
 #include "intel_gt_types.h"
 
 void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno);
+bool intel_gt_invalidate_tlb_range(struct intel_gt *gt, u64 start, u64 length);
 
 void intel_gt_init_tlb(stru

[Intel-gfx] [RFC PATCH 01/10] drm/i915: Add GuC TLB Invalidation device info flags

2023-10-10 Thread Jonathan Cavitt 
Add device info flags for if GuC TLB Invalidation is enabled.

Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb60fc9cf8737..6a2a78c61f212 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,6 +794,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_GUC_DEPRIVILEGE(i915) \
(INTEL_INFO(i915)->has_guc_deprivilege)
 
+#define HAS_GUC_TLB_INVALIDATION(i915) 
(INTEL_INFO(i915)->has_guc_tlb_invalidation)
+
 #define HAS_3D_PIPELINE(i915)  (INTEL_INFO(i915)->has_3d_pipeline)
 
 #define HAS_ONE_EU_PER_FUSE_BIT(i915)  
(INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 39817490b13fd..eba2f0b919c87 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
+   func(has_guc_tlb_invalidation); \
func(has_l3_ccs_read); \
func(has_l3_dpf); \
func(has_llc); \
-- 
2.25.1

[Intel-gfx] [PATCH dii-client 2/2] drm/i915: Use selective tlb invalidations where supported

2023-10-10 Thread Jonathan Cavitt 
For platforms supporting selective tlb invalidations, we don't need to
do a full tlb invalidation. Rather do a range based tlb invalidation for
every unbind of purged vma belongs to an active vm.

Signed-off-by: Prathap Kumar Valsan 
Cc: Niranjana Vishwanathapura 
Cc: Fei Yang 
Signed-off-by: Mauro Carvalho Chehab 
Signed-off-by: Jonathan Cavitt 
---
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  2 +-
 drivers/gpu/drm/i915/i915_vma.c   | 14 +-
 drivers/gpu/drm/i915/i915_vma.h   |  3 ++-
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c 
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index d07a4f97b9434..b43dae3cbd59f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
return;
 
vm->clear_range(vm, vma_res->start, vma_res->vma_size);
-   vma_invalidate_tlb(vm, vma_res->tlb);
+   vma_invalidate_tlb(vm, vma_res->tlb, vma_res->start, vma_res->vma_size);
 }
 
 static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index d09aad34ba37f..cb05d794f0d0f 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1339,7 +1339,8 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct 
i915_vma *vma)
return err;
 }
 
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb
+   u64 start, u64 size)
 {
struct intel_gt *gt;
int id;
@@ -1355,9 +1356,11 @@ void vma_invalidate_tlb(struct i915_address_space *vm, 
u32 *tlb)
 * the most recent TLB invalidation seqno, and if we have not yet
 * flushed the TLBs upon release, perform a full invalidation.
 */
-   for_each_gt(gt, vm->i915, id)
-   WRITE_ONCE(tlb[id],
-  intel_gt_next_invalidate_tlb_full(gt));
+   for_each_gt(gt, vm->i915, id) {
+   if (!intel_gt_invalidate_tlb_range(gt, start, size))
+   WRITE_ONCE(tlb[id],
+  intel_gt_next_invalidate_tlb_full(gt));
+   }
 }
 
 static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
@@ -2041,7 +2044,8 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, 
bool async)
dma_fence_put(unbind_fence);
unbind_fence = NULL;
}
-   vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+   vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb,
+  vma->node.start, vma->size);
}
 
/*
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index e356dfb883d34..5a604aad55dfe 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -260,7 +260,8 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
u64 size, u64 alignment, u64 flags);
 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
 void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+   u64 start, u64 size);
 struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
 int __i915_vma_unbind(struct i915_vma *vma);
 int __must_check i915_vma_unbind(struct i915_vma *vma);
-- 
2.25.1

[Intel-gfx] [RFC PATCH 00/10] drm/i915: Implement range-based TLB

2023-10-10 Thread Jonathan Cavitt 
Implement range-based TLB invalidations on top of GuC-based TLB
invalidations.  This is the future plan for GuC-based TLB
invalidations because it helps improve performance over performing
full tlb invalidations all the time.

Jonathan Cavitt (7):
  drm/i915: Add GuC TLB Invalidation device info flags
  drm/i915/guc: Add CT size delay helper
  drm/i915: No TLB invalidation on suspended GT
  drm/i915: No TLB invalidation on wedged GT
  drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
  drm/i915: Enable GuC TLB invalidations for MTL
  drm/i915: Use selective tlb invalidations where supported

Prathap Kumar Valsan (3):
  drm/i915: Define and use GuC and CTB TLB invalidation routines
  drm/i915: Define GuC Based TLB invalidation routines
  drm/i915: Add generic interface for tlb invalidation

 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  34 +-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |   8 +
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |   2 +-
 drivers/gpu/drm/i915/gt/intel_tlb.c   |  68 +++-
 drivers/gpu/drm/i915/gt/intel_tlb.h   |   1 +
 drivers/gpu/drm/i915/gt/selftest_tlb.c|  99 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  35 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  34 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   4 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  13 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 290 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |   7 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_pci.c   |   1 +
 drivers/gpu/drm/i915/i915_vma.c   |  14 +-
 drivers/gpu/drm/i915/i915_vma.h   |   3 +-
 drivers/gpu/drm/i915/intel_device_info.h  |   1 +
 .../drm/i915/selftests/i915_mock_selftests.h  |   1 +
 19 files changed, 597 insertions(+), 21 deletions(-)

-- 
2.25.1

Re: [Intel-gfx] [PATCH v2] drm/i915/gt: Temporarily force MTL into uncached mode

2023-10-10 Thread John Harrison 

On 10/10/2023 07:36, Jonathan Cavitt wrote:

FIXME: CAT errors are cropping up on MTL.  This removes them,
but the real root cause must still be diagnosed.
I think 'hides' would be more accurate than 'removes'. At least until we 
have a better understanding of the issue.


Also, is there any performance penalty with this change? If we are going 
from fully cached to write combined then one assumes that something, 
somewhere is going to notice? Do we have any benchmark results or other 
tests that show an impact?


John.




Signed-off-by: Jonathan Cavitt 
---

v2: Apply FIXME to shmem_utils as well.

  drivers/gpu/drm/i915/gt/intel_gt.c | 6 +-
  drivers/gpu/drm/i915/gt/intel_lrc.c| 5 -
  drivers/gpu/drm/i915/gt/shmem_utils.c  | 8 +++-
  drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 -
  4 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index ed32bf5b15464..b52c8eb0b033f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1026,8 +1026,12 @@ enum i915_map_type intel_gt_coherent_map_type(struct 
intel_gt *gt,
/*
 * Wa_22016122933: always return I915_MAP_WC for Media
 * version 13.0 when the object is on the Media GT
+*
+* FIXME: CAT errors are cropping up on MTL.  This removes them,
+* but the real root cause must still be diagnosed.
 */
-   if (i915_gem_object_is_lmem(obj) || intel_gt_needs_wa_22016122933(gt))
+   if (i915_gem_object_is_lmem(obj) || intel_gt_needs_wa_22016122933(gt) ||
+   IS_METEORLAKE(gt->i915))
return I915_MAP_WC;
if (HAS_LLC(gt->i915) || always_coherent)
return I915_MAP_WB;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index eaf66d9031665..8aaa4df84cb3e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1124,8 +1124,11 @@ __lrc_alloc_state(struct intel_context *ce, struct 
intel_engine_cs *engine)
 * Wa_22016122933: For Media version 13.0, all Media GT shared
 * memory needs to be mapped as WC on CPU side and UC (PAT
 * index 2) on GPU side.
+*
+* FIXME: CAT errors are cropping up on MTL.  This removes them,
+* but the real root cause must still be diagnosed.
 */
-   if (intel_gt_needs_wa_22016122933(engine->gt))
+   if (intel_gt_needs_wa_22016122933(engine->gt) || 
IS_METEORLAKE(engine->i915))
i915_gem_object_set_cache_coherency(obj, 
I915_CACHE_NONE);
}
  
diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c b/drivers/gpu/drm/i915/gt/shmem_utils.c

index bccc3a1200bc6..a026c216fd286 100644
--- a/drivers/gpu/drm/i915/gt/shmem_utils.c
+++ b/drivers/gpu/drm/i915/gt/shmem_utils.c
@@ -43,7 +43,13 @@ struct file *shmem_create_from_object(struct 
drm_i915_gem_object *obj)
return file;
}
  
-	map_type = i915_gem_object_is_lmem(obj) ? I915_MAP_WC : I915_MAP_WB;

+   /*
+* FIXME: CAT errors are cropping up on MTL.  This removes them,
+* but the real root cause must still be diagnosed.
+*/
+   map_type = i915_gem_object_is_lmem(obj) ||
+  IS_METEORLAKE(to_i915(obj->base.dev)) ?
+  I915_MAP_WC : I915_MAP_WB;
ptr = i915_gem_object_pin_map_unlocked(obj, map_type);
if (IS_ERR(ptr))
return ERR_CAST(ptr);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 27df41c53b890..e3a7d61506188 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -774,8 +774,11 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc 
*guc, u32 size)
 * Wa_22016122933: For Media version 13.0, all Media GT shared
 * memory needs to be mapped as WC on CPU side and UC (PAT
 * index 2) on GPU side.
+*
+* FIXME: CAT errors are cropping up on MTL.  This removes them,
+* but the real root cause must still be diagnosed.
 */
-   if (intel_gt_needs_wa_22016122933(gt))
+   if (intel_gt_needs_wa_22016122933(gt) || IS_METEORLAKE(gt->i915))
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
  
  	vma = i915_vma_instance(obj, >->ggtt->vm, NULL);

[Intel-gfx] [PATCH 2/2] drm/i915/display: Use correct method to free crtc_state

2023-10-10 Thread Suraj Kandpal 
Even though there is no leaking of resource here lets
just use the correct method to free crtc_state

Fixes: 8a3b3df39757 ("drm/i915: Clean up variable names in old dpll functions")
Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 2255ad651486..d41c1dc9f66c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -7,6 +7,7 @@
 #include 
 
 #include "i915_reg.h"
+#include "intel_atomic.h"
 #include "intel_crtc.h"
 #include "intel_cx0_phy.h"
 #include "intel_de.h"
@@ -2006,7 +2007,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, 
enum pipe pipe,
vlv_enable_pll(crtc_state);
}
 
-   kfree(crtc_state);
+   intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
 
return 0;
 }
-- 
2.25.1

[Intel-gfx] [PATCH 1/2] drm/i915/display: Use intel_crtc_destroy_state instead kfree

2023-10-10 Thread Suraj Kandpal 
intel_encoder_current_mode() seems to leak some resource because
it uses kfree instead of intel_crtc_destroy_state let us fix that.

Fixes: de330815677d ("drm/i915: Reuse normal state readout for LVDS/DVO fixed 
mode")
Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index e309fda108ef..e7129a5630db 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3999,7 +3999,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
}
 
if (!intel_crtc_get_pipe_config(crtc_state)) {
-   kfree(crtc_state);
+   intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
kfree(mode);
return NULL;
}
@@ -4008,7 +4008,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
 
intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
 
-   kfree(crtc_state);
+   intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
 
return mode;
 }
-- 
2.25.1

[Intel-gfx] [PATCH 0/2] Use intel_crtc_destroy state

2023-10-10 Thread Suraj Kandpal 
Use intel_crtc_destroy_state to avoid leakage of any resources
instead of the usual kfree

Signed-off-by: Suraj Kandpal 

Suraj Kandpal (2):
  drm/i915/display: Use intel_crtc_destroy_state instead kfree
  drm/i915/display: Use correct method to free crtc_state

 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/display/intel_dpll.c| 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

-- 
2.25.1

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for More print message helper updates

2023-10-10 Thread John Harrison 

On 10/9/2023 19:26, Patchwork wrote:

Project List - Patchwork *Patch Details*
*Series:*   More print message helper updates
*URL:*  https://patchwork.freedesktop.org/series/124853/
*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124853v1/index.html



  CI Bug Log - changes from CI_DRM_13732 -> Patchwork_124853v1


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_124853v1 absolutely need 
to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_124853v1, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives 
in CI.


External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124853v1/index.html



Participating hosts (36 -> 34)

Missing (2): fi-kbl-soraka fi-snb-2520m


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_124853v1:



  CI changes


Possible regressions

  * boot:
  o fi-ilk-650: PASS


-> FAIL



System failed to boot properly. Didn't even get as far as loading the 
i915 module according to the logs. So definitely not caused by tweaking 
some debug prints within the i915 module. Also, system booted and ran 
just fine on the re-test.


John.


 *


Known issues

Here are the changes found in Patchwork_124853v1 that come from known 
issues:



  CI changes


Issues hit

  * boot:
  o fi-skl-guc: PASS


-> FAIL


(i915#8293 )


  IGT changes


Issues hit

 *

igt@gem_exec_suspend@basic-s0@lmem0:

  o bat-dg2-9: PASS


-> INCOMPLETE


(i915#9275 )
 *

igt@i915_selftest@live@requests:

  o bat-mtlp-8: PASS


-> ABORT


(i915#9414 )


Possible fixes

  * igt@kms_hdmi_inject@inject-audio:
  o fi-kbl-guc: FAIL


(IGT#3
)
-> PASS




Build changes

  * Linux: CI_DRM_13732 -> Patchwork_124853v1

CI-20190529: 20190529
CI_DRM_13732: 7c57bbfe2c6194cc4d4edf50466b057d7b191251 @ 
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7523: 361c2f92f1fe5641090f2fc59951fcaba15387f5 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_124853v1: 7c57bbfe2c6194cc4d4edf50466b057d7b191251 @ 
git://anongit.freedesktop.org/gfx-ci/linux



  Linux commits

6eb131b16d85 drm/i915: More use of GT specific print helpers
decb307d48d5 drm/i915/gt: More use of GT specific print helpers

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remove the module parameter 'fastboot' (rev4)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915: Remove the module parameter 'fastboot' (rev4)
URL   : https://patchwork.freedesktop.org/series/124255/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13733_full -> Patchwork_124255v4_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_124255v4_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_124255v4_full, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_124255v4_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_suspend@basic-s0@lmem0:
- shard-dg2:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-dg2-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@kms_draw_crc@draw-method-blt@xrgb2101010-ytiled:
- shard-glk:  [PASS][2] -> [DMESG-WARN][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-glk2/igt@kms_draw_crc@draw-method-...@xrgb2101010-ytiled.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-glk5/igt@kms_draw_crc@draw-method-...@xrgb2101010-ytiled.html

  
 Warnings 

  * igt@kms_rotation_crc@sprite-rotation-90:
- shard-rkl:  [INCOMPLETE][4] ([i915#8875]) -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-rkl-2/igt@kms_rotation_...@sprite-rotation-90.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-rkl-4/igt@kms_rotation_...@sprite-rotation-90.html

  
Known issues


  Here are the changes found in Patchwork_124255v4_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_fdinfo@busy-check-all@ccs0:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#8414]) +11 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-mtlp-7/igt@drm_fdinfo@busy-check-...@ccs0.html

  * igt@drm_fdinfo@busy-check-all@vecs1:
- shard-dg2:  NOTRUN -> [SKIP][7] ([i915#8414]) +10 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-dg2-11/igt@drm_fdinfo@busy-check-...@vecs1.html

  * igt@gem_busy@semaphore:
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#3936])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-mtlp-3/igt@gem_b...@semaphore.html

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [PASS][9] -> [FAIL][10] ([i915#6268])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-tglu-10/igt@gem_ctx_e...@basic-nohangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-tglu-2/igt@gem_ctx_e...@basic-nohangcheck.html
- shard-mtlp: NOTRUN -> [FAIL][11] ([i915#6268])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-mtlp-3/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_ctx_isolation@preservation-s3@vcs1:
- shard-mtlp: [PASS][12] -> [ABORT][13] ([i915#9262])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-mtlp-6/igt@gem_ctx_isolation@preservation...@vcs1.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-mtlp-4/igt@gem_ctx_isolation@preservation...@vcs1.html

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-mtlp: [PASS][14] -> [DMESG-WARN][15] ([i915#9262])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-mtlp-6/igt@gem_ctx_isolation@preservation...@vecs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-mtlp-4/igt@gem_ctx_isolation@preservation...@vecs0.html

  * igt@gem_ctx_persistence@engines-hang:
- shard-snb:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1099])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-snb5/igt@gem_ctx_persiste...@engines-hang.html

  * igt@gem_ctx_sseu@mmap-args:
- shard-dg2:  NOTRUN -> [SKIP][17] ([i915#280]) +1 other test skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-dg2-3/igt@gem_ctx_s...@mmap-args.html

  * igt@gem_eio@reset-stress:
- shard-snb:  NOTRUN -> [FAIL][18] ([i915#8898])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-snb5/igt@gem_...@reset-stress.html

  * igt@gem_exec_balancer@sliced:
- shard-mtlp: NOTRUN -> [SKIP][19] ([i915#4812])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124255v4/shard-mtlp-7/igt@gem_exec_balan...@sliced.html

  * igt@g

Re: [Intel-gfx] [PATCH RESEND v2 0/2] Add drm_dbg_ratelimited()

2023-10-10 Thread John Harrison 

On 10/10/2023 05:15, Andi Shyti wrote:

Hi,

I might have picked up the wrong series and missed some reviews
and the extra patch from Nirmoy with a real use of the
drm_dbg_ratelimited() that John was looking for.

Thanks,
Andi
I just found the original post of this from back in January 
(https://patchwork.freedesktop.org/series/112925/). Is there a reason 
why it was never merged? As noted, it appears to have a whole bunch of 
r-b's on it.


John.


v2:
pick the right patch with the following changes:
  - add more r-b's
  - add a patch 2 where the drm_dbg_ratelimited is actually used.

Nirmoy Das (2):
   drm/print: Add drm_dbg_ratelimited
   drm/i915: Ratelimit debug log in vm_fault_ttm

  drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 5 +++--
  include/drm/drm_print.h | 3 +++
  2 files changed, 6 insertions(+), 2 deletions(-)

Re: [Intel-gfx] [PATCH i-g-t v2 04/11] lib/kunit: Parse KTAP report from the main process thread

2023-10-10 Thread Janusz Krzysztofik 
Hi Mauro,

Thanks for review.

On Tuesday, 10 October 2023 15:33:57 CEST Mauro Carvalho Chehab wrote:
> On Mon,  9 Oct 2023 14:27:55 +0200
> Janusz Krzysztofik  wrote:
> 
> > There was an attempt to parse KTAP reports in the background while a kunit
> > test module is loading.  However, since dynamic sub-subtests can be
> > executed only from the main thread, that attempt was not quite successful,
> > as IGT results from all executed kunit test cases were generated only
> > after loading of kunit test module completed.
> > 
> > Now that the parser maintains its state and we can call it separately for
> > each input line of a KTAP report, it is perfectly possible to call the
> > parser from the main thread while the module is loading in the background,
> > and convert results from kunit test cases immediately to results of IGT
> > dynamic sub-subtests by running an igt_dynamic() section for each result
> > as soon as returned by the parser.
> > 
> > Drop igt_ktap_parser() thread and execute igt_dynamic() for each kunit
> > result obtained from igt_ktap_parse() called from the main thread.
> > 
> > Also, drop no longer needed functions from igt_ktap soruces.
> > 
> > v3: Fix ktap structure not freed on lseek error,
> >   - fix initial SIGCHLD handler not restored,
> >   - fix missing handling of potential errors returned by sigaction,
> >   - fix potential race of read() vs. ptherad_kill(), use robust mutex for
> > synchronization with modprobe thread,
> >   - fix potentially illegal use of igt_assert() called outside of
> > dynamic sub-subtest section,
> >   - fix unsupported exit code potentially passed to igt_fail(),
> >   - no need to fail a dynamic sub-subtest on potential KTAP parser error
> > after a valid result from the parser has been processed,
> >   - fix trailing newlines missing from error messages,
> >   - add more debug statements,
> >   - integrate common code around kunit_result_free() into it.
> > v2: Interrupt blocking read() on modprobe failure.
> > 
> > Signed-off-by: Janusz Krzysztofik 
> > Acked-by: Mauro Carvalho Chehab  # v2
> > ---
> >  lib/igt_kmod.c | 261 +++
> >  lib/igt_ktap.c | 568 -
> >  lib/igt_ktap.h |  22 --
> >  3 files changed, 222 insertions(+), 629 deletions(-)
> > 
> > diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
> > index 426ae5b26f..7bca4cdaab 100644
> > --- a/lib/igt_kmod.c
> > +++ b/lib/igt_kmod.c
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright © 2016 Intel Corporation
> > + * Copyright © 2016-2023 Intel Corporation
> >   *
> >   * Permission is hereby granted, free of charge, to any person obtaining a
> >   * copy of this software and associated documentation files (the 
> > "Software"),
> > @@ -26,7 +26,12 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> >  #include 
> > +#include 
> > +
> > +#include "assembler/brw_compat.h"  /* [un]likely() */
> >  
> >  #include "igt_aux.h"
> >  #include "igt_core.h"
> > @@ -748,9 +753,12 @@ void igt_kselftest_get_tests(struct kmod_module *kmod,
> >  }
> >  
> >  struct modprobe_data {
> > +   pthread_t parent;
> > struct kmod_module *kmod;
> > const char *opts;
> > int err;
> > +   pthread_mutex_t lock;
> > +   pthread_t thread;
> >  };
> >  
> >  static void *modprobe_task(void *arg)
> > @@ -759,16 +767,132 @@ static void *modprobe_task(void *arg)
> >  
> > data->err = modprobe(data->kmod, data->opts);
> >  
> > +   if (igt_debug_on(data->err)) {
> > +   int err;
> > +
> > +   while (err = pthread_mutex_trylock(&data->lock),
> > +  err && !igt_debug_on(err != EBUSY))
> > +   igt_debug_on(pthread_kill(data->parent, SIGCHLD));
> 
> I guess you need here an "igt_debug_on_once", as it doesn't make
> sense to have a (potentially) endless loop here printing error
> messages.

Right.  Since we don't have igt_debug_on_once() implemented, I'll open code 
that improvement.

Thanks,
Janusz

> 
> the other changes LGTM.
> 
> > +   } else {
> > +   /* let main thread use mutex to detect modprobe completion */
> > +   igt_debug_on(pthread_mutex_lock(&data->lock));
> > +   }
> > +
> > return NULL;
> >  }
> >  
> > +static void kunit_sigchld_handler(int signal)
> > +{
> > +   return;
> > +}
> > +
> > +static int kunit_kmsg_result_get(struct igt_list_head *results,
> > +struct modprobe_data *modprobe,
> > +int fd, struct igt_ktap_results *ktap)
> > +{
> > +   struct sigaction sigchld = { .sa_handler = kunit_sigchld_handler, },
> > +*saved;
> > +   char record[BUF_LEN + 1], *buf;
> > +   unsigned long taints;
> > +   int ret;
> > +
> > +   do {
> > +   int err;
> > +
> > +   if (igt_debug_on(igt_kernel_tainted(&taints)))
> > +   return -ENOTRECOVERABLE;
> > +
> > +   err = igt_debug_on(sigaction(SIGCHLD, &sigchld, saved));
> > +

Re: [Intel-gfx] [PATCH i-g-t v2 04/11] lib/kunit: Parse KTAP report from the main process thread

2023-10-10 Thread Janusz Krzysztofik 
Hi Kamil,

Thanks for review.

On Tuesday, 10 October 2023 17:59:56 CEST Kamil Konieczny wrote:
> Hi Janusz,
> On 2023-10-09 at 14:27:55 +0200, Janusz Krzysztofik wrote:
> > There was an attempt to parse KTAP reports in the background while a kunit
> > test module is loading.  However, since dynamic sub-subtests can be
> > executed only from the main thread, that attempt was not quite successful,
> > as IGT results from all executed kunit test cases were generated only
> > after loading of kunit test module completed.
> > 
> > Now that the parser maintains its state and we can call it separately for
> > each input line of a KTAP report, it is perfectly possible to call the
> > parser from the main thread while the module is loading in the background,
> > and convert results from kunit test cases immediately to results of IGT
> > dynamic sub-subtests by running an igt_dynamic() section for each result
> > as soon as returned by the parser.
> > 
> > Drop igt_ktap_parser() thread and execute igt_dynamic() for each kunit
> > result obtained from igt_ktap_parse() called from the main thread.
> > 
> > Also, drop no longer needed functions from igt_ktap soruces.
> > 
> > v3: Fix ktap structure not freed on lseek error,
> >   - fix initial SIGCHLD handler not restored,
> >   - fix missing handling of potential errors returned by sigaction,
> >   - fix potential race of read() vs. ptherad_kill(), use robust mutex for
> > synchronization with modprobe thread,
> >   - fix potentially illegal use of igt_assert() called outside of
> > dynamic sub-subtest section,
> >   - fix unsupported exit code potentially passed to igt_fail(),
> >   - no need to fail a dynamic sub-subtest on potential KTAP parser error
> > after a valid result from the parser has been processed,
> >   - fix trailing newlines missing from error messages,
> >   - add more debug statements,
> >   - integrate common code around kunit_result_free() into it.
> > v2: Interrupt blocking read() on modprobe failure.
> > 
> > Signed-off-by: Janusz Krzysztofik 
> > Acked-by: Mauro Carvalho Chehab  # v2
> > ---
> >  lib/igt_kmod.c | 261 +++
> >  lib/igt_ktap.c | 568 -
> >  lib/igt_ktap.h |  22 --
> >  3 files changed, 222 insertions(+), 629 deletions(-)
> > 
> > diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
> > index 426ae5b26f..7bca4cdaab 100644
> > --- a/lib/igt_kmod.c
> > +++ b/lib/igt_kmod.c
> > @@ -1,5 +1,5 @@
> >  /*
> > - * Copyright © 2016 Intel Corporation
> > + * Copyright © 2016-2023 Intel Corporation
> >   *
> >   * Permission is hereby granted, free of charge, to any person obtaining a
> >   * copy of this software and associated documentation files (the 
> > "Software"),
> > @@ -26,7 +26,12 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> >  #include 
> > +#include 
> > +
> > +#include "assembler/brw_compat.h"  /* [un]likely() */
>  ^
> Do we really need this?

I think the correct question is if wee really need [un]likely().  I'm using it 
to document unlikely cases, which is a widely accepted method of documenting 
cases like that, I believe.  Having that clarified, I hope you just tell me if 
you think we need those cases documented, and how, if not that way.

> 
> >  
> >  #include "igt_aux.h"
> >  #include "igt_core.h"
> > @@ -748,9 +753,12 @@ void igt_kselftest_get_tests(struct kmod_module *kmod,
> >  }
> >  
> >  struct modprobe_data {
> > +   pthread_t parent;
> --- 
> Please move it below to other related thread data.
> Also consider a comment why(or for what purpose)
> did you put this here.

No problem to move it to the bottom, if that's important to you, but regarding 
the comment, do you think that the purpose of this field of the structure, 
compared to other fields, is so unclear form review of the code, despite its 
name, that it requires a comment, unlike the other fields?

> 
> > struct kmod_module *kmod;
> > const char *opts;
> > int err;
> > +   pthread_mutex_t lock;
> > +   pthread_t thread;
> >  };
> >  
> >  static void *modprobe_task(void *arg)
> > @@ -759,16 +767,132 @@ static void *modprobe_task(void *arg)
> >  
> > data->err = modprobe(data->kmod, data->opts);
> >  
> > +   if (igt_debug_on(data->err)) {
> > +   int err;
> > +
> > +   while (err = pthread_mutex_trylock(&data->lock),
> > +  err && !igt_debug_on(err != EBUSY))
> > +   igt_debug_on(pthread_kill(data->parent, SIGCHLD));
> > +   } else {
> > +   /* let main thread use mutex to detect modprobe completion */
> > +   igt_debug_on(pthread_mutex_lock(&data->lock));
> > +   }
> > +
> > return NULL;
> >  }
> >  
> > +static void kunit_sigchld_handler(int signal)
> > +{
> > +   return;
> --- ^^^
> Why not removing this? checkpatch complains about return from void.

OK.

> 
> > +}
> > +
> > +static int kunit_kmsg_result_get(struct igt_list_

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Free crtc_state in verify_crtc_state (rev2)

2023-10-10 Thread Patchwork 
== Series Details ==

Series: drm/i915/display: Free crtc_state in verify_crtc_state (rev2)
URL   : https://patchwork.freedesktop.org/series/124811/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13733_full -> Patchwork_124811v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/index.html

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_124811v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@device_reset@unbind-cold-reset-rebind:
- shard-rkl:  NOTRUN -> [SKIP][1] ([i915#7701])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-rkl-1/igt@device_re...@unbind-cold-reset-rebind.html

  * igt@drm_fdinfo@busy-check-all@ccs0:
- shard-mtlp: NOTRUN -> [SKIP][2] ([i915#8414]) +11 other tests skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-mtlp-7/igt@drm_fdinfo@busy-check-...@ccs0.html

  * igt@drm_fdinfo@busy-check-all@vecs1:
- shard-dg2:  NOTRUN -> [SKIP][3] ([i915#8414]) +10 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-dg2-2/igt@drm_fdinfo@busy-check-...@vecs1.html

  * igt@gem_busy@semaphore:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#3936])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-mtlp-2/igt@gem_b...@semaphore.html

  * igt@gem_ccs@block-multicopy-inplace:
- shard-rkl:  NOTRUN -> [SKIP][5] ([i915#3555])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-rkl-1/igt@gem_...@block-multicopy-inplace.html

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [PASS][6] -> [FAIL][7] ([i915#6268])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-tglu-10/igt@gem_ctx_e...@basic-nohangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-tglu-9/igt@gem_ctx_e...@basic-nohangcheck.html
- shard-mtlp: NOTRUN -> [FAIL][8] ([i915#6268])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-mtlp-2/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_ctx_persistence@engines-hang:
- shard-snb:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-snb6/igt@gem_ctx_persiste...@engines-hang.html

  * igt@gem_ctx_sseu@mmap-args:
- shard-dg2:  NOTRUN -> [SKIP][10] ([i915#280]) +1 other test skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-dg2-5/igt@gem_ctx_s...@mmap-args.html

  * igt@gem_eio@hibernate:
- shard-tglu: [PASS][11] -> [ABORT][12] ([i915#7975] / [i915#8213] 
/ [i915#8398])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-tglu-7/igt@gem_...@hibernate.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-tglu-10/igt@gem_...@hibernate.html

  * igt@gem_eio@reset-stress:
- shard-snb:  NOTRUN -> [FAIL][13] ([i915#8898])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-snb6/igt@gem_...@reset-stress.html

  * igt@gem_exec_balancer@sliced:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#4812])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-mtlp-7/igt@gem_exec_balan...@sliced.html

  * igt@gem_exec_fair@basic-flow:
- shard-dg2:  NOTRUN -> [SKIP][15] ([i915#3539] / [i915#4852]) +1 
other test skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-dg2-6/igt@gem_exec_f...@basic-flow.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk:  [PASS][16] -> [FAIL][17] ([i915#2842])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-glk2/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [PASS][18] -> [FAIL][19] ([i915#2842])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-tglu-4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-tglu-2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fence@parallel@bcs0:
- shard-mtlp: [PASS][20] -> [TIMEOUT][21] ([i915#9137])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13733/shard-mtlp-1/igt@gem_exec_fence@paral...@bcs0.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124811v2/shard-mtlp-4/igt@gem_exec_fence@paral...@bcs0.html

  * igt@gem_exec_fence@parallel@rcs0:
- shard-mtlp: [PASS][22] -> [DMESG-FAIL][2

Re: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily force MTL into uncached mode

2023-10-10 Thread Matt Roper 
On Tue, Oct 10, 2023 at 05:42:28PM +0100, Tvrtko Ursulin wrote:
> 
> On 10/10/2023 17:17, Andi Shyti wrote:
> > Hi Matt,
> > 
> > > > > > FIXME: CAT errors are cropping up on MTL.  This removes them,
> > > > > > but the real root cause must still be diagnosed.
> > > > > 
> > > > > Do you have a link to specific IGT test(s) that illustrate the CAT
> > > > > errors so that we can ensure that they now appear fixed in CI?
> > > > 
> > > > this one:
> > > > 
> > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124599v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html
> > > > 
> > > > Andi
> > > 
> > > Wait, now I'm confused.  That's a failure caused by a different patch
> > > series (one that we won't be moving forward with).  The live@hugepages
> > > test is always passing on drm-tip today:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/igt@i915_selftest@l...@hugepages.html
> > 
> > yes, true, but that patch allows us to move forward with the
> > testing and hit the CAT error.
> > 
> > (it was the most reachable link I found :))
> > 
> > > Is there a test that's giving CAT errors on drm-tip itself (even
> > > sporadically) that we can monitor to see the impact of Jonathan's patch
> > > here?
> > 
> > Otherwise this one:
> > 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13667/re-mtlp-3/igt@gem_exec_fe...@parallel.html#dmesg-warnings11
> 
> Parachuting in on a tangent - please do not mix CAT and CT errors. CAT, for 
> me at least, associates with CATastrophic faults reported over CT channel, 
> like GuC page faulting IIRC.
> 
> For CT errors maybe GuC folks can sched some light what they mean.

0x6000 is GUC_ACTION_GUC2HOST_NOTIFY_MEMORY_CAT_ERROR so this actually
is a CAT error, delivered via the CT channel.


Matt

> 
> Regards,
> 
> Tvrtko

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH i-g-t 4/4] tools/intel_gpu_top: Handle narrow terminals more gracefully

2023-10-10 Thread Kamil Konieczny 
Hi Tvrtko,
On 2023-10-10 at 12:07:14 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Instead of asserting just skip trying to print columns when terminal is
> too narrow.
> 
> At the same time fix some type confusion to fix calculations going huge.
> 
> Signed-off-by: Tvrtko Ursulin 
> Closes: https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/issues/143

Did you tested this in screensaver? I mean running intel_gpu_top
in terminal windows under X (Gnome or other) and leaving desktop
unattanded, entering screen saver mode (possible with screen
turned off) and then re-enabling screen?

> ---
>  tools/intel_gpu_top.c | 12 +++-
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 472ce3f13ba9..6d1397cb8214 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -926,7 +926,7 @@ static void free_display_clients(struct igt_drm_clients 
> *clients)
>   free(clients);
>  }
>  
> -static unsigned int n_spaces(const unsigned int n)
> +static int n_spaces(const int n)
- ^^^
Could you make it int at your first patch touching this function?

With or without this suggestion,
Reviewed-by: Kamil Konieczny 

Regards,
Kamil

>  {
>   static const char *spaces[] = {
>   " ",
> @@ -950,7 +950,7 @@ static unsigned int n_spaces(const unsigned int n)
>   "   ",
>  #define MAX_SPACES 19
>   };
> - unsigned int i, r = n;
> + int i, r = n;
>  
>   while (r) {
>   if (r > MAX_SPACES)
> @@ -972,7 +972,8 @@ print_percentage_bar(double percent, double max, int 
> max_len, bool numeric)
>   int bar_len, i, len = max_len - 2;
>   const int w = 8;
>  
> - assert(max_len > 0);
> + if (len < 2) /* For edge lines '|' */
> + return;
>  
>   bar_len = ceil(w * percent * len / max);
>   if (bar_len > w * len)
> @@ -986,6 +987,8 @@ print_percentage_bar(double percent, double max, int 
> max_len, bool numeric)
>   printf("%s", bars[i]);
>  
>   len -= (bar_len + (w - 1)) / w;
> + if (len < 1)
> + return;
>   n_spaces(len);
>  
>   putchar('|');
> @@ -2001,8 +2004,7 @@ print_clients_header(struct igt_drm_clients *clients, 
> int lines,
>4 : clients->max_name_len; /* At least "NAME" 
> */
>  
>   if (output_mode == INTERACTIVE) {
> - unsigned int num_active = 0;
> - int len;
> + int len, num_active = 0;
>  
>   if (lines++ >= con_h)
>   return lines;
> -- 
> 2.39.2
>

Re: [Intel-gfx] [PATCH i-g-t 3/4] tools/intel_gpu_top: Optimise interactive display a bit

2023-10-10 Thread Kamil Konieczny 
Hi Tvrtko,
On 2023-10-10 at 12:07:13 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Padding the percentage bars and table columns with spaces happens quite a
> lot so lets do better than putchar at a time. Have a table of visually
> empty strings and build the required length out of those chunks.
> 
> While at it, also move the percentage bar table into its function scope.
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  tools/intel_gpu_top.c | 38 +-
>  1 file changed, 33 insertions(+), 5 deletions(-)
> 
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index c5abd0c92155..472ce3f13ba9 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -926,14 +926,40 @@ static void free_display_clients(struct igt_drm_clients 
> *clients)
>   free(clients);
>  }
>  
> -static const char *bars[] = { " ", "▏", "▎", "▍", "▌", "▋", "▊", "▉", "█" };
> -
>  static unsigned int n_spaces(const unsigned int n)
>  {
> - unsigned int i;
> + static const char *spaces[] = {
> + " ",
> + "  ",
> + "   ",
> + "",
> + " ",
> + "  ",
> + "   ",
> + "",
> + " ",
> + "  ",
> + "   ",
> + "",
> + " ",
> + "  ",
> + "   ",
> + "",
> + " ",
> + "  ",
> + "   ",
> +#define MAX_SPACES 19

imho better sizeof(spaces)

> + };
> + unsigned int i, r = n;
>  
> - for (i = 0; i < n; i++)
> - putchar(' ');
> + while (r) {
> + if (r > MAX_SPACES)
> + i = MAX_SPACES - 1;
> + else
> + i = r - 1;
> + fputs(spaces[i], stdout);
> + r -= i + 1;
> + }
>  
>   return n;
>  }
> @@ -941,6 +967,8 @@ static unsigned int n_spaces(const unsigned int n)
>  static void
>  print_percentage_bar(double percent, double max, int max_len, bool numeric)
>  {
> + static const char *bars[] =
> + { " ", "▏", "▎", "▍", "▌", "▋", "▊", "▉", "█" };

Please write it in one line or start with '= {' as checkpatch.pl
is complaining here.

Regards,
Kamil

>   int bar_len, i, len = max_len - 2;
>   const int w = 8;
>  
> -- 
> 2.39.2
>

Re: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily force MTL into uncached mode

2023-10-10 Thread Matt Roper 
On Tue, Oct 10, 2023 at 06:17:27PM +0200, Andi Shyti wrote:
> Hi Matt,
> 
> > > > > FIXME: CAT errors are cropping up on MTL.  This removes them,
> > > > > but the real root cause must still be diagnosed.
> > > > 
> > > > Do you have a link to specific IGT test(s) that illustrate the CAT
> > > > errors so that we can ensure that they now appear fixed in CI?
> > > 
> > > this one:
> > > 
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124599v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html
> > > 
> > > Andi
> > 
> > Wait, now I'm confused.  That's a failure caused by a different patch
> > series (one that we won't be moving forward with).  The live@hugepages
> > test is always passing on drm-tip today:
> > https://intel-gfx-ci.01.org/tree/drm-tip/igt@i915_selftest@l...@hugepages.html
> 
> yes, true, but that patch allows us to move forward with the
> testing and hit the CAT error.
> 
> (it was the most reachable link I found :))
> 
> > Is there a test that's giving CAT errors on drm-tip itself (even
> > sporadically) that we can monitor to see the impact of Jonathan's patch
> > here?
> 
> Otherwise this one:
> 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13667/re-mtlp-3/igt@gem_exec_fe...@parallel.html#dmesg-warnings11

Okay, looks like this is a pretty sporadic failure:


https://intel-gfx-ci.01.org/tree/drm-tip/igt@gem_exec_fence@paral...@rcs0.html

so we'll need to monitor this for quite a while to make sure it's truly
gone.  Assuming you've done enough local test cycles to confirm that
this definitely avoids the CAT errors,

Acked-by: Matt Roper 

as a short-term mitigation while we debug further.  We still need to
continue searching for a proper fix and/or drive this through the
hardware team and get them to document this as a new official workaround
for some kind of cache coherency problem.

BTW, it would also be good to have a patch that adds explicit handling
for GuC action 0x6000 (GUC_ACTION_GUC2HOST_NOTIFY_MEMORY_CAT_ERROR) so
that we'll at least have more meaningful error output if/when this is
encountered in the future.


Matt

> 
> Andi

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily force MTL into uncached mode

2023-10-10 Thread Tvrtko Ursulin 



On 10/10/2023 17:17, Andi Shyti wrote:

Hi Matt,


FIXME: CAT errors are cropping up on MTL.  This removes them,
but the real root cause must still be diagnosed.


Do you have a link to specific IGT test(s) that illustrate the CAT
errors so that we can ensure that they now appear fixed in CI?


this one:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124599v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html

Andi


Wait, now I'm confused.  That's a failure caused by a different patch
series (one that we won't be moving forward with).  The live@hugepages
test is always passing on drm-tip today:
https://intel-gfx-ci.01.org/tree/drm-tip/igt@i915_selftest@l...@hugepages.html


yes, true, but that patch allows us to move forward with the
testing and hit the CAT error.

(it was the most reachable link I found :))


Is there a test that's giving CAT errors on drm-tip itself (even
sporadically) that we can monitor to see the impact of Jonathan's patch
here?


Otherwise this one:

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13667/re-mtlp-3/igt@gem_exec_fe...@parallel.html#dmesg-warnings11


Parachuting in on a tangent - please do not mix CAT and CT errors. CAT, for me 
at least, associates with CATastrophic faults reported over CT channel, like 
GuC page faulting IIRC.

For CT errors maybe GuC folks can sched some light what they mean.

Regards,

Tvrtko

Re: [Intel-gfx] [PATCH 00/19] drm/i915: Store DSC DPCD capabilities in the connector

2023-10-10 Thread Ville Syrjälä 
On Fri, Oct 06, 2023 at 04:37:08PM +0300, Imre Deak wrote:
> This patchset moves the DSC DPCD capabilities from the encoder
> (intel_dp) to the connector. This is required since in an MST topology
> each connector has its own version of these capabilities, allowing
> to configure/enable the DSC decompression for each stream separately.
> 
> The changes are needed for a follow-up patchset, fixing the MST DSC
> functionality, making it also possible to enable the BW management on
> MST links. The follow-up changes are based on patches 12-25 in
> 
> https://lore.kernel.org/all/20230914192659.757475-1-imre.d...@intel.com
> 
> Imre Deak (19):
>   drm/i915/dp: Sanitize DPCD revision check in
> intel_dp_get_dsc_sink_cap()
>   drm/i915/dp: Store DSC DPCD capabilities in the connector
>   drm/i915/dp_mst: Set connector DSC capabilities and decompression AUX
>   drm/i915/dp: Use i915/intel connector local variables in
> i915_dsc_fec_support_show()
>   drm/i915/dp: Use connector DSC DPCD in i915_dsc_fec_support_show()
>   drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_max_bpp()
>   drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_fec()
>   drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_dsc()
>   drm/i915/dp: Use connector DSC DPCD in
> intel_dp_dsc_max_sink_compressed_bppx16()
>   drm/i915/dp: Pass connector DSC DPCD to
> drm_dp_dsc_sink_supported_input_bpcs()
>   drm/i915/dp: Pass only the required i915 to
> intel_dp_source_dsc_version_minor()
>   drm/i915/dp: Pass only the required DSC DPCD to
> intel_dp_sink_dsc_version_minor()
>   drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_params()
>   drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_supports_format()
>   drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_get_slice_count()
>   drm/i915/dp: Use connector DSC DPCD in intel_dp_mode_valid()
>   drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_config()
>   drm/i915/dp_mst: Use connector DSC DPCD in
> intel_dp_mst_mode_valid_ctx()
>   drm/i915/dp: Remove unused DSC caps from intel_dp

Looks reasonable to me. The one open question I have is how the DSC/FEC
capabilities get discovered in the MST topology, but I presume that'll
happen in some followup series.

Series is
Reviewed-by: Ville Syrjälä 

> 
>  .../drm/i915/display/intel_display_debugfs.c  |  22 +--
>  .../drm/i915/display/intel_display_types.h|   8 +-
>  drivers/gpu/drm/i915/display/intel_dp.c   | 154 ++
>  drivers/gpu/drm/i915/display/intel_dp.h   |   8 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  35 +++-
>  5 files changed, 136 insertions(+), 91 deletions(-)
> 
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/4] tools/intel_gpu_top: Fix client layout on first sample period

2023-10-10 Thread Kamil Konieczny 
Hi Tvrtko,
On 2023-10-10 at 12:07:12 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> When I moved the client name to be last, I did not account for the fact
> current code skips showing engine utilisation until at least two sampling
> periods have passed. Consequence of this is that client name gets printed
> as the second field and not under the "NAME" column header.
> 
> Fix it by emitting spaces instead of engine utilisation until two samples
> have been collected.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  tools/intel_gpu_top.c | 13 +
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 60fe06917531..c5abd0c92155 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -928,12 +928,14 @@ static void free_display_clients(struct igt_drm_clients 
> *clients)
>  
>  static const char *bars[] = { " ", "▏", "▎", "▍", "▌", "▋", "▊", "▉", "█" };
>  
> -static void n_spaces(const unsigned int n)
> +static unsigned int n_spaces(const unsigned int n)
>  {
>   unsigned int i;
>  
>   for (i = 0; i < n; i++)
>   putchar(' ');
> +
> + return n;
>  }
>  
>  static void
> @@ -2043,14 +2045,17 @@ print_client(struct igt_drm_client *c, struct engines 
> *engines, double t, int li
>  
>   len = printf("%*s ", clients->max_pid_len, c->pid_str);
>  
> - for (i = 0;
> -  c->samples > 1 && i <= iclients->classes.max_engine_id;
> -  i++) {
> + for (i = 0; i <= iclients->classes.max_engine_id; i++) {
>   double pct, max;
>  
>   if (!iclients->classes.capacity[i])
>   continue;
>  
> + if (c->samples < 2) {
> + len += n_spaces(*class_w);
> + continue;
> + }
> +
>   pct = (double)c->val[i] / period_us / 1e3 * 100;
>  
>   /*
> -- 
> 2.39.2
>

Re: [Intel-gfx] [PATCH i-g-t 1/4] tools/intel_gpu_top: Fix clients header width when no clients

2023-10-10 Thread Kamil Konieczny 
Hi Tvrtko,
On 2023-10-10 at 12:07:11 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Recent refactoring broke the clients header in cases when there are no
> clients displayed. To fix it we need to account the width of the "NAME"
> label.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  tools/intel_gpu_top.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 10601e66b18e..60fe06917531 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -1967,6 +1967,8 @@ print_clients_header(struct igt_drm_clients *clients, 
> int lines,
>int con_w, int con_h, int *class_w)
>  {
>   struct intel_clients *iclients = clients->private_data;
> + const int max_name_len = clients->max_name_len < 4 ?
> +  4 : clients->max_name_len; /* At least "NAME" 
> */
>  
>   if (output_mode == INTERACTIVE) {
>   unsigned int num_active = 0;
> @@ -1990,9 +1992,8 @@ print_clients_header(struct igt_drm_clients *clients, 
> int lines,
>   num_active++;
>   }
>  
> - *class_w = width =
> - (con_w - len - clients->max_name_len - 1) /
> - num_active;
> + *class_w = width = (con_w - len - max_name_len - 1) /
> +num_active;
>  
>   for (i = 0; i <= iclients->classes.max_engine_id; i++) {
>   const char *name = iclients->classes.names[i];
> -- 
> 2.39.2
>

Re: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily force MTL into uncached mode

2023-10-10 Thread Andi Shyti 
Hi Matt,

> > > > FIXME: CAT errors are cropping up on MTL.  This removes them,
> > > > but the real root cause must still be diagnosed.
> > > 
> > > Do you have a link to specific IGT test(s) that illustrate the CAT
> > > errors so that we can ensure that they now appear fixed in CI?
> > 
> > this one:
> > 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124599v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html
> > 
> > Andi
> 
> Wait, now I'm confused.  That's a failure caused by a different patch
> series (one that we won't be moving forward with).  The live@hugepages
> test is always passing on drm-tip today:
> https://intel-gfx-ci.01.org/tree/drm-tip/igt@i915_selftest@l...@hugepages.html

yes, true, but that patch allows us to move forward with the
testing and hit the CAT error.

(it was the most reachable link I found :))

> Is there a test that's giving CAT errors on drm-tip itself (even
> sporadically) that we can monitor to see the impact of Jonathan's patch
> here?

Otherwise this one:

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13667/re-mtlp-3/igt@gem_exec_fe...@parallel.html#dmesg-warnings11

Andi

Re: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily force MTL into uncached mode

2023-10-10 Thread Matt Roper 
On Tue, Oct 10, 2023 at 05:11:54PM +0200, Andi Shyti wrote:
> Hi Matt,
> 
> On Tue, Oct 10, 2023 at 06:58:27AM -0700, Matt Roper wrote:
> > On Mon, Oct 09, 2023 at 04:38:56PM -0700, Jonathan Cavitt wrote:
> > > FIXME: CAT errors are cropping up on MTL.  This removes them,
> > > but the real root cause must still be diagnosed.
> > 
> > Do you have a link to specific IGT test(s) that illustrate the CAT
> > errors so that we can ensure that they now appear fixed in CI?
> 
> this one:
> 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124599v1/bat-mtlp-8/igt@i915_selftest@l...@hugepages.html
> 
> Andi

Wait, now I'm confused.  That's a failure caused by a different patch
series (one that we won't be moving forward with).  The live@hugepages
test is always passing on drm-tip today:
https://intel-gfx-ci.01.org/tree/drm-tip/igt@i915_selftest@l...@hugepages.html

Is there a test that's giving CAT errors on drm-tip itself (even
sporadically) that we can monitor to see the impact of Jonathan's patch
here?


Matt

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH i-g-t v2 04/11] lib/kunit: Parse KTAP report from the main process thread

2023-10-10 Thread Kamil Konieczny 
Hi Janusz,
On 2023-10-09 at 14:27:55 +0200, Janusz Krzysztofik wrote:
> There was an attempt to parse KTAP reports in the background while a kunit
> test module is loading.  However, since dynamic sub-subtests can be
> executed only from the main thread, that attempt was not quite successful,
> as IGT results from all executed kunit test cases were generated only
> after loading of kunit test module completed.
> 
> Now that the parser maintains its state and we can call it separately for
> each input line of a KTAP report, it is perfectly possible to call the
> parser from the main thread while the module is loading in the background,
> and convert results from kunit test cases immediately to results of IGT
> dynamic sub-subtests by running an igt_dynamic() section for each result
> as soon as returned by the parser.
> 
> Drop igt_ktap_parser() thread and execute igt_dynamic() for each kunit
> result obtained from igt_ktap_parse() called from the main thread.
> 
> Also, drop no longer needed functions from igt_ktap soruces.
> 
> v3: Fix ktap structure not freed on lseek error,
>   - fix initial SIGCHLD handler not restored,
>   - fix missing handling of potential errors returned by sigaction,
>   - fix potential race of read() vs. ptherad_kill(), use robust mutex for
> synchronization with modprobe thread,
>   - fix potentially illegal use of igt_assert() called outside of
> dynamic sub-subtest section,
>   - fix unsupported exit code potentially passed to igt_fail(),
>   - no need to fail a dynamic sub-subtest on potential KTAP parser error
> after a valid result from the parser has been processed,
>   - fix trailing newlines missing from error messages,
>   - add more debug statements,
>   - integrate common code around kunit_result_free() into it.
> v2: Interrupt blocking read() on modprobe failure.
> 
> Signed-off-by: Janusz Krzysztofik 
> Acked-by: Mauro Carvalho Chehab  # v2
> ---
>  lib/igt_kmod.c | 261 +++
>  lib/igt_ktap.c | 568 -
>  lib/igt_ktap.h |  22 --
>  3 files changed, 222 insertions(+), 629 deletions(-)
> 
> diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
> index 426ae5b26f..7bca4cdaab 100644
> --- a/lib/igt_kmod.c
> +++ b/lib/igt_kmod.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright © 2016 Intel Corporation
> + * Copyright © 2016-2023 Intel Corporation
>   *
>   * Permission is hereby granted, free of charge, to any person obtaining a
>   * copy of this software and associated documentation files (the "Software"),
> @@ -26,7 +26,12 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  #include 
> +#include 
> +
> +#include "assembler/brw_compat.h"/* [un]likely() */
 ^
Do we really need this?

>  
>  #include "igt_aux.h"
>  #include "igt_core.h"
> @@ -748,9 +753,12 @@ void igt_kselftest_get_tests(struct kmod_module *kmod,
>  }
>  
>  struct modprobe_data {
> + pthread_t parent;
--- 
Please move it below to other related thread data.
Also consider a comment why(or for what purpose)
did you put this here.

>   struct kmod_module *kmod;
>   const char *opts;
>   int err;
> + pthread_mutex_t lock;
> + pthread_t thread;
>  };
>  
>  static void *modprobe_task(void *arg)
> @@ -759,16 +767,132 @@ static void *modprobe_task(void *arg)
>  
>   data->err = modprobe(data->kmod, data->opts);
>  
> + if (igt_debug_on(data->err)) {
> + int err;
> +
> + while (err = pthread_mutex_trylock(&data->lock),
> +err && !igt_debug_on(err != EBUSY))
> + igt_debug_on(pthread_kill(data->parent, SIGCHLD));
> + } else {
> + /* let main thread use mutex to detect modprobe completion */
> + igt_debug_on(pthread_mutex_lock(&data->lock));
> + }
> +
>   return NULL;
>  }
>  
> +static void kunit_sigchld_handler(int signal)
> +{
> + return;
--- ^^^
Why not removing this? checkpatch complains about return from void.

> +}
> +
> +static int kunit_kmsg_result_get(struct igt_list_head *results,
> +  struct modprobe_data *modprobe,
> +  int fd, struct igt_ktap_results *ktap)
> +{
> + struct sigaction sigchld = { .sa_handler = kunit_sigchld_handler, },
> +  *saved;
> + char record[BUF_LEN + 1], *buf;
> + unsigned long taints;
> + int ret;
> +
> + do {
> + int err;
> +
> + if (igt_debug_on(igt_kernel_tainted(&taints)))
> + return -ENOTRECOVERABLE;
> +
> + err = igt_debug_on(sigaction(SIGCHLD, &sigchld, saved));
> + if (err == -1)
> + return -errno;
> + else if (unlikely(err))
> + return err;
> +
> + err = pthread_mutex_lock(&modprobe->lock);
> + switch (err) {
> + case EOWNERDEAD:
> + /* leave the mut

Re: [Intel-gfx] [PATCH 1/2] drm/i915: drop -Wall and related disables from cflags as redundant

2023-10-10 Thread Nick Desaulniers 
On Tue, Oct 10, 2023 at 1:50 AM Jani Nikula  wrote:
>
> On Tue, 10 Oct 2023, Jani Nikula  wrote:
> > On Mon, 09 Oct 2023, Nathan Chancellor  wrote:
> >> On Sun, Oct 08, 2023 at 12:28:46AM +0900, Masahiro Yamada wrote:
> >>> On Fri, Oct 6, 2023 at 9:35 PM Jani Nikula  wrote:
> >>> >
> >>> > The kernel top level Makefile, and recently scripts/Makefile.extrawarn,
> >>> > have included -Wall, and the disables -Wno-format-security and
> >>> > $(call cc-disable-warning,frame-address,) for a very long time. They're
> >>> > redundant in our local subdir-ccflags-y and can be dropped.
> >>> >
> >>> > Cc: Arnd Bergmann 
> >>> > Cc: Nick Desaulniers 
> >>> > Cc: Nathan Chancellor 
> >>> > Cc: Masahiro Yamada 
> >>> > Signed-off-by: Jani Nikula 
> >>>
> >>>
> >>> I made a similar suggestion in the past
> >>> https://lore.kernel.org/dri-devel/20190515043753.9853-1-yamada.masah...@socionext.com/
> >>>
> >>> So, I am glad that Intel has decided to de-duplicate the flags.
> >>>
> >>>
> >>>
> >>> I think you can drop more flags.
> >>>
> >>> For example,
> >>>
> >>>  subdir-ccflags-y += -Wno-sign-compare
> >>>
> >>>
> >>> It is set by scripts/Makefile.extrawarn
> >>> unless W=3 is passed.
> >>>
> >>>
> >>> If W=3 is set by a user, -Wsign-compare should be warned
> >>> as it is the user's request.
> >>>
> >>>
> >>> drivers/gpu/drm/i915/Makefile negates W=3.
> >>> There is no good reason to do so.
> >>>
> >>>
> >>> Same applied to
> >>>
> >>>
> >>> subdir-ccflags-y += -Wno-shift-negative-value
> >>
> >> As I point out in my review of the second patch [1], I am not sure these
> >> should be dropped because -Wextra turns these warnings back on, at least
> >> for clang according to this build report [2] and my own testing, so they
> >> need to be disabled again.
> >
> > Yeah. The focus is on enabling W=1 warnings by default for i915. I get
> > that the disables we have to add to achieve that also disable some W=2
> > and W=3 warnings. But taking all of that into account requires
> > duplicating even more of Makefile.extrawarn (checking for warning
> > levels, maintaining parity with the different levels, etc.).
> >
> > I guess we could check if KBUILD_EXTRA_WARN does not have any of 1, 2,
> > or 3, but very few places outside of the build system look at
> > KBUILD_EXTRA_WARN, so feels wrong.
>
> This is the simplest I could think of:
>
> # The following turn off the warnings enabled by -Wextra
> ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
> KBUILD_CFLAGS += -Wno-missing-field-initializers
> KBUILD_CFLAGS += -Wno-type-limits
> KBUILD_CFLAGS += -Wno-shift-negative-value
> endif
> ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)
> KBUILD_CFLAGS += -Wno-sign-compare
> endif
>
> Masahiro, I'd like to get your feedback on which to choose,
> unconditionally silencing the W=2/W=3 warnings for i915, or looking at
> KBUILD_EXTRA_WARN.

KBUILD_EXTRA_WARN looks better to me; otherwise they would be hidden
forever (or nearly).  Suffer some duplication, w/e.

-- 
Thanks,
~Nick Desaulniers

Re: [Intel-gfx] [PATCH v10 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

2023-10-10 Thread Andi Shyti 
Hi Jonathan,

On Tue, Oct 10, 2023 at 08:02:37AM -0700, Jonathan Cavitt wrote:
> Implement GuC-based TLB invalidations and use them on MTL.

I have to admit that I'm a bit biased on this series. Given this
premise, you can add

Reviewed-by: Andi Shyti  

to all the patches.

Nevertheless to get this merged we still an need ack/r-b from a
third party, like Tvrtko and/or John and/or Matt.

Thanks,
Andi

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