Re: [Intel-gfx] [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support for panel replay

[Hogander, Jouni]

On Fri, 2023-11-03 at 06:10 +, Manna, Animesh wrote:
> 
> 
> > -Original Message-
> > From: Hogander, Jouni 
> > Sent: Thursday, November 2, 2023 1:08 PM
> > To: Manna, Animesh ; intel-
> > g...@lists.freedesktop.org
> > Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> > ; Nikula, Jani 
> > Subject: Re: [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support
> > for
> > panel replay
> > 
> > On Wed, 2023-10-11 at 16:39 +0530, Animesh Manna wrote:
> > > Add debugfs support which will print source and sink status per
> > > connector basis.
> > 
> > Sorry for late review. Noticed only by now that you have added this
> > patch
> > into you set.
> 
> Added from v5.
> 
> > 
> > Can you please describe in commit message how you see the output of
> > debugfs interface will look like after your changes?
> 
> Sure.
> 
> > 
> > > 
> > > v1: Initial version. [rb-ed by Arun]
> > > v2: Added check for DP 2.0 and connector type in
> > > connector_debugfs_add().
> > > 
> > > Cc: Jouni Högander 
> > > Cc: Arun R Murthy 
> > > Cc: Jani Nikula 
> > > Signed-off-by: Animesh Manna 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 136
> > > +
> > > --
> > >  1 file changed, 102 insertions(+), 34 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 80de831c2f60..399fc0a8e636 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -2823,6 +2823,25 @@ static int
> > > psr_get_status_and_error_status(struct intel_dp *intel_dp,
> > > return 0;
> > >  }
> > > 
> > > +static int panel_replay_get_status_and_error_status(struct
> > > intel_dp
> > > *intel_dp,
> > > +   u8 *status,
> > > u8
> > > *error_status)
> > > +{
> > > +   struct drm_dp_aux *aux = &intel_dp->aux;
> > > +   int ret;
> > > +
> > > +   ret = drm_dp_dpcd_readb(aux,
> > > DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS, status);
> > > +   if (ret != 1)
> > > +   return ret;
> > > +
> > > +   ret = drm_dp_dpcd_readb(aux,
> > > DP_PANEL_REPLAY_ERROR_STATUS,
> > > error_status);
> > > +   if (ret != 1)
> > > +   return ret;
> > > +
> > > +   *status = *status & DP_PSR_SINK_STATE_MASK;
> > > +
> > > +   return 0;
> > > +}
> > > +
> > 
> > I think you should modify  psr_get_status_and_error_status instead
> > of
> > duplicating most of it.
> 
> DPCD addresses are different for panel replay, I did not get the need
> of it. 

I would like to see:

unsigned int offset = intel_dp->psr.panel_replay_enabled ?
DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS;

ret = drm_dp_dpcd_readb(aux, offset, status);

rather than duplicating it.

>  
> > 
> > >  static void psr_alpm_check(struct intel_dp *intel_dp)
> > >  {
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > @@
> > > -3035,7 +3054,7 @@ psr_source_status(struct intel_dp *intel_dp,
> > > struct
> > > seq_file *m)
> > > status = live_status[status_val];
> > > }
> > > 
> > > -   seq_printf(m, "Source PSR status: %s [0x%08x]\n", status,
> > > val);
> > > +   seq_printf(m, "Source PSR/PanelReplay status: %s
> > > [0x%08x]\n",
> > > status, val);
> > >  }
> > > 
> > >  static int intel_psr_status(struct seq_file *m, struct intel_dp
> > > *intel_dp)
> > > @@ -3048,18 +3067,23 @@ static int intel_psr_status(struct
> > > seq_file
> > > *m, struct intel_dp *intel_dp)
> > > bool enabled;
> > > u32 val;
> > > 
> > > -   seq_printf(m, "Sink support: %s", str_yes_no(psr-
> > > > sink_support));
> > > -   if (psr->sink_support)
> > > +   seq_printf(m, "Sink support: PSR = %s, Panel Replay =
> > > %s",
> > > +  str_yes_no(psr->sink_support),
> > > +  str_yes_no(psr->sink_panel_replay_support));
> > > +
> > > +   if (psr->sink_support || psr->sink_panel_replay_support)
> > > seq_printf(m, " [0x%02x]", intel_dp-
> > > >psr_dpcd[0]);
> > > seq_puts(m, "\n");
> > > 
> > > -   if (!psr->sink_support)
> > > +   if (!(psr->sink_support || psr-
> > > >sink_panel_replay_support))
> > > return 0;
> > > 
> > > wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> > > mutex_lock(&psr->lock);
> > > 
> > > -   if (psr->enabled)
> > > +   if (psr->panel_replay_enabled)
> > > +   status = "Panel Replay Enabled";
> > > +   else if (psr->enabled)
> > > status = psr->psr2_enabled ? "PSR2 enabled" :
> > > "PSR1
> > > enabled";
> > > else
> > > status = "disabled";
> > > @@ -3072,14 +3096,17 @@ static int intel_psr_status(struct
> > > seq_file
> > > *m, struct intel_dp *intel_dp)
> > > goto unlock;
> > > }
> > > 
> > > -   if (psr->psr2_enabled) {
> > > +   if (psr->panel

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gt: Temporarily disable CPU caching into DMA for MTL

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Temporarily disable CPU caching into DMA for MTL
URL   : https://patchwork.freedesktop.org/series/125926/
State : warning

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/125926/revisions/1/mbox/ not 
found

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Temporarily disable CPU caching into DMA for MTL

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Temporarily disable CPU caching into DMA for MTL
URL   : https://patchwork.freedesktop.org/series/125926/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125926v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/index.html

Participating hosts (37 -> 37)
--

  Additional (3): bat-kbl-2 bat-dg2-9 fi-bsw-n3050 
  Missing(3): fi-kbl-soraka bat-adls-5 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_125926v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-hsw-4770:[FAIL][1] ([i915#8293]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1849])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-kbl-2/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s0@lmem0:
- bat-dg2-9:  NOTRUN -> [INCOMPLETE][4] ([i915#9275])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][5] ([fdo#109271]) +39 other tests 
skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050:   NOTRUN -> [SKIP][6] ([fdo#109271]) +18 other tests 
skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#4083])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][11] ([i915#9527])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-apl-guc: [PASS][12] -> [INCOMPLETE][13] ([i915#4528])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-apl-guc/igt@i915_susp...@basic-s2idle-without-i915.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/fi-apl-guc/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([i915#5190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#5190])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#4215] / [i915#5190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#4212]) +6 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#4212] / [i915#5608])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125926v1/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_forc

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp_mst: Disable DSC on ICL+ MST outputs (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp_mst: Disable DSC on ICL+ MST outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/125895/
State : warning

== Summary ==

Error: dim checkpatch failed
4e8024b4a423 drm/i915/dp_mst: Disable DSC on ICL+ MST outputs
-:19: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line 
(possible unwrapped commit description?)
#19: 
[1] https://lore.kernel.org/all/20231030155843.2251023-1-imre.d...@intel.com

total: 0 errors, 1 warnings, 0 checks, 34 lines checked

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp_mst: Disable DSC on ICL+ MST outputs (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp_mst: Disable DSC on ICL+ MST outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/125895/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125895v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_125895v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125895v2, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/index.html

Participating hosts (37 -> 37)
--

  Additional (4): bat-dg2-8 bat-kbl-2 bat-dg2-9 fi-bsw-n3050 
  Missing(4): fi-kbl-soraka bat-adls-5 fi-snb-2520m fi-pnv-d510 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_125895v2:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem_contexts:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/fi-hsw-4770/igt@i915_selftest@live@gem_contexts.html

  
Known issues


  Here are the changes found in Patchwork_125895v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-bsw-n3050:   NOTRUN -> [FAIL][2] ([i915#8293])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/fi-bsw-n3050/boot.html

  
 Possible fixes 

  * boot:
- fi-hsw-4770:[FAIL][3] ([i915#8293]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1849])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-kbl-2/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3:  [PASS][6] -> [INCOMPLETE][7] ([i915#9275])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][8] ([fdo#109271]) +39 other tests 
skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4083])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-dg2-9/igt@gem_m...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-dg2-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-dg2-9/igt@gem_mmap_...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-dg2-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-8:  NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_module_load@reload:
- fi-apl-guc: [PASS][15] -> [DMESG-WARN][16] ([i915#180] / 
[i915#1982] / [i915#7634] / [i915#8585])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-apl-guc/igt@i915_module_l...@reload.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/fi-apl-guc/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@module-reload:
- fi-apl-guc: [PASS][17] -> [DMESG-WARN][18] ([i915#180] / 
[i915#7634] / [i915#8585]) +2 other tests dmesg-warn
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-apl-guc/igt@i915_pm_...@module-reload.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/fi-apl-guc/igt@i915_pm_...@module-reload.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#6621])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v2/bat-dg2-9/igt@i915_pm_...@basic-api.html
- bat-dg2

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/xe2lpd: choose between PSR2 and FBC

[Patchwork]

== Series Details ==

Series: drm/i915/xe2lpd: choose between PSR2 and FBC
URL   : https://patchwork.freedesktop.org/series/125932/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/includ

Re: [Intel-gfx] [PATCH v2] drm/i915: Fix potential spectre vulnerability

[Tvrtko Ursulin]

On 03/11/2023 06:56, Krzysztof Kozlowski wrote:

On 03/11/2023 03:32, Kunwu Chan wrote:

Fix smatch warning:
drivers/gpu/drm/i915/gem/i915_gem_context.c:847 set_proto_ctx_sseu()
warn: potential spectre issue 'pc->user_engines' [r] (local cap)

Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create 
parameters (v5)")
Cc:  # v5.15+
Signed-off-by: Kunwu Chan 
Suggested-by: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin 


Where did you receive this tag? There is nothing under link below.

Link: https://lore.kernel.org/all/20231102101642.52988-1-chen...@kylinos.cn


It is fine, I gave the conditional r-b in 
https://lore.kernel.org/all/d300506c-ab82-4cc1-b750-61e54ec2a...@linux.intel.com/.


Suggested-by I did not and it is not true so I can drop it while applying.

Regards,

Tvrtko

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d is enabled

[Tvrtko Ursulin]

On 02/11/2023 22:14, Sripada, Radhakrishna wrote:

Hi Tvrtko,


-Original Message-
From: Tvrtko Ursulin 
Sent: Thursday, November 2, 2023 10:41 AM
To: Hajda, Andrzej ; Sripada, Radhakrishna
; intel-gfx@lists.freedesktop.org
Cc: Chris Wilson 
Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d is
enabled


On 02/11/2023 16:58, Andrzej Hajda wrote:

On 02.11.2023 17:06, Radhakrishna Sripada wrote:

Experiments were conducted with different multipliers to VTD_GUARD macro
with multiplier of 185 we were observing occasional pipe faults when
running kms_cursor_legacy --run-subtest single-bo

There could possibly be an underlying issue that is being
investigated, for
now bump the guard pages for MTL.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2017
Cc: Gustavo Sousa 
Cc: Chris Wilson 
Signed-off-by: Radhakrishna Sripada 
---
   drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
   1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 3770828f2eaf..b65f84c6bb3f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -456,6 +456,9 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
   if (intel_scanout_needs_vtd_wa(i915)) {
   unsigned int guard = VTD_GUARD;
+    if (IS_METEORLAKE(i915))
+    guard *= 200;
+


200 * VTD_GUARD = 200 * 168 * 4K = 131MB

Looks insanely high, 131MB for padding, if this is before and after it
becomes even 262MB of wasted address per plane. Just signalling, I do
not know if this actually hurts.


Yeah this feels crazy. There must be some other explanation which is
getting hidden by the crazy amount of padding so I'd rather we figured
it out.

With 262MiB per fb how many fit in GGTT before eviction hits? N screens
with double/triple buffering?


I believe with this method we will have to limit the no of frame buffers in the 
system. One alternative
that worked is to do a proper clear range for the ggtt instead of doing a nop. 
Although it adds marginal
time during suspend/resume/boot it does not add restrictions to the no of fb's 
that can be used.


And if we remember the guard pages replaced clearing to scratch, to 
improve suspend resume times, exactly for improving user experience. :(


Luckily there is time to fix this properly on MTL one way or the other. 
Is it just kms_cursor_legacy --run-subtest single-bo that is affected?


Regards,

Tvrtko




Regards,

Tvrtko

P.S. Where did the 185 from the commit message come from?

185 came from experiment to increase the guard size. It is not a standard 
number.

Regards,
Radhakrishna(RK) Sripada

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/xe2lpd: choose between PSR2 and FBC

[Patchwork]

== Series Details ==

Series: drm/i915/xe2lpd: choose between PSR2 and FBC
URL   : https://patchwork.freedesktop.org/series/125932/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125932v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_125932v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125932v1, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/index.html

Participating hosts (37 -> 36)
--

  Additional (3): bat-kbl-2 bat-dg2-9 fi-bsw-n3050 
  Missing(4): fi-kbl-soraka bat-dg2-11 bat-adls-5 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_125932v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@vma:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/fi-hsw-4770/igt@i915_selftest@l...@vma.html

  
Known issues


  Here are the changes found in Patchwork_125932v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-hsw-4770:[FAIL][2] ([i915#8293]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1849])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-kbl-2/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-9:  NOTRUN -> [INCOMPLETE][5] ([i915#9275])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600:   [PASS][6] -> [FAIL][7] ([fdo#103375])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][8] ([fdo#109271]) +39 other tests 
skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050:   NOTRUN -> [SKIP][9] ([fdo#109271]) +18 other tests 
skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([i915#5190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#5190])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#4215] / [i915#5190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#4212]) +6 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125932v1/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#4212] / [i915#5608])

Re: [Intel-gfx] [PATCH v3] drm/i915: handle uncore spinlock when not available

[Coelho, Luciano]

On Fri, 2023-11-03 at 03:31 +, Vivi, Rodrigo wrote:
> > > 
> > > Any other suggestions?
> > 
> > I think it will boil down to the reason uncore lock is held over
> > the 
> > respective sections ie. the comment in i915_get_crtc_scanoutpos.
> > 
> > If it is timing sensitive to the extent irq off was needed it may
> > apply 
> > to Xe as well. Likewise the need to use mmio helpers which rely on
> > the 
> > uncore lock already held. Question of whether there is conceptual 
> > commonality, will probably drive the best name, or the best
> > approach
> > in 
> > general.
> 
> yeap, this is how I'm seeing this. If i915-display needs this global
> lock around mmio operations, then we wound need to add it to the
> xe_mmio as well and then solve the name, etc.
> 
> However, I don't believe that other users of the mmio would need
> this lock. So I believe the right thing to do is to create a i915-
> display only spin_lock, around the intel_de_mmio calls and here.
> 
> With this we entirely kill the dependency on someone-else's lock
> and have something that is entirely inside display code so it
> doesn't need to be ported to one or another driver core components.

Right, I agree too.

My patch was just trying to address the quick hack made for Xe, not the
actual implementation in Xe's side.  But it makes sense to implement
this new lock internally in the display so there are no dependencies or
wrappers needed.

I'll respin.

--
Cheers,
Luca.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/xe2lpd: alternate WA for underruns with PSR2 and FBC

[Patchwork]

== Series Details ==

Series: drm/i915/xe2lpd: alternate WA for underruns with PSR2 and FBC
URL   : https://patchwork.freedesktop.org/series/125934/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125934v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/index.html

Participating hosts (37 -> 35)
--

  Additional (3): bat-kbl-2 bat-adlp-6 fi-bsw-n3050 
  Missing(5): fi-kbl-soraka bat-adls-5 bat-dg1-5 fi-snb-2520m bat-dg2-11 

Known issues


  Here are the changes found in Patchwork_125934v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-bsw-n3050:   NOTRUN -> [FAIL][1] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/fi-bsw-n3050/boot.html

  
 Possible fixes 

  * boot:
- fi-hsw-4770:[FAIL][2] ([i915#8293]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-adlp-6: NOTRUN -> [SKIP][4] ([i915#9318])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/bat-adlp-6/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1849])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/bat-kbl-2/igt@fb...@info.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][6] ([fdo#109271]) +39 other tests 
skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-6: NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/bat-adlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][8] ([i915#9527])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#5190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adlp-6: NOTRUN -> [SKIP][10] ([i915#4103] / [i915#5608]) +1 
other test skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/bat-adlp-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-adlp-6: NOTRUN -> [SKIP][11] ([i915#3555] / [i915#3840])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/bat-adlp-6/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-6: NOTRUN -> [SKIP][12] ([fdo#109285])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/bat-adlp-6/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271]) +12 other tests 
skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-vga-1.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3 
other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@dmabuf@all-tests@dma_fence:
- fi-pnv-d510:[FAIL][15] -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-pnv-d510/igt@dmabuf@all-tests@dma_fence.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/fi-pnv-d510/igt@dmabuf@all-tests@dma_fence.html

  * igt@dmabuf@all-tests@sanitycheck:
- fi-pnv-d510:[ABORT][17] -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-pnv-d510/igt@dmabuf@all-te...@sanitycheck.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/fi-pnv-d510/igt@dmabuf@all-te...@sanitycheck.html

  
 Warnings 

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: [ABORT][19] ([i915#7978] / [i915#8668]) -> 
[INCOMPLETE][20] ([i915#7443])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125934v1/bat-rpls

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Print SSEU information of all GTs for debugfs

[Jani Nikula]

On Fri, 03 Nov 2023, Gareth Yu  wrote:
> Print another SSEU information addition to the first one.
>
> Cc : Tejas Upadhyay 
> Cc : Matt Roper 
> Cc : Ville Syrjälä 

Superfluous space between Cc and :.

> Signed-off-by: Gareth Yu 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c   | 13 ++---
>  drivers/gpu/drm/i915/i915_gpu_error.c |  6 +-
>  2 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index e9b79c2c37d8..b5914a2c0597 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -63,13 +63,16 @@ static int i915_capabilities(struct seq_file *m, void 
> *data)
>  {
>   struct drm_i915_private *i915 = node_to_i915(m->private);
>   struct drm_printer p = drm_seq_file_printer(m);
> + struct intel_gt *gt;
> + unsigned int i;

Please just use plain int. Ditto below.

BR,
Jani.

>  
>   seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
>  
>   intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p);
>   intel_display_device_info_print(DISPLAY_INFO(i915), 
> DISPLAY_RUNTIME_INFO(i915), &p);
>   i915_print_iommu_status(i915, &p);
> - intel_gt_info_print(&to_gt(i915)->info, &p);
> + for_each_gt(gt, i915, i)
> + intel_gt_info_print(>->info, &p);
>   intel_driver_caps_print(&i915->caps, &p);
>  
>   kernel_param_lock(THIS_MODULE);
> @@ -783,9 +786,13 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
>  static int i915_sseu_status(struct seq_file *m, void *unused)
>  {
>   struct drm_i915_private *i915 = node_to_i915(m->private);
> - struct intel_gt *gt = to_gt(i915);
> + struct intel_gt *gt;
> + unsigned int i;
> +
> + for_each_gt(gt, i915, i)
> + intel_sseu_status(m, gt);
>  
> - return intel_sseu_status(m, gt);
> + return 0;
>  }
>  
>  static int i915_forcewake_open(struct inode *inode, struct file *file)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index b4e31e59c799..2adc317af944 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -722,9 +722,13 @@ static void err_print_gt_info(struct 
> drm_i915_error_state_buf *m,
> struct intel_gt_coredump *gt)
>  {
>   struct drm_printer p = i915_error_printer(m);
> + struct drm_i915_private *i915 = gt->_gt->i915;
> + struct intel_gt *gt_n;
> + unsigned int n;
>  
>   intel_gt_info_print(>->info, &p);
> - intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p);
> + for_each_gt(gt_n, i915, n)
> + intel_sseu_print_topology(gt_n->i915, >_n->info.sseu, &p);
>  }
>  
>  static void err_print_gt_display(struct drm_i915_error_state_buf *m,

-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH v1 1/1] drm/i915/xe2lpd: alternate WA for underruns with PSR2 and FBC

[Jani Nikula]

On Fri, 03 Nov 2023, Vinod Govindapillai  wrote:
> Implement the alternate WA for the underruns when both PSR2
> and FBC is enabled.

But we don't enable FBC when PSR2 is enabled, for display 12+.

See intel_fbc.c line 1200 or so.

BR,
Jani.


>
> Signed-off-by: Vinod Govindapillai 
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index bde12fe62275..b9cd92a997cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
>  static void ivb_fbc_activate(struct intel_fbc *fbc)
>  {
>   struct drm_i915_private *i915 = fbc->i915;
> + u32 dpfc_ctl;
>  
>   if (DISPLAY_VER(i915) >= 10)
>   glk_fbc_program_cfb_stride(fbc);
> @@ -617,8 +618,17 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
>   if (intel_gt_support_legacy_fencing(to_gt(i915)))
>   snb_fbc_program_fence(fbc);
>  
> + /*
> +  * Alternate WA for HW bug with PSR2 + FBC.
> +  * 1.Write FBC_CTL with Plane binding set correctly with FBC enable = 0
> +  * 2.Write FBC_CTL with Plane binding set correctly with FBC enable = 1
> +  */
> + dpfc_ctl = ivb_dpfc_ctl(fbc);
> + if (DISPLAY_VER(i915) >= 20)
> + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> +
>   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> -DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
> +DPFC_CTL_EN | dpfc_ctl);
>  }
>  
>  static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)

-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH v7 1/6] drm/panelreplay: dpcd register definition for panelreplay

[Jani Nikula]

On Wed, 11 Oct 2023, Animesh Manna  wrote:
> Add DPCD register definition for discovering, enabling and
> checking status of panel replay of the sink.
>
> Cc: Jouni Högander 
> Cc: Arun R Murthy 
> Cc: Jani Nikula 
> Reviewed-by: Arun R Murthy 
> Signed-off-by: Animesh Manna 

Maarten, Maxime, Thomas -

Ack for merging this via drm-intel-next?

Thanks,
Jani.

> ---
>  include/drm/display/drm_dp.h | 23 +++
>  1 file changed, 23 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index e69cece404b3..fc42b622ef32 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -543,6 +543,10 @@
>  /* DFP Capability Extension */
>  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0a3   /* 2.0 */
>  
> +#define DP_PANEL_REPLAY_CAP 0x0b0  /* DP 2.0 */
> +# define DP_PANEL_REPLAY_SUPPORT(1 << 0)
> +# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1)
> +
>  /* Link Configuration */
>  #define  DP_LINK_BW_SET  0x100
>  # define DP_LINK_RATE_TABLE  0x00/* eDP 1.4 */
> @@ -716,6 +720,13 @@
>  #define DP_BRANCH_DEVICE_CTRL0x1a1
>  # define DP_BRANCH_DEVICE_IRQ_HPD(1 << 0)
>  
> +#define PANEL_REPLAY_CONFIG 0x1b0  /* DP 2.0 */
> +# define DP_PANEL_REPLAY_ENABLE (1 << 0)
> +# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3)
> +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN   (1 << 4)
> +# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN  (1 << 5)
> +# define DP_PANEL_REPLAY_SU_ENABLE  (1 << 6)
> +
>  #define DP_PAYLOAD_ALLOCATE_SET  0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
> @@ -1105,6 +1116,18 @@
>  #define DP_LANE_ALIGN_STATUS_UPDATED_ESI   0x200e /* status same as 
> 0x204 */
>  #define DP_SINK_STATUS_ESI 0x200f /* status same as 
> 0x205 */
>  
> +#define DP_PANEL_REPLAY_ERROR_STATUS   0x2020  /* DP 2.1*/
> +# define DP_PANEL_REPLAY_LINK_CRC_ERROR(1 << 0)
> +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 1)
> +# define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR   (1 << 2)
> +
> +#define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS0x2022  /* DP 2.1 */
> +# define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK   (7 << 0)
> +# define DP_SINK_FRAME_LOCKED_SHIFT3
> +# define DP_SINK_FRAME_LOCKED_MASK (3 << 3)
> +# define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT   5
> +# define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK(1 << 5)
> +
>  /* Extended Receiver Capability: See DP_DPCD_REV for definitions */
>  #define DP_DP13_DPCD_REV0x2200

-- 
Jani Nikula, Intel

[Intel-gfx] [PATCH v3] drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier

[Mika Kahola]

Display driver shall read DPCD 00071h[3:1] during configuration
to get PSR setup time. This register provides the setup time
requirement on the VSC SDP entry packet. If setup time cannot be
met with the current timings
(e.g., PSR setup time + other blanking requirements > blanking time),
driver should enable sending VSC SDP one frame earlier before sending
the capture frame.

BSpec: 69895 (PSR Entry Setup Frames 17:16)

v2: Write frames before su entry to correct register (Ville, Jouni)
Move frames before su entry calculation to it's
own function (Ville, Jouni)
Rename PSR Entry Setup Frames register to indicate
Lunarlake specificity (Jouni)
v3: Modify setup entry frames calculation function to
return the actual frames (Ville)
Match comment with actual implementation (Jouni)

Signed-off-by: Mika Kahola 
---
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_psr.c  | 82 +++
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 +
 3 files changed, 71 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 047fe3f8905a..92f06d67fd1e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1708,6 +1708,7 @@ struct intel_psr {
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
+   u8 entry_setup_frames;
 };
 
 struct intel_dp {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index ecd24a0b86cb..497e4c26f4a6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -592,6 +592,9 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
if (intel_dp->psr.req_psr2_sdp_prior_scanline)
dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
 
+   if (intel_dp->psr.entry_setup_frames > 0)
+   dpcd_val |= DP_PSR_FRAME_CAPTURE;
+
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
@@ -690,6 +693,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 8)
val |= EDP_PSR_CRC_ENABLE;
 
+   if (DISPLAY_VER(dev_priv) >= 20)
+   val |= 
LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
+
intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder),
 ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val);
 }
@@ -727,11 +733,27 @@ static int psr2_block_count(struct intel_dp *intel_dp)
return psr2_block_count_lines(intel_dp) / 4;
 }
 
+static u8 get_frames_before_su_entry(struct intel_dp *intel_dp)
+{
+   u8 frames_before_su_entry;
+
+   frames_before_su_entry = max_t(u8,
+  intel_dp->psr.sink_sync_latency + 1,
+  2);
+
+   /* Entry setup frames must be at least 1 less than frames before SU 
entry */
+   if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)
+   frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;
+
+   return frames_before_su_entry;
+}
+
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
u32 val = EDP_PSR2_ENABLE;
+   u32 psr_val = 0;
 
val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
 
@@ -741,7 +763,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
val |= EDP_Y_COORDINATE_ENABLE;
 
-   val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, 
intel_dp->psr.sink_sync_latency + 1, 2));
+   val |= EDP_PSR2_FRAME_BEFORE_SU(get_frames_before_su_entry(intel_dp));
+
val |= intel_psr2_get_tp_time(intel_dp);
 
if (DISPLAY_VER(dev_priv) >= 12) {
@@ -785,6 +808,9 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (intel_dp->psr.req_psr2_sdp_prior_scanline)
val |= EDP_PSR2_SU_SDP_SCANLINE;
 
+   if (DISPLAY_VER(dev_priv) >= 20)
+   psr_val |= 
LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
+
if (intel_dp->psr.psr2_sel_fetch_enabled) {
u32 tmp;
 
@@ -798,7 +824,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
 * recommending keep this bit unset while PSR2 is enabled.
 */
-   intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), 0);
+   intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), 
psr_val);
 
intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val);
 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Print SSEU information of all GTs for debugfs

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Print SSEU information of all GTs for debugfs
URL   : https://patchwork.freedesktop.org/series/125941/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125941v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/index.html

Participating hosts (37 -> 38)
--

  Additional (5): bat-kbl-2 fi-bsw-n3050 bat-dg2-8 bat-dg2-9 bat-adlp-6 
  Missing(4): bat-dg2-11 bat-adls-5 fi-snb-2520m bat-dg1-5 

New tests
-

  New tests have been introduced between CI_DRM_13833 and Patchwork_125941v1:

### New IGT tests (1) ###

  * igt@gem_exec_basic:
- Statuses :
- Exec time: [None] s

  

Known issues


  Here are the changes found in Patchwork_125941v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- bat-adlp-11:[PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/bat-adlp-11/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-adlp-11/boot.html

  
 Possible fixes 

  * boot:
- fi-hsw-4770:[FAIL][3] ([i915#8293]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-adlp-6: NOTRUN -> [SKIP][5] ([i915#9318])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-adlp-6/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1849])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-kbl-2/igt@fb...@info.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][7] ([fdo#109271]) +39 other tests 
skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050:   NOTRUN -> [SKIP][8] ([fdo#109271]) +18 other tests 
skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4083])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-dg2-9/igt@gem_m...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-dg2-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-dg2-9/igt@gem_mmap_...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-dg2-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-6: NOTRUN -> [SKIP][14] ([i915#3282])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-adlp-6/igt@gem_tiled_pread_basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#6621])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-dg2-9/igt@i915_pm_...@basic-api.html
- bat-dg2-8:  NOTRUN -> [SKIP][17] ([i915#6621])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-dg2-8/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@mman:
- bat-rpls-1: [PASS][18] -> [TIMEOUT][19] ([i915#6794] / 
[i915#7392])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/bat-rpls-1/igt@i915_selftest@l...@mman.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/bat-rpls-1/igt@i915_selftest@l...@mman.html

  * igt@i915_selftest@live@requests:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][20] ([i915#9527])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125941v1/fi-hsw-4770/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-1: [PASS][21] -> [WARN][22] ([i915#8747])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/bat-r

Re: [Intel-gfx] [PATCH v3] drm/i915: handle uncore spinlock when not available

[Tvrtko Ursulin]

On 03/11/2023 08:58, Coelho, Luciano wrote:

On Fri, 2023-11-03 at 03:31 +, Vivi, Rodrigo wrote:


Any other suggestions?


I think it will boil down to the reason uncore lock is held over
the
respective sections ie. the comment in i915_get_crtc_scanoutpos.

If it is timing sensitive to the extent irq off was needed it may
apply
to Xe as well. Likewise the need to use mmio helpers which rely on
the
uncore lock already held. Question of whether there is conceptual
commonality, will probably drive the best name, or the best
approach
in
general.


yeap, this is how I'm seeing this. If i915-display needs this global
lock around mmio operations, then we wound need to add it to the
xe_mmio as well and then solve the name, etc.

However, I don't believe that other users of the mmio would need
this lock. So I believe the right thing to do is to create a i915-
display only spin_lock, around the intel_de_mmio calls and here.

With this we entirely kill the dependency on someone-else's lock
and have something that is entirely inside display code so it
doesn't need to be ported to one or another driver core components.


Right, I agree too.

My patch was just trying to address the quick hack made for Xe, not the
actual implementation in Xe's side.  But it makes sense to implement
this new lock internally in the display so there are no dependencies or
wrappers needed.

I'll respin.


You could also make sure it needs to be a lock and not just say a 
preempt off or irq section?


Regards,

Tvrtko

Re: [Intel-gfx] [PATCH v1 1/1] drm/i915/xe2lpd: alternate WA for underruns with PSR2 and FBC

[Govindapillai, Vinod]

Hi,


On Fri, 2023-11-03 at 11:21 +0200, Jani Nikula wrote:
> On Fri, 03 Nov 2023, Vinod Govindapillai  
> wrote:
> > Implement the alternate WA for the underruns when both PSR2
> > and FBC is enabled.
> 
> But we don't enable FBC when PSR2 is enabled, for display 12+.
> 
> See intel_fbc.c line 1200 or so.

Yes. I had another series to enable FBC + PSR for xe2lpd.
https://patchwork.freedesktop.org/series/125932/
I should mention that here.


Thanks
Vinod

> 
> BR,
> Jani.
> 
> 
> > 
> > Signed-off-by: Vinod Govindapillai 
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index bde12fe62275..b9cd92a997cd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
> >  static void ivb_fbc_activate(struct intel_fbc *fbc)
> >  {
> > struct drm_i915_private *i915 = fbc->i915;
> > +   u32 dpfc_ctl;
> >  
> > if (DISPLAY_VER(i915) >= 10)
> > glk_fbc_program_cfb_stride(fbc);
> > @@ -617,8 +618,17 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> > if (intel_gt_support_legacy_fencing(to_gt(i915)))
> > snb_fbc_program_fence(fbc);
> >  
> > +   /*
> > +    * Alternate WA for HW bug with PSR2 + FBC.
> > +    * 1.Write FBC_CTL with Plane binding set correctly with FBC enable 
> > = 0
> > +    * 2.Write FBC_CTL with Plane binding set correctly with FBC enable 
> > = 1
> > +    */
> > +   dpfc_ctl = ivb_dpfc_ctl(fbc);
> > +   if (DISPLAY_VER(i915) >= 20)
> > +   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> > +
> > intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> > -  DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
> > +  DPFC_CTL_EN | dpfc_ctl);
> >  }
> >  
> >  static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
> 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: C20 state verification (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: C20 state verification (rev2)
URL   : https://patchwork.freedesktop.org/series/125855/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125855v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_125855v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125855v2, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/index.html

Participating hosts (37 -> 36)
--

  Additional (4): bat-kbl-2 bat-dg2-9 bat-adlp-6 fi-bsw-n3050 
  Missing(5): bat-adls-5 fi-snb-2520m bat-atsm-1 fi-pnv-d510 bat-dg2-11 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_125855v2:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@dmabuf:
- bat-mtlp-8: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/bat-mtlp-8/igt@i915_selftest@l...@dmabuf.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-mtlp-8/igt@i915_selftest@l...@dmabuf.html

  
Known issues


  Here are the changes found in Patchwork_125855v2 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-hsw-4770:[FAIL][3] ([i915#8293]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-adlp-6: NOTRUN -> [SKIP][5] ([i915#9318])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-adlp-6/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1849])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-kbl-2/igt@fb...@info.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][7] ([fdo#109271]) +39 other tests 
skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050:   NOTRUN -> [SKIP][8] ([fdo#109271]) +18 other tests 
skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4083])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-6: NOTRUN -> [SKIP][12] ([i915#3282])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-adlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@mman:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][14] ([i915#9527])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/fi-hsw-4770/igt@i915_selftest@l...@mman.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][15] ([i915#5190])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
- fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#5190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#4215] / [i915#5190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125855v2/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#4212]) +6 other tests skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchw

Re: [Intel-gfx] [PATCH v1 1/1] drm/i915/xe2lpd: alternate WA for underruns with PSR2 and FBC

[Jani Nikula]

On Fri, 03 Nov 2023, "Govindapillai, Vinod"  
wrote:
> Hi,
>
>
> On Fri, 2023-11-03 at 11:21 +0200, Jani Nikula wrote:
>> On Fri, 03 Nov 2023, Vinod Govindapillai  
>> wrote:
>> > Implement the alternate WA for the underruns when both PSR2
>> > and FBC is enabled.
>> 
>> But we don't enable FBC when PSR2 is enabled, for display 12+.
>> 
>> See intel_fbc.c line 1200 or so.
>
> Yes. I had another series to enable FBC + PSR for xe2lpd.
> https://patchwork.freedesktop.org/series/125932/
> I should mention that here.

Well, this depends on that stuff, so maybe these should all be part of
the same series?

BR,
Jani.

>
>
> Thanks
> Vinod
>
>> 
>> BR,
>> Jani.
>> 
>> 
>> > 
>> > Signed-off-by: Vinod Govindapillai 
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++-
>> >  1 file changed, 11 insertions(+), 1 deletion(-)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
>> > b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > index bde12fe62275..b9cd92a997cd 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > @@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
>> >  static void ivb_fbc_activate(struct intel_fbc *fbc)
>> >  {
>> > struct drm_i915_private *i915 = fbc->i915;
>> > +   u32 dpfc_ctl;
>> >  
>> > if (DISPLAY_VER(i915) >= 10)
>> > glk_fbc_program_cfb_stride(fbc);
>> > @@ -617,8 +618,17 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
>> > if (intel_gt_support_legacy_fencing(to_gt(i915)))
>> > snb_fbc_program_fence(fbc);
>> >  
>> > +   /*
>> > +    * Alternate WA for HW bug with PSR2 + FBC.
>> > +    * 1.Write FBC_CTL with Plane binding set correctly with FBC 
>> > enable = 0
>> > +    * 2.Write FBC_CTL with Plane binding set correctly with FBC 
>> > enable = 1
>> > +    */
>> > +   dpfc_ctl = ivb_dpfc_ctl(fbc);
>> > +   if (DISPLAY_VER(i915) >= 20)
>> > +   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
>> > +
>> > intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
>> > -  DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
>> > +  DPFC_CTL_EN | dpfc_ctl);
>> >  }
>> >  
>> >  static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
>> 
>

-- 
Jani Nikula, Intel

Re: [Intel-gfx] [PATCH 0/5] drm/i915/pmu: hide struct i915_pmu

[Tvrtko Ursulin]

On 02/11/2023 16:47, Jani Nikula wrote:

On Thu, 02 Nov 2023, Tvrtko Ursulin  wrote:

On 02/11/2023 15:42, Jani Nikula wrote:

The implementation details of pmu should be implementation details
hidden inside i915_pmu.c. Make it so.


Don't tell me i915->pmu bothers xe somehow?


It doesn't bother xe, it bothers me...


I am not a fan of the series
on a glance. Replacing an increment with a function call for instance.


I think you glanced at the wart of this series. ;)

It just bugs me that we expose a plethora of data that should be
internal to pmu, basically just for that one increment.

And we pull in a bunch of headers to define struct i915_pmu, and then we
implicitly depend on those headers in a ton of places through incredible
chains of includes.

And we rebuild everything and a half when those headers change. Or when
the pmu implementation details change.


On the other hand i915_pmu.h is a small header file, which does not 
include _any_ other internal i915 headers (only uapi) and is always 
present (if you ignore gens <= 2) which does not driver the allocate on 
demand approach. In the past three years it had like seven edits.


Given all that, the change of direction you propose here sounds a bit 
radical and I would rather not replace that increment with a function 
call, when it is questionable if the same separation of components 
approach can be, or will be, applied to the whole driver. Gut feeling 
says it is bound to be hard and possibly not happen in which case I 
don't see what is gained by churning on the tiny and quiet i915_pmu.h|c.


Regards,

Tvrtko




BR,
Jani.



Regards,

Tvrtko


BR,
Jani.


Jani Nikula (5):
drm/i915/pmu: report irqs to pmu code
drm/i915/pmu: convert one more container_of() to event_to_pmu()
drm/i915/pmu: change attr_group allocation and initialization
drm/i915/pmu: hide struct i915_pmu inside i915_pmu.c
drm/i915: add a number of explicit includes to avoid implicit ones

   .../gpu/drm/i915/gem/i915_gem_execbuffer.c|   1 +
   drivers/gpu/drm/i915/gem/i915_gem_mman.c  |   1 +
   .../gpu/drm/i915/gem/selftests/huge_pages.c   |   1 +
   .../drm/i915/gem/selftests/i915_gem_context.c |   2 +
   drivers/gpu/drm/i915/gt/intel_engine_cs.c |   1 +
   drivers/gpu/drm/i915/gt/selftest_execlists.c  |   1 +
   drivers/gpu/drm/i915/gt/selftest_migrate.c|   1 +
   drivers/gpu/drm/i915/gt/selftest_slpc.c   |   2 +
   drivers/gpu/drm/i915/i915_drv.h   |   5 +-
   drivers/gpu/drm/i915/i915_irq.c   |   6 +-
   drivers/gpu/drm/i915/i915_pmu.c   | 216 --
   drivers/gpu/drm/i915/i915_pmu.h   | 138 +--
   drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |   1 +
   drivers/gpu/drm/i915/selftests/i915_request.c |   4 +-
   drivers/gpu/drm/i915/selftests/igt_mmap.c |   2 +
   .../drm/i915/selftests/intel_memory_region.c  |   1 +
   16 files changed, 214 insertions(+), 169 deletions(-)

[Intel-gfx] [CI] drm/i915: Fix potential spectre vulnerability

[Tvrtko Ursulin]

From: Kunwu Chan 

Fix smatch warning:
drivers/gpu/drm/i915/gem/i915_gem_context.c:847 set_proto_ctx_sseu()
warn: potential spectre issue 'pc->user_engines' [r] (local cap)

Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create 
parameters (v5)")
Cc:  # v5.15+
Signed-off-by: Kunwu Chan 
Reviewed-by: Tvrtko Ursulin 
Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 9a9ff84c90d7..e38f06a6e56e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -844,6 +844,7 @@ static int set_proto_ctx_sseu(struct drm_i915_file_private 
*fpriv,
if (idx >= pc->num_user_engines)
return -EINVAL;
 
+   idx = array_index_nospec(idx, pc->num_user_engines);
pe = &pc->user_engines[idx];
 
/* Only render engine supports RPCS configuration. */
-- 
2.39.2

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Print SSEU information of all GTs for debugfs

[Tvrtko Ursulin]

On 03/11/2023 05:29, Gareth Yu wrote:

Print another SSEU information addition to the first one.

Cc : Tejas Upadhyay 
Cc : Matt Roper 
Cc : Ville Syrjälä 
Signed-off-by: Gareth Yu 
---
  drivers/gpu/drm/i915/i915_debugfs.c   | 13 ++---
  drivers/gpu/drm/i915/i915_gpu_error.c |  6 +-
  2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e9b79c2c37d8..b5914a2c0597 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -63,13 +63,16 @@ static int i915_capabilities(struct seq_file *m, void *data)
  {
struct drm_i915_private *i915 = node_to_i915(m->private);
struct drm_printer p = drm_seq_file_printer(m);
+   struct intel_gt *gt;
+   unsigned int i;
  
  	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
  
  	intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p);

intel_display_device_info_print(DISPLAY_INFO(i915), 
DISPLAY_RUNTIME_INFO(i915), &p);
i915_print_iommu_status(i915, &p);
-   intel_gt_info_print(&to_gt(i915)->info, &p);
+   for_each_gt(gt, i915, i)
+   intel_gt_info_print(>->info, &p);
intel_driver_caps_print(&i915->caps, &p);
  
  	kernel_param_lock(THIS_MODULE);

@@ -783,9 +786,13 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
  static int i915_sseu_status(struct seq_file *m, void *unused)
  {
struct drm_i915_private *i915 = node_to_i915(m->private);
-   struct intel_gt *gt = to_gt(i915);
+   struct intel_gt *gt;
+   unsigned int i;
+
+   for_each_gt(gt, i915, i)
+   intel_sseu_status(m, gt);


Don't we have the per GT debugfs directories and files already!?

  
-	return intel_sseu_status(m, gt);

+   return 0;
  }
  
  static int i915_forcewake_open(struct inode *inode, struct file *file)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b4e31e59c799..2adc317af944 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -722,9 +722,13 @@ static void err_print_gt_info(struct 
drm_i915_error_state_buf *m,
  struct intel_gt_coredump *gt)
  {
struct drm_printer p = i915_error_printer(m);
+   struct drm_i915_private *i915 = gt->_gt->i915;
+   struct intel_gt *gt_n;
+   unsigned int n;
  
  	intel_gt_info_print(>->info, &p);

-   intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p);
+   for_each_gt(gt_n, i915, n)
+   intel_sseu_print_topology(gt_n->i915, >_n->info.sseu, &p);


Do we need a consistent story across all error capture? Aka why is sseu 
special.


Also the intel_gt_info_print() above calls intel_sseu_dump so we end up 
with root tile SSEU printed twice?


There possibly was a Jira years ago to do stuff about multi-tile error 
capture but maybe it got lost.


Adding Andi if he has comments.

Regards,

Tvrtko


  }
  
  static void err_print_gt_display(struct drm_i915_error_state_buf *m,

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Support PSR entry VSC packet to be transmitted one 
frame earlier (rev3)
URL   : https://patchwork.freedesktop.org/series/125558/
State : warning

== Summary ==

Error: dim checkpatch failed
b58bf98ad0fd drm/i915/display: Support PSR entry VSC packet to be transmitted 
one frame earlier
-:139: CHECK:LINE_SPACING: Please don't use multiple blank lines
#139: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1109:
+
+

-:205: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#205: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:39:
+#define   LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x)
REG_FIELD_PREP(LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK, (x))

total: 0 errors, 1 warnings, 1 checks, 158 lines checked

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Support PSR entry VSC packet to be transmitted one 
frame earlier (rev3)
URL   : https://patchwork.freedesktop.org/series/125558/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125558v3


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_125558v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125558v3, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/index.html

Participating hosts (37 -> 38)
--

  Additional (3): bat-kbl-2 bat-adlp-6 fi-bsw-n3050 
  Missing(2): bat-adls-5 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_125558v3:

### IGT changes ###

 Possible regressions 

  * igt@dmabuf@all-tests@dma_fence_chain:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-hsw-4770/igt@dmabuf@all-tests@dma_fence_chain.html

  
Known issues


  Here are the changes found in Patchwork_125558v3 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-hsw-4770:[FAIL][2] ([i915#8293]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-adlp-6: NOTRUN -> [SKIP][4] ([i915#9318])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1849])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-kbl-2/igt@fb...@info.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][6] ([fdo#109271]) +39 other tests 
skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050:   NOTRUN -> [SKIP][7] ([fdo#109271]) +18 other tests 
skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-6: NOTRUN -> [SKIP][8] ([i915#3282])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005:   [PASS][9] -> [DMESG-FAIL][10] ([i915#5334])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [PASS][11] -> [DMESG-FAIL][12] ([i915#9549])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#5190])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adlp-6: NOTRUN -> [SKIP][14] ([i915#4103] / [i915#5608]) +1 
other test skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-adlp-6: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#3840])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-6: NOTRUN -> [SKIP][16] ([fdo#109285])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-bsw-n3050:   NOTRUN -> [FAIL][17] ([IGT#3])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-bsw-n3050/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
- fi-hsw-4770:NOTRUN -> [SKIP][

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: move display mutex inits to display code (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: move display mutex inits to 
display code (rev2)
URL   : https://patchwork.freedesktop.org/series/125912/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced 
symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced 
symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced 
symbol 'mask'
+./includ

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier (rev3)

[Kahola, Mika]

From: Patchwork 
Sent: Friday, November 3, 2023 1:37 PM
To: Kahola, Mika 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for drm/i915/display: Support PSR entry VSC 
packet to be transmitted one frame earlier (rev3)

Patch Details
Series:
drm/i915/display: Support PSR entry VSC packet to be transmitted one frame 
earlier (rev3)
URL:
https://patchwork.freedesktop.org/series/125558/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/index.html
CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125558v3
Summary

FAILURE

Serious unknown changes coming with Patchwork_125558v3 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125558v3, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/index.html

Participating hosts (37 -> 38)

Additional (3): bat-kbl-2 bat-adlp-6 fi-bsw-n3050
Missing (2): bat-adls-5 fi-snb-2520m

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_125558v3:

IGT changes
Possible regressions

  *   igt@dmabuf@all-tests@dma_fence_chain:

 *   fi-hsw-4770: NOTRUN -> 
INCOMPLETE
The patch doesn’t touch hsw. This is false positive regression. Maybe we can 
rerun BAT?
-Mika-
Known issues

Here are the changes found in Patchwork_125558v3 that come from known issues:

CI changes
Possible fixes

  *   boot:

 *   fi-hsw-4770: 
FAIL
 (i915#8293) -> 
PASS

IGT changes
Issues hit

  *   igt@debugfs_test@basic-hwmon:

 *   bat-adlp-6: NOTRUN -> 
SKIP
 (i915#9318)

  *   igt@fbdev@info:

 *   bat-kbl-2: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#1849)

  *   igt@gem_lmem_swapping@parallel-random-engines:

 *   bat-kbl-2: NOTRUN -> 
SKIP
 (fdo#109271) +39 other 
tests skip

  *   igt@gem_lmem_swapping@random-engines:

 *   fi-bsw-n3050: NOTRUN -> 
SKIP
 (fdo#109271) +18 other 
tests skip

  *   igt@gem_tiled_pread_basic:

 *   bat-adlp-6: NOTRUN -> 
SKIP
 (i915#3282)

  *   igt@i915_selftest@live@gt_heartbeat:

 *   fi-glk-j4005: 
PASS
 -> 
DMESG-FAIL
 (i915#5334)

  *   igt@i915_selftest@live@hangcheck:

 *   fi-skl-guc: 
PASS
 -> 
DMESG-FAIL
 (i915#9549)

  *   igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:

 *   fi-hsw-4770: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#5190)

  *   igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:

 *   bat-adlp-6: NOTRUN -> 
SKIP
 (i915#4103 / 
i915#5608) +1 other test 
skip

  *   igt@kms_dsc@dsc-basic:

 *   bat-adlp-6: NOTRUN -> 
SKIP

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: move display mutex inits to display code (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: move display mutex inits to 
display code (rev2)
URL   : https://patchwork.freedesktop.org/series/125912/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125912v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/index.html

Participating hosts (37 -> 35)
--

  Additional (2): bat-adlp-6 fi-bsw-n3050 
  Missing(4): bat-mtlp-8 bat-adls-5 fi-snb-2520m bat-dg1-5 

Known issues


  Here are the changes found in Patchwork_125912v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-bsw-n3050:   NOTRUN -> [FAIL][1] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/fi-bsw-n3050/boot.html
- bat-jsl-1:  [PASS][2] -> [FAIL][3] ([i915#8293])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/bat-jsl-1/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/bat-jsl-1/boot.html

  
 Possible fixes 

  * boot:
- fi-hsw-4770:[FAIL][4] ([i915#8293]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-adlp-6: NOTRUN -> [SKIP][6] ([i915#9318])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/bat-adlp-6/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-6: NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/bat-adlp-6/igt@gem_tiled_pread_basic.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#5190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adlp-6: NOTRUN -> [SKIP][9] ([i915#4103] / [i915#5608]) +1 
other test skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/bat-adlp-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-adlp-6: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#3840])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/bat-adlp-6/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-6: NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/bat-adlp-6/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271]) +12 other tests 
skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-vga-1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#1845] / [i915#9197]) +2 
other tests skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3 
other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@dmabuf@all-tests@dma_fence:
- fi-pnv-d510:[FAIL][15] -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-pnv-d510/igt@dmabuf@all-tests@dma_fence.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/fi-pnv-d510/igt@dmabuf@all-tests@dma_fence.html

  * igt@dmabuf@all-tests@sanitycheck:
- fi-pnv-d510:[ABORT][17] -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-pnv-d510/igt@dmabuf@all-te...@sanitycheck.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/fi-pnv-d510/igt@dmabuf@all-te...@sanitycheck.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][19] ([IGT#3]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125912v2/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#3]: https://gitlab.freedeskt

Re: [Intel-gfx] [PATCH v1 1/1] drm/i915/xe2lpd: alternate WA for underruns with PSR2 and FBC

[Govindapillai, Vinod]

On Fri, 2023-11-03 at 12:33 +0200, Jani Nikula wrote:
> On Fri, 03 Nov 2023, "Govindapillai, Vinod"  
> wrote:
> > Hi,
> > 
> > 
> > On Fri, 2023-11-03 at 11:21 +0200, Jani Nikula wrote:
> > > On Fri, 03 Nov 2023, Vinod Govindapillai  
> > > wrote:
> > > > Implement the alternate WA for the underruns when both PSR2
> > > > and FBC is enabled.
> > > 
> > > But we don't enable FBC when PSR2 is enabled, for display 12+.
> > > 
> > > See intel_fbc.c line 1200 or so.
> > 
> > Yes. I had another series to enable FBC + PSR for xe2lpd.
> > https://patchwork.freedesktop.org/series/125932/
> > I should mention that here.
> 
> Well, this depends on that stuff, so maybe these should all be part of
> the same series?

Okay! I can make this as part of the PSR + FBC series

BR
Vinod

> 
> BR,
> Jani.
> 
> > 
> > 
> > Thanks
> > Vinod
> > 
> > > 
> > > BR,
> > > Jani.
> > > 
> > > 
> > > > 
> > > > Signed-off-by: Vinod Govindapillai 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++-
> > > >  1 file changed, 11 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index bde12fe62275..b9cd92a997cd 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
> > > >  static void ivb_fbc_activate(struct intel_fbc *fbc)
> > > >  {
> > > > struct drm_i915_private *i915 = fbc->i915;
> > > > +   u32 dpfc_ctl;
> > > >  
> > > > if (DISPLAY_VER(i915) >= 10)
> > > > glk_fbc_program_cfb_stride(fbc);
> > > > @@ -617,8 +618,17 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> > > > if (intel_gt_support_legacy_fencing(to_gt(i915)))
> > > > snb_fbc_program_fence(fbc);
> > > >  
> > > > +   /*
> > > > +    * Alternate WA for HW bug with PSR2 + FBC.
> > > > +    * 1.Write FBC_CTL with Plane binding set correctly with FBC 
> > > > enable = 0
> > > > +    * 2.Write FBC_CTL with Plane binding set correctly with FBC 
> > > > enable = 1
> > > > +    */
> > > > +   dpfc_ctl = ivb_dpfc_ctl(fbc);
> > > > +   if (DISPLAY_VER(i915) >= 20)
> > > > +   intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), 
> > > > dpfc_ctl);
> > > > +
> > > > intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> > > > -  DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
> > > > +  DPFC_CTL_EN | dpfc_ctl);
> > > >  }
> > > >  
> > > >  static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
> > > 
> > 
> 

Re: [Intel-gfx] [PATCH] drm/i915/mtl: C20 state verification

[Kahola, Mika]

Please ignore this patch. There is a bug in the patch that I still need to fix.

Thanks!

-Mika-

> -Original Message-
> From: Kahola, Mika 
> Sent: Wednesday, November 1, 2023 4:05 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sousa, Gustavo ; Kahola, Mika 
> 
> Subject: [PATCH] drm/i915/mtl: C20 state verification
> 
> Add state verification for C20 as we have one for C10.
> 
> Signed-off-by: Mika Kahola 
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 111 ++
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   2 +-
>  .../drm/i915/display/intel_modeset_verify.c   |   2 +-
>  3 files changed, 88 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index b2ad4c6172f6..654e91deb7e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3017,35 +3017,15 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
>   return ICL_PORT_DPLL_DEFAULT;
>  }
> 
> -void intel_c10pll_state_verify(struct intel_atomic_state *state,
> -struct intel_crtc *crtc)
> +static void intel_c10pll_state_verify(const struct intel_crtc_state *state,
> +   struct intel_crtc *crtc,
> +   struct intel_encoder *encoder)
>  {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> - const struct intel_crtc_state *new_crtc_state =
> - intel_atomic_get_new_crtc_state(state, crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>   struct intel_c10pll_state mpllb_hw_state = {};
> - const struct intel_c10pll_state *mpllb_sw_state = 
> &new_crtc_state->cx0pll_state.c10;
> - struct intel_encoder *encoder;
> - enum phy phy;
> + const struct intel_c10pll_state *mpllb_sw_state =
> +&state->cx0pll_state.c10;
>   int i;
> 
> - if (DISPLAY_VER(i915) < 14)
> - return;
> -
> - if (!new_crtc_state->hw.active)
> - return;
> -
> - /* intel_get_crtc_new_encoder() only works for modeset/fastset commits 
> */
> - if (!intel_crtc_needs_modeset(new_crtc_state) &&
> - !intel_crtc_needs_fastset(new_crtc_state))
> - return;
> -
> - encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> - phy = intel_port_to_phy(i915, encoder->port);
> -
> - if (!intel_is_c10phy(i915, phy))
> - return;
> -
>   intel_c10pll_readout_hw_state(encoder, &mpllb_hw_state);
> 
>   for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { @@ -3091,3 
> +3071,84 @@ int intel_cx0pll_calc_port_clock(struct
> intel_encoder *encoder,
> 
>   return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);  }
> +
> +static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
> +   struct intel_crtc *crtc,
> +   struct intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_c20pll_state mpll_hw_state = {};
> + const struct intel_c20pll_state *mpll_sw_state = 
> &state->cx0pll_state.c20;
> + bool use_mplla;
> + int i;
> +
> + intel_c20pll_readout_hw_state(encoder, &mpll_hw_state);
> +
> + use_mplla = intel_c20_use_mplla(mpll_hw_state.clock);
> + if (use_mplla) {
> + for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
> + u8 expected = mpll_sw_state->mplla[i];
> +
> + I915_STATE_WARN(i915, mpll_hw_state.mplla[i] != 
> expected,
> + "[CRTC:%d:%s] mismatch in C20MPLLA: 
> Register[%d] (expected 0x%02x, found
> 0x%02x)",
> + crtc->base.base.id, crtc->base.name, i,
> + expected, mpll_hw_state.mplla[i]);
> + }
> + } else {
> + for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {
> + u8 expected = mpll_sw_state->mpllb[i];
> +
> + I915_STATE_WARN(i915, mpll_hw_state.mpllb[i] != 
> expected,
> + "[CRTC:%d:%s] mismatch in C20MPLLB: 
> Register[%d] (expected 0x%02x, found
> 0x%02x)",
> + crtc->base.base.id, crtc->base.name, i,
> + expected, mpll_hw_state.mpllb[i]);
> + }
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {
> + I915_STATE_WARN(i915, mpll_hw_state.tx[i] != 
> mpll_sw_state->tx[i],
> + "[CRTC:%d:%s] mismatch in C20MPLL%s: Register 
> TX[%i] (expected 0x%02x, found 0x%02x)",
> + crtc->base.base.id, crtc->base.name,
> + use_mplla ? "A" : "B",
> + i,
> + mpll_sw_s

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix potential spectre vulnerability

[Patchwork]

== Series Details ==

Series: drm/i915: Fix potential spectre vulnerability
URL   : https://patchwork.freedesktop.org/series/125950/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125950v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/index.html

Participating hosts (37 -> 35)
--

  Additional (2): bat-kbl-2 bat-adlp-6 
  Missing(4): bat-mtlp-8 bat-adls-5 fi-snb-2520m bat-dg1-5 

Known issues


  Here are the changes found in Patchwork_125950v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-hsw-4770:[FAIL][1] ([i915#8293]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/fi-hsw-4770/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-adlp-6: NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/bat-adlp-6/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1849])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/bat-kbl-2/igt@fb...@info.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][5] ([fdo#109271]) +39 other tests 
skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-6: NOTRUN -> [SKIP][6] ([i915#3282])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/bat-adlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka:  [PASS][7] -> [DMESG-FAIL][8] ([i915#5334] / 
[i915#7872])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][9] ([i915#9527])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#5190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adlp-6: NOTRUN -> [SKIP][11] ([i915#4103] / [i915#5608]) +1 
other test skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/bat-adlp-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-adlp-6: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#3840])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/bat-adlp-6/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-6: NOTRUN -> [SKIP][13] ([fdo#109285])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/bat-adlp-6/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271]) +12 other tests 
skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-vga-1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#1845] / [i915#9197]) +2 
other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1072]) +3 
other tests skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@dmabuf@all-tests@dma_fence:
- fi-pnv-d510:[FAIL][17] -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-pnv-d510/igt@dmabuf@all-tests@dma_fence.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125950v1/fi-pnv-d510/igt@dmabuf@all-tests@dma_fence.html

  * igt@dmabuf@all-tests@sanitycheck:
- fi-pnv-d510:[ABORT][19] -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-pnv-d510/igt@dmabuf@all-te...@sanitycheck.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/

Re: [Intel-gfx] [PATCH v3] drm/i915: handle uncore spinlock when not available

[Vivi, Rodrigo]

On Fri, 2023-11-03 at 09:47 +, Tvrtko Ursulin wrote:
> 
> On 03/11/2023 08:58, Coelho, Luciano wrote:
> > On Fri, 2023-11-03 at 03:31 +, Vivi, Rodrigo wrote:
> > > > > 
> > > > > Any other suggestions?
> > > > 
> > > > I think it will boil down to the reason uncore lock is held
> > > > over
> > > > the
> > > > respective sections ie. the comment in
> > > > i915_get_crtc_scanoutpos.
> > > > 
> > > > If it is timing sensitive to the extent irq off was needed it
> > > > may
> > > > apply
> > > > to Xe as well. Likewise the need to use mmio helpers which rely
> > > > on
> > > > the
> > > > uncore lock already held. Question of whether there is
> > > > conceptual
> > > > commonality, will probably drive the best name, or the best
> > > > approach
> > > > in
> > > > general.
> > > 
> > > yeap, this is how I'm seeing this. If i915-display needs this
> > > global
> > > lock around mmio operations, then we wound need to add it to the
> > > xe_mmio as well and then solve the name, etc.
> > > 
> > > However, I don't believe that other users of the mmio would need
> > > this lock. So I believe the right thing to do is to create a
> > > i915-
> > > display only spin_lock, around the intel_de_mmio calls and here.
> > > 
> > > With this we entirely kill the dependency on someone-else's lock
> > > and have something that is entirely inside display code so it
> > > doesn't need to be ported to one or another driver core
> > > components.
> > 
> > Right, I agree too.
> > 
> > My patch was just trying to address the quick hack made for Xe, not
> > the
> > actual implementation in Xe's side.  But it makes sense to
> > implement
> > this new lock internally in the display so there are no
> > dependencies or
> > wrappers needed.
> > 
> > I'll respin.
> 
> You could also make sure it needs to be a lock and not just say a 
> preempt off or irq section?

indeed a good question. maybe we don't need the lock at all there...

> 
> Regards,
> 
> Tvrtko

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Clear possible sticky bits on PICA message bus

[Kahola, Mika]

> -Original Message-
> From: Intel-gfx  On Behalf Of 
> Kahola, Mika
> Sent: Thursday, November 2, 2023 4:54 PM
> To: Sousa, Gustavo ; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Syrjala, Ville 
> 
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Clear possible sticky bits on 
> PICA message bus
> 
> > -Original Message-
> > From: Sousa, Gustavo 
> > Sent: Thursday, November 2, 2023 4:23 PM
> > To: Kahola, Mika ;
> > intel-gfx@lists.freedesktop.org
> > Cc: Kahola, Mika ; Nikula, Jani
> > ; Syrjala, Ville 
> > Subject: Re: [PATCH] drm/i915/mtl: Clear possible sticky bits on PICA
> > message bus
> >
> > Quoting Mika Kahola (2023-11-01 07:31:01-03:00)
> > >It is possible that sticky bits or error bits are left on message bus
> > >status register. Reading and then writing the value back to
> > >messagebus status register clears all possible sticky bits and errors.
> > >
> > >Signed-off-by: Mika Kahola 
> > >---
> > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 ++
> > > 1 file changed, 14 insertions(+)
> > >
> > >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > >index b2ad4c6172f6..f439f0c7b400 100644
> > >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > >@@ -195,6 +195,13 @@ static int __intel_cx0_read_once(struct 
> > >drm_i915_private *i915, enum port port,
> > > return -ETIMEDOUT;
> > > }
> > >
> > >+/*
> > >+ * write XELPDP_PORT_P2M_MSGBUS_STATUS register after read to 
> > >clear
> > >+ * any error sticky bits set from previous transactions
> > >+ */
> > >+val = intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, 
> > >lane));
> > >+intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port,
> > >+ lane), val);
> > >+
> > > intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> > >XELPDP_PORT_M2P_TRANSACTION_PENDING |
> > >XELPDP_PORT_M2P_COMMAND_READ | @@ -262,6
> > >+269,13 @@ static int __intel_cx0_write_once(struct drm_i915_private
> > >+*i915, enum port port,
> > > return -ETIMEDOUT;
> > > }
> > >
> > >+/*
> > >+ * write XELPDP_PORT_P2M_MSGBUS_STATUS register after read to 
> > >clear
> > >+ * any error sticky bits set from previous transactions
> > >+ */
> > >+val = intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, 
> > >lane));
> > >+intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port,
> > >+ lane), val);
> > >+
> >
> > Looking at the current state of the code, looks like to me that we already 
> > clear the bits from both the "success" and "failure"
> paths.
> > For the "success"
> > paths, that is done by a direct call to
> > intel_clear_response_ready_flag(); for the "failure" case, the call to
> > intel_clear_response_ready_flag() is done as part of intel_cx0_bus_reset().
> >
> > Thus, considering that we start using the msgbus from a clean state,
> > maybe these extra steps are not necessary? Have you tried adding a
> > call to
> > intel_cx0_bus_reset() as part of intel_cx0_phy_transaction_begin()?
> That I haven't try to reset bus at the stage. I can give it a go and check 
> what happens. To me it seems, that we are sometimes
> stuck at waiting the ack and eventually we time out and bail out. I have no 
> clue why this happens from time to time. We already
> reset the bus after every read/write operation. In addition, a small delay 
> seem to help and clear the sporadic read/write failures
> to the bus. However, this is more like a workaround and I'm not really happy 
> about this sort of hack.
> 
> I will give a go for your suggestion and come back once I have the results.

I ran a test with intel_cx0_bus_reset() when placed in 
intel_cx0_phy_transaction_begin(). This didn't help either as with kms_flip IGT 
test I was able to trigger this read failure

[drm] *ERROR* PHY G Read 0d80 failed after 3 retries.

This was with the configuration where the test vehicle had 4K and eDP monitors 
connected.


> 
> Thanks!
> -Mika-
> 
> >
> > Also, I think it would be good if we understood better were those uncleared 
> > bits are coming from...
> >
> > --
> > Gustavo Sousa
> >
> > > intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> > >XELPDP_PORT_M2P_TRANSACTION_PENDING |
> > >(committed ? 
> > > XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
> > >--
> > >2.34.1
> > >

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Clear possible sticky bits on PICA message bus

[Kahola, Mika]

> -Original Message-
> From: Kahola, Mika 
> Sent: Friday, November 3, 2023 4:47 PM
> To: Kahola, Mika ; Sousa, Gustavo 
> ; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Syrjala, Ville 
> 
> Subject: RE: [PATCH] drm/i915/mtl: Clear possible sticky bits on PICA message 
> bus
> 
> > -Original Message-
> > From: Intel-gfx  On Behalf Of
> > Kahola, Mika
> > Sent: Thursday, November 2, 2023 4:54 PM
> > To: Sousa, Gustavo ;
> > intel-gfx@lists.freedesktop.org
> > Cc: Nikula, Jani ; Syrjala, Ville
> > 
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Clear possible sticky
> > bits on PICA message bus
> >
> > > -Original Message-
> > > From: Sousa, Gustavo 
> > > Sent: Thursday, November 2, 2023 4:23 PM
> > > To: Kahola, Mika ;
> > > intel-gfx@lists.freedesktop.org
> > > Cc: Kahola, Mika ; Nikula, Jani
> > > ; Syrjala, Ville 
> > > Subject: Re: [PATCH] drm/i915/mtl: Clear possible sticky bits on
> > > PICA message bus
> > >
> > > Quoting Mika Kahola (2023-11-01 07:31:01-03:00)
> > > >It is possible that sticky bits or error bits are left on message
> > > >bus status register. Reading and then writing the value back to
> > > >messagebus status register clears all possible sticky bits and errors.
> > > >
> > > >Signed-off-by: Mika Kahola 
> > > >---
> > > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 ++
> > > > 1 file changed, 14 insertions(+)
> > > >
> > > >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > >index b2ad4c6172f6..f439f0c7b400 100644
> > > >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > >@@ -195,6 +195,13 @@ static int __intel_cx0_read_once(struct 
> > > >drm_i915_private *i915, enum port port,
> > > > return -ETIMEDOUT;
> > > > }
> > > >
> > > >+/*
> > > >+ * write XELPDP_PORT_P2M_MSGBUS_STATUS register after read to 
> > > >clear
> > > >+ * any error sticky bits set from previous transactions
> > > >+ */
> > > >+val = intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, 
> > > >lane));
> > > >+intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port,
> > > >+ lane), val);
> > > >+
> > > > intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> > > >XELPDP_PORT_M2P_TRANSACTION_PENDING |
> > > >XELPDP_PORT_M2P_COMMAND_READ | @@ -262,6
> > > >+269,13 @@ static int __intel_cx0_write_once(struct
> > > >+drm_i915_private *i915, enum port port,
> > > > return -ETIMEDOUT;
> > > > }
> > > >
> > > >+/*
> > > >+ * write XELPDP_PORT_P2M_MSGBUS_STATUS register after read to 
> > > >clear
> > > >+ * any error sticky bits set from previous transactions
> > > >+ */
> > > >+val = intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, 
> > > >lane));
> > > >+intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port,
> > > >+ lane), val);
> > > >+
> > >
> > > Looking at the current state of the code, looks like to me that we 
> > > already clear the bits from both the "success" and "failure"
> > paths.
> > > For the "success"
> > > paths, that is done by a direct call to
> > > intel_clear_response_ready_flag(); for the "failure" case, the call
> > > to
> > > intel_clear_response_ready_flag() is done as part of 
> > > intel_cx0_bus_reset().
> > >
> > > Thus, considering that we start using the msgbus from a clean state,
> > > maybe these extra steps are not necessary? Have you tried adding a
> > > call to
> > > intel_cx0_bus_reset() as part of intel_cx0_phy_transaction_begin()?
> > That I haven't try to reset bus at the stage. I can give it a go and
> > check what happens. To me it seems, that we are sometimes stuck at
> > waiting the ack and eventually we time out and bail out. I have no
> > clue why this happens from time to time. We already reset the bus after 
> > every read/write operation. In addition, a small delay
> seem to help and clear the sporadic read/write failures to the bus. However, 
> this is more like a workaround and I'm not really
> happy about this sort of hack.
> >
> > I will give a go for your suggestion and come back once I have the results.
> 
> I ran a test with intel_cx0_bus_reset() when placed in 
> intel_cx0_phy_transaction_begin(). This didn't help either as with kms_flip
> IGT test I was able to trigger this read failure
> 
> [drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
> 
> This was with the configuration where the test vehicle had 4K and eDP 
> monitors connected.

I think we can ignore this patch. I was able to trigger this error with this 
patch applied as well. This doesn't fix the issue either.

Sorry for the noise.

-Mika-

> 
> 
> >
> > Thanks!
> > -Mika-
> >
> > >
> > > Also, I think it would be good if we understood better were those 
> > > uncleared bits are coming from...
> > >

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d is enabled

[Rodrigo Vivi]

On Thu, Nov 02, 2023 at 01:35:53PM -0300, Gustavo Sousa wrote:
> Quoting Radhakrishna Sripada (2023-11-02 13:06:44-03:00)
> >Experiments were conducted with different multipliers to VTD_GUARD macro
> >with multiplier of 185 we were observing occasional pipe faults when
> >running kms_cursor_legacy --run-subtest single-bo
> >
> >There could possibly be an underlying issue that is being investigated, for
> >now bump the guard pages for MTL.
> >
> >Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2017
> >Cc: Gustavo Sousa 
> >Cc: Chris Wilson 
> >Signed-off-by: Radhakrishna Sripada 
> >---
> > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c 
> >b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> >index 3770828f2eaf..b65f84c6bb3f 100644
> >--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> >+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> >@@ -456,6 +456,9 @@ i915_gem_object_pin_to_display_plane(struct 
> >drm_i915_gem_object *obj,
> > if (intel_scanout_needs_vtd_wa(i915)) {
> > unsigned int guard = VTD_GUARD;
> > 
> 
> I remember trying increasing the guard, but with a much smaller multiplier. So
> it turns out that using a much higher value did the "trick".

a much smaller multiplier could mess with the flags range?
it is really hard to understand what of that 'flags' is really those 12 flags
or what is this 'guard' and where that ends up...

> 
> I would add a FIXME comment here to remind us that this is a hack.
> 
> With the FIXME in place,
> 
> Reviewed-by: Gustavo Sousa 
> 
> >+if (IS_METEORLAKE(i915))
> >+guard *= 200;
> >+
> > if (i915_gem_object_is_tiled(obj))
> > guard = max(guard,
> > i915_gem_object_get_tile_row_size(obj));
> >-- 
> >2.34.1
> >

Re: [Intel-gfx] [PATCH] drm/i915: Skip pxp init if gt is wedged

[Rodrigo Vivi]

On Wed, Nov 01, 2023 at 02:44:46PM -0700, Zhanjun Dong wrote:
> The gt wedged could be triggered by missing guc firmware file, HW not
> working, etc. Once triggered, it means all gt usage is dead, therefore we
> can't enable pxp under this fatal error condition.
> 
> v2: Updated commit message.
> 
> Signed-off-by: Zhanjun Dong 
> ---
>  drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c 
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index dc327cf40b5a..923f233c91e1 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -212,6 +212,9 @@ int intel_pxp_init(struct drm_i915_private *i915)
>   if (!gt)
>   return -ENODEV;
>  
> + if (intel_gt_is_wedged(gt))
> + return -ENODEV;

we need some error message.
also we need to fix the fact that these returns are entirely ignored.

or you convert this function to void and then add a message here before
return; on this case.

Or you return some different error and at probe if error but error different
then ENODEV you print a message saying pxp init failed.

but we need some log/error information. I honestly would prefer to convert to
void and print the msg here.

with some changes like this you can count with my rv-b

> +
>   /*
>* At this point, we will either enable full featured PXP capabilities
>* including session and object management, or we will init the backend 
> tee
> -- 
> 2.34.1
> 

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d is enabled

[Sripada, Radhakrishna]

Hi Tvrtko,

> -Original Message-
> From: Tvrtko Ursulin 
> Sent: Friday, November 3, 2023 1:30 AM
> To: Sripada, Radhakrishna ; Hajda, Andrzej
> ; intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson 
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d 
> is
> enabled
> 
> 
> On 02/11/2023 22:14, Sripada, Radhakrishna wrote:
> > Hi Tvrtko,
> >
> >> -Original Message-
> >> From: Tvrtko Ursulin 
> >> Sent: Thursday, November 2, 2023 10:41 AM
> >> To: Hajda, Andrzej ; Sripada, Radhakrishna
> >> ; intel-gfx@lists.freedesktop.org
> >> Cc: Chris Wilson 
> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when 
> >> vt-d
> is
> >> enabled
> >>
> >>
> >> On 02/11/2023 16:58, Andrzej Hajda wrote:
> >>> On 02.11.2023 17:06, Radhakrishna Sripada wrote:
>  Experiments were conducted with different multipliers to VTD_GUARD
> macro
>  with multiplier of 185 we were observing occasional pipe faults when
>  running kms_cursor_legacy --run-subtest single-bo
> 
>  There could possibly be an underlying issue that is being
>  investigated, for
>  now bump the guard pages for MTL.
> 
>  Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2017
>  Cc: Gustavo Sousa 
>  Cc: Chris Wilson 
>  Signed-off-by: Radhakrishna Sripada 
>  ---
>     drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
>     1 file changed, 3 insertions(+)
> 
>  diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>  b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>  index 3770828f2eaf..b65f84c6bb3f 100644
>  --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>  +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>  @@ -456,6 +456,9 @@ i915_gem_object_pin_to_display_plane(struct
>  drm_i915_gem_object *obj,
>     if (intel_scanout_needs_vtd_wa(i915)) {
>     unsigned int guard = VTD_GUARD;
>  +    if (IS_METEORLAKE(i915))
>  +    guard *= 200;
>  +
> >>>
> >>> 200 * VTD_GUARD = 200 * 168 * 4K = 131MB
> >>>
> >>> Looks insanely high, 131MB for padding, if this is before and after it
> >>> becomes even 262MB of wasted address per plane. Just signalling, I do
> >>> not know if this actually hurts.
> >>
> >> Yeah this feels crazy. There must be some other explanation which is
> >> getting hidden by the crazy amount of padding so I'd rather we figured
> >> it out.
> >>
> >> With 262MiB per fb how many fit in GGTT before eviction hits? N screens
> >> with double/triple buffering?
> >
> > I believe with this method we will have to limit the no of frame buffers in 
> > the
> system. One alternative
> > that worked is to do a proper clear range for the ggtt instead of doing a 
> > nop.
> Although it adds marginal
> > time during suspend/resume/boot it does not add restrictions to the no of 
> > fb's
> that can be used.
> 
> And if we remember the guard pages replaced clearing to scratch, to
> improve suspend resume times, exactly for improving user experience. :(
> 
> Luckily there is time to fix this properly on MTL one way or the other.
> Is it just kms_cursor_legacy --run-subtest single-bo that is affected?

I am trying to dump the page table entries at the time of failure for bot the 
fame buffer and if required
For the guard pages. Will see if I get some info from there.

Yes the test kms_cursor_legacy is used to reliably reproduce. Looking at public 
CI, I also see pipe errors
being reported with varying occurrences while running kms_cursor_crc, 
kms_pipe_crc_basic,
and kms_plane_scaling. More details on the occurrence can be found here [1].

Thanks,
RK

1. 
http://gfx-ci.igk.intel.com/cibuglog-ng/results/knownfailures?query_key=d9c3297dd17dda35a6c638eb96b3139bd1a6633c

> 
> Regards,
> 
> Tvrtko
> 
> 
> >>
> >> Regards,
> >>
> >> Tvrtko
> >>
> >> P.S. Where did the 185 from the commit message come from?
> > 185 came from experiment to increase the guard size. It is not a standard
> number.
> >
> > Regards,
> > Radhakrishna(RK) Sripada

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Print SSEU information of all GTs for debugfs

[Matt Roper]

On Fri, Nov 03, 2023 at 11:17:18AM +, Tvrtko Ursulin wrote:
> 
> On 03/11/2023 05:29, Gareth Yu wrote:
> > Print another SSEU information addition to the first one.
> > 
> > Cc : Tejas Upadhyay 
> > Cc : Matt Roper 
> > Cc : Ville Syrjälä 
> > Signed-off-by: Gareth Yu 
> > ---
> >   drivers/gpu/drm/i915/i915_debugfs.c   | 13 ++---
> >   drivers/gpu/drm/i915/i915_gpu_error.c |  6 +-
> >   2 files changed, 15 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index e9b79c2c37d8..b5914a2c0597 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -63,13 +63,16 @@ static int i915_capabilities(struct seq_file *m, void 
> > *data)
> >   {
> > struct drm_i915_private *i915 = node_to_i915(m->private);
> > struct drm_printer p = drm_seq_file_printer(m);
> > +   struct intel_gt *gt;
> > +   unsigned int i;
> > seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
> > intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p);
> > intel_display_device_info_print(DISPLAY_INFO(i915), 
> > DISPLAY_RUNTIME_INFO(i915), &p);
> > i915_print_iommu_status(i915, &p);
> > -   intel_gt_info_print(&to_gt(i915)->info, &p);
> > +   for_each_gt(gt, i915, i)
> > +   intel_gt_info_print(>->info, &p);
> > intel_driver_caps_print(&i915->caps, &p);
> > kernel_param_lock(THIS_MODULE);
> > @@ -783,9 +786,13 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
> >   static int i915_sseu_status(struct seq_file *m, void *unused)
> >   {
> > struct drm_i915_private *i915 = node_to_i915(m->private);
> > -   struct intel_gt *gt = to_gt(i915);
> > +   struct intel_gt *gt;
> > +   unsigned int i;
> > +
> > +   for_each_gt(gt, i915, i)
> > +   intel_sseu_status(m, gt);
> 
> Don't we have the per GT debugfs directories and files already!?

Yeah, we shouldn't be updating this.  Commit a00eda7d8996 ("drm/i915:
Move sseu debugfs under gt/") notes:

"The sseu_status debugfs has also been kept at the top level as
we do have tests that use it; it will be removed once we teach
the tests to look into the new path."

If there are still IGT tests that haven't been updated, dumping both GTs
here will probably break them since they aren't expecting it.  If they
have all been updated, then we should just move forward with deleting
this device-level SSEU instead.

> 
> > -   return intel_sseu_status(m, gt);
> > +   return 0;
> >   }
> >   static int i915_forcewake_open(struct inode *inode, struct file *file)
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index b4e31e59c799..2adc317af944 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -722,9 +722,13 @@ static void err_print_gt_info(struct 
> > drm_i915_error_state_buf *m,
> >   struct intel_gt_coredump *gt)
> >   {
> > struct drm_printer p = i915_error_printer(m);
> > +   struct drm_i915_private *i915 = gt->_gt->i915;
> > +   struct intel_gt *gt_n;
> > +   unsigned int n;
> > intel_gt_info_print(>->info, &p);
> > -   intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p);
> > +   for_each_gt(gt_n, i915, n)
> > +   intel_sseu_print_topology(gt_n->i915, >_n->info.sseu, &p);
> 
> Do we need a consistent story across all error capture? Aka why is sseu
> special.
> 
> Also the intel_gt_info_print() above calls intel_sseu_dump so we end up with
> root tile SSEU printed twice?

I'm guessing this call was supposed to be deleted by 0b6613c6b91e
("drm/i915/sseu: Move sseu_info under gt_info").  We should probably go
ahead and do that now do remove the redundancy.

err_print_gt_info() should be printing the GT information (including
SSEU) for whichever GT had the error.  I don't see a reason why we'd
want to dump extra SSEU information for a different GT that wasn't
involved in the error.

Actually, SSEU is the _least_ useful thing to print for extra GTs
because once xehpsdv/pvc are gone from i915, the only platforms that
have multiple GTs are MTL/ARL and the SSEU information will always be
empty on the media GT (there's no DSS or EUs there).


Matt

> 
> There possibly was a Jira years ago to do stuff about multi-tile error
> capture but maybe it got lost.
> 
> Adding Andi if he has comments.
> 
> Regards,
> 
> Tvrtko
> 
> >   }
> >   static void err_print_gt_display(struct drm_i915_error_state_buf *m,

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d is enabled

[Sripada, Radhakrishna]

Hi Rodrigo,

> -Original Message-
> From: Vivi, Rodrigo 
> Sent: Friday, November 3, 2023 8:35 AM
> To: Sousa, Gustavo 
> Cc: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org; Chris Wilson 
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d 
> is
> enabled
> 
> On Thu, Nov 02, 2023 at 01:35:53PM -0300, Gustavo Sousa wrote:
> > Quoting Radhakrishna Sripada (2023-11-02 13:06:44-03:00)
> > >Experiments were conducted with different multipliers to VTD_GUARD macro
> > >with multiplier of 185 we were observing occasional pipe faults when
> > >running kms_cursor_legacy --run-subtest single-bo
> > >
> > >There could possibly be an underlying issue that is being investigated, for
> > >now bump the guard pages for MTL.
> > >
> > >Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2017
> > >Cc: Gustavo Sousa 
> > >Cc: Chris Wilson 
> > >Signed-off-by: Radhakrishna Sripada 
> > >---
> > > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> > >index 3770828f2eaf..b65f84c6bb3f 100644
> > >--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> > >+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> > >@@ -456,6 +456,9 @@ i915_gem_object_pin_to_display_plane(struct
> drm_i915_gem_object *obj,
> > > if (intel_scanout_needs_vtd_wa(i915)) {
> > > unsigned int guard = VTD_GUARD;
> > >
> >
> > I remember trying increasing the guard, but with a much smaller multiplier. 
> > So
> > it turns out that using a much higher value did the "trick".
> 
> a much smaller multiplier could mess with the flags range?
> it is really hard to understand what of that 'flags' is really those 12 flags
> or what is this 'guard' and where that ends up...
Based on my glance, if the multiplier fits in 32 bits then it should work. But 
the
problem here pointed out by Tvrtko is that we are adding awful lot(262 mb per 
fb) of padding
in the gurad pages clobbering up the ggtt address pace. Enough(10 to 20) fb's 
created we
will fall into the realm of evictions.

Regards,
Radhakrishna(RK) Sripada

> 
> >
> > I would add a FIXME comment here to remind us that this is a hack.
> >
> > With the FIXME in place,
> >
> > Reviewed-by: Gustavo Sousa 
> >
> > >+if (IS_METEORLAKE(i915))
> > >+guard *= 200;
> > >+
> > > if (i915_gem_object_is_tiled(obj))
> > > guard = max(guard,
> > > 
> > > i915_gem_object_get_tile_row_size(obj));
> > >--
> > >2.34.1
> > >

Re: [Intel-gfx] [PATCH i-g-t 1/9] tests/i915/drm_fdinfo: Check engine info is supported

[Kamil Konieczny]

Hi Tvrtko,
On 2023-10-12 at 09:15:39 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> On top of checking that parsing works, check that there are some engines
> present. This will be needed once the memory stats are added and so return
> value from __igt_parse_drm_fdinfo() will then be possible to be greater
> than zero even when engine stats are not supported.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  tests/intel/drm_fdinfo.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/tests/intel/drm_fdinfo.c b/tests/intel/drm_fdinfo.c
> index aca19db50680..344c44dce78b 100644
> --- a/tests/intel/drm_fdinfo.c
> +++ b/tests/intel/drm_fdinfo.c
> @@ -737,6 +737,7 @@ igt_main
>  
>   igt_require_gem(i915);
>   igt_require(igt_parse_drm_fdinfo(i915, &info, NULL, 0, NULL, 
> 0));
> + igt_require(info.num_engines);
>  
>   ctx = intel_ctx_create_all_physical(i915);
>  
> -- 
> 2.39.2
> 

Re: [Intel-gfx] [PATCH i-g-t 2/9] tests/i915/drm_fdinfo: Stress test context close versus fdinfo reads

[Kamil Konieczny]

Hi Tvrtko,
On 2023-10-12 at 09:15:40 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> A short smoke tests to exercise fdinfo reads in parallel to contexts
> getting created and destroyed.
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  tests/intel/drm_fdinfo.c | 68 
>  1 file changed, 68 insertions(+)
> 
> diff --git a/tests/intel/drm_fdinfo.c b/tests/intel/drm_fdinfo.c
> index 344c44dce78b..c4218b0d16e6 100644
> --- a/tests/intel/drm_fdinfo.c
> +++ b/tests/intel/drm_fdinfo.c
> @@ -22,11 +22,14 @@
>   *
>   */
>  
> +#include 
> +
>  #include "igt.h"
>  #include "igt_core.h"
>  #include "igt_device.h"
>  #include "igt_drm_fdinfo.h"
>  #include "i915/gem.h"
> +#include "i915/gem_create.h"
>  #include "i915/gem_vm.h"
>  #include "intel_ctx.h"
>  /**
> @@ -72,6 +75,8 @@
>   * SUBTEST: virtual-busy-idle-all
>   *
>   * SUBTEST: virtual-idle
> + *
> + * SUBTEST: context-close-stress
>   */
>  
>  IGT_TEST_DESCRIPTION("Test the i915 drm fdinfo data");
> @@ -717,6 +722,56 @@ virtual_all(int i915, const intel_ctx_cfg_t *base_cfg, 
> unsigned int flags)
>   }
>  }
>  
> +static void stress_context_close(int i915)
> +{
> + const uint32_t bbe = MI_BATCH_BUFFER_END;
> + struct igt_helper_process reader = { };
> + struct drm_client_fdinfo info;
> + uint32_t batch;
> + int dir, ret;
> + char buf[64];
> +
> + ret = snprintf(buf, sizeof(buf), "%u", i915);
> + igt_assert(ret > 0 && ret < sizeof(buf));
> +
> + dir = open("/proc/self/fdinfo", O_DIRECTORY | O_RDONLY);
> + igt_assert_fd(dir);
> +
> + memset(&info, 0, sizeof(info));
> + ret = __igt_parse_drm_fdinfo(dir, buf, &info, NULL, 0, NULL, 0);
> + igt_assert(ret > 0);

You repeat this pattern later, it can be made into
function:

igt_parse_drm_fdinfo(dir, buf, *info, p1, i1, p2, i2)
{
memset(info, 0, sizeof(*info));
ret = __igt_parse_drm_fdinfo(dir, buf, info, p1, i1, p2, i2);
igt_assert(ret > 0);
}

> + igt_require(info.num_regions);
> +
> + batch = gem_create(i915, 4096);
> + gem_write(i915, batch, 0, &bbe, sizeof(bbe));
> +
> + igt_fork_helper(&reader) {
> + for (;;) {
> + memset(&info, 0, sizeof(info));
> + ret = __igt_parse_drm_fdinfo(dir, buf, &info,
> +  NULL, 0, NULL, 0);
> + igt_assert(ret > 0);

Here you repeat this.

With or without makeing this a function,
Reviewed-by: Kamil Konieczny 

> + }
> + }
> +
> + igt_until_timeout(10) {
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = batch,
> + };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffers_ptr = to_user_pointer(&obj),
> + .buffer_count = 1,
> + };
> +
> + eb.rsvd1 = gem_context_create(i915);
> + igt_assert(eb.rsvd1);
> + gem_execbuf(i915, &eb);
> + gem_context_destroy(i915, eb.rsvd1);
> + }
> +
> + igt_stop_helper(&reader);
> +}
> +
>  #define test_each_engine(T, i915, ctx, e) \
>   igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
>   igt_dynamic_f("%s", e->name)
> @@ -848,6 +903,19 @@ igt_main
>   test_each_engine("isolation", i915, ctx, e)
>   single(i915, ctx, e, TEST_BUSY | TEST_ISOLATION);
>  
> + igt_subtest_group {
> + int newfd;
> +
> + igt_fixture
> + newfd = drm_reopen_driver(i915);
> +
> + igt_subtest("context-close-stress")
> + stress_context_close(newfd);
> +
> + igt_fixture
> + drm_close_driver(newfd);
> + }
> +
>   igt_fixture {
>   intel_ctx_destroy(i915, ctx);
>   drm_close_driver(i915);
> -- 
> 2.39.2
> 

Re: [Intel-gfx] [PATCH i-g-t 6/9] lib/igt_drm_clients: Allow passing in the memory region map

[Kamil Konieczny]

Hi Tvrtko,
On 2023-10-12 at 09:15:44 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Same concept as with the engine map, allowing callers to pass in fixed
> map of names to indices, simplifying their implementation and avoiding
> auto-detection while parsing.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  lib/igt_drm_clients.c | 5 +++--
>  lib/igt_drm_clients.h | 3 ++-
>  tools/gputop.c| 4 ++--
>  tools/intel_gpu_top.c | 8 +---
>  4 files changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
> index da51d7335b2b..025d60c51503 100644
> --- a/lib/igt_drm_clients.c
> +++ b/lib/igt_drm_clients.c
> @@ -445,7 +445,8 @@ struct igt_drm_clients *
>  igt_drm_clients_scan(struct igt_drm_clients *clients,
>bool (*filter_client)(const struct igt_drm_clients *,
>  const struct drm_client_fdinfo *),
> -  const char **name_map, unsigned int map_entries)
> +  const char **name_map, unsigned int map_entries,
> +  const char **region_map, unsigned int region_entries)
>  {
>   struct dirent *proc_dent;
>   struct igt_drm_client *c;
> @@ -524,7 +525,7 @@ igt_drm_clients_scan(struct igt_drm_clients *clients,
>   if (!__igt_parse_drm_fdinfo(dirfd(fdinfo_dir),
>   fdinfo_dent->d_name, &info,
>   name_map, map_entries,
> - NULL, 0))
> + region_map, region_entries))
>   continue;
>  
>   if (filter_client && !filter_client(clients, &info))
> diff --git a/lib/igt_drm_clients.h b/lib/igt_drm_clients.h
> index cd37f8508b20..52888aedc25a 100644
> --- a/lib/igt_drm_clients.h
> +++ b/lib/igt_drm_clients.h
> @@ -93,7 +93,8 @@ struct igt_drm_clients *
>  igt_drm_clients_scan(struct igt_drm_clients *clients,
>bool (*filter_client)(const struct igt_drm_clients *,
>  const struct drm_client_fdinfo *),
> -  const char **name_map, unsigned int map_entries);
> +  const char **name_map, unsigned int map_entries,
> +  const char **region_map, unsigned int region_entries);
>  
>  struct igt_drm_clients *
>  igt_drm_clients_sort(struct igt_drm_clients *clients,
> diff --git a/tools/gputop.c b/tools/gputop.c
> index ea95e0333dd2..71e28f43ee4c 100644
> --- a/tools/gputop.c
> +++ b/tools/gputop.c
> @@ -253,7 +253,7 @@ int main(int argc, char **argv)
>   if (!clients)
>   exit(1);
>  
> - igt_drm_clients_scan(clients, NULL, NULL, 0);
> + igt_drm_clients_scan(clients, NULL, NULL, 0, NULL, 0);
>  
>   for (;;) {
>   struct igt_drm_client *c, *prevc = NULL;
> @@ -270,7 +270,7 @@ int main(int argc, char **argv)
>   }
>   }
>  
> - igt_drm_clients_scan(clients, NULL, NULL, 0);
> + igt_drm_clients_scan(clients, NULL, NULL, 0, NULL, 0);
>   igt_drm_clients_sort(clients, client_cmp);
>  
>   printf("\033[H\033[J");
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 34fa99235e11..091fe28068dc 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -2619,8 +2619,9 @@ int main(int argc, char **argv)
>   }
>  
>   pmu_sample(engines);
> - igt_drm_clients_scan(clients, client_match, engine_map,
> -  ARRAY_SIZE(engine_map));
> + igt_drm_clients_scan(clients, client_match,
> +  engine_map, ARRAY_SIZE(engine_map),
> +  NULL, 0);
>   gettime(&ts);
>  
>   if (output_mode == JSON)
> @@ -2655,7 +2656,8 @@ int main(int argc, char **argv)
>   display_clients(igt_drm_clients_scan(clients,
>client_match,
>engine_map,
> -  
> ARRAY_SIZE(engine_map)));
> +  
> ARRAY_SIZE(engine_map),
> +  NULL, 0));
>   scan_us = elapsed_us(&ts, period_us);
>  
>   if (stop_top)
> -- 
> 2.39.2
> 

Re: [Intel-gfx] [PATCH i-g-t 5/9] lib/igt_drm_clients: Fix client id type confusion

[Kamil Konieczny]

Hi Tvrtko,
On 2023-10-12 at 09:15:43 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Igt_drm_fdinfo defines it as an unsigned long so it is best that it
> matches here as well.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  lib/igt_drm_clients.c | 2 +-
>  lib/igt_drm_clients.h | 2 +-
>  tools/intel_gpu_top.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/lib/igt_drm_clients.c b/lib/igt_drm_clients.c
> index 47ad137d5f1f..da51d7335b2b 100644
> --- a/lib/igt_drm_clients.c
> +++ b/lib/igt_drm_clients.c
> @@ -49,7 +49,7 @@ struct igt_drm_clients *igt_drm_clients_init(void 
> *private_data)
>  static struct igt_drm_client *
>  igt_drm_clients_find(struct igt_drm_clients *clients,
>enum igt_drm_client_status status,
> -  unsigned int drm_minor, unsigned int id)
> +  unsigned int drm_minor, unsigned long id)
>  {
>   unsigned int start, num;
>   struct igt_drm_client *c;
> diff --git a/lib/igt_drm_clients.h b/lib/igt_drm_clients.h
> index 07bd236d43bf..cd37f8508b20 100644
> --- a/lib/igt_drm_clients.h
> +++ b/lib/igt_drm_clients.h
> @@ -56,7 +56,7 @@ struct igt_drm_client {
>   enum igt_drm_client_status status;
>   struct igt_drm_client_regions *regions; /* Memory regions present in 
> this client, to map with memory usage. */
>   struct igt_drm_client_engines *engines; /* Engines used by this client, 
> to map with busynees data. */
> - unsigned int id; /* DRM client id from fdinfo. */
> + unsigned long id; /* DRM client id from fdinfo. */
>   unsigned int drm_minor; /* DRM minor of this client. */
>   unsigned int pid; /* PID which has this DRM fd open. */
>   char pid_str[10]; /* Cached PID representation. */
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 00506c63db4e..34fa99235e11 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -2106,7 +2106,7 @@ print_client(struct igt_drm_client *c, struct engines 
> *engines, double t, int li
>   } else if (output_mode == JSON) {
>   char buf[64];
>  
> - snprintf(buf, sizeof(buf), "%u", c->id);
> + snprintf(buf, sizeof(buf), "%lu", c->id);
>   pops->open_struct(buf);
>  
>   __json_add_member("name", c->print_name);
> -- 
> 2.39.2
> 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 4/9] lib/igt_drm_fdinfo: Copy over region map name on match

[Kamil Konieczny]

Hi Tvrtko,
On 2023-10-12 at 09:15:42 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> I will need some record of which regions were found for intel_gpu_top so
> lets just copy over the region name from the map on the first match.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  lib/igt_drm_fdinfo.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
> index b72822894782..222ccbfb1fd6 100644
> --- a/lib/igt_drm_fdinfo.c
> +++ b/lib/igt_drm_fdinfo.c
> @@ -148,6 +148,10 @@ static int parse_region(char *line, struct 
> drm_client_fdinfo *info,
>   for (i = 0; i < region_entries; i++) {
>   if (!strncmp(name, region_map[i], name_len)) {
>   found = i;
> + if (!info->region_names[info->num_regions][0]) {
> + assert(name_len < 
> sizeof(info->region_names[i]));
> + strncpy(info->region_names[i], name, 
> name_len);
> + }
>   break;
>   }
>   }
> -- 
> 2.39.2
> 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 7/9] tools/intel_gpu_top: Fully wrap clients operations

[Kamil Konieczny]

Hi Tvrtko,
On 2023-10-12 at 09:15:45 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Wrap all operations on clients via the Intel specific wrappers in order to
> simplify upcoming work.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  tools/intel_gpu_top.c | 42 ++
>  1 file changed, 22 insertions(+), 20 deletions(-)
> 
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 091fe28068dc..b2e81d5f9ffb 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -132,6 +132,7 @@ struct engines {
>  struct intel_clients {
>   const char *pci_slot;
>   struct igt_drm_client_engines classes;
> + struct igt_drm_clients *clients;
>  };
>  
>  static struct termios termios_orig;
> @@ -2436,19 +2437,22 @@ intel_init_clients(struct intel_clients *iclients,
>   iclients->classes.capacity[i] = engines->class[i].num_engines;
>   iclients->classes.names[i] = strdup(engines->class[i].name);
>   }
> +
> + iclients->clients = igt_drm_clients_init(iclients);
>  }
>  
>  static void intel_free_clients(struct intel_clients *iclients)
>  {
> + if (iclients->clients)
> + igt_drm_clients_free(iclients->clients);
> +
>   free((void *)iclients->pci_slot);
>   free(iclients->classes.capacity);
>   free(iclients->classes.names);
>  }
>  
> -int main(int argc, char **argv)
> +static void intel_scan_clients(struct intel_clients *iclients)
>  {
> - unsigned int period_us = DEFAULT_PERIOD_MS * 1000;
> - struct igt_drm_clients *clients = NULL;
>   static const char *engine_map[] = {
>   "render",
>   "copy",
> @@ -2456,6 +2460,15 @@ int main(int argc, char **argv)
>   "video-enhance",
>   "compute",
>   };
> +
> + igt_drm_clients_scan(iclients->clients, client_match,
> +  engine_map, ARRAY_SIZE(engine_map),
> +  NULL, 0);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + unsigned int period_us = DEFAULT_PERIOD_MS * 1000;
>   bool physical_engines = false;
>   struct intel_clients iclients;
>   int con_w = -1, con_h = -1;
> @@ -2613,15 +2626,11 @@ int main(int argc, char **argv)
>  
>   init_engine_classes(engines);
>  
> - if (has_drm_fdinfo(&card)) {
> + if (has_drm_fdinfo(&card))
>   intel_init_clients(&iclients, &card, engines);
> - clients = igt_drm_clients_init(&iclients);
> - }
>  
>   pmu_sample(engines);
> - igt_drm_clients_scan(clients, client_match,
> -  engine_map, ARRAY_SIZE(engine_map),
> -  NULL, 0);
> + intel_scan_clients(&iclients);
>   gettime(&ts);
>  
>   if (output_mode == JSON)
> @@ -2652,12 +2661,8 @@ int main(int argc, char **argv)
>   pmu_sample(engines);
>   t = (double)(engines->ts.cur - engines->ts.prev) / 1e9;
>  
> - disp_clients =
> - display_clients(igt_drm_clients_scan(clients,
> -  client_match,
> -  engine_map,
> -  
> ARRAY_SIZE(engine_map),
> -  NULL, 0));
> + intel_scan_clients(&iclients);
> + disp_clients = display_clients(iclients.clients);
>   scan_us = elapsed_us(&ts, period_us);
>  
>   if (stop_top)
> @@ -2708,7 +2713,7 @@ int main(int argc, char **argv)
>   pops->close_struct();
>   }
>  
> - if (disp_clients != clients)
> + if (disp_clients != iclients.clients)
>   free_display_clients(disp_clients);
>  
>   if (stop_top)
> @@ -2723,10 +2728,7 @@ int main(int argc, char **argv)
>   if (output_mode == JSON)
>   printf("]\n");
>  
> - if (clients) {
> - igt_drm_clients_free(clients);
> - intel_free_clients(&iclients);
> - }
> + intel_free_clients(&iclients);
>  
>   free(codename);
>  err_pmu:
> -- 
> 2.39.2
> 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 8/9] tools/intel_gpu_top: Add per client memory info

[Kamil Konieczny]

Hi Tvrtko,
On 2023-10-12 at 09:15:46 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> JSON output has the full breakdown but for now the interactive mode only
> shows total and resident aggregated for all memory regions.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  tools/intel_gpu_top.c | 114 +-
>  1 file changed, 112 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index b2e81d5f9ffb..2c09895c79dd 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -133,11 +133,24 @@ struct intel_clients {
>   const char *pci_slot;
>   struct igt_drm_client_engines classes;
>   struct igt_drm_clients *clients;
> + struct igt_drm_client_regions *regions; /* Borrowed from first client */
>  };
>  
>  static struct termios termios_orig;
>  static bool class_view;
>  
> +/* Maps i915 fdinfo names to indices */
> +static const char *memory_region_map[] = {
> + "system0",
> + "local0",
> +};
> +
> +/* For JSON, 1:1 with indices above. */
> +static const char *json_memory_region_names[] = {
> + "system",
> + "local",
> +};
> +
>  __attribute__((format(scanf,3,4)))
>  static int igt_sysfs_scanf(int dir, const char *attr, const char *fmt, ...)
>  {
> @@ -882,6 +895,9 @@ static struct igt_drm_clients *display_clients(struct 
> igt_drm_clients *clients)
>   ac->val = calloc(c->engines->max_engine_id + 1,
>sizeof(ac->val[0]));
>   assert(ac->val);
> + ac->regions = c->regions;
> + ac->memory = calloc(c->regions->max_region_id + 1,
> + sizeof(ac->memory[0]));
>   ac->samples = 1;
>   }
>  
> @@ -896,6 +912,14 @@ static struct igt_drm_clients *display_clients(struct 
> igt_drm_clients *clients)
>  
>   for (i = 0; i <= c->engines->max_engine_id; i++)
>   ac->val[i] += c->val[i];
> +
> + for (i = 0; i <= c->regions->max_region_id; i++) {
> + ac->memory[i].total += c->memory[i].total;
> + ac->memory[i].shared += c->memory[i].shared;
> + ac->memory[i].resident += c->memory[i].resident;
> + ac->memory[i].purgeable += c->memory[i].purgeable;
> + ac->memory[i].active += c->memory[i].active;
> + }
>   }
>  
>   aggregated->num_clients = num;
> @@ -920,8 +944,10 @@ static void free_display_clients(struct igt_drm_clients 
> *clients)
>* "display" clients are not proper clients and have un-initialized
>* or borrowed fields which we don't want the library to try and free.
>*/
> - igt_for_each_drm_client(clients, c, tmp)
> + igt_for_each_drm_client(clients, c, tmp) {
>   free(c->val);
> + free(c->memory);
> + }
>  
>   free(clients->client);
>   free(clients);
> @@ -2016,6 +2042,9 @@ print_clients_header(struct igt_drm_clients *clients, 
> int lines,
>   if (lines++ >= con_h || len >= con_w)
>   return lines;
>  
> + if (iclients->regions)
> + len += printf(" MEM  RSS ");
> +
>   if (iclients->classes.num_engines) {
>   unsigned int i;
>   int width;
> @@ -2059,6 +2088,20 @@ print_clients_header(struct igt_drm_clients *clients, 
> int lines,
>  static bool numeric_clients;
>  static bool filter_idle;
>  
> +static int print_size(uint64_t sz)
> +{
> + char units[] = { ' ', 'K', 'M', 'G' };
> + unsigned int u;
> +
> + for (u = 0; u < ARRAY_SIZE(units) - 1; u++) {
> + if (sz & 1023 || sz < 1024)
> + break;
> + sz /= 1024;
> + }
> +
> + return printf("%7"PRIu64"%c ", sz, units[u]);
> +}
> +
>  static int
>  print_client(struct igt_drm_client *c, struct engines *engines, double t, 
> int lines,
>int con_w, int con_h, unsigned int period_us, int *class_w)
> @@ -2076,6 +2119,18 @@ print_client(struct igt_drm_client *c, struct engines 
> *engines, double t, int li
>  
>   len = printf("%*s ", clients->max_pid_len, c->pid_str);
>  
> + if (iclients->regions) {
> + uint64_t sz;
> +
> + for (sz = 0, i = 0; i <= c->regions->max_region_id; i++)
> + sz += c->memory[i].total;
> + len += print_size(sz);
> +
> + for (sz = 0, i = 0; i <= c->regions->max_region_id; i++)
> + sz += c->memory[i].resident;
> + len += print_size(sz);
> + }
> +
>   for (i = 0; i <= iclients->classes.max_engine_id; i++) {
>   double pct, max;
>  
> @@ -2115,6 +2170,42 @@ print_clie

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 9/9] tools/intel_gpu_top: Add ability to show memory region breakdown

[Kamil Konieczny]

Hi Tvrtko,
On 2023-10-12 at 09:15:47 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Similar as we can toggle between aggregated engines and clients, add the
> capability to toggle between aggregated and per memory region stats.
> 
> It starts in aggregated mode by default and interactive command 'm' and
> command line switch '-m' can be used to toggle that.
> 
> Both only affect the interactive view, while JSON output always contains
> separate memory regions.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  man/intel_gpu_top.rst |  4 
>  tools/intel_gpu_top.c | 55 ++-
>  2 files changed, 48 insertions(+), 11 deletions(-)
> 
> diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
> index 9499f87f1b4d..44a54a5f219d 100644
> --- a/man/intel_gpu_top.rst
> +++ b/man/intel_gpu_top.rst
> @@ -55,6 +55,9 @@ OPTIONS
>  -p
> Default to showing physical engines instead of aggregated classes.
>  
> +-m
> +   Default to showing all memory regions separately.
> +
>  RUNTIME CONTROL
>  ===
>  
> @@ -68,6 +71,7 @@ Supported keys:
>  |'s'Toggle between sort modes (runtime, total runtime, pid, client 
> id).
>  |'i'Toggle display of clients which used no GPU time.
>  |'H'Toggle between per PID aggregation and individual clients.
> +|'m'Toggle between aggregated memory regions and full breakdown.
>  
>  DEVICE SELECTION
>  
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index 2c09895c79dd..046ead15a122 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -138,6 +138,7 @@ struct intel_clients {
>  
>  static struct termios termios_orig;
>  static bool class_view;
> +static bool aggregate_regions;
>  
>  /* Maps i915 fdinfo names to indices */
>  static const char *memory_region_map[] = {
> @@ -1050,6 +1051,7 @@ usage(const char *appname)
>   "\t[-L]List all cards.\n"
>   "\t[-d ]   Device filter, please check manual page for 
> more details.\n"
>   "\t[-p]Default to showing physical engines instead 
> of classes.\n"
> + "\t[-m]Default to showing all memory regions.\n"
>   "\n",
>   appname, DEFAULT_PERIOD_MS);
>   igt_device_print_filter_types();
> @@ -2032,6 +2034,7 @@ print_clients_header(struct igt_drm_clients *clients, 
> int lines,
>  
>   if (output_mode == INTERACTIVE) {
>   int len, num_active = 0;
> + unsigned int i;
>  
>   if (lines++ >= con_h)
>   return lines;
> @@ -2042,11 +2045,17 @@ print_clients_header(struct igt_drm_clients *clients, 
> int lines,
>   if (lines++ >= con_h || len >= con_w)
>   return lines;
>  
> - if (iclients->regions)
> - len += printf(" MEM  RSS ");
> + if (iclients->regions) {
> + if (aggregate_regions) {
> + len += printf(" MEM  RSS ");
> + } else {
> + len += printf(" RAM  RSS ");
> + if (iclients->regions->num_regions > 1)
> + len += printf("VRAM VRSS ");
> + }
> + }
>  
>   if (iclients->classes.num_engines) {
> - unsigned int i;
>   int width;
>  
>   for (i = 0; i <= iclients->classes.max_engine_id; i++) {
> @@ -2120,15 +2129,26 @@ print_client(struct igt_drm_client *c, struct engines 
> *engines, double t, int li
>   len = printf("%*s ", clients->max_pid_len, c->pid_str);
>  
>   if (iclients->regions) {
> - uint64_t sz;
> + if (aggregate_regions) {
> + uint64_t sz;
>  
> - for (sz = 0, i = 0; i <= c->regions->max_region_id; i++)
> - sz += c->memory[i].total;
> - len += print_size(sz);
> + for (sz = 0, i = 0;
> +  i <= c->regions->max_region_id; i++)
> + sz += c->memory[i].total;
> + len += print_size(sz);
>  
> - for (sz = 0, i = 0; i <= c->regions->max_region_id; i++)
> - sz += c->memory[i].resident;
> - len += print_size(sz);
> + for (sz = 0, i = 0;
> +  i <= c->regions->max_region_id; i++)
> + sz += c->memory[i].resident;
> + len += print_size(sz);
> + } else {
> + len += print_size(c->memory[0].total);
> + len += prin

Re: [Intel-gfx] [PATCH i-g-t 3/9] tests/i915/drm_fdinfo: Add some memory info tests

[Kamil Konieczny]

Hi Tvrtko,
On 2023-10-12 at 09:15:41 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> A few basic smoke tests to check per client memory info looks legit.
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: Kamil Konieczny 

> ---
>  tests/intel/drm_fdinfo.c | 217 +++
>  1 file changed, 217 insertions(+)
> 
> diff --git a/tests/intel/drm_fdinfo.c b/tests/intel/drm_fdinfo.c
> index c4218b0d16e6..3ced658f2faa 100644
> --- a/tests/intel/drm_fdinfo.c
> +++ b/tests/intel/drm_fdinfo.c
> @@ -23,6 +23,7 @@
>   */
>  
>  #include 
> +#include 
>  
>  #include "igt.h"
>  #include "igt_core.h"
> @@ -76,6 +77,16 @@
>   *
>   * SUBTEST: virtual-idle
>   *
> + * SUBTEST: memory-info-idle
> + *
> + * SUBTEST: memory-info-active
> + *
> + * SUBTEST: memory-info-resident
> + *
> + * SUBTEST: memory-info-purgeable
> + *
> + * SUBTEST: memory-info-shared
> + *
>   * SUBTEST: context-close-stress
>   */
>  
> @@ -143,6 +154,11 @@ static unsigned int measured_usleep(unsigned int usec)
>  #define FLAG_HANG (8)
>  #define TEST_ISOLATION (16)
>  
> +#define TEST_ACTIVE TEST_BUSY
> +#define TEST_RESIDENT (32)
> +#define TEST_PURGEABLE (64)
> +#define TEST_SHARED (128)
> +
>  static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>  {
>   if (!spin)
> @@ -772,6 +788,172 @@ static void stress_context_close(int i915)
>   igt_stop_helper(&reader);
>  }
>  
> +static size_t read_fdinfo(char *buf, const size_t sz, int at, const char 
> *name)
> +{
> + size_t count;
> + int fd;
> +
> + fd = openat(at, name, O_RDONLY);
> + if (fd < 0)
> + return 0;
> +
> + count = read(fd, buf, sz - 1);
> + if (count > 0)
> + buf[count - 1] = 0;
> + close(fd);
> +
> + return count > 0 ? count : 0;
> +}
> +
> +/*
> + * At least this much, but maybe less if we started with a driver internal
> + * baseline which can go away behind our back.
> + */
> +#define fdinfo_assert_gte(cur, prev, sz, base) \
> +({ \
> + int64_t __sz = (sz) - (base); \
> + int64_t __d = (cur) - (prev); \
> + igt_assert_f(__d >= __sz, \
> +  "prev=%"PRIu64" cur=%"PRIu64" delta=%"PRId64" sz=%"PRIu64" 
> baseline=%"PRIu64"\n%s\n", \
> +  (prev), (cur), __d, (sz), (base), fdinfo_buf); \
> +})
> +
> +#define fdinfo_assert_eq(cur, prev, sz, base) \
> +({ \
> + int64_t __d = (cur) - (prev); \
> + igt_assert_f(__d == 0, \
> +  "prev=%"PRIu64" cur=%"PRIu64" delta=%"PRId64" sz=%"PRIu64" 
> baseline=%"PRIu64"\n%s\n", \
> +  (prev), (cur), __d, (sz), (base), fdinfo_buf); \
> +})
> +
> +static void
> +test_memory(int i915, struct gem_memory_region *mr, unsigned int flags)
> +{
> + const unsigned int r = mr->ci.memory_class == I915_MEMORY_CLASS_SYSTEM 
> ? 0 : 1; /* See region map */
> + const uint64_t max_mem = 512ull * 1024 * 1024;
> + const uint64_t max_bo = 16ull * 1024 * 1024;
> + struct drm_client_fdinfo base_info, prev_info = { };
> + struct drm_client_fdinfo info = { };
> + char buf[64], fdinfo_buf[4096];
> + igt_spin_t *spin = NULL;
> + uint64_t total = 0, sz;
> + uint64_t ahnd;
> + int ret, dir;
> +
> + i915 = drm_reopen_driver(i915);
> +
> + ahnd = get_reloc_ahnd(i915, 0);
> +
> + ret = snprintf(buf, sizeof(buf), "%u", i915);
> + igt_assert(ret > 0 && ret < sizeof(buf));
> +
> + dir = open("/proc/self/fdinfo", O_DIRECTORY | O_RDONLY);
> + igt_assert_fd(dir);
> +
> + gem_quiescent_gpu(i915);
> + ret =  __igt_parse_drm_fdinfo(dir, buf, &info, NULL, 0, NULL, 0);
> + igt_assert(ret > 0);
> + igt_require(info.num_regions);
> + memcpy(&prev_info, &info, sizeof(info));
> + memcpy(&base_info, &info, sizeof(info));
> +
> + while (total < max_mem) {
> + static const char *region_map[] = {
> + "system0",
> + "local0",
> + };
> + uint32_t bo;
> +
> + sz = random() % max_bo;
> + ret = __gem_create_in_memory_region_list(i915, &bo, &sz, 0,
> +  &mr->ci, 1);
> + igt_assert_eq(ret, 0);
> + total += sz;
> +
> + if (flags & (TEST_RESIDENT | TEST_PURGEABLE | TEST_ACTIVE))
> + spin = igt_spin_new(i915,
> + .dependency = bo,
> + .ahnd = ahnd);
> + else
> + spin = NULL;
> +
> + if (flags & TEST_PURGEABLE) {
> + gem_madvise(i915, bo, I915_MADV_DONTNEED);
> + igt_spin_free(i915, spin);
> + gem_quiescent_gpu(i915);
> + spin = NULL;
> + }
> +
> + if (flags & TEST_SHARED) {
> + struct drm_gem_open open_struct;
> + struct drm_gem_flink flink;
> +
> +   

Re: [Intel-gfx] [PATCH v3 14/15] drm/i915/dsi: Replace poking of CHV GPIOs behind the driver's back

[kernel test robot]

Hi Andy,

kernel test robot noticed the following build errors:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-intel/for-linux-next-fixes linus/master v6.6 
next-20231103]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:
https://github.com/intel-lab-lkp/linux/commits/Andy-Shevchenko/drm-i915-dsi-assume-BXT-gpio-works-for-non-native-GPIO/20231103-064642
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:
https://lore.kernel.org/r/20231102151228.668842-15-andriy.shevchenko%40linux.intel.com
patch subject: [PATCH v3 14/15] drm/i915/dsi: Replace poking of CHV GPIOs 
behind the driver's back
config: x86_64-rhel-8.3-rust 
(https://download.01.org/0day-ci/archive/20231104/202311040312.tf6btkw0-...@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git 
ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): 
(https://download.01.org/0day-ci/archive/20231104/202311040312.tf6btkw0-...@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot 
| Closes: 
https://lore.kernel.org/oe-kbuild-all/202311040312.tf6btkw0-...@intel.com/

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_dsi_vbt.c:272:4: error: call to 
>> undeclared function 'soc_exec_opaque_gpio'; ISO C99 and later do not support 
>> implicit function declarations [-Wimplicit-function-declaration]
   soc_exec_opaque_gpio(connector, gpio_index, 
"INT33FF:03", "Panel SE",
   ^
   drivers/gpu/drm/i915/display/intel_dsi_vbt.c:275:4: error: call to 
undeclared function 'soc_exec_opaque_gpio'; ISO C99 and later do not support 
implicit function declarations [-Wimplicit-function-declaration]
   soc_exec_opaque_gpio(connector, gpio_index, 
"INT33FF:00", "Panel SW",
   ^
   drivers/gpu/drm/i915/display/intel_dsi_vbt.c:278:4: error: call to 
undeclared function 'soc_exec_opaque_gpio'; ISO C99 and later do not support 
implicit function declarations [-Wimplicit-function-declaration]
   soc_exec_opaque_gpio(connector, gpio_index, 
"INT33FF:02", "Panel E",
   ^
   drivers/gpu/drm/i915/display/intel_dsi_vbt.c:281:4: error: call to 
undeclared function 'soc_exec_opaque_gpio'; ISO C99 and later do not support 
implicit function declarations [-Wimplicit-function-declaration]
   soc_exec_opaque_gpio(connector, gpio_index, 
"INT33FF:01", "Panel N",
   ^
   drivers/gpu/drm/i915/display/intel_dsi_vbt.c:299:3: error: call to 
undeclared function 'soc_exec_opaque_gpio'; ISO C99 and later do not support 
implicit function declarations [-Wimplicit-function-declaration]
   soc_exec_opaque_gpio(connector, gpio_index, "INT33FF:01", 
"Panel N",
   ^
   5 errors generated.


vim +/soc_exec_opaque_gpio +272 drivers/gpu/drm/i915/display/intel_dsi_vbt.c

   263  
   264  static void chv_gpio_set_value(struct intel_connector *connector,
   265 u8 gpio_source, u8 gpio_index, bool 
value)
   266  {
   267  struct drm_i915_private *dev_priv = 
to_i915(connector->base.dev);
   268  
   269  if (connector->panel.vbt.dsi.seq_version >= 3) {
   270  if (gpio_index >= CHV_GPIO_IDX_START_SE) {
   271  /* XXX: it's unclear whether 255->57 is part of 
SE. */
 > 272  soc_exec_opaque_gpio(connector, gpio_index, 
 > "INT33FF:03", "Panel SE",
   273   gpio_index - 
CHV_GPIO_IDX_START_SW, value);
   274  } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
   275  soc_exec_opaque_gpio(connector, gpio_index, 
"INT33FF:00", "Panel SW",
   276   gpio_index - 
CHV_GPIO_IDX_START_SW, value);
   277  } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
   278  soc_exec_opaque_gpio(connector, gpio_index, 
"INT33FF:02", "Panel E",
   279   gpio_index - 
CHV_GPIO_IDX_START_E, value);
   280  } else {
   281  soc_exec_opaque_gpio(connector, gpio_index, 
"INT33FF:01", "Panel N",
   282   

Re: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching into DMA for MTL

[Sripada, Radhakrishna]

Hi Jonathan,

> -Original Message-
> From: Intel-gfx  On Behalf Of 
> Jonathan
> Cavitt
> Sent: Thursday, November 2, 2023 10:59 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, saurabhg ; Cavitt, Jonathan
> ; chris.p.wil...@linux.intel.com
> Subject: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching into
> DMA for MTL
> 
> FIXME: It is suspected that some Address Translation Service (ATS)
> issue on IOMMU is causing CAT errors to occur on some MTL workloads.
> Applying a write barrier to the ppgtt set entry functions appeared
> to have no effect, so we must temporarily use I915_MAP_WC in the
> map_pt_dma class of functions on MTL until a proper ATS solution is
> found.
> 
What is the performance impact here? Are we disabling caching only
for the pte changes/scratch pages or does it extend beyond?

Regards,
Radhakrishna(RK) Sripada 
> Signed-off-by: Jonathan Cavitt 
> CC: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/gt/intel_gtt.c | 20 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
> b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 4fbed27ef0ecc..21719563a602a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -95,6 +95,16 @@ int map_pt_dma(struct i915_address_space *vm, struct
> drm_i915_gem_object *obj)
>   void *vaddr;
> 
>   type = intel_gt_coherent_map_type(vm->gt, obj, true);
> + /*
> +  * FIXME: It is suspected that some Address Translation Service (ATS)
> +  * issue on IOMMU is causing CAT errors to occur on some MTL
> workloads.
> +  * Applying a write barrier to the ppgtt set entry functions appeared
> +  * to have no effect, so we must temporarily use I915_MAP_WC here on
> +  * MTL until a proper ATS solution is found.
> +  */
> + if (IS_METEORLAKE(vm->i915))
> + type = I915_MAP_WC;
> +
>   vaddr = i915_gem_object_pin_map_unlocked(obj, type);
>   if (IS_ERR(vaddr))
>   return PTR_ERR(vaddr);
> @@ -109,6 +119,16 @@ int map_pt_dma_locked(struct i915_address_space
> *vm, struct drm_i915_gem_object
>   void *vaddr;
> 
>   type = intel_gt_coherent_map_type(vm->gt, obj, true);
> + /*
> +  * FIXME: It is suspected that some Address Translation Service (ATS)
> +  * issue on IOMMU is causing CAT errors to occur on some MTL
> workloads.
> +  * Applying a write barrier to the ppgtt set entry functions appeared
> +  * to have no effect, so we must temporarily use I915_MAP_WC here on
> +  * MTL until a proper ATS solution is found.
> +  */
> + if (IS_METEORLAKE(vm->i915))
> + type = I915_MAP_WC;
> +
>   vaddr = i915_gem_object_pin_map(obj, type);
>   if (IS_ERR(vaddr))
>   return PTR_ERR(vaddr);
> --
> 2.25.1

Re: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching into DMA for MTL

[Cavitt, Jonathan]

-Original Message-
From: Sripada, Radhakrishna  
Sent: Friday, November 3, 2023 1:02 PM
To: Cavitt, Jonathan ; 
intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; Cavitt, Jonathan 
; chris.p.wil...@linux.intel.com
Subject: RE: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching 
into DMA for MTL
> 
> Hi Jonathan,
> 
> > -Original Message-
> > From: Intel-gfx  On Behalf Of 
> > Jonathan
> > Cavitt
> > Sent: Thursday, November 2, 2023 10:59 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Gupta, saurabhg ; Cavitt, Jonathan
> > ; chris.p.wil...@linux.intel.com
> > Subject: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching 
> > into
> > DMA for MTL
> > 
> > FIXME: It is suspected that some Address Translation Service (ATS)
> > issue on IOMMU is causing CAT errors to occur on some MTL workloads.
> > Applying a write barrier to the ppgtt set entry functions appeared
> > to have no effect, so we must temporarily use I915_MAP_WC in the
> > map_pt_dma class of functions on MTL until a proper ATS solution is
> > found.
> > 
> What is the performance impact here? Are we disabling caching only
> for the pte changes/scratch pages or does it extend beyond?


I don't actually know what map_pt_dma is used for, but if the name is
indicative of its purpose, it should only impact mappings into the dma
page table.
As for the performance impact, I don't imagine it'll be much.  Maybe
a single-digit percentage slowdown?  It might actually improve
performance if we're avoiding enough cache misses, but the true
performance impact would have to be measured empirically.
-Jonathan Cavitt


> 
> Regards,
> Radhakrishna(RK) Sripada 
> > Signed-off-by: Jonathan Cavitt 
> > CC: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gtt.c | 20 
> >  1 file changed, 20 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > index 4fbed27ef0ecc..21719563a602a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > @@ -95,6 +95,16 @@ int map_pt_dma(struct i915_address_space *vm, struct
> > drm_i915_gem_object *obj)
> > void *vaddr;
> > 
> > type = intel_gt_coherent_map_type(vm->gt, obj, true);
> > +   /*
> > +* FIXME: It is suspected that some Address Translation Service (ATS)
> > +* issue on IOMMU is causing CAT errors to occur on some MTL
> > workloads.
> > +* Applying a write barrier to the ppgtt set entry functions appeared
> > +* to have no effect, so we must temporarily use I915_MAP_WC here on
> > +* MTL until a proper ATS solution is found.
> > +*/
> > +   if (IS_METEORLAKE(vm->i915))
> > +   type = I915_MAP_WC;
> > +
> > vaddr = i915_gem_object_pin_map_unlocked(obj, type);
> > if (IS_ERR(vaddr))
> > return PTR_ERR(vaddr);
> > @@ -109,6 +119,16 @@ int map_pt_dma_locked(struct i915_address_space
> > *vm, struct drm_i915_gem_object
> > void *vaddr;
> > 
> > type = intel_gt_coherent_map_type(vm->gt, obj, true);
> > +   /*
> > +* FIXME: It is suspected that some Address Translation Service (ATS)
> > +* issue on IOMMU is causing CAT errors to occur on some MTL
> > workloads.
> > +* Applying a write barrier to the ppgtt set entry functions appeared
> > +* to have no effect, so we must temporarily use I915_MAP_WC here on
> > +* MTL until a proper ATS solution is found.
> > +*/
> > +   if (IS_METEORLAKE(vm->i915))
> > +   type = I915_MAP_WC;
> > +
> > vaddr = i915_gem_object_pin_map(obj, type);
> > if (IS_ERR(vaddr))
> > return PTR_ERR(vaddr);
> > --
> > 2.25.1
> 
> 

[Intel-gfx] [PATCH v4 02/16] drm/i915/dsi: switch mipi_exec_gpio() from dev_priv to i915

[Andy Shevchenko]

From: Jani Nikula 

Follow the contemporary conventions.

Cc: Andy Shevchenko 
Cc: Hans de Goede 
Signed-off-by: Jani Nikula 
Signed-off-by: Andy Shevchenko 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index b2c0cc11f8c1..8b962f2ac475 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -454,11 +454,11 @@ static void icl_native_gpio_set_value(struct 
drm_i915_private *dev_priv,
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
struct drm_device *dev = intel_dsi->base.base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
+   struct drm_i915_private *i915 = to_i915(dev);
struct intel_connector *connector = intel_dsi->attached_connector;
u8 gpio_source, gpio_index = 0, gpio_number;
bool value;
-   bool native = DISPLAY_VER(dev_priv) >= 11;
+   bool native = DISPLAY_VER(i915) >= 11;
 
if (connector->panel.vbt.dsi.seq_version >= 3)
gpio_index = *data++;
@@ -477,16 +477,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
/* pull up/down */
value = *data++ & 1;
 
-   drm_dbg_kms(&dev_priv->drm, "GPIO index %u, number %u, source %u, 
native %s, set to %s\n",
+   drm_dbg_kms(&i915->drm, "GPIO index %u, number %u, source %u, native 
%s, set to %s\n",
gpio_index, gpio_number, gpio_source, str_yes_no(native), 
str_on_off(value));
 
if (native)
-   icl_native_gpio_set_value(dev_priv, gpio_number, value);
-   else if (DISPLAY_VER(dev_priv) >= 11)
+   icl_native_gpio_set_value(i915, gpio_number, value);
+   else if (DISPLAY_VER(i915) >= 11)
bxt_exec_gpio(connector, gpio_source, gpio_index, value);
-   else if (IS_VALLEYVIEW(dev_priv))
+   else if (IS_VALLEYVIEW(i915))
vlv_exec_gpio(connector, gpio_source, gpio_number, value);
-   else if (IS_CHERRYVIEW(dev_priv))
+   else if (IS_CHERRYVIEW(i915))
chv_exec_gpio(connector, gpio_source, gpio_number, value);
else
bxt_exec_gpio(connector, gpio_source, gpio_index, value);
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 03/16] drm/i915/dsi: clarify GPIO exec sequence

[Andy Shevchenko]

From: Jani Nikula 

With the various sequence versions and pointer increments interleaved,
it's a bit hard to decipher what's going on. Add separate paths for
different sequence versions.

Cc: Andy Shevchenko 
Cc: Hans de Goede 
Signed-off-by: Jani Nikula 
Signed-off-by: Andy Shevchenko 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 31 +++-
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 8b962f2ac475..11073efe26c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -456,26 +456,29 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *i915 = to_i915(dev);
struct intel_connector *connector = intel_dsi->attached_connector;
-   u8 gpio_source, gpio_index = 0, gpio_number;
+   u8 gpio_source = 0, gpio_index = 0, gpio_number;
bool value;
+   int size;
bool native = DISPLAY_VER(i915) >= 11;
 
-   if (connector->panel.vbt.dsi.seq_version >= 3)
-   gpio_index = *data++;
+   if (connector->panel.vbt.dsi.seq_version >= 3) {
+   size = 3;
 
-   gpio_number = *data++;
+   gpio_index = data[0];
+   gpio_number = data[1];
+   value = data[2] & BIT(0);
 
-   /* gpio source in sequence v2 only */
-   if (connector->panel.vbt.dsi.seq_version == 2)
-   gpio_source = (*data >> 1) & 3;
-   else
-   gpio_source = 0;
+   if (connector->panel.vbt.dsi.seq_version >= 4 && data[2] & 
BIT(1))
+   native = false;
+   } else {
+   size = 2;
 
-   if (connector->panel.vbt.dsi.seq_version >= 4 && *data & BIT(1))
-   native = false;
+   gpio_number = data[0];
+   value = data[1] & BIT(0);
 
-   /* pull up/down */
-   value = *data++ & 1;
+   if (connector->panel.vbt.dsi.seq_version == 2)
+   gpio_source = (data[1] >> 1) & 3;
+   }
 
drm_dbg_kms(&i915->drm, "GPIO index %u, number %u, source %u, native 
%s, set to %s\n",
gpio_index, gpio_number, gpio_source, str_yes_no(native), 
str_on_off(value));
@@ -491,7 +494,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
else
bxt_exec_gpio(connector, gpio_source, gpio_index, value);
 
-   return data;
+   return data + size;
 }
 
 #ifdef CONFIG_ACPI
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 04/16] drm/i915/dsi: rename platform specific *_exec_gpio() to *_gpio_set_value()

[Andy Shevchenko]

From: Jani Nikula 

The lowest level functions are about setting GPIO values, not about
executing any sequences anymore.

Cc: Andy Shevchenko 
Cc: Hans de Goede 
Signed-off-by: Jani Nikula 
Signed-off-by: Andy Shevchenko 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 11073efe26c0..f977d63a0ad4 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -243,8 +243,8 @@ static const u8 *mipi_exec_delay(struct intel_dsi 
*intel_dsi, const u8 *data)
return data;
 }
 
-static void vlv_exec_gpio(struct intel_connector *connector,
- u8 gpio_source, u8 gpio_index, bool value)
+static void vlv_gpio_set_value(struct intel_connector *connector,
+  u8 gpio_source, u8 gpio_index, bool value)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct gpio_map *map;
@@ -291,8 +291,8 @@ static void vlv_exec_gpio(struct intel_connector *connector,
vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 }
 
-static void chv_exec_gpio(struct intel_connector *connector,
- u8 gpio_source, u8 gpio_index, bool value)
+static void chv_gpio_set_value(struct intel_connector *connector,
+  u8 gpio_source, u8 gpio_index, bool value)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
u16 cfg0, cfg1;
@@ -345,8 +345,8 @@ static void chv_exec_gpio(struct intel_connector *connector,
vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 }
 
-static void bxt_exec_gpio(struct intel_connector *connector,
- u8 gpio_source, u8 gpio_index, bool value)
+static void bxt_gpio_set_value(struct intel_connector *connector,
+  u8 gpio_source, u8 gpio_index, bool value)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
/* XXX: this table is a quick ugly hack. */
@@ -486,13 +486,13 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
if (native)
icl_native_gpio_set_value(i915, gpio_number, value);
else if (DISPLAY_VER(i915) >= 11)
-   bxt_exec_gpio(connector, gpio_source, gpio_index, value);
+   bxt_gpio_set_value(connector, gpio_source, gpio_index, value);
else if (IS_VALLEYVIEW(i915))
-   vlv_exec_gpio(connector, gpio_source, gpio_number, value);
+   vlv_gpio_set_value(connector, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(i915))
-   chv_exec_gpio(connector, gpio_source, gpio_number, value);
+   chv_gpio_set_value(connector, gpio_source, gpio_number, value);
else
-   bxt_exec_gpio(connector, gpio_source, gpio_index, value);
+   bxt_gpio_set_value(connector, gpio_source, gpio_index, value);
 
return data + size;
 }
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 10/16] drm/i915/dsi: Fix wrong initial value for GPIOs in bxt_gpio_set_value()

[Andy Shevchenko]

From: Hans de Goede 

Fix wrong initial value for GPIOs in bxt_gpio_set_value().

Signed-off-by: Hans de Goede 
Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 8e6beef90e5e..0f9da0168a7b 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -356,9 +356,7 @@ static void bxt_gpio_set_value(struct intel_connector 
*connector,
if (!gpio_desc) {
gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
 NULL, gpio_index,
-value ? GPIOD_OUT_LOW :
-GPIOD_OUT_HIGH);
-
+value ? GPIOD_OUT_HIGH : 
GPIOD_OUT_LOW);
if (IS_ERR_OR_NULL(gpio_desc)) {
drm_err(&dev_priv->drm,
"GPIO index %u request failed (%ld)\n",
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 01/16] drm/i915/dsi: assume BXT gpio works for non-native GPIO

[Andy Shevchenko]

From: Jani Nikula 

Purely a guess. Drop the nop function.

Cc: Andy Shevchenko 
Cc: Hans de Goede 
Signed-off-by: Jani Nikula 
Signed-off-by: Andy Shevchenko 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 10 +-
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 24b2cbcfc1ef..b2c0cc11f8c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -372,14 +372,6 @@ static void bxt_exec_gpio(struct intel_connector 
*connector,
gpiod_set_value(gpio_desc, value);
 }
 
-static void icl_exec_gpio(struct intel_connector *connector,
- u8 gpio_source, u8 gpio_index, bool value)
-{
-   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-
-   drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
-}
-
 enum {
MIPI_RESET_1 = 0,
MIPI_AVDD_EN_1,
@@ -491,7 +483,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
if (native)
icl_native_gpio_set_value(dev_priv, gpio_number, value);
else if (DISPLAY_VER(dev_priv) >= 11)
-   icl_exec_gpio(connector, gpio_source, gpio_index, value);
+   bxt_exec_gpio(connector, gpio_source, gpio_index, value);
else if (IS_VALLEYVIEW(dev_priv))
vlv_exec_gpio(connector, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(dev_priv))
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 12/16] drm/i915/dsi: Replace poking of VLV GPIOs behind the driver's back

[Andy Shevchenko]

It's a dirty hack in the driver that pokes GPIO registers behind
the driver's back. Moreoever it might be problematic as simultaneous
I/O may hang the system, see the commit 40ecab551232 ("pinctrl:
baytrail: Really serialize all register accesses") for the details.
Taking all this into consideration replace the hack with proper
GPIO APIs being used.

Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 98 ++--
 1 file changed, 28 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 9847a92fdfc3..552bc6564d79 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -55,43 +55,6 @@
 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
 #define MIPI_PORT_SHIFT3
 
-/* base offsets for gpio pads */
-#define VLV_GPIO_NC_0_HV_DDI0_HPD  0x4130
-#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA  0x4120
-#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL  0x4110
-#define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
-#define VLV_GPIO_NC_4_PANEL0_BKLTEN0x4150
-#define VLV_GPIO_NC_5_PANEL0_BKLTCTL   0x4160
-#define VLV_GPIO_NC_6_HV_DDI1_HPD  0x4180
-#define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA  0x4190
-#define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL  0x4170
-#define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
-#define VLV_GPIO_NC_10_PANEL1_BKLTEN   0x40E0
-#define VLV_GPIO_NC_11_PANEL1_BKLTCTL  0x40F0
-
-#define VLV_GPIO_PCONF0(base_offset)   (base_offset)
-#define VLV_GPIO_PAD_VAL(base_offset)  ((base_offset) + 8)
-
-struct gpio_map {
-   u16 base_offset;
-   bool init;
-};
-
-static struct gpio_map vlv_gpio_table[] = {
-   { VLV_GPIO_NC_0_HV_DDI0_HPD },
-   { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
-   { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
-   { VLV_GPIO_NC_3_PANEL0_VDDEN },
-   { VLV_GPIO_NC_4_PANEL0_BKLTEN },
-   { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
-   { VLV_GPIO_NC_6_HV_DDI1_HPD },
-   { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
-   { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
-   { VLV_GPIO_NC_9_PANEL1_VDDEN },
-   { VLV_GPIO_NC_10_PANEL1_BKLTEN },
-   { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
-};
-
 struct i2c_adapter_lookup {
u16 slave_addr;
struct intel_dsi *intel_dsi;
@@ -268,52 +231,47 @@ static void soc_gpio_set_value(struct intel_connector 
*connector, const char *co
}
 }
 
+static void soc_opaque_gpio_set_value(struct intel_connector *connector,
+ const char *chip, const char *con_id,
+ u8 gpio_index, bool value)
+{
+   struct gpiod_lookup_table *lookup;
+
+   lookup = kzalloc(struct_size(lookup, table, 2), GFP_KERNEL);
+   if (!lookup)
+   return;
+
+   lookup->dev_id = ":00:02.0";
+   lookup->table[0] =
+   GPIO_LOOKUP_IDX(chip, gpio_index, con_id, gpio_index, 
GPIO_ACTIVE_HIGH);
+
+   gpiod_add_lookup_table(lookup);
+
+   soc_gpio_set_value(connector, con_id, gpio_index, value);
+
+   gpiod_remove_lookup_table(lookup);
+   kfree(lookup);
+}
+
 static void vlv_gpio_set_value(struct intel_connector *connector,
   u8 gpio_source, u8 gpio_index, bool value)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   struct gpio_map *map;
-   u16 pconf0, padval;
-   u32 tmp;
-   u8 port;
 
-   if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
-   drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",
-   gpio_index);
-   return;
-   }
-
-   map = &vlv_gpio_table[gpio_index];
-
-   if (connector->panel.vbt.dsi.seq_version >= 3) {
-   /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
-   port = IOSF_PORT_GPIO_NC;
-   } else {
-   if (gpio_source == 0) {
-   port = IOSF_PORT_GPIO_NC;
-   } else if (gpio_source == 1) {
+   /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
+   if (connector->panel.vbt.dsi.seq_version < 3) {
+   if (gpio_source == 1) {
drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
return;
-   } else {
+   }
+   if (gpio_source > 1) {
drm_dbg_kms(&dev_priv->drm,
"unknown gpio source %u\n", gpio_source);
return;
}
}
 
-   pconf0 = VLV_GPIO_PCONF0(map->base_offset);
-   padval = VLV_GPIO_PAD_VAL(map->base_offset);
-
-   vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
-   if (!map->init) {
-   /* FIXME: remove constant below */
-   vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
-   map->init = true;
-   }
-
-   tmp = 0x4 | value;
-   vlv_iosf_

[Intel-gfx] [PATCH v4 05/16] drm/i915/dsi: bxt/icl GPIO set value do not need gpio source

[Andy Shevchenko]

From: Jani Nikula 

Drop the unused parameter.

Cc: Andy Shevchenko 
Cc: Hans de Goede 
Signed-off-by: Jani Nikula 
Signed-off-by: Andy Shevchenko 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index f977d63a0ad4..4af43cf3cee0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -346,7 +346,7 @@ static void chv_gpio_set_value(struct intel_connector 
*connector,
 }
 
 static void bxt_gpio_set_value(struct intel_connector *connector,
-  u8 gpio_source, u8 gpio_index, bool value)
+  u8 gpio_index, bool value)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
/* XXX: this table is a quick ugly hack. */
@@ -486,13 +486,13 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
if (native)
icl_native_gpio_set_value(i915, gpio_number, value);
else if (DISPLAY_VER(i915) >= 11)
-   bxt_gpio_set_value(connector, gpio_source, gpio_index, value);
+   bxt_gpio_set_value(connector, gpio_index, value);
else if (IS_VALLEYVIEW(i915))
vlv_gpio_set_value(connector, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(i915))
chv_gpio_set_value(connector, gpio_source, gpio_number, value);
else
-   bxt_gpio_set_value(connector, gpio_source, gpio_index, value);
+   bxt_gpio_set_value(connector, gpio_index, value);
 
return data + size;
 }
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [rft, PATCH v4 00/16] drm/i915/dsi: 4th attempt to get rid of IOSF GPIO

[Andy Shevchenko]

DSI code for VBT has a set of ugly GPIO hacks, one of which is direct
talking to GPIO IP behind the actual driver's back. A second attempt
to fix that is here.

If I understood correctly, my approach should work in the similar way as
the current IOSF GPIO.

Hans, I believe you have some devices that use this piece of code,
is it possible to give a test run on (one of) them?

In v4:
- fixed compile time errors in patch 14 (Hans, LKP)
- fixed cover letter Subject
- added patch 15 (as suggested by Ville)
- added Ack tag (Jani)

In v3:
- incorporated series by Jani
- incorporated couple of precursor patches by Hans
- added Rb tag for used to be first three patches (Andi)
- rebased on top of the above changes
- fixed indexing for multi-community devices, such as Cherry View

In v2:
- added a few cleanup patches
- reworked to use dynamic GPIO lookup tables
- converted CHV as well

Andy Shevchenko (9):
  drm/i915/dsi: Replace while(1) with one with clear exit condition
  drm/i915/dsi: Get rid of redundant 'else'
  drm/i915/dsi: Replace check with a (missing) MIPI sequence name
  drm/i915/dsi: Extract common soc_gpio_set_value() helper
  drm/i915/dsi: Replace poking of VLV GPIOs behind the driver's back
  drm/i915/dsi: Prepare soc_gpio_set_value() to distinguish GPIO
communities
  drm/i915/dsi: Replace poking of CHV GPIOs behind the driver's back
  drm/i915/dsi: Combine checks in mipi_exec_gpio()
  drm/i915/iosf: Drop unused APIs

Hans de Goede (2):
  drm/i915/dsi: Remove GPIO lookup table at the end of
intel_dsi_vbt_gpio_init()
  drm/i915/dsi: Fix wrong initial value for GPIOs in
bxt_gpio_set_value()

Jani Nikula (5):
  drm/i915/dsi: assume BXT gpio works for non-native GPIO
  drm/i915/dsi: switch mipi_exec_gpio() from dev_priv to i915
  drm/i915/dsi: clarify GPIO exec sequence
  drm/i915/dsi: rename platform specific *_exec_gpio() to
*_gpio_set_value()
  drm/i915/dsi: bxt/icl GPIO set value do not need gpio source

 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 355 +++
 drivers/gpu/drm/i915/vlv_sideband.c  |  17 -
 drivers/gpu/drm/i915/vlv_sideband.h  |   3 -
 3 files changed, 136 insertions(+), 239 deletions(-)

-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 06/16] drm/i915/dsi: Replace while(1) with one with clear exit condition

[Andy Shevchenko]

Move existing condition to while(), so it will be clear on what
circumstances the loop is successfully finishing.

Reviewed-by: Andi Shyti 
Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 4af43cf3cee0..290a112f1b63 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -702,13 +702,10 @@ static void intel_dsi_vbt_exec(struct intel_dsi 
*intel_dsi,
if (connector->panel.vbt.dsi.seq_version >= 3)
data += 4;
 
-   while (1) {
+   while (*data != MIPI_SEQ_ELEM_END) {
u8 operation_byte = *data++;
u8 operation_size = 0;
 
-   if (operation_byte == MIPI_SEQ_ELEM_END)
-   break;
-
if (operation_byte < ARRAY_SIZE(exec_elem))
mipi_elem_exec = exec_elem[operation_byte];
else
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 09/16] drm/i915/dsi: Remove GPIO lookup table at the end of intel_dsi_vbt_gpio_init()

[Andy Shevchenko]

From: Hans de Goede 

To properly deal with GPIOs used in MIPI panel sequences a temporary
GPIO lookup will be used. Since there can only be 1 GPIO lookup table
for the ":00:02.0" device this will not work if the GPIO lookup
table used by intel_dsi_vbt_gpio_init() is still registered.

After getting the "backlight" and "panel" GPIOs the lookup table
registered by intel_dsi_vbt_gpio_init() is no longer necessary,
remove it so that another temporary lookup-table for the ":00:02.0"
device can be added.

Signed-off-by: Hans de Goede 
Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 25 +++-
 1 file changed, 9 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index d270437217b3..8e6beef90e5e 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -955,6 +955,7 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, 
bool panel_is_on)
struct intel_connector *connector = intel_dsi->attached_connector;
struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
+   struct gpiod_lookup_table *gpiod_lookup_table = NULL;
bool want_backlight_gpio = false;
bool want_panel_gpio = false;
struct pinctrl *pinctrl;
@@ -962,12 +963,12 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, 
bool panel_is_on)
 
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
mipi_config->pwm_blc == PPS_BLC_PMIC) {
-   gpiod_add_lookup_table(&pmic_panel_gpio_table);
+   gpiod_lookup_table = &pmic_panel_gpio_table;
want_panel_gpio = true;
}
 
if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
-   gpiod_add_lookup_table(&soc_panel_gpio_table);
+   gpiod_lookup_table = &soc_panel_gpio_table;
want_panel_gpio = true;
want_backlight_gpio = true;
 
@@ -984,6 +985,9 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, 
bool panel_is_on)
"Failed to set pinmux to PWM\n");
}
 
+   if (gpiod_lookup_table)
+   gpiod_add_lookup_table(gpiod_lookup_table);
+
if (want_panel_gpio) {
intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
if (IS_ERR(intel_dsi->gpio_panel)) {
@@ -1002,15 +1006,13 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi 
*intel_dsi, bool panel_is_on)
intel_dsi->gpio_backlight = NULL;
}
}
+
+   if (gpiod_lookup_table)
+   gpiod_remove_lookup_table(gpiod_lookup_table);
 }
 
 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
 {
-   struct drm_device *dev = intel_dsi->base.base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_connector *connector = intel_dsi->attached_connector;
-   struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
-
if (intel_dsi->gpio_panel) {
gpiod_put(intel_dsi->gpio_panel);
intel_dsi->gpio_panel = NULL;
@@ -1020,13 +1022,4 @@ void intel_dsi_vbt_gpio_cleanup(struct intel_dsi 
*intel_dsi)
gpiod_put(intel_dsi->gpio_backlight);
intel_dsi->gpio_backlight = NULL;
}
-
-   if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
-   mipi_config->pwm_blc == PPS_BLC_PMIC)
-   gpiod_remove_lookup_table(&pmic_panel_gpio_table);
-
-   if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
-   pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
-   gpiod_remove_lookup_table(&soc_panel_gpio_table);
-   }
 }
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 11/16] drm/i915/dsi: Extract common soc_gpio_set_value() helper

[Andy Shevchenko]

Extract a common soc_gpio_set_value() helper that may be used by a few SoCs.

Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 46 +++-
 1 file changed, 26 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 0f9da0168a7b..9847a92fdfc3 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -243,6 +243,31 @@ static const u8 *mipi_exec_delay(struct intel_dsi 
*intel_dsi, const u8 *data)
return data;
 }
 
+static void soc_gpio_set_value(struct intel_connector *connector, const char 
*con_id,
+  u8 gpio_index, bool value)
+{
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+   /* XXX: this table is a quick ugly hack. */
+   static struct gpio_desc *soc_gpio_table[U8_MAX + 1];
+   struct gpio_desc *gpio_desc = soc_gpio_table[gpio_index];
+
+   if (gpio_desc) {
+   gpiod_set_value(gpio_desc, value);
+   } else {
+   gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
+con_id, gpio_index,
+value ? GPIOD_OUT_HIGH : 
GPIOD_OUT_LOW);
+   if (IS_ERR(gpio_desc)) {
+   drm_err(&dev_priv->drm,
+   "GPIO index %u request failed (%pe)\n",
+   gpio_index, gpio_desc);
+   return;
+   }
+
+   soc_gpio_table[gpio_index] = gpio_desc;
+   }
+}
+
 static void vlv_gpio_set_value(struct intel_connector *connector,
   u8 gpio_source, u8 gpio_index, bool value)
 {
@@ -348,26 +373,7 @@ static void chv_gpio_set_value(struct intel_connector 
*connector,
 static void bxt_gpio_set_value(struct intel_connector *connector,
   u8 gpio_index, bool value)
 {
-   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   /* XXX: this table is a quick ugly hack. */
-   static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
-   struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
-
-   if (!gpio_desc) {
-   gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
-NULL, gpio_index,
-value ? GPIOD_OUT_HIGH : 
GPIOD_OUT_LOW);
-   if (IS_ERR_OR_NULL(gpio_desc)) {
-   drm_err(&dev_priv->drm,
-   "GPIO index %u request failed (%ld)\n",
-   gpio_index, PTR_ERR(gpio_desc));
-   return;
-   }
-
-   bxt_gpio_table[gpio_index] = gpio_desc;
-   }
-
-   gpiod_set_value(gpio_desc, value);
+   soc_gpio_set_value(connector, NULL, gpio_index, value);
 }
 
 enum {
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 15/16] drm/i915/dsi: Combine checks in mipi_exec_gpio()

[Andy Shevchenko]

For a couple of cases the branches call the same bxt_gpio_set_value().
As Ville suggested they can be combined by dropping the DISPLAY_VER()
check from Gen 11 to Gen 9. Do it that way.

Suggested-by: Ville Syrjälä 
Signed-off-by: Andy Shevchenko 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 9c6946ccb193..275d0218394c 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -420,14 +420,12 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
 
if (native)
icl_native_gpio_set_value(i915, gpio_number, value);
-   else if (DISPLAY_VER(i915) >= 11)
+   else if (DISPLAY_VER(i915) >= 9)
bxt_gpio_set_value(connector, gpio_index, value);
else if (IS_VALLEYVIEW(i915))
vlv_gpio_set_value(connector, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(i915))
chv_gpio_set_value(connector, gpio_source, gpio_number, value);
-   else
-   bxt_gpio_set_value(connector, gpio_index, value);
 
return data + size;
 }
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 08/16] drm/i915/dsi: Replace check with a (missing) MIPI sequence name

[Andy Shevchenko]

Names of the MIPI sequence steps are sequential and defined, no
need to check for the gaps. However in seq_name the MIPI_SEQ_END
is missing. Add it there, and drop unneeded NULL check in
sequence_name().

Reviewed-by: Andi Shyti 
Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 4ed5ede9ec5b..d270437217b3 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -653,6 +653,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
  */
 
 static const char * const seq_name[] = {
+   [MIPI_SEQ_END] = "MIPI_SEQ_END",
[MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
[MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
[MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
@@ -668,7 +669,7 @@ static const char * const seq_name[] = {
 
 static const char *sequence_name(enum mipi_seq seq_id)
 {
-   if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
+   if (seq_id < ARRAY_SIZE(seq_name))
return seq_name[seq_id];
 
return "(unknown)";
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 14/16] drm/i915/dsi: Replace poking of CHV GPIOs behind the driver's back

[Andy Shevchenko]

It's a dirty hack in the driver that pokes GPIO registers behind
the driver's back. Moreoever it might be problematic as simultaneous
I/O may hang the system, see the commit 0bd50d719b00 ("pinctrl:
cherryview: prevent concurrent access to GPIO controllers") for
the details. Taking all this into consideration replace the hack
with proper GPIO APIs being used.

Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 47 +---
 1 file changed, 10 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index b1736c1301ea..9c6946ccb193 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -66,19 +66,6 @@ struct i2c_adapter_lookup {
 #define CHV_GPIO_IDX_START_SW  100
 #define CHV_GPIO_IDX_START_SE  198
 
-#define CHV_VBT_MAX_PINS_PER_FMLY  15
-
-#define CHV_GPIO_PAD_CFG0(f, i)(0x4400 + (f) * 0x400 + (i) * 8)
-#define  CHV_GPIO_GPIOEN   (1 << 15)
-#define  CHV_GPIO_GPIOCFG_GPIO (0 << 8)
-#define  CHV_GPIO_GPIOCFG_GPO  (1 << 8)
-#define  CHV_GPIO_GPIOCFG_GPI  (2 << 8)
-#define  CHV_GPIO_GPIOCFG_HIZ  (3 << 8)
-#define  CHV_GPIO_GPIOTXSTATE(state)   ((!!(state)) << 1)
-
-#define CHV_GPIO_PAD_CFG1(f, i)(0x4400 + (f) * 0x400 + (i) * 8 
+ 4)
-#define  CHV_GPIO_CFGLOCK  (1 << 31)
-
 /* ICL DSI Display GPIO Pins */
 #define  ICL_GPIO_DDSP_HPD_A   0
 #define  ICL_GPIO_L_VDDEN_11
@@ -278,23 +265,21 @@ static void chv_gpio_set_value(struct intel_connector 
*connector,
   u8 gpio_source, u8 gpio_index, bool value)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   u16 cfg0, cfg1;
-   u16 family_num;
-   u8 port;
 
if (connector->panel.vbt.dsi.seq_version >= 3) {
if (gpio_index >= CHV_GPIO_IDX_START_SE) {
/* XXX: it's unclear whether 255->57 is part of SE. */
-   gpio_index -= CHV_GPIO_IDX_START_SE;
-   port = CHV_IOSF_PORT_GPIO_SE;
+   soc_opaque_gpio_set_value(connector, gpio_index, 
"INT33FF:03", "Panel SE",
+ gpio_index - 
CHV_GPIO_IDX_START_SE, value);
} else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
-   gpio_index -= CHV_GPIO_IDX_START_SW;
-   port = CHV_IOSF_PORT_GPIO_SW;
+   soc_opaque_gpio_set_value(connector, gpio_index, 
"INT33FF:00", "Panel SW",
+ gpio_index - 
CHV_GPIO_IDX_START_SW, value);
} else if (gpio_index >= CHV_GPIO_IDX_START_E) {
-   gpio_index -= CHV_GPIO_IDX_START_E;
-   port = CHV_IOSF_PORT_GPIO_E;
+   soc_opaque_gpio_set_value(connector, gpio_index, 
"INT33FF:02", "Panel E",
+ gpio_index - 
CHV_GPIO_IDX_START_E, value);
} else {
-   port = CHV_IOSF_PORT_GPIO_N;
+   soc_opaque_gpio_set_value(connector, gpio_index, 
"INT33FF:01", "Panel N",
+ gpio_index - 
CHV_GPIO_IDX_START_N, value);
}
} else {
/* XXX: The spec is unclear about CHV GPIO on seq v2 */
@@ -311,21 +296,9 @@ static void chv_gpio_set_value(struct intel_connector 
*connector,
return;
}
 
-   port = CHV_IOSF_PORT_GPIO_N;
+   soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", 
"Panel N",
+ gpio_index - CHV_GPIO_IDX_START_N, 
value);
}
-
-   family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
-   gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
-
-   cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
-   cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
-
-   vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
-   vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
-   vlv_iosf_sb_write(dev_priv, port, cfg0,
- CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
- CHV_GPIO_GPIOTXSTATE(value));
-   vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 }
 
 static void bxt_gpio_set_value(struct intel_connector *connector,
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 13/16] drm/i915/dsi: Prepare soc_gpio_set_value() to distinguish GPIO communities

[Andy Shevchenko]

Currently soc_gpio_set_value() supports only a single indexing for GPIO pin.
For CHV case, for example, we will need to distinguish community based index
from the one that VBT is using. Introduce an additional parameter to
soc_gpio_set_value() and its callers.

Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 552bc6564d79..b1736c1301ea 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -206,8 +206,8 @@ static const u8 *mipi_exec_delay(struct intel_dsi 
*intel_dsi, const u8 *data)
return data;
 }
 
-static void soc_gpio_set_value(struct intel_connector *connector, const char 
*con_id,
-  u8 gpio_index, bool value)
+static void soc_gpio_set_value(struct intel_connector *connector, u8 
gpio_index,
+  const char *con_id, u8 idx, bool value)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
/* XXX: this table is a quick ugly hack. */
@@ -217,8 +217,7 @@ static void soc_gpio_set_value(struct intel_connector 
*connector, const char *co
if (gpio_desc) {
gpiod_set_value(gpio_desc, value);
} else {
-   gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
-con_id, gpio_index,
+   gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, con_id, idx,
 value ? GPIOD_OUT_HIGH : 
GPIOD_OUT_LOW);
if (IS_ERR(gpio_desc)) {
drm_err(&dev_priv->drm,
@@ -232,8 +231,8 @@ static void soc_gpio_set_value(struct intel_connector 
*connector, const char *co
 }
 
 static void soc_opaque_gpio_set_value(struct intel_connector *connector,
- const char *chip, const char *con_id,
- u8 gpio_index, bool value)
+ u8 gpio_index, const char *chip,
+ const char *con_id, u8 idx, bool value)
 {
struct gpiod_lookup_table *lookup;
 
@@ -243,11 +242,11 @@ static void soc_opaque_gpio_set_value(struct 
intel_connector *connector,
 
lookup->dev_id = ":00:02.0";
lookup->table[0] =
-   GPIO_LOOKUP_IDX(chip, gpio_index, con_id, gpio_index, 
GPIO_ACTIVE_HIGH);
+   GPIO_LOOKUP_IDX(chip, idx, con_id, idx, GPIO_ACTIVE_HIGH);
 
gpiod_add_lookup_table(lookup);
 
-   soc_gpio_set_value(connector, con_id, gpio_index, value);
+   soc_gpio_set_value(connector, gpio_index, con_id, idx, value);
 
gpiod_remove_lookup_table(lookup);
kfree(lookup);
@@ -271,7 +270,8 @@ static void vlv_gpio_set_value(struct intel_connector 
*connector,
}
}
 
-   soc_opaque_gpio_set_value(connector, "INT33FC:01", "Panel N", 
gpio_index, value);
+   soc_opaque_gpio_set_value(connector, gpio_index,
+ "INT33FC:01", "Panel N", gpio_index, value);
 }
 
 static void chv_gpio_set_value(struct intel_connector *connector,
@@ -331,7 +331,7 @@ static void chv_gpio_set_value(struct intel_connector 
*connector,
 static void bxt_gpio_set_value(struct intel_connector *connector,
   u8 gpio_index, bool value)
 {
-   soc_gpio_set_value(connector, NULL, gpio_index, value);
+   soc_gpio_set_value(connector, gpio_index, NULL, gpio_index, value);
 }
 
 enum {
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 07/16] drm/i915/dsi: Get rid of redundant 'else'

[Andy Shevchenko]

In the snippets like the following

if (...)
return / goto / break / continue ...;
else
...

the 'else' is redundant. Get rid of it.

Reviewed-by: Andi Shyti 
Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 58 ++--
 1 file changed, 28 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 290a112f1b63..4ed5ede9ec5b 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -142,7 +142,7 @@ static enum port intel_dsi_seq_port_to_port(struct 
intel_dsi *intel_dsi,
if (seq_port) {
if (intel_dsi->ports & BIT(PORT_B))
return PORT_B;
-   else if (intel_dsi->ports & BIT(PORT_C))
+   if (intel_dsi->ports & BIT(PORT_C))
return PORT_C;
}
 
@@ -670,8 +670,8 @@ static const char *sequence_name(enum mipi_seq seq_id)
 {
if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
return seq_name[seq_id];
-   else
-   return "(unknown)";
+
+   return "(unknown)";
 }
 
 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
@@ -865,36 +865,34 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 
panel_id)
 * multiply by 100 to preserve remainder
 */
if (intel_dsi->video_mode == BURST_MODE) {
-   if (mipi_config->target_burst_mode_freq) {
-   u32 bitrate = intel_dsi_bitrate(intel_dsi);
+   u32 bitrate;
 
-   /*
-* Sometimes the VBT contains a slightly lower clock,
-* then the bitrate we have calculated, in this case
-* just replace it with the calculated bitrate.
-*/
-   if (mipi_config->target_burst_mode_freq < bitrate &&
-   intel_fuzzy_clock_check(
-   mipi_config->target_burst_mode_freq,
-   bitrate))
-   mipi_config->target_burst_mode_freq = bitrate;
-
-   if (mipi_config->target_burst_mode_freq < bitrate) {
-   drm_err(&dev_priv->drm,
-   "Burst mode freq is less than 
computed\n");
-   return false;
-   }
-
-   burst_mode_ratio = DIV_ROUND_UP(
-   mipi_config->target_burst_mode_freq * 100,
-   bitrate);
-
-   intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * 
burst_mode_ratio, 100);
-   } else {
-   drm_err(&dev_priv->drm,
-   "Burst mode target is not set\n");
+   if (mipi_config->target_burst_mode_freq == 0) {
+   drm_err(&dev_priv->drm, "Burst mode target is not 
set\n");
return false;
}
+
+   bitrate = intel_dsi_bitrate(intel_dsi);
+
+   /*
+* Sometimes the VBT contains a slightly lower clock, then
+* the bitrate we have calculated, in this case just replace it
+* with the calculated bitrate.
+*/
+   if (mipi_config->target_burst_mode_freq < bitrate &&
+   intel_fuzzy_clock_check(mipi_config->target_burst_mode_freq,
+   bitrate))
+   mipi_config->target_burst_mode_freq = bitrate;
+
+   if (mipi_config->target_burst_mode_freq < bitrate) {
+   drm_err(&dev_priv->drm, "Burst mode freq is less than 
computed\n");
+   return false;
+   }
+
+   burst_mode_ratio =
+   DIV_ROUND_UP(mipi_config->target_burst_mode_freq * 100, 
bitrate);
+
+   intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * 
burst_mode_ratio, 100);
} else
burst_mode_ratio = 100;
 
-- 
2.40.0.1.gaa8946217a0b

[Intel-gfx] [PATCH v4 16/16] drm/i915/iosf: Drop unused APIs

[Andy Shevchenko]

Drop unused vlv_iosf_sb_read() and vlv_iosf_sb_write().

Signed-off-by: Andy Shevchenko 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/vlv_sideband.c | 17 -
 drivers/gpu/drm/i915/vlv_sideband.h |  3 ---
 2 files changed, 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/vlv_sideband.c 
b/drivers/gpu/drm/i915/vlv_sideband.c
index b98dec3ad817..13b644958e38 100644
--- a/drivers/gpu/drm/i915/vlv_sideband.c
+++ b/drivers/gpu/drm/i915/vlv_sideband.c
@@ -166,23 +166,6 @@ u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
return val;
 }
 
-u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
-{
-   u32 val = 0;
-
-   vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
-   SB_CRRDDA_NP, reg, &val);
-
-   return val;
-}
-
-void vlv_iosf_sb_write(struct drm_i915_private *i915,
-  u8 port, u32 reg, u32 val)
-{
-   vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
-   SB_CRWRDA_NP, reg, &val);
-}
-
 u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
 {
u32 val = 0;
diff --git a/drivers/gpu/drm/i915/vlv_sideband.h 
b/drivers/gpu/drm/i915/vlv_sideband.h
index 9ce283d96b80..8b4495e14bce 100644
--- a/drivers/gpu/drm/i915/vlv_sideband.h
+++ b/drivers/gpu/drm/i915/vlv_sideband.h
@@ -26,9 +26,6 @@ enum {
 };
 
 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
-u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
-void vlv_iosf_sb_write(struct drm_i915_private *i915,
-  u8 port, u32 reg, u32 val);
 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
 
 static inline void vlv_bunit_get(struct drm_i915_private *i915)
-- 
2.40.0.1.gaa8946217a0b

Re: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching into DMA for MTL

[Sripada, Radhakrishna]

Hi Jonathan,

> -Original Message-
> From: Cavitt, Jonathan 
> Sent: Friday, November 3, 2023 1:15 PM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Cc: Gupta, saurabhg ;
> chris.p.wil...@linux.intel.com
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching
> into DMA for MTL
> 
> -Original Message-
> From: Sripada, Radhakrishna 
> Sent: Friday, November 3, 2023 1:02 PM
> To: Cavitt, Jonathan ; 
> intel-gfx@lists.freedesktop.org
> Cc: Gupta, saurabhg ; Cavitt, Jonathan
> ; chris.p.wil...@linux.intel.com
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching
> into DMA for MTL
> >
> > Hi Jonathan,
> >
> > > -Original Message-
> > > From: Intel-gfx  On Behalf Of
> Jonathan
> > > Cavitt
> > > Sent: Thursday, November 2, 2023 10:59 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Gupta, saurabhg ; Cavitt, Jonathan
> > > ; chris.p.wil...@linux.intel.com
> > > Subject: [Intel-gfx] [PATCH] drm/i915/gt: Temporarily disable CPU caching 
> > > into
> > > DMA for MTL
> > >
> > > FIXME: It is suspected that some Address Translation Service (ATS)
> > > issue on IOMMU is causing CAT errors to occur on some MTL workloads.
> > > Applying a write barrier to the ppgtt set entry functions appeared
> > > to have no effect, so we must temporarily use I915_MAP_WC in the
> > > map_pt_dma class of functions on MTL until a proper ATS solution is
> > > found.
> > >
> > What is the performance impact here? Are we disabling caching only
> > for the pte changes/scratch pages or does it extend beyond?
> 
> 
> I don't actually know what map_pt_dma is used for, but if the name is
> indicative of its purpose, it should only impact mappings into the dma
> page table.
> As for the performance impact, I don't imagine it'll be much.  Maybe
> a single-digit percentage slowdown?  It might actually improve
> performance if we're avoiding enough cache misses, but the true
> performance impact would have to be measured empirically.
> -Jonathan Cavitt
> 
Even I am assuming the performance impact to be low as only pte uncached
would be uncached and hence
Reviewed-by: Radhakrishna Sripada 


> 
> >
> > Regards,
> > Radhakrishna(RK) Sripada
> > > Signed-off-by: Jonathan Cavitt 
> > > CC: Chris Wilson 
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_gtt.c | 20 
> > >  1 file changed, 20 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > index 4fbed27ef0ecc..21719563a602a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > @@ -95,6 +95,16 @@ int map_pt_dma(struct i915_address_space *vm,
> struct
> > > drm_i915_gem_object *obj)
> > >   void *vaddr;
> > >
> > >   type = intel_gt_coherent_map_type(vm->gt, obj, true);
> > > + /*
> > > +  * FIXME: It is suspected that some Address Translation Service (ATS)
> > > +  * issue on IOMMU is causing CAT errors to occur on some MTL
> > > workloads.
> > > +  * Applying a write barrier to the ppgtt set entry functions appeared
> > > +  * to have no effect, so we must temporarily use I915_MAP_WC here on
> > > +  * MTL until a proper ATS solution is found.
> > > +  */
> > > + if (IS_METEORLAKE(vm->i915))
> > > + type = I915_MAP_WC;
> > > +
> > >   vaddr = i915_gem_object_pin_map_unlocked(obj, type);
> > >   if (IS_ERR(vaddr))
> > >   return PTR_ERR(vaddr);
> > > @@ -109,6 +119,16 @@ int map_pt_dma_locked(struct i915_address_space
> > > *vm, struct drm_i915_gem_object
> > >   void *vaddr;
> > >
> > >   type = intel_gt_coherent_map_type(vm->gt, obj, true);
> > > + /*
> > > +  * FIXME: It is suspected that some Address Translation Service (ATS)
> > > +  * issue on IOMMU is causing CAT errors to occur on some MTL
> > > workloads.
> > > +  * Applying a write barrier to the ppgtt set entry functions appeared
> > > +  * to have no effect, so we must temporarily use I915_MAP_WC here on
> > > +  * MTL until a proper ATS solution is found.
> > > +  */
> > > + if (IS_METEORLAKE(vm->i915))
> > > + type = I915_MAP_WC;
> > > +
> > >   vaddr = i915_gem_object_pin_map(obj, type);
> > >   if (IS_ERR(vaddr))
> > >   return PTR_ERR(vaddr);
> > > --
> > > 2.25.1
> >
> >

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp_mst: Disable DSC on ICL+ MST outputs (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dp_mst: Disable DSC on ICL+ MST outputs (rev3)
URL   : https://patchwork.freedesktop.org/series/125895/
State : warning

== Summary ==

Error: dim checkpatch failed
757b351472e1 drm/i915/dp_mst: Disable DSC on ICL+ MST outputs
-:19: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line 
(possible unwrapped commit description?)
#19: 
[1] https://lore.kernel.org/all/20231030155843.2251023-1-imre.d...@intel.com

total: 0 errors, 1 warnings, 0 checks, 34 lines checked

[Intel-gfx] [PATCH v8 0/6] Panel replay phase1 implementation

[Animesh Manna]

Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.

These patches are basic enablement patches added on top of
existing psr framework to enable full-screen live active frame
update mode of panel replay. Panel replay also can be enabled
in selective update mode which will be enabled in a incremental
approach.

As per current design panel replay priority is higher than psr.
intel_dp->psr.panel_replay_enabled flag indicate panel replay is enabled.
intel_dp->psr.panel_replay_enabled + intel_dp->psr.psr2_enabled indicates
panel replay is enabled in selective update mode.
intel_dp->psr.panel_replay_enabled + intel_dp->psr.psr2_enabled +
intel_psr.selective_fetch enabled indicates panel replay is
enabled in selective update mode with selective fetch.
PSR replated flags remain same like before.

Note: The patches are under testing by using panel replay emulator and
panel is not avalible.

Cc: Jouni Högander 
Cc: Arun R Murthy 
Cc: Jani Nikula 
Signed-off-by: Animesh Manna 

Animesh Manna (5):
  drm/panelreplay: dpcd register definition for panelreplay
  drm/i915/panelreplay: Initializaton and compute config for panel
replay
  drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
  drm/i915/panelreplay: enable/disable panel replay
  drm/i915/panelreplay: Debugfs support for panel replay

Jouni Högander (1):
  drm/i915/psr: Move psr specific dpcd init into own function

 drivers/gpu/drm/i915/display/intel_ddi.c  |   7 +-
 .../drm/i915/display/intel_display_types.h|  15 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |  49 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c  | 292 +-
 drivers/gpu/drm/i915/display/intel_psr.h  |   7 +
 include/drm/display/drm_dp.h  |  23 ++
 7 files changed, 291 insertions(+), 105 deletions(-)

-- 
2.29.0

[Intel-gfx] [PATCH v8 1/6] drm/panelreplay: dpcd register definition for panelreplay

[Animesh Manna]

Add DPCD register definition for discovering, enabling and
checking status of panel replay of the sink.

Cc: Jouni Högander 
Cc: Arun R Murthy 
Cc: Jani Nikula 
Reviewed-by: Arun R Murthy 
Signed-off-by: Animesh Manna 
---
 include/drm/display/drm_dp.h | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e69cece404b3..fc42b622ef32 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -543,6 +543,10 @@
 /* DFP Capability Extension */
 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0a3   /* 2.0 */
 
+#define DP_PANEL_REPLAY_CAP 0x0b0  /* DP 2.0 */
+# define DP_PANEL_REPLAY_SUPPORT(1 << 0)
+# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1)
+
 /* Link Configuration */
 #defineDP_LINK_BW_SET  0x100
 # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */
@@ -716,6 +720,13 @@
 #define DP_BRANCH_DEVICE_CTRL  0x1a1
 # define DP_BRANCH_DEVICE_IRQ_HPD  (1 << 0)
 
+#define PANEL_REPLAY_CONFIG 0x1b0  /* DP 2.0 */
+# define DP_PANEL_REPLAY_ENABLE (1 << 0)
+# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3)
+# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN   (1 << 4)
+# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN  (1 << 5)
+# define DP_PANEL_REPLAY_SU_ENABLE  (1 << 6)
+
 #define DP_PAYLOAD_ALLOCATE_SET0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
@@ -1105,6 +1116,18 @@
 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI   0x200e /* status same as 0x204 
*/
 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 
*/
 
+#define DP_PANEL_REPLAY_ERROR_STATUS   0x2020  /* DP 2.1*/
+# define DP_PANEL_REPLAY_LINK_CRC_ERROR(1 << 0)
+# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 1)
+# define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR   (1 << 2)
+
+#define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS0x2022  /* DP 2.1 */
+# define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK   (7 << 0)
+# define DP_SINK_FRAME_LOCKED_SHIFT3
+# define DP_SINK_FRAME_LOCKED_MASK (3 << 3)
+# define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT   5
+# define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK(1 << 5)
+
 /* Extended Receiver Capability: See DP_DPCD_REV for definitions */
 #define DP_DP13_DPCD_REV0x2200
 
-- 
2.29.0

[Intel-gfx] [PATCH v8 2/6] drm/i915/psr: Move psr specific dpcd init into own function

[Animesh Manna]

From: Jouni Högander 

This patch is preparing adding panel replay specific dpcd init.

Cc: Arun R Murthy 
Cc: Jani Nikula 
Reviewed-by: Arun R Murthy 
Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 41 +---
 1 file changed, 23 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index ecd24a0b86cb..48da60005ceb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -474,27 +474,22 @@ static void intel_dp_get_su_granularity(struct intel_dp 
*intel_dp)
intel_dp->psr.su_y_granularity = y;
 }
 
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp)
 {
-   struct drm_i915_private *dev_priv =
+   struct drm_i915_private *i915 =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 
-   drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
-sizeof(intel_dp->psr_dpcd));
-
-   if (!intel_dp->psr_dpcd[0])
-   return;
-   drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
+   drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n",
intel_dp->psr_dpcd[0]);
 
if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
-   drm_dbg_kms(&dev_priv->drm,
+   drm_dbg_kms(&i915->drm,
"PSR support not currently available for this 
panel\n");
return;
}
 
if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
-   drm_dbg_kms(&dev_priv->drm,
+   drm_dbg_kms(&i915->drm,
"Panel lacks power state control, PSR cannot be 
enabled\n");
return;
}
@@ -503,8 +498,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
intel_dp->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
 
-   if (DISPLAY_VER(dev_priv) >= 9 &&
-   (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
+   if (DISPLAY_VER(i915) >= 9 &&
+   intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
bool y_req = intel_dp->psr_dpcd[1] &
 DP_PSR2_SU_Y_COORDINATE_REQUIRED;
bool alpm = intel_dp_get_alpm_status(intel_dp);
@@ -521,14 +516,24 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 * GTC first.
 */
intel_dp->psr.sink_psr2_support = y_req && alpm;
-   drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
+   drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n",
intel_dp->psr.sink_psr2_support ? "" : "not ");
+   }
+}
 
-   if (intel_dp->psr.sink_psr2_support) {
-   intel_dp->psr.colorimetry_support =
-   intel_dp_get_colorimetry_status(intel_dp);
-   intel_dp_get_su_granularity(intel_dp);
-   }
+void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+{
+   drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
+sizeof(intel_dp->psr_dpcd));
+
+   if (intel_dp->psr_dpcd[0])
+   _psr_init_dpcd(intel_dp);
+   /* TODO: Add PR case here */
+
+   if (intel_dp->psr.sink_psr2_support) {
+   intel_dp->psr.colorimetry_support =
+   intel_dp_get_colorimetry_status(intel_dp);
+   intel_dp_get_su_granularity(intel_dp);
}
 }
 
-- 
2.29.0

[Intel-gfx] [PATCH v8 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Animesh Manna]

Modify existing PSR implementation to enable panel replay feature of DP 2.0
which is similar to PSR feature of EDP panel. There is different DPCD
address to check panel capability compare to PSR and vsc sdp header
is different.

v1: Initial version.
v2:
- Set source_panel_replay_support flag under HAS_PANEL_REPLAY()
condition check. [Jouni]
- Code restructured around intel_panel_replay_init
and renamed to intel_panel_replay_init_dpcd. [Jouni]
- Remove the initial code modification around has_psr2 flag. [Jouni]
- Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
enable in intel_psr_post_plane_update. [Jouni]
v3:
- Initialize both psr and panel-replay. [Jouni]
- Initialize both panel replay and psr if detected. [Jouni]
- Refactoring psr function by introducing _psr_compute_config(). [Jouni]
- Add check for !is_edp while deriving source_panel_replay_support. [Jouni]
- Enable panel replay dpcd initialization in a separate patch. [Jouni]

v4:
- HAS_PANEL_REPLAY() check not needed during sink capability check. [Jouni]
- Set either panel replay source support or psr. [Jouni]

v5:
- HAS_PANEL_REPLAY() removed and use HAS_DP20() instead. [Jouni]
- Move psr related code to intel_psr.c. [Jani]
- Reset sink_panel_replay_support flag during disconnection. [Jani]

v6: return statement restored which is removed by misatke. [Jouni]
v7: cosmetic changes. [Arun]

Cc: Jouni Högander 
Cc: Arun R Murthy 
Cc: Jani Nikula 
Reviewed-by: Arun R Murthy 
Signed-off-by: Animesh Manna 
---
 .../drm/i915/display/intel_display_types.h| 14 +--
 drivers/gpu/drm/i915/display/intel_dp.c   | 49 --
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  3 +
 drivers/gpu/drm/i915/display/intel_psr.c  | 96 ++-
 drivers/gpu/drm/i915/display/intel_psr.h  |  7 ++
 5 files changed, 123 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 047fe3f8905a..7d46bece7e06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1208,6 +1208,7 @@ struct intel_crtc_state {
bool has_psr2;
bool enable_psr2_sel_fetch;
bool req_psr2_sdp_prior_scanline;
+   bool has_panel_replay;
bool wm_level_disabled;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1705,6 +1706,8 @@ struct intel_psr {
bool irq_aux_error;
u16 su_w_granularity;
u16 su_y_granularity;
+   bool source_panel_replay_support;
+   bool sink_panel_replay_support;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
@@ -1990,17 +1993,6 @@ dp_to_lspcon(struct intel_dp *intel_dp)
 
 #define dp_to_i915(__intel_dp) 
to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
 
-#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
-  (intel_dp)->psr.source_support)
-
-static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
-{
-   if (!intel_encoder_is_dp(encoder))
-   return false;
-
-   return CAN_PSR(enc_to_intel_dp(encoder));
-}
-
 static inline struct intel_digital_port *
 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5391b2a83405..8260fa638aa6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2439,12 +2439,22 @@ static void intel_dp_compute_vsc_colorimetry(const 
struct intel_crtc_state *crtc
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-   /*
-* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
-* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-* Colorimetry Format indication.
-*/
-   vsc->revision = 0x5;
+   if (crtc_state->has_panel_replay) {
+   /*
+* Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+* VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+* Encoding/Colorimetry Format indication.
+*/
+   vsc->revision = 0x7;
+   } else {
+   /*
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+* Colorimetry Format indication.
+*/
+   vsc->revision = 0x5;
+   }
+
vsc->length = 0x13;
 
/* DP 1.4a spec, Table 2-120 */
@@ -2553,6 +2563,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp 
*intel_dp,
vsc->revision = 0x4;
vsc->length = 0xe;
}
+   } else if (crtc_state->has_panel_replay) {
+   if (intel_dp->psr.colorimetry_support &&
+ 

[Intel-gfx] [PATCH v8 4/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP

[Animesh Manna]

Due to similarity panel replay dpcd initialization got added in psr
function which is specific for edp panel. This patch enables panel
replay initialization for dp connector.

Cc: Jouni Högander 
Cc: Arun R Murthy 
Cc: Jani Nikula 
Reviewed-by: Arun R Murthy 
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 3c66257b6bb2..e53a2217627a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2742,6 +2742,9 @@ void intel_psr_init(struct intel_dp *intel_dp)
if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
return;
 
+   if (!intel_dp_is_edp(intel_dp))
+   intel_psr_init_dpcd(intel_dp);
+
/*
 * HSW spec explicitly says PSR is tied to port A.
 * BDW+ platforms have a instance of PSR registers per transcoder but
-- 
2.29.0

[Intel-gfx] [PATCH v8 5/6] drm/i915/panelreplay: enable/disable panel replay

[Animesh Manna]

TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.

Bspec: 1407940617

v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni]

v3: Cover letter updated and selective fetch condition check is added
before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]

v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped. [Jouni]

v5: Added PSR2_MAN_TRK_CTL programming as needed for Continuous Full
Frame (CFF) update.

v6: Rebased on latest.

Note: Initial plan is to enable panel replay in  full-screen live active
frame update mode. In a incremental approach panel replay will be enabled
in selctive update mode if there is any gap in curent implementation.

Cc: Jouni Högander 
Cc: Arun R Murthy 
Cc: Jani Nikula 
Reviewed-by: Arun R Murthy 
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |  7 ++-
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_psr.c  | 63 ++-
 3 files changed, 55 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2e37708fecdd..c446d8ef210f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2717,10 +2717,15 @@ static void intel_ddi_pre_enable_dp(struct 
intel_atomic_state *state,
const struct drm_connector_state 
*conn_state)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-   if (HAS_DP20(dev_priv))
+   if (HAS_DP20(dev_priv)) {
intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
crtc_state);
+   if (crtc_state->has_panel_replay)
+   drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+  DP_PANEL_REPLAY_ENABLE);
+   }
 
if (DISPLAY_VER(dev_priv) >= 14)
mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7d46bece7e06..81a7c6efa4a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1708,6 +1708,7 @@ struct intel_psr {
u16 su_y_granularity;
bool source_panel_replay_support;
bool sink_panel_replay_support;
+   bool panel_replay_enabled;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index e53a2217627a..8ed4684b4528 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -608,8 +608,11 @@ static void intel_psr_enable_sink(struct intel_dp 
*intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
 
-   /* Enable ALPM at sink for psr2 */
+   if (intel_dp->psr.panel_replay_enabled)
+   return;
+
if (intel_dp->psr.psr2_enabled) {
+   /* Enable ALPM at sink for psr2 */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
   DP_ALPM_ENABLE |
   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -761,6 +764,17 @@ static int psr2_block_count(struct intel_dp *intel_dp)
return psr2_block_count_lines(intel_dp) / 4;
 }
 
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+   intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
+
+   intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1325,18 +1339,23 @@ void intel_psr_get_config(struct intel_encoder *encoder,
return;
 
intel_dp = &dig_port->dp;
-   if (!CAN_PSR(intel_dp))
+   if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
return;
 
mutex_lock(&intel_dp->psr.lock);
if (!intel_dp->psr.enabled)
goto unlock;
 
-   /*
-* Not possible to read EDP_PSR/PSR2_CTL registers as it is
-* enabled/disabled because of frontbuffer tracking and others.
-*/
-   pipe_config->has_psr = true;
+   if (intel_dp->psr.panel_replay_enabled) {
+   pipe_config->has_panel_r

[Intel-gfx] [PATCH v8 6/6] drm/i915/panelreplay: Debugfs support for panel replay

[Animesh Manna]

Add debugfs support which will print source and sink status
per connector basis. Existing i915_psr_status and
i915_psr_sink_status will be used to get the source and
sink status of panel replay.

v1: Initial version. [rb-ed by Arun]
v2: Added check for DP 2.0 and connector type in connector_debugfs_add().
v3: Optimization and cosmetic changes. [Jouni]

Cc: Jouni Högander 
Cc: Arun R Murthy 
Cc: Jani Nikula 
Reviewed-by: Arun R Murthy 
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 93 +---
 1 file changed, 66 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 8ed4684b4528..8b7c03cd4989 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2813,12 +2813,19 @@ static int psr_get_status_and_error_status(struct 
intel_dp *intel_dp,
 {
struct drm_dp_aux *aux = &intel_dp->aux;
int ret;
+   unsigned int offset;
 
-   ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
+   offset = intel_dp->psr.panel_replay_enabled ?
+DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS;
+
+   ret = drm_dp_dpcd_readb(aux, offset, status);
if (ret != 1)
return ret;
 
-   ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
+   offset = intel_dp->psr.panel_replay_enabled ?
+DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS;
+
+   ret = drm_dp_dpcd_readb(aux, offset, error_status);
if (ret != 1)
return ret;
 
@@ -3039,7 +3046,7 @@ psr_source_status(struct intel_dp *intel_dp, struct 
seq_file *m)
status = live_status[status_val];
}
 
-   seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
+   seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, 
val);
 }
 
 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
@@ -3052,18 +3059,23 @@ static int intel_psr_status(struct seq_file *m, struct 
intel_dp *intel_dp)
bool enabled;
u32 val;
 
-   seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support));
-   if (psr->sink_support)
+   seq_printf(m, "Sink support: PSR = %s, Panel Replay = %s",
+  str_yes_no(psr->sink_support),
+  str_yes_no(psr->sink_panel_replay_support));
+
+   if (psr->sink_support || psr->sink_panel_replay_support)
seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
seq_puts(m, "\n");
 
-   if (!psr->sink_support)
+   if (!(psr->sink_support || psr->sink_panel_replay_support))
return 0;
 
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
mutex_lock(&psr->lock);
 
-   if (psr->enabled)
+   if (psr->panel_replay_enabled)
+   status = "Panel Replay Enabled";
+   else if (psr->enabled)
status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
else
status = "disabled";
@@ -3076,14 +3088,17 @@ static int intel_psr_status(struct seq_file *m, struct 
intel_dp *intel_dp)
goto unlock;
}
 
-   if (psr->psr2_enabled) {
+   if (psr->panel_replay_enabled) {
+   val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));
+   enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
+   } else if (psr->psr2_enabled) {
val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
enabled = val & EDP_PSR2_ENABLE;
} else {
val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, 
cpu_transcoder));
enabled = val & EDP_PSR_ENABLE;
}
-   seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
+   seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n",
   str_enabled_disabled(enabled), val);
psr_source_status(intel_dp, m);
seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
@@ -3221,6 +3236,15 @@ void intel_psr_debugfs_register(struct drm_i915_private 
*i915)
i915, &i915_edp_psr_status_fops);
 }
 
+static const char *psr_mode_str(struct intel_dp *intel_dp) {
+   if (intel_dp->psr.panel_replay_enabled)
+   return "PANEL-REPLAY";
+   else if(intel_dp->psr.enabled)
+   return "PSR";
+
+   return "unknown";
+}
+
 static int i915_psr_sink_status_show(struct seq_file *m, void *data)
 {
struct intel_connector *connector = m->private;
@@ -3235,12 +3259,19 @@ static int i915_psr_sink_status_show(struct seq_file 
*m, void *data)
"reserved",
"sink internal error",
};
+   static const char * const panel_replay_status[] = {
+   "Sink device frame is locked to the Source device",
+   "Sink device is coasting, using the VTotal target",
+   "Sink d

Re: [Intel-gfx] [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support for panel replay

[Manna, Animesh]

> -Original Message-
> From: Hogander, Jouni 
> Sent: Friday, November 3, 2023 12:32 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani 
> Subject: Re: [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support for
> panel replay
> 
> On Fri, 2023-11-03 at 06:10 +, Manna, Animesh wrote:
> >
> >
> > > -Original Message-
> > > From: Hogander, Jouni 
> > > Sent: Thursday, November 2, 2023 1:08 PM
> > > To: Manna, Animesh ; intel-
> > > g...@lists.freedesktop.org
> > > Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> > > ; Nikula, Jani 
> > > Subject: Re: [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support
> > > for panel replay
> > >
> > > On Wed, 2023-10-11 at 16:39 +0530, Animesh Manna wrote:
> > > > Add debugfs support which will print source and sink status per
> > > > connector basis.
> > >
> > > Sorry for late review. Noticed only by now that you have added this
> > > patch into you set.
> >
> > Added from v5.
> >
> > >
> > > Can you please describe in commit message how you see the output of
> > > debugfs interface will look like after your changes?
> >
> > Sure.
> >
> > >
> > > >
> > > > v1: Initial version. [rb-ed by Arun]
> > > > v2: Added check for DP 2.0 and connector type in
> > > > connector_debugfs_add().
> > > >
> > > > Cc: Jouni Högander 
> > > > Cc: Arun R Murthy 
> > > > Cc: Jani Nikula 
> > > > Signed-off-by: Animesh Manna 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_psr.c | 136
> > > > +
> > > > --
> > > >  1 file changed, 102 insertions(+), 34 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 80de831c2f60..399fc0a8e636 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -2823,6 +2823,25 @@ static int
> > > > psr_get_status_and_error_status(struct intel_dp *intel_dp,
> > > > return 0;
> > > >  }
> > > >
> > > > +static int panel_replay_get_status_and_error_status(struct
> > > > intel_dp
> > > > *intel_dp,
> > > > +   u8 *status,
> > > > u8
> > > > *error_status)
> > > > +{
> > > > +   struct drm_dp_aux *aux = &intel_dp->aux;
> > > > +   int ret;
> > > > +
> > > > +   ret = drm_dp_dpcd_readb(aux,
> > > > DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS, status);
> > > > +   if (ret != 1)
> > > > +   return ret;
> > > > +
> > > > +   ret = drm_dp_dpcd_readb(aux,
> > > > DP_PANEL_REPLAY_ERROR_STATUS,
> > > > error_status);
> > > > +   if (ret != 1)
> > > > +   return ret;
> > > > +
> > > > +   *status = *status & DP_PSR_SINK_STATE_MASK;
> > > > +
> > > > +   return 0;
> > > > +}
> > > > +
> > >
> > > I think you should modify  psr_get_status_and_error_status instead
> > > of duplicating most of it.
> >
> > DPCD addresses are different for panel replay, I did not get the need
> > of it.
> 
> I would like to see:
> 
> unsigned int offset = intel_dp->psr.panel_replay_enabled ?
> DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS;
> 
> ret = drm_dp_dpcd_readb(aux, offset, status);
> 
> rather than duplicating it.

Added in v8.

> 
> >
> > >
> > > >  static void psr_alpm_check(struct intel_dp *intel_dp)
> > > >  {
> > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > @@
> > > > -3035,7 +3054,7 @@ psr_source_status(struct intel_dp *intel_dp,
> > > > struct seq_file *m)
> > > > status = live_status[status_val];
> > > > }
> > > >
> > > > -   seq_printf(m, "Source PSR status: %s [0x%08x]\n", status,
> > > > val);
> > > > +   seq_printf(m, "Source PSR/PanelReplay status: %s
> > > > [0x%08x]\n",
> > > > status, val);
> > > >  }
> > > >
> > > >  static int intel_psr_status(struct seq_file *m, struct intel_dp
> > > > *intel_dp)
> > > > @@ -3048,18 +3067,23 @@ static int intel_psr_status(struct
> > > > seq_file *m, struct intel_dp *intel_dp)
> > > > bool enabled;
> > > > u32 val;
> > > >
> > > > -   seq_printf(m, "Sink support: %s", str_yes_no(psr-
> > > > > sink_support));
> > > > -   if (psr->sink_support)
> > > > +   seq_printf(m, "Sink support: PSR = %s, Panel Replay =
> > > > %s",
> > > > +  str_yes_no(psr->sink_support),
> > > > +  str_yes_no(psr->sink_panel_replay_support));
> > > > +
> > > > +   if (psr->sink_support || psr->sink_panel_replay_support)
> > > > seq_printf(m, " [0x%02x]", intel_dp-
> > > > >psr_dpcd[0]);
> > > > seq_puts(m, "\n");
> > > >
> > > > -   if (!psr->sink_support)
> > > > +   if (!(psr->sink_support || psr-
> > > > >sink_panel_replay_support))
> > > > return 0;
> > > >
> > > > wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> > > > mutex_lock(&psr->lock);
> > > >
>

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d is enabled

[Andrzej Hajda]

On 03.11.2023 16:53, Sripada, Radhakrishna wrote:

Hi Tvrtko,


-Original Message-
From: Tvrtko Ursulin 
Sent: Friday, November 3, 2023 1:30 AM
To: Sripada, Radhakrishna ; Hajda, Andrzej
; intel-gfx@lists.freedesktop.org
Cc: Chris Wilson 
Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d is
enabled


On 02/11/2023 22:14, Sripada, Radhakrishna wrote:

Hi Tvrtko,


-Original Message-
From: Tvrtko Ursulin 
Sent: Thursday, November 2, 2023 10:41 AM
To: Hajda, Andrzej ; Sripada, Radhakrishna
; intel-gfx@lists.freedesktop.org
Cc: Chris Wilson 
Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d

is

enabled


On 02/11/2023 16:58, Andrzej Hajda wrote:

On 02.11.2023 17:06, Radhakrishna Sripada wrote:

Experiments were conducted with different multipliers to VTD_GUARD

macro

with multiplier of 185 we were observing occasional pipe faults when
running kms_cursor_legacy --run-subtest single-bo

There could possibly be an underlying issue that is being
investigated, for
now bump the guard pages for MTL.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2017
Cc: Gustavo Sousa 
Cc: Chris Wilson 
Signed-off-by: Radhakrishna Sripada 
---
    drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
    1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 3770828f2eaf..b65f84c6bb3f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -456,6 +456,9 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
    if (intel_scanout_needs_vtd_wa(i915)) {
    unsigned int guard = VTD_GUARD;
+    if (IS_METEORLAKE(i915))
+    guard *= 200;
+

200 * VTD_GUARD = 200 * 168 * 4K = 131MB

Looks insanely high, 131MB for padding, if this is before and after it
becomes even 262MB of wasted address per plane. Just signalling, I do
not know if this actually hurts.

Yeah this feels crazy. There must be some other explanation which is
getting hidden by the crazy amount of padding so I'd rather we figured
it out.

With 262MiB per fb how many fit in GGTT before eviction hits? N screens
with double/triple buffering?

I believe with this method we will have to limit the no of frame buffers in the

system. One alternative

that worked is to do a proper clear range for the ggtt instead of doing a nop.

Although it adds marginal

time during suspend/resume/boot it does not add restrictions to the no of fb's

that can be used.

And if we remember the guard pages replaced clearing to scratch, to
improve suspend resume times, exactly for improving user experience. :(

Luckily there is time to fix this properly on MTL one way or the other.
Is it just kms_cursor_legacy --run-subtest single-bo that is affected?

I am trying to dump the page table entries at the time of failure for bot the 
fame buffer and if required
For the guard pages. Will see if I get some info from there.

Yes the test kms_cursor_legacy is used to reliably reproduce. Looking at public 
CI, I also see pipe errors
being reported with varying occurrences while running kms_cursor_crc, 
kms_pipe_crc_basic,
and kms_plane_scaling. More details on the occurrence can be found here [1].

Thanks,
RK

1. 
http://gfx-ci.igk.intel.com/cibuglog-ng/results/knownfailures?query_key=d9c3297dd17dda35a6c638eb96b3139bd1a6633c


Could you check if [1] helps?

[1]: https://patchwork.freedesktop.org/series/125926/

Regards
Andrzej


Regards,

Tvrtko



Regards,

Tvrtko

P.S. Where did the 185 from the commit message come from?

185 came from experiment to increase the guard size. It is not a standard

number.

Regards,
Radhakrishna(RK) Sripada

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp_mst: Disable DSC on ICL+ MST outputs (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dp_mst: Disable DSC on ICL+ MST outputs (rev3)
URL   : https://patchwork.freedesktop.org/series/125895/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13835 -> Patchwork_125895v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/index.html

Participating hosts (36 -> 37)
--

  Additional (3): bat-dg2-8 bat-dg2-9 fi-pnv-d510 
  Missing(2): fi-kbl-x1275 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_125895v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_busy@busy@all-engines:
- bat-mtlp-8: [PASS][1] -> [DMESG-FAIL][2] ([i915#8962])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13835/bat-mtlp-8/igt@gem_busy@b...@all-engines.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-mtlp-8/igt@gem_busy@b...@all-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) +3 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/fi-hsw-4770/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-9/igt@gem_m...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-9/igt@gem_mmap_...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-8:  NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_module_load@reload:
- fi-skl-6600u:   [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13835/fi-skl-6600u/igt@i915_module_l...@reload.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/fi-skl-6600u/igt@i915_module_l...@reload.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#6621])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-9/igt@i915_pm_...@basic-api.html
- bat-dg2-8:  NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-8/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_lrc:
- bat-rpls-1: [PASS][14] -> [INCOMPLETE][15] ([i915#9413])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13835/bat-rpls-1/igt@i915_selftest@live@gt_lrc.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-rpls-1/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-dg2-8:  NOTRUN -> [SKIP][16] ([i915#6645])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#5190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
- bat-dg2-8:  NOTRUN -> [SKIP][18] ([i915#5190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][19] ([i915#4215] / [i915#5190])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
- bat-dg2-8:  NOTRUN -> [SKIP][20] ([i915#4215] / [i915#5190])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][21] ([i915#4212]) +6 other tests skip
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125895v3/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html
- bat-dg2-8:  NOTRUN -> [SKIP

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: 4th attempt to get rid of IOSF GPIO

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: 4th attempt to get rid of IOSF GPIO
URL   : https://patchwork.freedesktop.org/series/125977/
State : warning

== Summary ==

Error: dim checkpatch failed
cf6ba57516da drm/i915/dsi: assume BXT gpio works for non-native GPIO
481d4ce37fe4 drm/i915/dsi: switch mipi_exec_gpio() from dev_priv to i915
b80582bcf739 drm/i915/dsi: clarify GPIO exec sequence
54a9044c6b7d drm/i915/dsi: rename platform specific *_exec_gpio() to 
*_gpio_set_value()
d3cef67d2948 drm/i915/dsi: bxt/icl GPIO set value do not need gpio source
312e37a9127d drm/i915/dsi: Replace while(1) with one with clear exit condition
427e3034b75e drm/i915/dsi: Get rid of redundant 'else'
5af3f32b334f drm/i915/dsi: Replace check with a (missing) MIPI sequence name
02afcfea30ea drm/i915/dsi: Remove GPIO lookup table at the end of 
intel_dsi_vbt_gpio_init()
bf81f18f5ffd drm/i915/dsi: Fix wrong initial value for GPIOs in 
bxt_gpio_set_value()
aa88caa8c7f5 drm/i915/dsi: Extract common soc_gpio_set_value() helper
-:6: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible 
unwrapped commit description?)
#6: 
Extract a common soc_gpio_set_value() helper that may be used by a few SoCs.

total: 0 errors, 1 warnings, 0 checks, 58 lines checked
30ced6d15ea3 drm/i915/dsi: Replace poking of VLV GPIOs behind the driver's back
66a96cfbc330 drm/i915/dsi: Prepare soc_gpio_set_value() to distinguish GPIO 
communities
-:7: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible 
unwrapped commit description?)
#7: 
Currently soc_gpio_set_value() supports only a single indexing for GPIO pin.

total: 0 errors, 1 warnings, 0 checks, 59 lines checked
5484103c5d64 drm/i915/dsi: Replace poking of CHV GPIOs behind the driver's back
a4d061726bbd drm/i915/dsi: Combine checks in mipi_exec_gpio()
49380e2b55f6 drm/i915/iosf: Drop unused APIs

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d is enabled

[Sripada, Radhakrishna]

Hi Andrzej,

The patch mentioned below does not help with the issue.

Thanks,
RK

> -Original Message-
> From: Hajda, Andrzej 
> Sent: Friday, November 3, 2023 2:18 PM
> To: Sripada, Radhakrishna ; Tvrtko Ursulin
> ; intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson ; Vivi, Rodrigo
> 
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when vt-d 
> is
> enabled
> 
> 
> 
> On 03.11.2023 16:53, Sripada, Radhakrishna wrote:
> > Hi Tvrtko,
> >
> >> -Original Message-
> >> From: Tvrtko Ursulin 
> >> Sent: Friday, November 3, 2023 1:30 AM
> >> To: Sripada, Radhakrishna ; Hajda, Andrzej
> >> ; intel-gfx@lists.freedesktop.org
> >> Cc: Chris Wilson 
> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when 
> >> vt-d
> is
> >> enabled
> >>
> >>
> >> On 02/11/2023 22:14, Sripada, Radhakrishna wrote:
> >>> Hi Tvrtko,
> >>>
>  -Original Message-
>  From: Tvrtko Ursulin 
>  Sent: Thursday, November 2, 2023 10:41 AM
>  To: Hajda, Andrzej ; Sripada, Radhakrishna
>  ; intel-gfx@lists.freedesktop.org
>  Cc: Chris Wilson 
>  Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: Increase guard pages when
> vt-d
> >> is
>  enabled
> 
> 
>  On 02/11/2023 16:58, Andrzej Hajda wrote:
> > On 02.11.2023 17:06, Radhakrishna Sripada wrote:
> >> Experiments were conducted with different multipliers to VTD_GUARD
> >> macro
> >> with multiplier of 185 we were observing occasional pipe faults when
> >> running kms_cursor_legacy --run-subtest single-bo
> >>
> >> There could possibly be an underlying issue that is being
> >> investigated, for
> >> now bump the guard pages for MTL.
> >>
> >> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2017
> >> Cc: Gustavo Sousa 
> >> Cc: Chris Wilson 
> >> Signed-off-by: Radhakrishna Sripada 
> >> ---
> >>     drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
> >>     1 file changed, 3 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> >> b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> >> index 3770828f2eaf..b65f84c6bb3f 100644
> >> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> >> @@ -456,6 +456,9 @@ i915_gem_object_pin_to_display_plane(struct
> >> drm_i915_gem_object *obj,
> >>     if (intel_scanout_needs_vtd_wa(i915)) {
> >>     unsigned int guard = VTD_GUARD;
> >> +    if (IS_METEORLAKE(i915))
> >> +    guard *= 200;
> >> +
> > 200 * VTD_GUARD = 200 * 168 * 4K = 131MB
> >
> > Looks insanely high, 131MB for padding, if this is before and after it
> > becomes even 262MB of wasted address per plane. Just signalling, I do
> > not know if this actually hurts.
>  Yeah this feels crazy. There must be some other explanation which is
>  getting hidden by the crazy amount of padding so I'd rather we figured
>  it out.
> 
>  With 262MiB per fb how many fit in GGTT before eviction hits? N screens
>  with double/triple buffering?
> >>> I believe with this method we will have to limit the no of frame buffers 
> >>> in the
> >> system. One alternative
> >>> that worked is to do a proper clear range for the ggtt instead of doing a 
> >>> nop.
> >> Although it adds marginal
> >>> time during suspend/resume/boot it does not add restrictions to the no of
> fb's
> >> that can be used.
> >>
> >> And if we remember the guard pages replaced clearing to scratch, to
> >> improve suspend resume times, exactly for improving user experience. :(
> >>
> >> Luckily there is time to fix this properly on MTL one way or the other.
> >> Is it just kms_cursor_legacy --run-subtest single-bo that is affected?
> > I am trying to dump the page table entries at the time of failure for bot 
> > the fame
> buffer and if required
> > For the guard pages. Will see if I get some info from there.
> >
> > Yes the test kms_cursor_legacy is used to reliably reproduce. Looking at 
> > public
> CI, I also see pipe errors
> > being reported with varying occurrences while running kms_cursor_crc,
> kms_pipe_crc_basic,
> > and kms_plane_scaling. More details on the occurrence can be found here [1].
> >
> > Thanks,
> > RK
> >
> > 1. http://gfx-ci.igk.intel.com/cibuglog-
> ng/results/knownfailures?query_key=d9c3297dd17dda35a6c638eb96b3139bd1a
> 6633c
> 
> Could you check if [1] helps?
> 
> [1]: https://patchwork.freedesktop.org/series/125926/
> 
> Regards
> Andrzej
> 
> >> Regards,
> >>
> >> Tvrtko
> >>
> >>
>  Regards,
> 
>  Tvrtko
> 
>  P.S. Where did the 185 from the commit message come from?
> >>> 185 came from experiment to increase the guard size. It is not a standard
> >> number.
> >>> Regards,
> >>> Radhakrishna(RK) Sripada

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsi: 4th attempt to get rid of IOSF GPIO

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: 4th attempt to get rid of IOSF GPIO
URL   : https://patchwork.freedesktop.org/series/125977/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13835 -> Patchwork_125977v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_125977v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125977v1, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/index.html

Participating hosts (36 -> 37)
--

  Additional (2): fi-kbl-soraka bat-dg2-9 
  Missing(1): fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_125977v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hangcheck:
- bat-atsm-1: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13835/bat-atsm-1/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-atsm-1/igt@i915_selftest@l...@hangcheck.html

  
Known issues


  Here are the changes found in Patchwork_125977v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][9] ([i915#1886])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#5190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4215] / [i915#5190])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#4212]) +6 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#4212] / [i915#5608])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][15] ([fdo#109271]) +9 other tests 
skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/fi-kbl-soraka/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([fdo#109285])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125977v1/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#5274])

Re: [Intel-gfx] [PATCH v4 00/30] drm/i915: Improve BW management on MST links

[Lyude Paul]

BTW - sorry it took me a little while to get back to this, I'm still getting
back into the swing of things but I should be able to review this next week :)

Thanks for all of the work you've done so far!

On Mon, 2023-10-30 at 17:58 +0200, Imre Deak wrote:
> This is v4 of [1] with the following changes:
> 
> - Fix a race condition between connector setup and registration
>   (added patch 1).
> - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK
>   (Ville, patch 9).
> - Fix setting crtc_state->fec_enable, once crtc_state->port_clock
>   required for it is already set (patch 10).
> - Fix passing the correct fec_enable parameter to
>   intel_dp_bw_fec_overhead() (patch 12).
> - Fix TU size, making it match the payload size in the payload table
>   (Patch 13).
> - Apply the HBLANK expansion quirk whenever the HBLANK period is
>   300ns or less (Patch 21).
> - Fix refcounting of the DSC AUX decompression device
>   (Stan, patch 25).
> - Fix HW readout/sanitize for the connector DSC decompression enabled
>   state (patch 25).
> - Move intel_crtc_needs_modeset() check to callers of
>   clear_pipe_update_flags_on_modeset_crtc() (Ville, patch 26).
> - Fix forcing modeset on CRTC due to a change in MST topology
>   (Ville, patch 27).
> - Add missing DocBooks, fix typos.
> 
> [1] https://lore.kernel.org/all/20231024010925.3949910-1-imre.d...@intel.com
> 
> Cc: Stanislav Lisovskiy 
> Cc: Lyude Paul 
> Cc: Ville Syrjälä 
> Cc: Ankit Nautiyal 
> Cc: Arun R Murthy 
> 
> Imre Deak (28):
>   drm/i915/dp_mst: Fix race between connector registration and setup
>   drm/dp_mst: Add helper to determine if an MST port is downstream of
> another port
>   drm/dp_mst: Factor out a helper to check the atomic state of a
> topology manager
>   drm/dp_mst: Swap the order of checking root vs. non-root port BW
> limitations
>   drm/dp_mst: Allow DSC in any Synaptics last branch device
>   drm/dp: Add DP_HBLANK_EXPANSION_CAPABLE and DSC_PASSTHROUGH_EN DPCD
> flags
>   drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs
>   drm/dp: Add helpers to calculate the link BW overhead
>   drm/i915/dp_mst: Enable FEC early once it's known DSC is needed
>   drm/i915/dp: Specify the FEC overhead as an increment vs. a remainder
>   drm/i915/dp: Pass actual BW overhead to m_n calculation
>   drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
>   drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
>   drm/i915/dp_mst: Program the DSC PPS SDP for each stream
>   drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is
> disabled
>   drm/i915/dp_mst: Add missing DSC compression disabling
>   drm/i915/dp: Rename intel_ddi_disable_fec_state() to
> intel_ddi_disable_fec()
>   drm/i915/dp: Wait for FEC detected status in the sink
>   drm/i915/dp: Disable FEC ready flag in the sink
>   drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
>   drm/i915/dp_mst: Enable decompression in the sink from the MST encoder
> hooks
>   drm/i915/dp: Enable DSC via the connector decompression AUX
>   drm/i915/dp_mst: Enable DSC passthrough
>   drm/i915/dp_mst: Enable MST DSC decompression for all streams
>   drm/i915: Factor out function to clear pipe update flags
>   drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
>   drm/i915/dp_mst: Improve BW sharing between MST streams
>   drm/i915/dp_mst: Check BW limitations only after all streams are
> computed
> 
> Stanislav Lisovskiy (1):
>   drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
> info
> 
> Ville Syrjälä (1):
>   drm/dp_mst: Fix fractional DSC bpp handling
> 
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   2 +-
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |   2 +-
>  drivers/gpu/drm/display/drm_dp_helper.c   | 134 +
>  drivers/gpu/drm/display/drm_dp_mst_topology.c | 206 +--
>  drivers/gpu/drm/i915/display/intel_ddi.c  | 136 -
>  drivers/gpu/drm/i915/display/intel_ddi.h  |   3 +
>  drivers/gpu/drm/i915/display/intel_display.c  | 101 ++--
>  drivers/gpu/drm/i915/display/intel_display.h  |   4 +-
>  .../drm/i915/display/intel_display_types.h|   3 +
>  drivers/gpu/drm/i915/display/intel_dp.c   | 256 +++-
>  drivers/gpu/drm/i915/display/intel_dp.h   |  23 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 564 +++---
>  drivers/gpu/drm/i915/display/intel_dp_mst.h   |   5 +
>  drivers/gpu/drm/i915/display/intel_fdi.c  |   5 +-
>  drivers/gpu/drm/i915/display/intel_link_bw.c  |  16 +-
>  drivers/gpu/drm/i915/display/intel_link_bw.h  |   1 +
>  .../drm/i915/display/intel_modeset_setup.c|   6 +
>  drivers/gpu/drm/nouveau/dispnv50/disp.c   |   3 +-
>  .../gpu/drm/tests/drm_dp_mst_helper_test.c|   6 +-
>  include/drm/display/drm_dp.h  |   2 +
>  include/drm/display/drm_dp_helper.h   |  18 +
>  include/drm/display/drm_dp_mst_helper.h   |   9 +-
>  22 files changed, 1270 insertions

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation (rev10)

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation (rev10)
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

Error: dim checkpatch failed
f025bc5ed357 drm/panelreplay: dpcd register definition for panelreplay
a6ba947cd35c drm/i915/psr: Move psr specific dpcd init into own function
d0b4de45d90a drm/i915/panelreplay: Initializaton and compute config for panel 
replay
-:366: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible 
side-effects?
#366: FILE: drivers/gpu/drm/i915/display/intel_psr.h:24:
+#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
+  (intel_dp)->psr.source_support)

-:369: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible 
side-effects?
#369: FILE: drivers/gpu/drm/i915/display/intel_psr.h:27:
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support 
&& \
+   (intel_dp)->psr.source_panel_replay_support)

total: 0 errors, 0 warnings, 2 checks, 289 lines checked
5225e39b90ad drm/i915/panelreplay: Enable panel replay dpcd initialization for 
DP
bf1255857ce0 drm/i915/panelreplay: enable/disable panel replay
96064a75ad28 drm/i915/panelreplay: Debugfs support for panel replay
-:111: ERROR:OPEN_BRACE: open brace '{' following function definitions go on 
the next line
#111: FILE: drivers/gpu/drm/i915/display/intel_psr.c:3239:
+static const char *psr_mode_str(struct intel_dp *intel_dp) {

-:114: ERROR:SPACING: space required before the open parenthesis '('
#114: FILE: drivers/gpu/drm/i915/display/intel_psr.c:3242:
+   else if(intel_dp->psr.enabled)

-:171: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (8, 24)
#171: FILE: drivers/gpu/drm/i915/display/intel_psr.c:3300:
if (error_status & (DP_PSR_RFB_STORAGE_ERROR |
[...]
+   seq_puts(m, ":\n");

total: 2 errors, 1 warnings, 0 checks, 176 lines checked

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev10)

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation (rev10)
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for Panel replay phase1 implementation (rev10)

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation (rev10)
URL   : https://patchwork.freedesktop.org/series/94470/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13835 -> Patchwork_94470v10


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_94470v10 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_94470v10, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/index.html

Participating hosts (36 -> 36)
--

  Additional (2): bat-dg2-9 fi-pnv-d510 
  Missing(2): fi-hsw-4770 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_94470v10:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_store@basic:
- fi-rkl-11600:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13835/fi-rkl-11600/igt@gem_exec_st...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/fi-rkl-11600/igt@gem_exec_st...@basic.html

  * igt@i915_selftest@live@gt_mocs:
- bat-rpls-1: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13835/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html

  
Known issues


  Here are the changes found in Patchwork_94470v10 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- bat-jsl-1:  [PASS][5] -> [FAIL][6] ([i915#8293])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13835/bat-jsl-1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-jsl-1/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#4083])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@migrate:
- bat-mtlp-6: [PASS][11] -> [DMESG-FAIL][12] ([i915#7699])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13835/bat-mtlp-6/igt@i915_selftest@l...@migrate.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-mtlp-6/igt@i915_selftest@l...@migrate.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#5190])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([i915#4215] / [i915#5190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][15] ([i915#4212]) +6 other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#4212] / [i915#5608])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213] / 
[i915#5608]) +1 other test skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([fdo#109285])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v10/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9:  NOTRUN -> [