Re: [Intel-gfx] [PATCH 11/11] drm/i915/dp_mst: Add support for forcing dsc fractional bpp via debugfs
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, November 10, 2023 3:40 PM
> To: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sharma, Swati2 ; Kulkarni, Vandita
> ; Kandpal, Suraj ;
> suijingf...@loongson.cn
> Subject: [PATCH 11/11] drm/i915/dp_mst: Add support for forcing dsc
> fractional bpp via debugfs
>
> If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
> compressed bpp is fractional. Continue if the computed compressed bpp
> turns out to be a integer.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 322046bb7d42..26b51ba6871d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -172,6 +172,10 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> struct intel_link_m_n remote_m_n;
> int link_bpp_x16;
>
> + if (dsc && intel_dp->force_dsc_fractional_bpp_en &&
> + !to_bpp_frac(bpp_x16))
> + continue;
> +
> drm_dbg_kms(&i915->drm, "Trying bpp " BPP_X16_FMT "\n",
> BPP_X16_ARGS(bpp_x16));
>
> ret = intel_dp_mst_check_constraints(i915, bpp_x16,
> adjusted_mode, crtc_state, dsc); @@ -225,12 +229,16 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
> slots);
> } else {
> - if (!dsc)
> - crtc_state->pipe_bpp = to_bpp_int(bpp_x16);
> - else
> + if (dsc) {
> crtc_state->dsc.compressed_bpp_x16 = bpp_x16;
> + if (intel_dp->force_dsc_fractional_bpp_en &&
> to_bpp_frac(bpp_x16))
> + drm_dbg_kms(&i915->drm, "Forcing DSC
> fractional bpp\n");
> + } else {
> + crtc_state->pipe_bpp = to_bpp_int(bpp_x16);
> + }
> drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp "
> BPP_X16_FMT " dsc %d\n",
> slots, BPP_X16_ARGS(bpp_x16), dsc);
> +
> }
>
> return slots;
> --
> 2.40.1
Re: [Intel-gfx] [PATCH 10/11] drm/i916/dp_mst: Iterate over the DSC bpps as per DSC precision support
> Subject: [PATCH 10/11] drm/i916/dp_mst: Iterate over the DSC bpps as per > DSC precision support > > Currently we iterate over the bpp_x16 in step of 16. > Use DSC fractional bpp precision supported by the sink to compute the > appropriate steps to iterate over the bpps. > LGTM. Reviewed-by: Suraj Kandpal > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 - > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index e7806fe11b9d..322046bb7d42 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -273,6 +273,8 @@ static int > intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, > int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; > u8 dsc_max_bpc; > int min_compressed_bpp, max_compressed_bpp; > + int bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector- > >dp.dsc_dpcd); > + int bppx16_step; > > /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ > if (DISPLAY_VER(i915) >= 12) > @@ -327,11 +329,16 @@ static int > intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, > min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, > min_compressed_bpp, > crtc_state- > >pipe_bpp); > > + if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1) > + bppx16_step = 16; > + else > + bppx16_step = 16 / bppx16_incr; > + > slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, > > to_bpp_x16(max_compressed_bpp), > > to_bpp_x16(min_compressed_bpp), >limits, > - conn_state, 16, true); > + conn_state, bppx16_step, > true); > > if (slots < 0) > return slots; > -- > 2.40.1
Re: [Intel-gfx] [PATCH 09/11] drm/i915/dp_mst: Use precision of 1/16 for computing bpp
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, November 10, 2023 3:40 PM
> To: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sharma, Swati2 ; Kulkarni, Vandita
> ; Kandpal, Suraj ;
> suijingf...@loongson.cn
> Subject: [PATCH 09/11] drm/i915/dp_mst: Use precision of 1/16 for computing
> bpp
>
> Modify the functions to deal with bpps with 1/16 precision.
> This will make way for cases when DSC with fractional bpp is used.
> For bpp without DSC, there is no change, as we still use whole numbers.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 56 +++--
> 1 file changed, 30 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 5c7e9d296483..e7806fe11b9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -47,20 +47,21 @@
> #include "intel_vdsc.h"
> #include "skl_scaler.h"
>
> -static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int
> bpp,
> +static int intel_dp_mst_check_constraints(struct drm_i915_private
> +*i915, int bpp_x16,
> const struct drm_display_mode
> *adjusted_mode,
> struct intel_crtc_state *crtc_state,
> bool dsc)
> {
> if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) <= 13 && dsc) {
> - int output_bpp = bpp;
> + int output_bpp_x16 = bpp_x16;
> /* DisplayPort 2 128b/132b, bits per lane is always 32 */
> int symbol_clock = crtc_state->port_clock / 32;
>
> - if (output_bpp * adjusted_mode->crtc_clock >=
> + if (DIV_ROUND_UP(output_bpp_x16 * adjusted_mode-
> >crtc_clock, 16) >=
> symbol_clock * 72) {
> drm_dbg_kms(&i915->drm, "UHBR check
> failed(required bw %d available %d)\n",
> - output_bpp * adjusted_mode->crtc_clock,
> symbol_clock * 72);
> + DIV_ROUND_UP(output_bpp_x16 *
> adjusted_mode->crtc_clock, 16),
> + symbol_clock * 72);
> return -EINVAL;
> }
> }
> @@ -127,8 +128,8 @@ static void intel_dp_mst_compute_m_n(const struct
> intel_crtc_state *crtc_state,
>
> static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder
> *encoder,
> struct intel_crtc_state
> *crtc_state,
> - int max_bpp,
> - int min_bpp,
> + int max_bpp_x16,
> + int min_bpp_x16,
> struct link_config_limits
> *limits,
> struct drm_connector_state
> *conn_state,
> int step,
> @@ -143,7 +144,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
> intel_encoder *encoder,
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> const struct drm_display_mode *adjusted_mode =
> &crtc_state->hw.adjusted_mode;
> - int bpp, slots = -EINVAL;
> + int bpp_x16, slots = -EINVAL;
> int ret = 0;
>
> mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp-
> >mst_mgr); @@ -164,25 +165,25 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> crtc_state->port_clock,
> crtc_state->lane_count);
>
> - drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d
> max bpp %d\n",
> - min_bpp, max_bpp);
> + drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp "
> BPP_X16_FMT " max bpp " BPP_X16_FMT "\n",
> + BPP_X16_ARGS(min_bpp_x16),
> BPP_X16_ARGS(max_bpp_x16));
>
> - for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
> + for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -=
> step) {
> struct intel_link_m_n remote_m_n;
> - int link_bpp;
> + int link_bpp_x16;
>
> - drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
> + drm_dbg_kms(&i915->drm, "Trying bpp " BPP_X16_FMT "\n",
> +BPP_X16_ARGS(bpp_x16));
>
> - ret = intel_dp_mst_check_constraints(i915, bpp,
> adjusted_mode, crtc_state, dsc);
> + ret = intel_dp_mst_check_constraints(i915, bpp_x16,
> adjusted_mode,
> +crtc_state, dsc);
> if (ret)
> continue;
>
> - link_bpp = dsc ? bpp :
> - intel_dp_output_bpp(crtc_st
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/xe2lpd: WA for underruns during FBC enable (rev3)
== Series Details ==
Series: drm/i915/xe2lpd: WA for underruns during FBC enable (rev3)
URL : https://patchwork.freedesktop.org/series/126143/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13865 -> Patchwork_126143v3
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_126143v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_126143v3, please notify your bug team
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/index.html
Participating hosts (33 -> 33)
--
Additional (1): fi-hsw-4770
Missing(1): bat-rpls-1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_126143v3:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13865/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_pm:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/fi-hsw-4770/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@slpc:
- fi-kbl-soraka: NOTRUN -> [ABORT][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/fi-kbl-soraka/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13865/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html
Known issues
Here are the changes found in Patchwork_126143v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334] /
[i915#7872])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13865/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
- fi-apl-guc: [PASS][9] -> [DMESG-FAIL][10] ([i915#5334])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13865/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-jsl-3: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13865/bat-jsl-3/igt@i915_susp...@basic-s2idle-without-i915.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/bat-jsl-3/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#5190])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271]) +12 other tests
skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-vga-1.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1072]) +3
other tests skip
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
Possible fixes
* igt@kms_psr@sprite_plane_onoff:
- bat-jsl-3: [SKIP][16] ([i915#9648]) -> [PASS][17] +3 other tests
pass
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13865/bat-jsl-3/igt@kms_psr@sprite_plane_onoff.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126143v3/bat-jsl-3/igt@kms_psr@sprite_plane_onoff.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5334]: https://gitlab.f
[Intel-gfx] [PATCH v4 1/1] drm/i915/xe2lpd: implement WA for underruns while enabling FBC
FIFO underruns are observed when FBC is enabled on plane 2 or
plane 3. Recommended WA is to update the FBC enabling sequence.
The plane binding register bits need to be updated separately
before programming the FBC enable bit.
Bspec: 74151
Reviewed-by: Mika Kahola #v3
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index bde12fe62275..b73cf1c5ba33 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
static void ivb_fbc_activate(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
+ u32 dpfc_ctl;
if (DISPLAY_VER(i915) >= 10)
glk_fbc_program_cfb_stride(fbc);
@@ -617,8 +618,13 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
if (intel_gt_support_legacy_fencing(to_gt(i915)))
snb_fbc_program_fence(fbc);
+ /* wa_14019417088 Alternative WA*/
+ dpfc_ctl = ivb_dpfc_ctl(fbc);
+ if (DISPLAY_VER(i915) >= 20)
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
+
intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
- DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
+ DPFC_CTL_EN | dpfc_ctl);
}
static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
--
2.34.1
[Intel-gfx] [PATCH v4 0/1] drm/i915/xe2lpd: WA for underruns during FBC enable
Update the FBC enabling sequence. The plane binding register bits need to programmed before fbc enable bit. v2: update the patch subject and description as this underrun is not tied to PSR. FIFO underruns are observed when FBC is enabled on planes 2 or 3. v3: Updated the comments and removed reference to PSR from the comments Added reference to HSD v4: updated the comments to include wa number Vinod Govindapillai (1): drm/i915/xe2lpd: implement WA for underruns while enabling FBC drivers/gpu/drm/i915/display/intel_fbc.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.34.1
