✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/display/dp: Check for MSTM_CAP before MSTM_CTRL write
== Series Details == Series: series starting with [1/2] drm/display/dp: Check for MSTM_CAP before MSTM_CTRL write URL : https://patchwork.freedesktop.org/series/129229/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
✓ Fi.CI.BAT: success for Enable ccs compressed framebuffers on Xe2 (rev4)
== Series Details == Series: Enable ccs compressed framebuffers on Xe2 (rev4) URL : https://patchwork.freedesktop.org/series/128947/ State : success == Summary == CI Bug Log - changes from CI_DRM_14187 -> Patchwork_128947v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v4/index.html Participating hosts (35 -> 32) -- Missing(3): bat-kbl-2 fi-snb-2520m bat-adls-6 Known issues Here are the changes found in Patchwork_128947v4 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] ([i915#10137]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14187/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v4/fi-bsw-nick/igt@i915_selftest@l...@execlists.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-bsw-nick:[DMESG-FAIL][3] -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14187/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v4/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_lrc: - bat-adlm-1: [INCOMPLETE][5] ([i915#9413]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14187/bat-adlm-1/igt@i915_selftest@live@gt_lrc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v4/bat-adlm-1/igt@i915_selftest@live@gt_lrc.html [i915#10137]: https://gitlab.freedesktop.org/drm/intel/issues/10137 [i915#9413]: https://gitlab.freedesktop.org/drm/intel/issues/9413 Build changes - * Linux: CI_DRM_14187 -> Patchwork_128947v4 CI-20190529: 20190529 CI_DRM_14187: 0f1b42b9d395bd4097b2846230a13869dc638216 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7694: 814cd9883b94be1c61d830b2c1279dc2265476bf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_128947v4: 0f1b42b9d395bd4097b2846230a13869dc638216 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 6020d5a60593 drm/i915/display: On Xe2 always enable decompression with tile4 bd4fc9a6b228 drm/xe/xe2: Limit ccs framebuffers to tile4 only 9023696a4285 drm/xe: store bind time pat index to xe_bo 84520e9668e3 drm/xe: add bind time pat index to xe_bo structure c5f74e43b29f drm/xe/pat: annotate pat index table with compression information == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v4/index.html
[PATCH 6/6] drm/i915/hdcp: Read Rxcaps for robustibility
We see some monitors and docks report incorrect hdcp version
and capability in first few reads so we read rx_caps three times
before we conclude the monitor's or docks HDCP capability
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 22
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 5b724bd89329..f1b96bb3b727 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -640,7 +640,7 @@ int intel_dp_hdcp2_capable(struct intel_connector
*connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_dp_aux *aux;
u8 rx_caps[3];
- int ret;
+ int ret, i;
if (remote_req)
aux = >port->aux;
@@ -648,15 +648,19 @@ int intel_dp_hdcp2_capable(struct intel_connector
*connector,
aux = _port->dp.aux;
*capable = false;
- ret = drm_dp_dpcd_read(aux,
- DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
- rx_caps, HDCP_2_2_RXCAPS_LEN);
- if (ret != HDCP_2_2_RXCAPS_LEN)
- return ret >= 0 ? -EIO : ret;
+ for (i = 0; i < 3; i++) {
+ ret = drm_dp_dpcd_read(aux,
+ DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
+ rx_caps, HDCP_2_2_RXCAPS_LEN);
+ if (ret != HDCP_2_2_RXCAPS_LEN)
+ return ret >= 0 ? -EIO : ret;
- if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
- HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
- *capable = true;
+ if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
+ HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) {
+ *capable = true;
+ break;
+ }
+ }
return 0;
}
--
2.25.1
[PATCH 4/6] drm/i915/hdcp: Extract hdcp structure from correct connector
Currently intel_hdcp is not being extracted from primary connector
this patch fixes that.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 21c503566fdd..5b724bd89329 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -389,7 +389,9 @@ intel_dp_hdcp2_wait_for_msg(struct intel_connector
*connector,
const struct hdcp2_dp_msg_data *hdcp2_msg_data)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct intel_hdcp *hdcp = >hdcp;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct intel_dp *dp = _port->dp;
+ struct intel_hdcp *hdcp = >attached_connector->hdcp;
u8 msg_id = hdcp2_msg_data->msg_id;
int ret, timeout;
bool msg_ready = false;
@@ -505,8 +507,9 @@ int intel_dp_hdcp2_read_msg(struct intel_connector
*connector,
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_hdcp *hdcp = >hdcp;
struct drm_dp_aux *aux = _port->dp.aux;
+ struct intel_dp *dp = _port->dp;
+ struct intel_hdcp *hdcp = >attached_connector->hdcp;
unsigned int offset;
u8 *byte = buf;
ssize_t ret, bytes_to_recv, len;
--
2.25.1
[PATCH 5/6] drm/i915/hdcp: Allocate stream id after HDCP AKE stage
Allocate stream id after HDCP AKE stage and not before so that it
can also be done during link integrity check.
Right now for MST scenarios LIC fails after hdcp enablement for this
reason.
Signed-off-by: Suraj Kandpal
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_hdcp.c | 124 --
2 files changed, 59 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index aa559598f049..d627cedc11a1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -541,6 +541,7 @@ struct intel_hdcp {
u64 value;
struct delayed_work check_work;
struct work_struct prop_work;
+ struct drm_modeset_acquire_ctx *acquire_ctx;
/* HDCP1.4 Encryption status */
bool hdcp_encrypted;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b88a4713e6a8..1ba9ebe67a29 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -30,8 +30,9 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
-static int intel_conn_to_vcpi(struct drm_atomic_state *state,
- struct intel_connector *connector)
+static int
+intel_conn_to_vcpi(struct drm_modeset_acquire_ctx *acquire_ctx,
+ struct intel_connector *connector)
{
struct drm_dp_mst_topology_mgr *mgr;
struct drm_dp_mst_atomic_payload *payload;
@@ -43,7 +44,7 @@ static int intel_conn_to_vcpi(struct drm_atomic_state *state,
return 0;
mgr = connector->port->mgr;
- drm_modeset_lock(>base.lock, state->acquire_ctx);
+ drm_modeset_lock(>base.lock, acquire_ctx);
mst_state = to_drm_dp_mst_topology_state(mgr->base.state);
payload = drm_atomic_get_mst_payload_state(mst_state, connector->port);
if (drm_WARN_ON(mgr->dev, !payload))
@@ -68,19 +69,51 @@ static int intel_conn_to_vcpi(struct drm_atomic_state
*state,
* DP MST topology. Though it is not compulsory, security fw should change its
* policy to mark different content_types for different streams.
*/
-static void
-intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+static int
+intel_hdcp_required_content_stream(struct intel_hdcp *hdcp,
+ struct intel_digital_port *dig_port)
{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct hdcp_port_data *data = _port->hdcp_port_data;
bool enforce_type0 = false;
int k;
if (dig_port->hdcp_auth_status)
- return;
+ return 0;
+
+ data->k = 0;
if (!dig_port->hdcp_mst_type1_capable)
enforce_type0 = true;
+ drm_connector_list_iter_begin(>drm, _iter);
+ for_each_intel_connector_iter(connector, _iter) {
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ data->streams[data->k].stream_id =
+ intel_conn_to_vcpi(hdcp->acquire_ctx, connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(_iter);
+
+ if (drm_WARN_ON(>drm, data->k > INTEL_NUM_PIPES(i915) || data->k
== 0))
+ return -EINVAL;
+
/*
* Apply common protection level across all streams in DP MST Topology.
* Use highest supported content type for all streams in DP MST
Topology.
@@ -88,18 +121,23 @@ intel_hdcp_required_content_stream(struct
intel_digital_port *dig_port)
for (k = 0; k < data->k; k++)
data->streams[k].stream_type =
enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 :
DRM_MODE_HDCP_CONTENT_TYPE1;
+
+ return 0;
}
-static void intel_hdcp_prepare_streams(struct intel_connector *connector)
+static int intel_hdcp_prepare_streams(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = _port->hdcp_port_data;
struct intel_hdcp *hdcp = >hdcp;
if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
+ data->k = 1;
+ data->streams[0].stream_id = 0;
[PATCH 3/6] drm/i915/hdcp: Remove additional timing for reading mst hdcp message
Now that we have moved back to direct reads the additional timing
is not required hence this can be removed.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 4979c9e25cf0..21c503566fdd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -549,13 +549,8 @@ int intel_dp_hdcp2_read_msg(struct intel_connector
*connector,
/* Entire msg read timeout since initiate of msg read */
if (bytes_to_recv == size - 1 &&
hdcp2_msg_data->msg_read_timeout > 0) {
- if (intel_encoder_is_mst(connector->encoder))
- msg_end = ktime_add_ms(ktime_get_raw(),
-
hdcp2_msg_data->msg_read_timeout *
-
connector->port->parent->num_ports);
- else
- msg_end = ktime_add_ms(ktime_get_raw(),
-
hdcp2_msg_data->msg_read_timeout);
+ msg_end = ktime_add_ms(ktime_get_raw(),
+
hdcp2_msg_data->msg_read_timeout);
}
ret = drm_dp_dpcd_read(aux, offset,
--
2.25.1
[PATCH 1/6] drm/i915/hdcp: Move to direct reads for HDCP
Even for MST scenarios we need to do direct reads only on the
immediate downstream device the rest of the authentication is taken
care by that device. Remote reads will only be used to check
capability of the monitors in MST topology.
--v2
-Add fixes tag [Ankit]
-Derive aux where needed rather than through a function [Ankit]
Fixes: ae4f902bb344 ("drm/i915/hdcp: Send the correct aux for DPMST HDCP
scenario")
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 31 ++--
1 file changed, 9 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 3a595cd433d4..defc90936317 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -330,23 +330,13 @@ static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[]
= {
0, 0 },
};
-static struct drm_dp_aux *
-intel_dp_hdcp_get_aux(struct intel_connector *connector)
-{
- struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
-
- if (intel_encoder_is_mst(connector->encoder))
- return >port->aux;
- else
- return _port->dp.aux;
-}
-
static int
intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
u8 *rx_status)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct drm_dp_aux *aux = intel_dp_hdcp_get_aux(connector);
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_dp_aux *aux = _port->dp.aux;
ssize_t ret;
ret = drm_dp_dpcd_read(aux,
@@ -454,8 +444,9 @@ int intel_dp_hdcp2_write_msg(struct intel_connector
*connector,
unsigned int offset;
u8 *byte = buf;
ssize_t ret, bytes_to_write, len;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_dp_aux *aux = _port->dp.aux;
const struct hdcp2_dp_msg_data *hdcp2_msg_data;
- struct drm_dp_aux *aux;
hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
if (!hdcp2_msg_data)
@@ -463,8 +454,6 @@ int intel_dp_hdcp2_write_msg(struct intel_connector
*connector,
offset = hdcp2_msg_data->offset;
- aux = intel_dp_hdcp_get_aux(connector);
-
/* No msg_id in DP HDCP2.2 msgs */
bytes_to_write = size - 1;
byte++;
@@ -490,7 +479,8 @@ static
ssize_t get_receiver_id_list_rx_info(struct intel_connector *connector,
u32 *dev_cnt, u8 *byte)
{
- struct drm_dp_aux *aux = intel_dp_hdcp_get_aux(connector);
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_dp_aux *aux = _port->dp.aux;
ssize_t ret;
u8 *rx_info = byte;
@@ -516,7 +506,7 @@ int intel_dp_hdcp2_read_msg(struct intel_connector
*connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_hdcp *hdcp = >hdcp;
- struct drm_dp_aux *aux;
+ struct drm_dp_aux *aux = _port->dp.aux;
unsigned int offset;
u8 *byte = buf;
ssize_t ret, bytes_to_recv, len;
@@ -530,8 +520,6 @@ int intel_dp_hdcp2_read_msg(struct intel_connector
*connector,
return -EINVAL;
offset = hdcp2_msg_data->offset;
- aux = intel_dp_hdcp_get_aux(connector);
-
ret = intel_dp_hdcp2_wait_for_msg(connector, hdcp2_msg_data);
if (ret < 0)
return ret;
@@ -651,12 +639,11 @@ static
int intel_dp_hdcp2_capable(struct intel_connector *connector,
bool *capable)
{
- struct drm_dp_aux *aux;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_dp_aux *aux = _port->dp.aux;
u8 rx_caps[3];
int ret;
- aux = intel_dp_hdcp_get_aux(connector);
-
*capable = false;
ret = drm_dp_dpcd_read(aux,
DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
--
2.25.1
[PATCH 2/6] drm/i915/hdcp: HDCP Capability for the downstream device
Currently we are only checking capability of remote device and not
immediate downstream device but during capability check we need are
concerned with only the HDCP capability of downstream device.
During i915_display_info reporting we need HDCP Capability for both
the monitors and downstream branch device if any this patch adds that.
--v2
-Use MST Hub HDCP version [Ankit]
Signed-off-by: Suraj Kandpal
---
.../drm/i915/display/intel_display_debugfs.c | 19 +++
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 9 +++--
drivers/gpu/drm/i915/display/intel_hdcp.c | 6 +++---
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
6 files changed, 28 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 6f2d13c8ccf7..69267d0c4021 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -188,7 +188,8 @@ static void intel_panel_info(struct seq_file *m,
}
static void intel_hdcp_info(struct seq_file *m,
- struct intel_connector *intel_connector)
+ struct intel_connector *intel_connector,
+ bool remote_req)
{
bool hdcp_cap, hdcp2_cap;
@@ -198,7 +199,7 @@ static void intel_hdcp_info(struct seq_file *m,
}
hdcp_cap = intel_hdcp_capable(intel_connector);
- hdcp2_cap = intel_hdcp2_capable(intel_connector);
+ hdcp2_cap = intel_hdcp2_capable(intel_connector, remote_req);
if (hdcp_cap)
seq_puts(m, "HDCP1.4 ");
@@ -285,7 +286,12 @@ static void intel_connector_info(struct seq_file *m,
}
seq_puts(m, "\tHDCP version: ");
- intel_hdcp_info(m, intel_connector);
+ intel_hdcp_info(m, intel_connector, true);
+
+ if (intel_encoder_is_mst(encoder)) {
+ seq_puts(m, "\tMST Hub HDCP version: ");
+ intel_hdcp_info(m, intel_connector, false);
+ }
seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc);
@@ -1131,7 +1137,12 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
seq_printf(m, "%s:%d HDCP version: ", connector->base.name,
connector->base.base.id);
- intel_hdcp_info(m, connector);
+ intel_hdcp_info(m, connector, true);
+
+ if (intel_encoder_is_mst(connector->encoder)) {
+ seq_puts(m, "\tMST Hub HDCP version: ");
+ intel_hdcp_info(m, connector, false);
+ }
out:
drm_modeset_unlock(>drm.mode_config.connection_mutex);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ae2e8cff9d69..aa559598f049 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -507,7 +507,7 @@ struct intel_hdcp_shim {
/* Detects whether sink is HDCP2.2 capable */
int (*hdcp_2_2_capable)(struct intel_connector *connector,
- bool *capable);
+ bool *capable, bool remote_req);
/* Write HDCP2.2 messages */
int (*write_2_2_msg)(struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index defc90936317..4979c9e25cf0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -637,13 +637,18 @@ int intel_dp_hdcp2_check_link(struct intel_digital_port
*dig_port,
static
int intel_dp_hdcp2_capable(struct intel_connector *connector,
- bool *capable)
+ bool *capable, bool remote_req)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
- struct drm_dp_aux *aux = _port->dp.aux;
+ struct drm_dp_aux *aux;
u8 rx_caps[3];
int ret;
+ if (remote_req)
+ aux = >port->aux;
+ else
+ aux = _port->dp.aux;
+
*capable = false;
ret = drm_dp_dpcd_read(aux,
DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index c3e692e7f790..b88a4713e6a8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -161,7 +161,7 @@ bool intel_hdcp_capable(struct intel_connector *connector)
}
/* Is HDCP2.2 capable on Platform and Sink */
-bool intel_hdcp2_capable(struct intel_connector *connector)
+bool intel_hdcp2_capable(struct intel_connector *connector, bool remote_req)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
[PATCH 0/6] HDCP Type1 MST fixes
We were seeing a blank screen whenever Type1 content was played. This was due to extra timing which was taken as we had moved to remote read and writes previously for MST scenario, which in turn was done as we were not able to do direct read and writes to the immediate downstream device. The correct flow should be that we talk only to the immediate downstream device and the rest needs to be taken care by that device. With this patch series we move back to direct reads and writes, fix the fastset setting because of which direct reads and writes to HDCP related DPCD register stopped working, derive hdcp structure correctly and increase robustability if rxcaps HDCP capability reporting. Signed-off-by: Suraj Kandpal Suraj Kandpal (6): drm/i915/hdcp: Move to direct reads for HDCP drm/i915/hdcp: HDCP Capability for the downstream device drm/i915/hdcp: Remove additional timing for reading mst hdcp message drm/i915/hdcp: Extract hdcp structure from correct connector drm/i915/hdcp: Allocate stream id after HDCP AKE stage drm/i915/hdcp: Read Rxcaps for robustibility .../drm/i915/display/intel_display_debugfs.c | 19 ++- .../drm/i915/display/intel_display_types.h| 3 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 72 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 130 -- drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- 6 files changed, 113 insertions(+), 115 deletions(-) -- 2.25.1
[PATCH 2/2] drm/i915/display/dp: 128/132b DP-capable with SST
With a value of '0' read from MSTM_CAP register MST to be enabled. DP2.1 SCR updates the spec for 128/132b DP capable supporting only one stream and not supporting single stream sideband MSG. The underlying protocol will be MST to enable use of MTP. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9ff0cbd9c0df..05722f10cdd7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4037,9 +4037,15 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) if (!intel_dp_mst_source_support(intel_dp)) return; - - intel_dp->is_mst = sink_can_mst && - i915->display.params.enable_dp_mst; + /* +* Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then +* DP2.1 can be enabled with underlying protocol using MST for MTP +* TODO: Need to accommodate MSTM_CAP bit[0]=0, bit[1]=1 condition, i.e +* one stream with single stream sideband msg. +*/ + intel_dp->is_mst = (sink_can_mst || (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & +DP_CAP_ANSI_128B132B)) && + i915->display.params.enable_dp_mst; drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr, intel_dp->is_mst); -- 2.25.1
[PATCH 1/2] drm/display/dp: Check for MSTM_CAP before MSTM_CTRL write
With DP2.1, multistream packetization and the underneth MST protocol
will be required for SST. So check for MSTM_CAP to see if MST is really
required and skip the MSTM_CTRL write so that we ensure that only the
underneth protocol and the multistream packetization will be enabled and
sink will not be confused by a corresponding dpcd write.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 26 +++
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 8ca01a6bf645..22d81732a978 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3666,10 +3666,11 @@ int drm_dp_mst_topology_mgr_set_mst(struct
drm_dp_mst_topology_mgr *mgr, bool ms
mgr->mst_primary = mstb;
drm_dp_mst_topology_get_mstb(mgr->mst_primary);
- ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-DP_MST_EN |
-DP_UP_REQ_EN |
-DP_UPSTREAM_IS_SRC);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+DP_MST_EN |
+DP_UP_REQ_EN |
+DP_UPSTREAM_IS_SRC);
if (ret < 0)
goto out_unlock;
@@ -3684,7 +3685,8 @@ int drm_dp_mst_topology_mgr_set_mst(struct
drm_dp_mst_topology_mgr *mgr, bool ms
mstb = mgr->mst_primary;
mgr->mst_primary = NULL;
/* this can fail if the device is gone */
- drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0);
ret = 0;
mgr->payload_id_table_cleared = false;
@@ -3724,8 +3726,9 @@ drm_dp_mst_topology_mgr_invalidate_mstb(struct
drm_dp_mst_branch *mstb)
void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr)
{
mutex_lock(>lock);
- drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
- DP_MST_EN | DP_UPSTREAM_IS_SRC);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+ DP_MST_EN | DP_UPSTREAM_IS_SRC);
mutex_unlock(>lock);
flush_work(>up_req_work);
flush_work(>work);
@@ -3773,10 +3776,11 @@ int drm_dp_mst_topology_mgr_resume(struct
drm_dp_mst_topology_mgr *mgr,
goto out_fail;
}
- ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
-DP_MST_EN |
-DP_UP_REQ_EN |
-DP_UPSTREAM_IS_SRC);
+ if (drm_dp_read_mst_cap(mgr->aux, mgr->dpcd))
+ ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+DP_MST_EN |
+DP_UP_REQ_EN |
+DP_UPSTREAM_IS_SRC);
if (ret < 0) {
drm_dbg_kms(mgr->dev, "mst write failed - undocked during
suspend?\n");
goto out_fail;
--
2.25.1
RE: [PATCH 2/7] drm/i915/hdcp: HDCP Capability for the downstream device
=
>
> On 1/24/2024 6:50 PM, Nautiyal, Ankit K wrote:
> >
> > On 1/12/2024 1:11 PM, Suraj Kandpal wrote:
> >> Currently we are only checking capability of remote device and not
> >> immediate downstream device but during capability check we need are
> >> concerned with only the HDCP capability of downstream device.
> >> During i915_display_info reporting we need HDCP Capability for both
> >> the monitors and downstream branch device if any this patch adds that.
> >
> >
> > I agree cases where MST hub/docker and sink are of different
> > capabilities, this creates a confusion.
> >
> > with this change, perhaps kms_content_protection IGT can also be
> > changed to check for MST hub's capability.
> >
> > Only thing is that for hdmi the 'remote_req' doesnt make sense.
> >
> Instead of changing the hdcp_2_2_capable can we just have a separate
> function for intel_dp_remote_hdcp2_capable(), which uses aux =
> >port->aux.
Yes I agree about the hdmi has a argument it wont use but I went with the lesser
Of the two evils . If I went with the approach suggested the problem would be
that
debug fs calls intel_hdcp2_capable which has other checks for mei, gsc and If
HW supports
hdcp2 or not so all this would also have to be put in this function
intel_dp_remote_hdcp2_capable()
which I feel would create much more of a mess
Regards,
Suraj Kandpal
>
> The common code for reading HDCP2_2 Rx caps can be pulled out in a
> separate function, which we can call only in case of MST when we read
> remote.
>
> Also we might need to have similar thing for HDCP1.4.
>
>
> Regards,
>
> Ankit
>
>
> >>
> >> Signed-off-by: Suraj Kandpal
> >> ---
> >> .../drm/i915/display/intel_display_debugfs.c | 19
> >> +++
> >> .../drm/i915/display/intel_display_types.h | 2 +-
> >> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
> >> drivers/gpu/drm/i915/display/intel_hdcp.c | 6 +++---
> >> drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
> >> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> >> 6 files changed, 23 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> index d951edb36687..457f13357fad 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> @@ -210,7 +210,8 @@ static void intel_panel_info(struct seq_file *m,
> >> }
> >> static void intel_hdcp_info(struct seq_file *m,
> >> - struct intel_connector *intel_connector)
> >> + struct intel_connector *intel_connector,
> >> + bool remote_req)
> >> {
> >> bool hdcp_cap, hdcp2_cap;
> >> @@ -220,7 +221,7 @@ static void intel_hdcp_info(struct seq_file *m,
> >> }
> >> hdcp_cap = intel_hdcp_capable(intel_connector);
> >> - hdcp2_cap = intel_hdcp2_capable(intel_connector);
> >> + hdcp2_cap = intel_hdcp2_capable(intel_connector, remote_req);
> >> if (hdcp_cap)
> >> seq_puts(m, "HDCP1.4 ");
> >> @@ -307,7 +308,12 @@ static void intel_connector_info(struct seq_file
> >> *m,
> >> }
> >> seq_puts(m, "\tHDCP version: ");
> >> - intel_hdcp_info(m, intel_connector);
> >> + intel_hdcp_info(m, intel_connector, true);
> >> +
> >> + if (intel_encoder_is_mst(encoder)) {
> >> + seq_puts(m, "\tHDCP Branch Device version: ");
> >> + intel_hdcp_info(m, intel_connector, false);
> >> + }
> >> seq_printf(m, "\tmax bpc: %u\n",
> >> connector->display_info.bpc);
> >> @@ -1153,7 +1159,12 @@ static int
> >> i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> >> seq_printf(m, "%s:%d HDCP version: ", connector->base.name,
> >> connector->base.base.id);
> >> - intel_hdcp_info(m, connector);
> >> + intel_hdcp_info(m, connector, true);
> >> +
> >> + if (intel_encoder_is_mst(connector->encoder)) {
> >> + seq_puts(m, "\tHDCP Branch Device version: ");
> >
> >
> > Perhaps MST HUB HDCP version?
> >
> >
> >> + intel_hdcp_info(m, connector, false);
> >> + }
> >> out:
> >> drm_modeset_unlock(>drm.mode_config.connection_mutex);
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index ae2e8cff9d69..aa559598f049 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -507,7 +507,7 @@ struct intel_hdcp_shim {
> >> /* Detects whether sink is HDCP2.2 capable */
> >> int (*hdcp_2_2_capable)(struct intel_connector *connector,
> >> - bool *capable);
> >> + bool *capable, bool remote_req);
> >> /* Write HDCP2.2 messages */
> >> int (*write_2_2_msg)(struct intel_connector *connector, diff
> >> --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> >>
✓ Fi.CI.BAT: success for drm/i915/display: Move some LNL registers
== Series Details == Series: drm/i915/display: Move some LNL registers URL : https://patchwork.freedesktop.org/series/129226/ State : success == Summary == CI Bug Log - changes from CI_DRM_14186 -> Patchwork_129226v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/index.html Participating hosts (34 -> 34) -- Additional (2): bat-kbl-2 bat-mtlp-8 Missing(2): fi-snb-2520m fi-pnv-d510 Known issues Here are the changes found in Patchwork_129226v1 that come from known issues: ### CI changes ### Possible fixes * boot: - bat-rpls-2: [FAIL][1] ([i915#10078]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14186/bat-rpls-2/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-rpls-2/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rpls-2: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-rpls-2/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-8: NOTRUN -> [SKIP][4] ([i915#9318]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-kbl-2: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1849]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-kbl-2/igt@fb...@info.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-kbl-2: NOTRUN -> [SKIP][6] ([fdo#109271]) +35 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-rpls-2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-rpls-2/igt@gem_lmem_swapp...@verify-random.html - bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-rpls-2: NOTRUN -> [SKIP][12] ([i915#3282]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-rpls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-rpls-2: NOTRUN -> [SKIP][13] ([i915#6621]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-rpls-2/igt@i915_pm_...@basic-api.html - bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#6621]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_pm: - bat-rpls-2: NOTRUN -> [DMESG-FAIL][15] ([i915#10010]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#5190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#4212]) +8 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-rpls-2: NOTRUN -> [SKIP][18] ([i915#4103]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-rpls-2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#4213]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129226v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-rpls-2: NOTRUN -> [SKIP][20] ([i915#3555] / [i915#3840] / [i915#9886]) [20]:
✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Move some LNL registers
== Series Details == Series: drm/i915/display: Move some LNL registers URL : https://patchwork.freedesktop.org/series/129226/ State : warning == Summary == Error: dim checkpatch failed b7a2f39f8e10 drm/i915/xe2lpd: Move D2D enable/disable -:87: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (16, 23) #87: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3345: + if (DISPLAY_VER(dev_priv) >= 20) + buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; total: 0 errors, 1 warnings, 0 checks, 80 lines checked 5b1009e12a6b drm/i915/xe2lpd: Move registers to PICA -:384: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #384: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:27: +#define __xe2lpd_port_idx(port) \ + (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A) -:384: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'port' may be better as '(port)' to avoid precedence issues #384: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:27: +#define __xe2lpd_port_idx(port) \ + (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A) -:397: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #397: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:39: +#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \ + (DISPLAY_VER(i915__) >= 20 ? \ +_XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \ +_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)) -:397: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'lane' - possible side-effects? #397: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:39: +#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \ + (DISPLAY_VER(i915__) >= 20 ? \ +_XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \ +_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)) -:415: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #415: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:59: +#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \ + (DISPLAY_VER(i915__) >= 20 ? \ +_XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \ +_XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) -:415: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'lane' - possible side-effects? #415: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:59: +#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \ + (DISPLAY_VER(i915__) >= 20 ? \ +_XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \ +_XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) -:432: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #432: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:90: +#define XELPDP_PORT_BUF_CTL1(i915__, port) \ + (DISPLAY_VER(i915__) >= 20 ? \ +_XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) : \ +_XELPDP_PORT_BUF_CTL1(port)) -:450: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #450: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:115: +#define XELPDP_PORT_BUF_CTL2(i915__, port) \ + (DISPLAY_VER(i915__) >= 20 ? \ +_XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) : \ +_XELPDP_PORT_BUF_CTL2(port)) -:467: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #467: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:138: +#define XELPDP_PORT_BUF_CTL3(i915__, port) \ + (DISPLAY_VER(i915__) >= 20 ? \ +_XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) : \ +_XELPDP_PORT_BUF_CTL3(port)) -:484: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #484: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:161: +#define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane) \ + (DISPLAY_VER(i915__) >= 20 ? \ +_XELPDP_PORT_MSGBUS_TIMER(__xe2lpd_port_idx(port), lane) : \ +_XELPDP_PORT_MSGBUS_TIMER(port, lane)) -:484: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'lane' - possible side-effects? #484: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:161: +#define
✗ Fi.CI.SPARSE: warning for drm/i915/display: Move some LNL registers
== Series Details == Series: drm/i915/display: Move some LNL registers URL : https://patchwork.freedesktop.org/series/129226/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
[PATCH 0/2] drm/i915/display: Move some LNL registers
2 patches removed from the earlier batch of updates in LNL due to using saved_port_bits which is not entirely correct. This time, instead of the 2 preparatory refactor patches, just make sure to set the the bits in later writes to DDI_BUF_CTL(). Notes that it's not needed to set clear the bit in intel_dp->DP when disabling since the enable part starts from scratch in intel_ddi_init_dp_buf_reg(). Lucas De Marchi (2): drm/i915/xe2lpd: Move D2D enable/disable drm/i915/xe2lpd: Move registers to PICA drivers/gpu/drm/i915/display/intel_cx0_phy.c | 87 ++- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 63 -- drivers/gpu/drm/i915/display/intel_ddi.c | 60 + drivers/gpu/drm/i915/display/intel_tc.c | 16 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 + 5 files changed, 155 insertions(+), 73 deletions(-) -- 2.43.0
[PATCH 2/2] drm/i915/xe2lpd: Move registers to PICA
Some registers for DDI A/B moved to PICA and now follow the same format
as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
- Share the implementation between xe2lpd and previous
platforms: there are minor layout changes, it's mostly the
register location that changed
- Handle offsets after TC ports
v2:
- Explain better the trick to use just the second range (Matt Roper)
- Add missing conversions after rebase (Matt Roper)
- Use macro instead of inline function, avoiding includes in the
header (Jani)
- Prefix old macros with underscore so they don't get used by mistake,
and name the new ones using the previous names
v3: Use the same logic for the recently-introduced XELPDP_PORT_MSGBUS_TIMER
(Gustavo)
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 87 ++-
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 63 --
drivers/gpu/drm/i915/display/intel_ddi.c | 20 +++--
drivers/gpu/drm/i915/display/intel_tc.c | 16 ++--
4 files changed, 121 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6b25e195232f..5b89233c709f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -78,7 +78,7 @@ static void intel_cx0_program_msgbus_timer(struct
intel_encoder *encoder)
for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)
intel_de_rmw(i915,
-XELPDP_PORT_MSGBUS_TIMER(encoder->port, lane),
+XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port,
lane),
XELPDP_PORT_MSGBUS_TIMER_VAL_MASK,
XELPDP_PORT_MSGBUS_TIMER_VAL);
}
@@ -117,7 +117,7 @@ static void intel_cx0_phy_transaction_end(struct
intel_encoder *encoder, intel_w
static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
enum port port, int lane)
{
- intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+ intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
0, XELPDP_PORT_P2M_RESPONSE_READY |
XELPDP_PORT_P2M_ERROR_SET);
}
@@ -125,10 +125,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private
*i915, enum port port, i
{
enum phy phy = intel_port_to_phy(i915, port);
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port,
lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915,
port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_err_once(>drm, "Failed to bring PHY %c to idle.\n",
phy_name(phy));
@@ -144,7 +144,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private
*i915, enum port port,
enum phy phy = intel_port_to_phy(i915, port);
if (__intel_de_wait_for_register(i915,
-XELPDP_PORT_P2M_MSGBUS_STATUS(port,
lane),
+XELPDP_PORT_P2M_MSGBUS_STATUS(i915,
port, lane),
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_MSGBUS_TIMEOUT_FAST_US,
@@ -152,7 +152,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private
*i915, enum port port,
drm_dbg_kms(>drm, "PHY %c Timeout waiting for message
ACK. Status: 0x%x\n",
phy_name(phy), *val);
- if (!(intel_de_read(i915, XELPDP_PORT_MSGBUS_TIMER(port, lane))
&
+ if (!(intel_de_read(i915, XELPDP_PORT_MSGBUS_TIMER(i915, port,
lane)) &
XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT))
drm_dbg_kms(>drm,
"PHY %c Hardware did not detect a
timeout\n",
@@ -186,7 +186,7 @@ static int __intel_cx0_read_once(struct drm_i915_private
*i915, enum port port,
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port,
lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915,
port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(>drm,
@@ -195,7 +195,7 @@ static int __intel_cx0_read_once(struct drm_i915_private
*i915, enum port port,
return -ETIMEDOUT;
}
[PATCH 1/2] drm/i915/xe2lpd: Move D2D enable/disable
Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL (now named DDI_CTL_DE in the spec).
Make the functions mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic
to work with multiple reg location and bitfield layout.
v2: Set/Clear XE2LPD_DDI_BUF_D2D_LINK_ENABLE in saved_port_bits when
enabling/disabling D2D so DDI_BUF_CTL is correctly programmed in
other places without overriding these bits (Clint)
v3: Leave saved_port_bits alone as those bits are not meant to be
modified outside of the port initialization. Rather propagate the
additional bit in DDI_BUF_CTL to be set when that register is
written again after D2D is enabled.
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 44 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 36 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 12a29363e5df..188c537dbb5d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2429,13 +2429,22 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
+ i915_reg_t reg;
+ u32 set_bits, wait_bits;
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
-XELPDP_PORT_BUF_D2D_LINK_ENABLE);
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ reg = DDI_BUF_CTL(port);
+ set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+ } else {
+ reg = XELPDP_PORT_BUF_CTL1(port);
+ set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+ }
- if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
-XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
- drm_err(_priv->drm, "Timeout waiting for D2D Link enable
for PORT_BUF_CTL %c\n",
+ intel_de_rmw(dev_priv, reg, 0, set_bits);
+ if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
+ drm_err(_priv->drm, "Timeout waiting for D2D Link enable
for DDI/PORT_BUF_CTL %c\n",
port_name(port));
}
}
@@ -2898,13 +2907,22 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
+ i915_reg_t reg;
+ u32 clr_bits, wait_bits;
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
-XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ reg = DDI_BUF_CTL(port);
+ clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+ } else {
+ reg = XELPDP_PORT_BUF_CTL1(port);
+ clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+ }
- if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
- XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
- drm_err(_priv->drm, "Timeout waiting for D2D Link disable
for PORT_BUF_CTL %c\n",
+ intel_de_rmw(dev_priv, reg, clr_bits, 0);
+ if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
+ drm_err(_priv->drm, "Timeout waiting for D2D Link disable
for DDI/PORT_BUF_CTL %c\n",
port_name(port));
}
@@ -3323,6 +3341,9 @@ static void intel_enable_ddi_hdmi(struct
intel_atomic_state *state,
XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL,
port_buf);
buf_ctl |= DDI_PORT_WIDTH(lane_count);
+
+ if (DISPLAY_VER(dev_priv) >= 20)
+ buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
drm_WARN_ON(_priv->drm,
!intel_tc_port_in_legacy_mode(dig_port));
buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
@@ -3543,6 +3564,9 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp
*intel_dp,
/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to
port slice */
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
+ if (DISPLAY_VER(dev_priv) >= 20)
+ intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27dc903f0553..f034b7b0f1da 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5684,6 +5684,8 @@ enum
Re: Re: Re: [PATCH 3/5] drm/ttm: replace busy placement with flags v6
On Fri, Jan 26, 2024 at 04:16:58PM -0600, Lucas De Marchi wrote:
On Thu, Jan 18, 2024 at 05:38:16PM +0100, Thomas Hellström wrote:
On 1/17/24 13:27, Thomas Hellström wrote:
On 1/17/24 11:47, Thomas Hellström wrote:
Hi, Christian
Xe changes look good. Will send the series to xe ci to check for
regressions.
Hmm, there are some checkpatch warnings about author / SOB email
mismatch,
With those fixed, this patch is
Reviewed-by: Thomas Hellström
it actually broke drm-tip now that this is merged:
../drivers/gpu/drm/xe/xe_bo.c:41:10: error: ‘struct ttm_placement’ has no
member named ‘num_busy_placement’; did you mean ‘num_placement’
41 | .num_busy_placement = 1,
| ^~
| num_placement
../drivers/gpu/drm/xe/xe_bo.c:41:31: error: excess elements in struct
initializer [-Werror]
41 | .num_busy_placement = 1,
| ^
Apparently a conflict with another patch that got applied a few days
ago: a201c6ee37d6 ("drm/xe/bo: Evict VRAM to TT rather than to system")
oh, no... apparently that commit is from a long time ago. The problem
was that drm-misc-next was not yet in sync with drm-next. Thomas, do you
have a fixup for this to put in rerere?
Lucas De Marchi
Re: Re: [PATCH 3/5] drm/ttm: replace busy placement with flags v6
On Thu, Jan 18, 2024 at 05:38:16PM +0100, Thomas Hellström wrote:
On 1/17/24 13:27, Thomas Hellström wrote:
On 1/17/24 11:47, Thomas Hellström wrote:
Hi, Christian
Xe changes look good. Will send the series to xe ci to check for
regressions.
Hmm, there are some checkpatch warnings about author / SOB email
mismatch,
With those fixed, this patch is
Reviewed-by: Thomas Hellström
it actually broke drm-tip now that this is merged:
../drivers/gpu/drm/xe/xe_bo.c:41:10: error: ‘struct ttm_placement’ has no
member named ‘num_busy_placement’; did you mean ‘num_placement’
41 | .num_busy_placement = 1,
| ^~
| num_placement
../drivers/gpu/drm/xe/xe_bo.c:41:31: error: excess elements in struct
initializer [-Werror]
41 | .num_busy_placement = 1,
| ^
Apparently a conflict with another patch that got applied a few days
ago: a201c6ee37d6 ("drm/xe/bo: Evict VRAM to TT rather than to system")
Lucas De Marchi
But worserthere are some regressions in the dma-buf ktest (it tests
evicting of a dynamic dma-buf),
https://patchwork.freedesktop.org/series/128873/
I'll take a look later today or tomorrow.
These are from the next patch. Will continue the discussion there.
/Thomas
/Thomas
/Thomas
On 1/12/24 13:51, Christian König wrote:
From: Somalapuram Amaranath
Instead of a list of separate busy placement add flags which indicate
that a placement should only be used when there is room or if we
need to
evict.
v2: add missing TTM_PL_FLAG_IDLE for i915
v3: fix auto build test ERROR on drm-tip/drm-tip
v4: fix some typos pointed out by checkpatch
v5: cleanup some rebase problems with VMWGFX
v6: implement some missing VMWGFX functionality pointed out by Zack,
rename the flags as suggested by Michel, rebase on drm-tip and
adjust XE as well
Signed-off-by: Christian König
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 +---
drivers/gpu/drm/drm_gem_vram_helper.c | 2 -
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 37 +--
drivers/gpu/drm/loongson/lsdc_ttm.c | 2 -
drivers/gpu/drm/nouveau/nouveau_bo.c | 59 +++--
drivers/gpu/drm/nouveau/nouveau_bo.h | 1 -
drivers/gpu/drm/qxl/qxl_object.c | 2 -
drivers/gpu/drm/qxl/qxl_ttm.c | 2 -
drivers/gpu/drm/radeon/radeon_object.c | 2 -
drivers/gpu/drm/radeon/radeon_ttm.c | 8 +--
drivers/gpu/drm/radeon/radeon_uvd.c | 1 -
drivers/gpu/drm/ttm/ttm_bo.c | 21 ---
drivers/gpu/drm/ttm/ttm_resource.c | 73
+-
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 33 +++---
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 4 --
drivers/gpu/drm/xe/xe_bo.c | 33 +-
include/drm/ttm/ttm_placement.h | 10 +--
include/drm/ttm/ttm_resource.h | 8 +--
19 files changed, 118 insertions(+), 197 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 425cebcc5cbf..b671b0665492 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -220,9 +220,6 @@ void amdgpu_bo_placement_from_domain(struct
amdgpu_bo *abo, u32 domain)
placement->num_placement = c;
placement->placement = places;
-
- placement->num_busy_placement = c;
- placement->busy_placement = places;
}
/**
@@ -1397,8 +1394,7 @@ vm_fault_t
amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
AMDGPU_GEM_DOMAIN_GTT);
/* Avoid costly evictions; only set GTT as a busy placement */
- abo->placement.num_busy_placement = 1;
- abo->placement.busy_placement = >placements[1];
+ abo->placements[0].flags |= TTM_PL_FLAG_DESIRED;
r = ttm_bo_validate(bo, >placement, );
if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 75c9fd2c6c2a..8722beba494e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -102,23 +102,19 @@ static void amdgpu_evict_flags(struct
ttm_buffer_object *bo,
/* Don't handle scatter gather BOs */
if (bo->type == ttm_bo_type_sg) {
placement->num_placement = 0;
- placement->num_busy_placement = 0;
return;
}
/* Object isn't an AMDGPU object so ignore */
if (!amdgpu_bo_is_amdgpu_bo(bo)) {
placement->placement =
- placement->busy_placement =
placement->num_placement = 1;
- placement->num_busy_placement = 1;
return;
}
abo = ttm_to_amdgpu_bo(bo);
if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
placement->num_placement = 0;
-
✓ Fi.CI.BAT: success for Enable ccs compressed framebuffers on Xe2 (rev3)
== Series Details ==
Series: Enable ccs compressed framebuffers on Xe2 (rev3)
URL : https://patchwork.freedesktop.org/series/128947/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14186 -> Patchwork_128947v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/index.html
Participating hosts (34 -> 34)
--
Additional (2): bat-kbl-2 bat-mtlp-8
Missing(2): fi-snb-2520m fi-pnv-d510
Known issues
Here are the changes found in Patchwork_128947v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1849])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-kbl-2/igt@fb...@info.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][3] ([fdo#109271]) +35 other tests
skip
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4083])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@gem_m...@basic.html
* igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@gem_mmap_...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#6621])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#5190])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4212]) +8 other tests skip
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4213]) +1 other test skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#3840] /
[i915#9159])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([fdo#109285])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#5274])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@kms_force_connector_ba...@prune-stale-modes.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#8809])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#3708] / [i915#4077]) +1
other test skip
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#3708]) +2 other tests skip
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128947v3/bat-mtlp-8/igt@prime_v...@basic-fence-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]:
[PATCH 2/5] drm/xe: add bind time pat index to xe_bo structure
Add BO bind time pat index member and framebuffer pin time pat index
to xe_bo structure.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/xe/xe_bo_types.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index 14ef13b7b421..ccf63058be66 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -91,6 +91,17 @@ struct xe_bo {
/** @vram_userfault_link: Link into @mem_access.vram_userfault.list */
struct list_head vram_userfault_link;
+
+ /**
+* @pat_index: The pat index requested when bind this BO
+*/
+ u16 pat_index;
+
+ /**
+* @pat_index_scanout: The pat index in use when pinning this BO
+* as framebuffer.
+*/
+ u16 pat_index_scanout;
};
#define intel_bo_to_drm_bo(bo) (&(bo)->ttm.base)
--
2.25.1
[PATCH 5/5] drm/i915/display: On Xe2 always enable decompression with tile4
With Xe2 always treat tile4 as if it was using flat ccs.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 511dc1544854..43209909593f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -948,6 +948,11 @@ static u32 skl_plane_ctl(const struct intel_crtc_state
*crtc_state,
if (DISPLAY_VER(dev_priv) == 13)
plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
+ if (GRAPHICS_VER(dev_priv) >= 20 &&
+ fb->modifier == I915_FORMAT_MOD_4_TILED) {
+ plane_ctl |= PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+ }
+
return plane_ctl;
}
--
2.25.1
[PATCH 4/5] drm/xe/xe2: Limit ccs framebuffers to tile4 only
Display engine support ccs only with tile4, prevent other modifiers
from using compressed memory. Store pin time pat index to xe_bo.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 722c84a56607..b2930a226f54 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -10,9 +10,18 @@
#include "intel_fb_pin.h"
#include "xe_ggtt.h"
#include "xe_gt.h"
+#include "xe_pat.h"
#include
+static bool is_compressed(const struct drm_framebuffer *fb)
+{
+ struct xe_bo *bo = intel_fb_obj(fb);
+ struct xe_device *xe = to_xe_device(to_intel_framebuffer(fb)->base.dev);
+
+ return xe_pat_index_has_compression(xe, bo->pat_index);
+}
+
static void
write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32
bo_ofs,
u32 width, u32 height, u32 src_stride, u32 dst_stride)
@@ -349,12 +358,22 @@ void intel_unpin_fb_vma(struct i915_vma *vma, unsigned
long flags)
int intel_plane_pin_fb(struct intel_plane_state *plane_state)
{
struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct xe_device *xe = to_xe_device(to_intel_framebuffer(fb)->base.dev);
struct xe_bo *bo = intel_fb_obj(fb);
struct i915_vma *vma;
/* We reject creating !SCANOUT fb's, so this is weird.. */
drm_WARN_ON(bo->ttm.base.dev, !(bo->flags & XE_BO_SCANOUT_BIT));
+ if (GRAPHICS_VER(xe) >= 20) {
+ if (fb->modifier != I915_FORMAT_MOD_4_TILED &&
+ is_compressed(fb)) {
+ drm_warn(>drm, "Cannot create ccs framebuffer with
other than tile4 mofifier\n");
+ return -EINVAL;
+ }
+ bo->pat_index_scanout = bo->pat_index;
+ }
+
vma = __xe_pin_fb_vma(to_intel_framebuffer(fb), _state->view.gtt);
if (IS_ERR(vma))
return PTR_ERR(vma);
--
2.25.1
[PATCH 1/5] drm/xe/pat: annotate pat index table with compression information
add compressed member into xe_pat_table_entry which will contain
boolean information if given pat_index is compressed or no.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/xe/xe_pat.c | 9 -
drivers/gpu/drm/xe/xe_pat.h | 8
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 1ff6bc79e7d4..c3cc6e90b068 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -104,7 +104,8 @@ static const struct xe_pat_table_entry xelpg_pat_table[] = {
REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \
REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \
REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \
- .coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : XE_COH_NONE \
+ .coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : XE_COH_NONE, \
+ .compressed = comp_en \
}
static const struct xe_pat_table_entry xe2_pat_table[] = {
@@ -148,6 +149,12 @@ u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16
pat_index)
return xe->pat.table[pat_index].coh_mode;
}
+bool xe_pat_index_has_compression(struct xe_device *xe, u16 pat_index)
+{
+ WARN_ON(pat_index >= xe->pat.n_entries);
+ return xe->pat.table[pat_index].compressed;
+}
+
static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry
table[],
int n_entries)
{
diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index fa0dfbe525cd..c8aacd30b184 100644
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -29,6 +29,7 @@ struct xe_pat_table_entry {
#define XE_COH_NONE 1
#define XE_COH_AT_LEAST_1WAY 2
u16 coh_mode;
+ bool compressed;
};
/**
@@ -58,4 +59,11 @@ void xe_pat_dump(struct xe_gt *gt, struct drm_printer *p);
*/
u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index);
+/**
+ * xe_pat_index_has_compression - Is pat_index using ccs compression
+ * @xe: xe device
+ * @pat_index: The pat_index to query
+ */
+bool xe_pat_index_has_compression(struct xe_device *xe, u16 pat_index);
+
#endif
--
2.25.1
[PATCH 3/5] drm/xe: store bind time pat index to xe_bo
Store pat index from xe_vma to xe_bo and check if bo was pinned
as framebuffer and verify pat index is not changing for pinned
framebuffers.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/xe/xe_pt.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index de1030a47588..0a5d7c7543b1 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -1208,10 +1208,11 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma
*vma, struct xe_exec_queue
struct dma_fence *fence;
struct invalidation_fence *ifence = NULL;
struct xe_range_fence *rfence;
+ struct xe_bo *bo = xe_vma_bo(vma);
int err;
bind_pt_update.locked = false;
- xe_bo_assert_held(xe_vma_bo(vma));
+ xe_bo_assert_held(bo);
xe_vm_assert_held(vm);
vm_dbg(_vma_vm(vma)->xe->drm,
@@ -1252,8 +1253,22 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma
*vma, struct xe_exec_queue
return ERR_PTR(-ENOMEM);
}
+ /*
+* BO which has XE_BO_SCANOUT_BIT set and was pinned as framebuffer
+* before with different PAT index cannot be bound with different PAT
+* index. This is to prevent switching CCS on/off from framebuffers
+* on the fly.
+*/
+ if (bo) {
+ if (bo->flags & XE_BO_SCANOUT_BIT && bo->pat_index_scanout &&
+ bo->pat_index_scanout != vma->pat_index)
+ return ERR_PTR(-EINVAL);
+
+ bo->pat_index = vma->pat_index;
+ }
+
fence = xe_migrate_update_pgtables(tile->migrate,
- vm, xe_vma_bo(vma), q,
+ vm, bo, q,
entries, num_entries,
syncs, num_syncs,
_pt_update.base);
@@ -1287,8 +1302,8 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma
*vma, struct xe_exec_queue
DMA_RESV_USAGE_KERNEL :
DMA_RESV_USAGE_BOOKKEEP);
- if (!xe_vma_has_no_bo(vma) && !xe_vma_bo(vma)->vm)
- dma_resv_add_fence(xe_vma_bo(vma)->ttm.base.resv, fence,
+ if (!xe_vma_has_no_bo(vma) && !bo->vm)
+ dma_resv_add_fence(bo->ttm.base.resv, fence,
DMA_RESV_USAGE_BOOKKEEP);
xe_pt_commit_bind(vma, entries, num_entries, rebind,
bind_pt_update.locked ? : NULL);
--
2.25.1
[PATCH 0/5] Enable ccs compressed framebuffers on Xe2
This patch set touches Xe and i915 drivers. On i915 is checked if running on Xe2 hardware and enable framebuffer ccs decompression unconditionally for tile4 framebuffers. On Xe driver with Xe2 hardware check if ccs compression is in use and behave accordingly; attempt to use ccs with linear and x-tiled framebuffers will result in -EINVAL as display does support decompression only on tile4. v2: Add compressed flag into pat index table and use that. Try to avoid situation where framebuffer can be bound with different pat index after it was pinned. Juha-Pekka Heikkila (5): drm/xe/pat: annotate pat index table with compression information drm/xe: add bind time pat index to xe_bo structure drm/xe: store bind time pat index to xe_bo drm/xe/xe2: Limit ccs framebuffers to tile4 only drm/i915/display: On Xe2 always enable decompression with tile4 .../drm/i915/display/skl_universal_plane.c| 5 drivers/gpu/drm/xe/display/xe_fb_pin.c| 19 +++ drivers/gpu/drm/xe/xe_bo_types.h | 11 + drivers/gpu/drm/xe/xe_pat.c | 9 +++- drivers/gpu/drm/xe/xe_pat.h | 8 +++ drivers/gpu/drm/xe/xe_pt.c| 23 +++ 6 files changed, 70 insertions(+), 5 deletions(-) -- 2.25.1
Re: [PATCH v3 1/2] pm: runtime: Simplify pm_runtime_get_if_active() usage
Hi Alex, On Fri, Jan 26, 2024 at 09:12:02AM -0600, Alex Elder wrote: > On 1/22/24 5:41 AM, Sakari Ailus wrote: > > There are two ways to opportunistically increment a device's runtime PM > > usage count, calling either pm_runtime_get_if_active() or > > pm_runtime_get_if_in_use(). The former has an argument to tell whether to > > ignore the usage count or not, and the latter simply calls the former with > > ign_usage_count set to false. The other users that want to ignore the > > usage_count will have to explitly set that argument to true which is a bit > > cumbersome. > > > > To make this function more practical to use, remove the ign_usage_count > > argument from the function. The main implementation is renamed as > > pm_runtime_get_conditional(). > > > > Signed-off-by: Sakari Ailus > > Reviewed-by: Alex Elder # drivers/net/ipa/ipa_smp2p.c > > I actually intended my "Reviewed-by" to cover the entire patch. I > checked every caller and they all looked good to me. Thanks, I'll drop the file name. AFAIR it was just below that file, so I added it, but I could be wrong, too. v5 will also squash the 2nd patch of v4 into this one https://lore.kernel.org/linux-pm/ZbBAWROxRKE8Y8VU@kekkonen.localdomain/T/#m76d34e679e12d8536a20eb29af6e826e2a85a24b>, I hope that's fine. -- Kind regards, Sakari Ailus
Re: [PATCH v3 1/2] pm: runtime: Simplify pm_runtime_get_if_active() usage
On 1/22/24 5:41 AM, Sakari Ailus wrote:
There are two ways to opportunistically increment a device's runtime PM
usage count, calling either pm_runtime_get_if_active() or
pm_runtime_get_if_in_use(). The former has an argument to tell whether to
ignore the usage count or not, and the latter simply calls the former with
ign_usage_count set to false. The other users that want to ignore the
usage_count will have to explitly set that argument to true which is a bit
cumbersome.
To make this function more practical to use, remove the ign_usage_count
argument from the function. The main implementation is renamed as
pm_runtime_get_conditional().
Signed-off-by: Sakari Ailus
Reviewed-by: Alex Elder # drivers/net/ipa/ipa_smp2p.c
I actually intended my "Reviewed-by" to cover the entire patch. I
checked every caller and they all looked good to me.
-Alex
Reviewed-by: Laurent Pinchart
Acked-by: Takashi Iwai # sound/
Reviewed-by: Jacek Lawrynowicz #
drivers/accel/ivpu/
Acked-by: Rodrigo Vivi # drivers/gpu/drm/i915/
Reviewed-by: Rodrigo Vivi
---
Documentation/power/runtime_pm.rst | 5 ++--
drivers/accel/ivpu/ivpu_pm.c| 2 +-
drivers/base/power/runtime.c| 10 +---
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
drivers/gpu/drm/xe/xe_pm.c | 2 +-
drivers/media/i2c/ccs/ccs-core.c| 2 +-
drivers/media/i2c/ov64a40.c | 2 +-
drivers/media/i2c/thp7312.c | 2 +-
drivers/net/ipa/ipa_smp2p.c | 2 +-
drivers/pci/pci.c | 2 +-
include/linux/pm_runtime.h | 32 +
sound/hda/hdac_device.c | 2 +-
12 files changed, 45 insertions(+), 20 deletions(-)
diff --git a/Documentation/power/runtime_pm.rst
b/Documentation/power/runtime_pm.rst
index 65b86e487afe..da99379071a4 100644
--- a/Documentation/power/runtime_pm.rst
+++ b/Documentation/power/runtime_pm.rst
@@ -396,10 +396,9 @@ drivers/base/power/runtime.c and
include/linux/pm_runtime.h:
nonzero, increment the counter and return 1; otherwise return 0 without
changing the counter
- `int pm_runtime_get_if_active(struct device *dev, bool ign_usage_count);`
+ `int pm_runtime_get_if_active(struct device *dev);`
- return -EINVAL if 'power.disable_depth' is nonzero; otherwise, if the
- runtime PM status is RPM_ACTIVE, and either ign_usage_count is true
- or the device's usage_count is non-zero, increment the counter and
+ runtime PM status is RPM_ACTIVE, increment the counter and
return 1; otherwise return 0 without changing the counter
`void pm_runtime_put_noidle(struct device *dev);`
diff --git a/drivers/accel/ivpu/ivpu_pm.c b/drivers/accel/ivpu/ivpu_pm.c
index 0af8864cb3b5..c6d93c7a1c58 100644
--- a/drivers/accel/ivpu/ivpu_pm.c
+++ b/drivers/accel/ivpu/ivpu_pm.c
@@ -292,7 +292,7 @@ int ivpu_rpm_get_if_active(struct ivpu_device *vdev)
{
int ret;
- ret = pm_runtime_get_if_active(vdev->drm.dev, false);
+ ret = pm_runtime_get_if_in_use(vdev->drm.dev);
drm_WARN_ON(>drm, ret < 0);
return ret;
diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c
index 05793c9fbb84..b4cb3f19b0d8 100644
--- a/drivers/base/power/runtime.c
+++ b/drivers/base/power/runtime.c
@@ -1176,7 +1176,7 @@ int __pm_runtime_resume(struct device *dev, int rpmflags)
EXPORT_SYMBOL_GPL(__pm_runtime_resume);
/**
- * pm_runtime_get_if_active - Conditionally bump up device usage counter.
+ * pm_runtime_get_conditional - Conditionally bump up device usage counter.
* @dev: Device to handle.
* @ign_usage_count: Whether or not to look at the current usage counter
value.
*
@@ -1196,8 +1196,12 @@ EXPORT_SYMBOL_GPL(__pm_runtime_resume);
*
* The caller is responsible for decrementing the runtime PM usage counter of
* @dev after this function has returned a positive value for it.
+ *
+ * This function is not primarily intended for use in drivers, most of which
are
+ * better served by either pm_runtime_get_if_active() or
+ * pm_runtime_get_if_in_use() instead.
*/
-int pm_runtime_get_if_active(struct device *dev, bool ign_usage_count)
+int pm_runtime_get_conditional(struct device *dev, bool ign_usage_count)
{
unsigned long flags;
int retval;
@@ -1218,7 +1222,7 @@ int pm_runtime_get_if_active(struct device *dev, bool
ign_usage_count)
return retval;
}
-EXPORT_SYMBOL_GPL(pm_runtime_get_if_active);
+EXPORT_SYMBOL_GPL(pm_runtime_get_conditional);
/**
* __pm_runtime_set_status - Set runtime PM status of a device.
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 860b51b56a92..b5f8abd2a22b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -246,7 +246,7 @@ static intel_wakeref_t
__intel_runtime_pm_get_if_active(struct intel_runtime_pm
✓ Fi.CI.BAT: success for series starting with [1/2] drm/ttm: improve idle/busy handling v4
== Series Details ==
Series: series starting with [1/2] drm/ttm: improve idle/busy handling v4
URL : https://patchwork.freedesktop.org/series/129197/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14181 -> Patchwork_129197v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/index.html
Participating hosts (37 -> 35)
--
Missing(2): bat-kbl-2 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_129197v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlm-1: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/bat-adlm-1/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_pm_rps@basic-api:
- bat-adlm-1: NOTRUN -> [SKIP][2] ([i915#6621])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/bat-adlm-1/igt@i915_pm_...@basic-api.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlm-1: NOTRUN -> [SKIP][3] ([fdo#109285])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/bat-adlm-1/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- bat-adlm-1: NOTRUN -> [SKIP][4] ([i915#1849] / [i915#4342])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/bat-adlm-1/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][5] ([i915#9875] / [i915#9900]) +6
other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/bat-adlm-1/igt@kms_pipe_crc_ba...@hang-read-crc.html
* igt@kms_pm_backlight@basic-brightness:
- bat-adlm-1: NOTRUN -> [SKIP][6] ([i915#5354])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/bat-adlm-1/igt@kms_pm_backli...@basic-brightness.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adlm-1: NOTRUN -> [SKIP][7] ([i915#3555])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/bat-adlm-1/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-adlm-1: NOTRUN -> [SKIP][8] ([i915#3708] / [i915#9900])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/bat-adlm-1/igt@prime_v...@basic-fence-flip.html
* igt@prime_vgem@basic-write:
- bat-adlm-1: NOTRUN -> [SKIP][9] ([i915#3708]) +2 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/bat-adlm-1/igt@prime_v...@basic-write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9875]: https://gitlab.freedesktop.org/drm/intel/issues/9875
[i915#9900]: https://gitlab.freedesktop.org/drm/intel/issues/9900
Build changes
-
* Linux: CI_DRM_14181 -> Patchwork_129197v1
CI-20190529: 20190529
CI_DRM_14181: 6aa961ab469df8db84bee01a55606a91a6ae5d67 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7693: f5f774ada63296536195fd381d8720f5ac7e2208 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_129197v1: 6aa961ab469df8db84bee01a55606a91a6ae5d67 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
21de0716d104 drm/amdgpu: use GTT only as fallback for VRAM|GTT
a4a9e7bef55e drm/ttm: improve idle/busy handling v4
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129197v1/index.html
[PULL] drm-intel-fixes
Hi Dave & Sima, Just one Cc stable patch (the rest was already in drm-intel-next-fixes). Tried to wait for CI results, but none yet. Best Regards, Joonas *** drm-intel-fixes-2024-01-26: - PSR fix for HSW The following changes since commit 6613476e225e090cc9aad49be7fa504e290dd33d: Linux 6.8-rc1 (2024-01-21 14:11:32 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2024-01-26 for you to fetch changes up to f9f031dd21a7ce13a13862fa5281d32e1029c70f: drm/i915/psr: Only allow PSR in LPSP mode on HSW non-ULT (2024-01-25 10:44:13 +0200) - PSR fix for HSW Ville Syrjälä (1): drm/i915/psr: Only allow PSR in LPSP mode on HSW non-ULT drivers/gpu/drm/i915/display/intel_psr.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-)
✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/ttm: improve idle/busy handling v4
== Series Details == Series: series starting with [1/2] drm/ttm: improve idle/busy handling v4 URL : https://patchwork.freedesktop.org/series/129197/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/ttm: improve idle/busy handling v4
== Series Details == Series: series starting with [1/2] drm/ttm: improve idle/busy handling v4 URL : https://patchwork.freedesktop.org/series/129197/ State : warning == Summary == Error: dim checkpatch failed 72c0fca2f3d6 drm/ttm: improve idle/busy handling v4 -:26: WARNING:BAD_SIGN_OFF: Unexpected content after email: 'Zack Rusin v3', should be: 'Zack Rusin (v3)' #26: Reviewed-by: Zack Rusin v3 -:387: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 2 warnings, 0 checks, 341 lines checked a894c42d4f6e drm/amdgpu: use GTT only as fallback for VRAM|GTT -:33: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" ' != 'Signed-off-by: Christian König ' total: 0 errors, 1 warnings, 0 checks, 12 lines checked
[PATCH 2/2] drm/amdgpu: use GTT only as fallback for VRAM|GTT
Try to fill up VRAM as well by setting the busy flag on GTT allocations. This fixes the issue that when VRAM was evacuated for suspend it's never filled up again unless the application is restarted. Signed-off-by: Christian König Reviewed-by: Zack Rusin --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index b671b0665492..0eac179a387c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -173,6 +173,12 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? AMDGPU_PL_PREEMPT : TTM_PL_TT; places[c].flags = 0; + /* +* When GTT is just an alternative to VRAM make sure that we +* only use it as fallback and still try to fill up VRAM first. +*/ + if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) + places[c].flags |= TTM_PL_FLAG_FALLBACK; c++; } -- 2.34.1
[PATCH 1/2] drm/ttm: improve idle/busy handling v4
Previously we would never try to move a BO into the preferred placements
when it ever landed in a busy placement since those were considered
compatible.
Rework the whole handling and finally unify the idle and busy handling.
ttm_bo_validate() is now responsible to try idle placement first and then
use the busy placement if that didn't worked.
Drawback is that we now always try the idle placement first for each
validation which might cause some additional CPU overhead on overcommit.
v2: fix kerneldoc warning and coding style
v3: take care of XE as well
v4: keep the ttm_bo_mem_space functionality as it is for now, only add
new handling for ttm_bo_validate as suggested by Thomas
Signed-off-by: Christian König
Reviewed-by: Zack Rusin v3
---
drivers/gpu/drm/ttm/ttm_bo.c | 231 +
drivers/gpu/drm/ttm/ttm_resource.c | 16 +-
include/drm/ttm/ttm_resource.h | 3 +-
3 files changed, 121 insertions(+), 129 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index ba3f09e2d7e6..b12f435542a9 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -724,64 +724,36 @@ static int ttm_bo_add_move_fence(struct ttm_buffer_object
*bo,
return ret;
}
-/*
- * Repeatedly evict memory from the LRU for @mem_type until we create enough
- * space, or we've evicted everything and there isn't enough space.
- */
-static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo,
- const struct ttm_place *place,
- struct ttm_resource **mem,
- struct ttm_operation_ctx *ctx)
-{
- struct ttm_device *bdev = bo->bdev;
- struct ttm_resource_manager *man;
- struct ww_acquire_ctx *ticket;
- int ret;
-
- man = ttm_manager_type(bdev, place->mem_type);
- ticket = dma_resv_locking_ctx(bo->base.resv);
- do {
- ret = ttm_resource_alloc(bo, place, mem);
- if (likely(!ret))
- break;
- if (unlikely(ret != -ENOSPC))
- return ret;
- ret = ttm_mem_evict_first(bdev, man, place, ctx,
- ticket);
- if (unlikely(ret != 0))
- return ret;
- } while (1);
-
- return ttm_bo_add_move_fence(bo, man, *mem, ctx->no_wait_gpu);
-}
-
/**
- * ttm_bo_mem_space
+ * ttm_bo_alloc_resource - Allocate backing store for a BO
*
- * @bo: Pointer to a struct ttm_buffer_object. the data of which
- * we want to allocate space for.
- * @placement: Proposed new placement for the buffer object.
- * @mem: A struct ttm_resource.
+ * @bo: Pointer to a struct ttm_buffer_object of which we want a resource for
+ * @placement: Proposed new placement for the buffer object
* @ctx: if and how to sleep, lock buffers and alloc memory
+ * @force_space: If we should evict buffers to force space
+ * @res: The resulting struct ttm_resource.
*
- * Allocate memory space for the buffer object pointed to by @bo, using
- * the placement flags in @placement, potentially evicting other idle buffer
objects.
- * This function may sleep while waiting for space to become available.
+ * Allocates a resource for the buffer object pointed to by @bo, using the
+ * placement flags in @placement, potentially evicting other buffer objects
when
+ * @force_space is true.
+ * This function may sleep while waiting for resources to become available.
* Returns:
- * -EBUSY: No space available (only if no_wait == 1).
+ * -EBUSY: No space available (only if no_wait == true).
* -ENOSPC: Could not allocate space for the buffer object, either due to
* fragmentation or concurrent allocators.
* -ERESTARTSYS: An interruptible sleep was interrupted by a signal.
*/
-int ttm_bo_mem_space(struct ttm_buffer_object *bo,
- struct ttm_placement *placement,
- struct ttm_resource **mem,
- struct ttm_operation_ctx *ctx)
+static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo,
+struct ttm_placement *placement,
+struct ttm_operation_ctx *ctx,
+bool force_space,
+struct ttm_resource **res)
{
struct ttm_device *bdev = bo->bdev;
- bool type_found = false;
+ struct ww_acquire_ctx *ticket;
int i, ret;
+ ticket = dma_resv_locking_ctx(bo->base.resv);
ret = dma_resv_reserve_fences(bo->base.resv, 1);
if (unlikely(ret))
return ret;
@@ -790,98 +762,73 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
const struct ttm_place *place = >placement[i];
struct ttm_resource_manager *man;
- if (place->flags & TTM_PL_FLAG_FALLBACK)
- continue;
-
man =
Rework TTMs busy handling
Hi guys, so pushed the first few patches from this series. I hope that I correctly managed to resolve the silent Xe merge conflict in drm-tip, but would be nice if somebody could double check. Then for the two remaining patches I've implemented most of what Thomas suggest, e.g. the existing functionality sticks around for eviction and hobs, but ttm_bo_validate will now try to always move things into the non-fallback placements on validation first. What I haven't done yet is to split up the preferred placement since I couldn't immediately see an use case for this, but it's really something we might do in the future as well. Please review and comment, Christian.
Re: [PATCH 01/19] drm/dp: Add drm_dp_max_dprx_data_rate()
On Fri, Jan 26, 2024 at 01:36:02PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 23, 2024 at 12:28:32PM +0200, Imre Deak wrote:
> > Copy intel_dp_max_data_rate() to DRM core. It will be needed by a
> > follow-up DP tunnel patch, checking the maximum rate the DPRX (sink)
> > supports. Accordingly use the drm_dp_max_dprx_data_rate() name for
> > clarity. This patchset will also switch calling the new DRM function
> > in i915 instead of intel_dp_max_data_rate().
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/display/drm_dp_helper.c | 58 +
> > include/drm/display/drm_dp_helper.h | 2 +
> > 2 files changed, 60 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
> > b/drivers/gpu/drm/display/drm_dp_helper.c
> > index b1ca3a1100dab..24911243d4d3a 100644
> > --- a/drivers/gpu/drm/display/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> > @@ -4058,3 +4058,61 @@ int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> > return 80;
> > }
> > EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> > +
> > +/*
> > + * Given a link rate and lanes, get the data bandwidth.
> > + *
> > + * Data bandwidth is the actual payload rate, which depends on the data
> > + * bandwidth efficiency and the link rate.
> > + *
> > + * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth
> > efficiency
> > + * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8)
> > =
> > + * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just
> > by
> > + * coincidence, the port clock in kHz matches the data bandwidth in kBps,
> > and
> > + * they equal the link bit rate in Gbps multiplied by 10. (Note that
> > this no
> > + * longer holds for data bandwidth as soon as FEC or MST is taken into
> > account!)
> > + *
> > + * For 128b/132b channel encoding, the data bandwidth efficiency is
> > 96.71%. For
> > + * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
> > + * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value
> > 100
> > + * does not match the symbol clock, the port clock (not even if you think
> > in
> > + * terms of a byte clock), nor the data bandwidth. It only matches the
> > link bit
> > + * rate in units of 1 bps.
> > + *
> > + * Note that protocol layers above the DPRX link level considered here can
> > + * further limit the maximum data rate. Such layers are the MST topology
> > (with
> > + * limits on the link between the source and first branch device as well
> > as on
> > + * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
> > + * which in turn can encapsulate an MST link with its own limit - with each
> > + * SST or MST encapsulated tunnel sharing the BW of a tunnel group.
> > + *
> > + * TODO: Add support for querying the max data rate with the above limits
> > as
> > + * well.
> > + *
> > + * Returns the maximum data rate in kBps units.
> > + */
> > +int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)
> > +{
> > + int ch_coding_efficiency =
> > +
> > drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
> > + int max_link_rate_kbps = max_link_rate * 10;
>
> That x10 value seems rather pointless.
I suppose the point was to make the units clearer, but it could be
clarified instead in max_link_rates' documentation, which is missing
atm.
> > +
> > + /*
> > +* UHBR rates always use 128b/132b channel encoding, and have
> > +* 97.71% data bandwidth efficiency. Consider max_link_rate the
> > +* link bit rate in units of 1 bps.
> > +*/
> > + /*
> > +* Lower than UHBR rates always use 8b/10b channel encoding, and have
> > +* 80% data bandwidth efficiency for SST non-FEC. However, this turns
> > +* out to be a nop by coincidence:
> > +*
> > +* int max_link_rate_kbps = max_link_rate * 10;
> > +* max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8,
> > 10);
> > +* max_link_rate = max_link_rate_kbps / 8;
> > +*/
>
> Not sure why we are repeating the nuts and bolts detils in the
> comments so much? Doesn't drm_dp_bw_channel_coding_efficiency()
> explain all this already?
I simply copied the function, but yes in this context there is
duplication, thanks for reading through all that. Will consolidate both
the above and the bigger comment before the function with the existing
docs here.
>
> > + return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes,
> > + ch_coding_efficiency),
> > + 100 * 8);
> > +}
> > +EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);
> > diff --git a/include/drm/display/drm_dp_helper.h
> > b/include/drm/display/drm_dp_helper.h
> > index 863b2e7add29e..454ae7517419a 100644
> > --- a/include/drm/display/drm_dp_helper.h
> > +++ b/include/drm/display/drm_dp_helper.h
> > @@ -813,4 +813,6
✗ Fi.CI.BAT: failure for drm/i915: update eDP MSO pipe mask for newer platforms
== Series Details ==
Series: drm/i915: update eDP MSO pipe mask for newer platforms
URL : https://patchwork.freedesktop.org/series/129191/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14181 -> Patchwork_129191v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_129191v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_129191v1, please notify your bug team
(i915-ci-in...@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/index.html
Participating hosts (37 -> 18)
--
ERROR: It appears as if the changes made in Patchwork_129191v1 prevented too
many machines from booting.
Missing(19): fi-rkl-11600 fi-apl-guc bat-adlp-6 fi-snb-2520m fi-blb-e6850
bat-rpls-2 fi-skl-6600u fi-elk-e7500 bat-jsl-3 fi-bsw-nick fi-kbl-7567u
bat-adlp-9 fi-skl-guc bat-mtlp-6 fi-tgl-1115g4 fi-cfl-guc fi-kbl-x1275
fi-cfl-8109u bat-dg2-14
Known issues
Here are the changes found in Patchwork_129191v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlm-1: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/bat-adlm-1/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_pm_rps@basic-api:
- bat-adlm-1: NOTRUN -> [SKIP][2] ([i915#6621])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/bat-adlm-1/igt@i915_pm_...@basic-api.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlm-1: NOTRUN -> [SKIP][3] ([fdo#109285])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/bat-adlm-1/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- bat-adlm-1: NOTRUN -> [SKIP][4] ([i915#1849] / [i915#4342])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/bat-adlm-1/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][5] ([i915#9875] / [i915#9900]) +6
other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/bat-adlm-1/igt@kms_pipe_crc_ba...@hang-read-crc.html
* igt@kms_pm_backlight@basic-brightness:
- bat-adlm-1: NOTRUN -> [SKIP][6] ([i915#5354])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/bat-adlm-1/igt@kms_pm_backli...@basic-brightness.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adlm-1: NOTRUN -> [SKIP][7] ([i915#3555])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/bat-adlm-1/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-adlm-1: NOTRUN -> [SKIP][8] ([i915#3708] / [i915#9900])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/bat-adlm-1/igt@prime_v...@basic-fence-flip.html
* igt@prime_vgem@basic-write:
- bat-adlm-1: NOTRUN -> [SKIP][9] ([i915#3708]) +2 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129191v1/bat-adlm-1/igt@prime_v...@basic-write.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9875]: https://gitlab.freedesktop.org/drm/intel/issues/9875
[i915#9900]: https://gitlab.freedesktop.org/drm/intel/issues/9900
Build changes
-
* Linux: CI_DRM_14181 -> Patchwork_129191v1
CI-20190529: 20190529
CI_DRM_14181: 6aa961ab469df8db84bee01a55606a91a6ae5d67 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7693: f5f774ada63296536195fd381d8720f5ac7e2208 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_129191v1: 6aa961ab469df8db84bee01a55606a91a6ae5d67 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
8c8742f3f28c drm/i915: update eDP MSO pipe mask for newer platforms
== Logs ==
For more details see:
[PULL] drm-misc-fixes
Hi Dave, Sima, Here's this week drm-misc-fixes PR. Maxime drm-misc-fixes-2024-01-26: Plenty of ivpu fixes to improve the general stability and debugging, a suspend fix for the anx7625 bridge, a revert to fix an initialization order bug between i915 and simpledrm and a documentation warning fix for dp_mst. The following changes since commit 6613476e225e090cc9aad49be7fa504e290dd33d: Linux 6.8-rc1 (2024-01-21 14:11:32 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2024-01-26 for you to fetch changes up to 27d19268cf394f2c78db732be0cb31852eeadb0a: accel/ivpu: Improve recovery and reset support (2024-01-25 10:17:37 +0100) Plenty of ivpu fixes to improve the general stability and debugging, a suspend fix for the anx7625 bridge, a revert to fix an initialization order bug between i915 and simpledrm and a documentation warning fix for dp_mst. Arnd Bergmann (1): drm/panel/raydium-rm692e5: select CONFIG_DRM_DISPLAY_DP_HELPER Artur Weber (1): drm/panel: samsung-s6d7aa0: drop DRM_BUS_FLAG_DE_HIGH for lsl080al02 Bagas Sanjaya (1): drm/dp_mst: Separate @failing_port list in drm_dp_mst_atomic_check_mgr() comment Douglas Anderson (2): drm/bridge: parade-ps8640: Wait for HPD when doing an AUX transfer drm/bridge: parade-ps8640: Make sure we drop the AUX mutex in the error case Hsin-Yi Wang (1): drm/bridge: anx7625: Ensure bridge is suspended in disable() Jacek Lawrynowicz (8): accel/ivpu: Fix for missing lock around drm_gem_shmem_vmap() accel/ivpu: Free buffer sgt on unbind accel/ivpu: Disable buffer sharing among VPU contexts accel/ivpu: Improve buffer object debug logs accel/ivpu: Disable PLL after VPU IP reset during FLR accel/ivpu: Fix dev open/close races with unbind accel/ivpu: Improve stability of ivpu_submit_ioctl() accel/ivpu: Improve recovery and reset support Markus Niebel (1): drm: panel-simple: add missing bus flags for Tianma tm070jvhg[30/33] Maxime Ripard (1): Merge v6.8-rc1 into drm-misc-fixes Michał Winiarski (1): drm/tests: mm: Call drm_mm_print in drm_test_mm_debug Pin-yen Lin (1): drm/bridge: parade-ps8640: Ensure bridge is suspended in .post_disable() Thomas Zimmermann (1): Revert "drivers/firmware: Move sysfb_init() from device_initcall to subsys_initcall_sync" Tomi Valkeinen (2): drm/bridge: sii902x: Fix probing race issue drm/bridge: sii902x: Fix audio codec unregistration Wachowski, Karol (5): accel/ivpu: Dump MMU events in case of VPU boot timeout accel/ivpu: Call diagnose failure in ivpu_mmu_cmdq_sync() accel/ivpu: Add debug prints for MMU map/unmap operations accel/ivpu: Add diagnostic messages when VPU fails to boot or suspend accel/ivpu: Deprecate DRM_IVPU_PARAM_CONTEXT_PRIORITY param Yangyu Chen (1): drm/ttm: allocate dummy_read_page without DMA32 on fail drivers/accel/ivpu/ivpu_debugfs.c | 20 +++- drivers/accel/ivpu/ivpu_drv.c | 124 +++- drivers/accel/ivpu/ivpu_drv.h | 5 +- drivers/accel/ivpu/ivpu_gem.c | 142 +-- drivers/accel/ivpu/ivpu_gem.h | 3 +- drivers/accel/ivpu/ivpu_hw_37xx.c | 14 +-- drivers/accel/ivpu/ivpu_hw_40xx.c | 29 - drivers/accel/ivpu/ivpu_ipc.c | 6 +- drivers/accel/ivpu/ivpu_job.c | 160 -- drivers/accel/ivpu/ivpu_job.h | 3 +- drivers/accel/ivpu/ivpu_mmu.c | 22 ++-- drivers/accel/ivpu/ivpu_mmu.h | 1 + drivers/accel/ivpu/ivpu_mmu_context.c | 9 ++ drivers/accel/ivpu/ivpu_pm.c | 52 ++--- drivers/accel/ivpu/ivpu_pm.h | 6 +- drivers/firmware/sysfb.c | 2 +- drivers/gpu/drm/bridge/analogix/anx7625.c | 7 +- drivers/gpu/drm/bridge/analogix/anx7625.h | 2 + drivers/gpu/drm/bridge/parade-ps8640.c| 23 drivers/gpu/drm/bridge/sii902x.c | 48 +--- drivers/gpu/drm/display/drm_dp_mst_topology.c | 2 + drivers/gpu/drm/panel/Kconfig | 2 + drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c | 2 +- drivers/gpu/drm/panel/panel-simple.c | 2 + drivers/gpu/drm/tests/drm_mm_test.c | 5 +- drivers/gpu/drm/ttm/ttm_device.c | 12 +- include/uapi/drm/ivpu_accel.h | 25 +++- 27 files changed, 413 insertions(+), 315 deletions(-) signature.asc Description: PGP signature
✗ Fi.CI.CHECKPATCH: warning for drm/i915: update eDP MSO pipe mask for newer platforms
== Series Details ==
Series: drm/i915: update eDP MSO pipe mask for newer platforms
URL : https://patchwork.freedesktop.org/series/129191/
State : warning
== Summary ==
Error: dim checkpatch failed
de4c77b139ce drm/i915: update eDP MSO pipe mask for newer platforms
-:34: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#34: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:2345:
{
+
total: 0 errors, 0 warnings, 1 checks, 23 lines checked
Re: [PATCH 01/19] drm/dp: Add drm_dp_max_dprx_data_rate()
On Tue, Jan 23, 2024 at 12:28:32PM +0200, Imre Deak wrote:
> Copy intel_dp_max_data_rate() to DRM core. It will be needed by a
> follow-up DP tunnel patch, checking the maximum rate the DPRX (sink)
> supports. Accordingly use the drm_dp_max_dprx_data_rate() name for
> clarity. This patchset will also switch calling the new DRM function
> in i915 instead of intel_dp_max_data_rate().
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 58 +
> include/drm/display/drm_dp_helper.h | 2 +
> 2 files changed, 60 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
> b/drivers/gpu/drm/display/drm_dp_helper.c
> index b1ca3a1100dab..24911243d4d3a 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -4058,3 +4058,61 @@ int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
> return 80;
> }
> EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
> +
> +/*
> + * Given a link rate and lanes, get the data bandwidth.
> + *
> + * Data bandwidth is the actual payload rate, which depends on the data
> + * bandwidth efficiency and the link rate.
> + *
> + * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth
> efficiency
> + * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
> + * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
> + * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
> + * they equal the link bit rate in Gbps multiplied by 10. (Note that
> this no
> + * longer holds for data bandwidth as soon as FEC or MST is taken into
> account!)
> + *
> + * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%.
> For
> + * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
> + * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value
> 100
> + * does not match the symbol clock, the port clock (not even if you think in
> + * terms of a byte clock), nor the data bandwidth. It only matches the link
> bit
> + * rate in units of 1 bps.
> + *
> + * Note that protocol layers above the DPRX link level considered here can
> + * further limit the maximum data rate. Such layers are the MST topology
> (with
> + * limits on the link between the source and first branch device as well as
> on
> + * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
> + * which in turn can encapsulate an MST link with its own limit - with each
> + * SST or MST encapsulated tunnel sharing the BW of a tunnel group.
> + *
> + * TODO: Add support for querying the max data rate with the above limits as
> + * well.
> + *
> + * Returns the maximum data rate in kBps units.
> + */
> +int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)
> +{
> + int ch_coding_efficiency =
> +
> drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
> + int max_link_rate_kbps = max_link_rate * 10;
That x10 value seems rather pointless.
> +
> + /*
> + * UHBR rates always use 128b/132b channel encoding, and have
> + * 97.71% data bandwidth efficiency. Consider max_link_rate the
> + * link bit rate in units of 1 bps.
> + */
> + /*
> + * Lower than UHBR rates always use 8b/10b channel encoding, and have
> + * 80% data bandwidth efficiency for SST non-FEC. However, this turns
> + * out to be a nop by coincidence:
> + *
> + * int max_link_rate_kbps = max_link_rate * 10;
> + * max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8,
> 10);
> + * max_link_rate = max_link_rate_kbps / 8;
> + */
Not sure why we are repeating the nuts and bolts detils in the
comments so much? Doesn't drm_dp_bw_channel_coding_efficiency()
explain all this already?
> + return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes,
> + ch_coding_efficiency),
> + 100 * 8);
> +}
> +EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);
> diff --git a/include/drm/display/drm_dp_helper.h
> b/include/drm/display/drm_dp_helper.h
> index 863b2e7add29e..454ae7517419a 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -813,4 +813,6 @@ int drm_dp_bw_overhead(int lane_count, int hactive,
> int bpp_x16, unsigned long flags);
> int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
>
> +int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
> +
> #endif /* _DRM_DP_HELPER_H_ */
> --
> 2.39.2
--
Ville Syrjälä
Intel
Re: [PATCH 2/2] drm/i915/fbc: Move DPFC_CHICKEN programming into intel_fbc_program_workarounds()
On Tue, Jan 23, 2024 at 10:42:46AM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-01-23 06:00:51-03:00)
> >From: Ville Syrjälä
> >
> >Move all DPFC_CHICKEN programming into intel_fbc_program_workarounds().
> >We already have one thing programmed there, whereas the rest is strewn
> >about in intel_display_wa_apply() and init_clock_gating(). Since we have
> >a single place doing all the programming (and it's serialized by the
> >crtc commits) there should be no danger of rmw races.
> >
> >Other FBC related workarounds also exist, but those require fiddling
> >with other registers that may also get programmed from other places,
> >so we'll need to think harder what to do with those.
> >
> >Signed-off-by: Ville Syrjälä
> >---
> > .../gpu/drm/i915/display/intel_display_wa.c | 8 -
> > drivers/gpu/drm/i915/display/intel_fbc.c | 32 --
> > drivers/gpu/drm/i915/intel_clock_gating.c | 33 ---
> > 3 files changed, 29 insertions(+), 44 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> >b/drivers/gpu/drm/i915/display/intel_display_wa.c
> >index ac136fd992ba..e5a8022db664 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> >+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> >@@ -10,20 +10,12 @@
> >
> > static void gen11_display_wa_apply(struct drm_i915_private *i915)
> > {
> >-/* Wa_1409120013 */
> >-intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> >- DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> >-
> > /* Wa_14010594013 */
> > intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
> > }
> >
> > static void xe_d_display_wa_apply(struct drm_i915_private *i915)
> > {
> >-/* Wa_1409120013 */
> >-intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> >- DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> >-
> > /* Wa_14013723622 */
> > intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
> > }
> >diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> >b/drivers/gpu/drm/i915/display/intel_fbc.c
> >index f17a1afb4929..1a2d4d91a85f 100644
> >--- a/drivers/gpu/drm/i915/display/intel_fbc.c
> >+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> >@@ -826,10 +826,36 @@ static void intel_fbc_program_cfb(struct intel_fbc
> >*fbc)
> >
> > static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
> > {
> >+struct drm_i915_private *i915 = fbc->i915;
> >+
> >+if (IS_SKYLAKE(i915) || IS_BROXTON(i915)) {
> >+/*
> >+ * WaFbcHighMemBwCorruptionAvoidance:skl,bxt
> >+ * Display WA #0883: skl,bxt
> >+ */
> >+intel_de_rmw(i915, ILK_DPFC_CHICKEN(fbc->id),
> >+ 0, DPFC_DISABLE_DUMMY0);
> >+}
> >+
> >+if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) ||
> >+IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
> >+/*
> >+ * WaFbcNukeOnHostModify:skl,kbl,cfl
> >+ * Display WA #0873: skl,kbl,cfl
> >+ */
> >+intel_de_rmw(i915, ILK_DPFC_CHICKEN(fbc->id),
> >+ 0, DPFC_NUKE_ON_ANY_MODIFICATION);
> >+}
> >+
> >+/* Wa_1409120013:icl,jsl,tgl,dg1 */
> >+if (IS_DISPLAY_VER(i915, 11, 12))
> >+intel_de_rmw(i915, ILK_DPFC_CHICKEN(fbc->id),
> >+ 0, DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> >+
> > /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */
> >-if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915))
> >-intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0,
> >- DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
> >+if (DISPLAY_VER(i915) >= 11 && !IS_DG2(i915))
> >+intel_de_rmw(i915, ILK_DPFC_CHICKEN(fbc->id),
> >+ 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
>
> Since we are writing to the same register, maybe we could have a single read,
> modify and write instead of multiple rmw calls?
Perhaps. Although we do at most do two rmws here on any given system.
So it's not particularly expensive to keep it simple like this.
I was also pondering about splitting this into vfuncs, which would
need multiple rmws anyway. But the whole thing is a bit of a mess
in terms of which platforms need what, so not sure it's make it
look any nicer.
>
> --
> Gustavo Sousa
>
> > }
> >
> > static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> >diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c
> >b/drivers/gpu/drm/i915/intel_clock_gating.c
> >index 9c21ce69bd98..39f23288e8a8 100644
> >--- a/drivers/gpu/drm/i915/intel_clock_gating.c
> >+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> >@@ -105,12 +105,6 @@ static void bxt_init_clock_gating(struct
> >drm_i915_private *i915)
> > * Display WA #0562: bxt
> > */
> >
Re: [PATCH v2] drm/i915: update eDP MSO pipe mask for newer platforms
On Fri, Jan 26, 2024 at 12:03:09PM +0200, Luca Coelho wrote:
> Starting from display version 14, pipes A and B are supported in eDP
> MSO. After display version 20 there are no restrictions.
>
> Update the function that returns the pipe mask for eDP MSO
> accordingly.
>
> Bspec: 68923, 55473
> Cc: Jani Nikula
> Cc: James Ausmus
> Reviewed-by: Gustavo Sousa
> Signed-off-by: Luca Coelho
> ---
>
> In v2:
>* allow pipes A and B from ver 14 to 20 [Gustavo]
>
>
> drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 922194b957be..29a616a8e72d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2336,13 +2336,20 @@ static void intel_ddi_power_up_lanes(struct
> intel_encoder *encoder,
> }
> }
>
> -/* Splitter enable for eDP MSO is limited to certain pipes. */
> +/*
> + * Splitter enable for eDP MSO is limited to certain pipes on certain
> + * platforms.
> + */
> static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
> {
> - if (IS_ALDERLAKE_P(i915))
> +
> + if (IS_ALDERLAKE_P(i915) ||
> + IS_DISPLAY_IP_RANGE(i915, IP_VER(14, 0), IP_VER(20, 0)))
> return BIT(PIPE_A) | BIT(PIPE_B);
> - else
> + else if (DISPLAY_VER(i915) < 14)
> return BIT(PIPE_A);
> +
> + return ~0;
That looks rather confusing. I'd make it something like:
if (VER >= whatever_is_the_new_version_that_i_can't_easily_find_from_bspec)
return ~0;
else if (VER >= 14 || ADL)
return A | B;
else
return A;
> }
>
> static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
> --
> 2.39.2
--
Ville Syrjälä
Intel
[PATCH v2] drm/i915: update eDP MSO pipe mask for newer platforms
Starting from display version 14, pipes A and B are supported in eDP
MSO. After display version 20 there are no restrictions.
Update the function that returns the pipe mask for eDP MSO
accordingly.
Bspec: 68923, 55473
Cc: Jani Nikula
Cc: James Ausmus
Reviewed-by: Gustavo Sousa
Signed-off-by: Luca Coelho
---
In v2:
* allow pipes A and B from ver 14 to 20 [Gustavo]
drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 922194b957be..29a616a8e72d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2336,13 +2336,20 @@ static void intel_ddi_power_up_lanes(struct
intel_encoder *encoder,
}
}
-/* Splitter enable for eDP MSO is limited to certain pipes. */
+/*
+ * Splitter enable for eDP MSO is limited to certain pipes on certain
+ * platforms.
+ */
static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
{
- if (IS_ALDERLAKE_P(i915))
+
+ if (IS_ALDERLAKE_P(i915) ||
+ IS_DISPLAY_IP_RANGE(i915, IP_VER(14, 0), IP_VER(20, 0)))
return BIT(PIPE_A) | BIT(PIPE_B);
- else
+ else if (DISPLAY_VER(i915) < 14)
return BIT(PIPE_A);
+
+ return ~0;
}
static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
--
2.39.2
✗ Fi.CI.BAT: failure for drm/i915/gvt: Fix uninitialized variable in handle_mmio()
== Series Details == Series: drm/i915/gvt: Fix uninitialized variable in handle_mmio() URL : https://patchwork.freedesktop.org/series/129190/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14180 -> Patchwork_129190v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_129190v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_129190v1, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129190v1/index.html Participating hosts (36 -> 33) -- Missing(3): fi-skl-guc fi-snb-2520m fi-pnv-d510 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_129190v1: ### IGT changes ### Possible regressions * igt@kms_flip@basic-flip-vs-dpms@d-edp1: - bat-adlp-6: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14180/bat-adlp-6/igt@kms_flip@basic-flip-vs-d...@d-edp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129190v1/bat-adlp-6/igt@kms_flip@basic-flip-vs-d...@d-edp1.html Known issues Here are the changes found in Patchwork_129190v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_pm: - bat-rpls-2: [PASS][3] -> [DMESG-FAIL][4] ([i915#10010]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14180/bat-rpls-2/igt@i915_selftest@live@gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129190v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#9197]) +1 other test skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129190v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html [i915#10010]: https://gitlab.freedesktop.org/drm/intel/issues/10010 [i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197 Build changes - * Linux: CI_DRM_14180 -> Patchwork_129190v1 CI-20190529: 20190529 CI_DRM_14180: 246d92693aa04ab89430fc3b028ed9b0b7e8a0c8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7692: 5d9c29c620701497323bf3721146da57efa50952 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_129190v1: 246d92693aa04ab89430fc3b028ed9b0b7e8a0c8 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits c0fb87b248d9 drm/i915/gvt: Fix uninitialized variable in handle_mmio() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129190v1/index.html
Re: [PATCH] drm/i915: limit eDP MSO pipe only for display version 20 and below
On Wed, 2024-01-24 at 10:22 -0300, Gustavo Sousa wrote:
> Hi, Luca!
Hi Gustavo!
> Quoting Luca Coelho (2024-01-24 05:52:29-03:00)
> > The pipes that can be used for eDP MSO are limited to pipe A (and
> > sometimes also pipe B) only for display version 20 and below.
> >
> > Modify the function that returns the pipe mask for eDP MSO so that
> > these limitations only apply to version 20 and below, enabling all
> > pipes otherwise.
> >
> > Bspec: 68923
> > Cc: Jani Nikula
> > Cc: James Ausmus
> > Signed-off-by: Luca Coelho
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 922194b957be..5c99ae148213 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2336,13 +2336,18 @@ static void intel_ddi_power_up_lanes(struct
> > intel_encoder *encoder,
> > }
> > }
> >
> > -/* Splitter enable for eDP MSO is limited to certain pipes. */
> > +/*
> > + * Splitter enable for eDP MSO is limited to certain pipes, on certain
> > + * platforms.
> > + */
> > static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
> > {
> > if (IS_ALDERLAKE_P(i915))
>
> Looks like Xe_LPD+ (MTL's display) and Xe2_LPD (LNL's display) both support
> both
> pipes A and B. For Xe_LPD+ we have that info in BSpec 55473 and for Xe2_LPD,
> in
> BSpec 68923. So, I think we could:
>
> a. OR the condition above with IS_DISPLAY_IP_RANGE(i915, IP_VER(14, 0),
> IP_VER(20, 0)), and
> b. And make the "else if" below be about display versions below 14.
Okay, but I guess we have never tested this with MTL and LNL, so can we
be sure we won't break anything?
In any case, we have bspecs for these, so I'll make the change as you
suggested.
> With those additions,
>
> Reviewed-by: Gustavo Sousa
Thanks!
--
Cheers,
Luca.
[PATCH] drm/i915/gvt: Fix uninitialized variable in handle_mmio()
This code prints the wrong variable in the warning message. It should
print "i" instead of "info->offset". On the first iteration "info" is
uninitialized leading to a crash and on subsequent iterations it prints
the previous offset instead of the current one.
Fixes: e0f74ed4634d ("i915/gvt: Separate the MMIO tracking table from GVT-g")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/i915/gvt/handlers.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index 90f6c1ece57d..efcb00472be2 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2849,8 +2849,7 @@ static int handle_mmio(struct intel_gvt_mmio_table_iter
*iter, u32 offset,
for (i = start; i < end; i += 4) {
p = intel_gvt_find_mmio_info(gvt, i);
if (p) {
- WARN(1, "dup mmio definition offset %x\n",
- info->offset);
+ WARN(1, "dup mmio definition offset %x\n", i);
/* We return -EEXIST here to make GVT-g load fail.
* So duplicated MMIO can be found as soon as
--
2.43.0
