✗ Fi.CI.BAT: failure for VBT read cleanup (rev6)
== Series Details == Series: VBT read cleanup (rev6) URL : https://patchwork.freedesktop.org/series/130528/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130528v6 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_130528v6 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_130528v6, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/index.html Participating hosts (41 -> 40) -- Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_130528v6: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_contexts: - bat-arls-2: NOTRUN -> [ABORT][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-2/igt@i915_selftest@live@gt_contexts.html Known issues Here are the changes found in Patchwork_130528v6 that come from known issues: ### CI changes ### Issues hit * boot: - fi-cfl-8109u: [PASS][2] -> [FAIL][3] ([i915#8293]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-cfl-8109u/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/fi-cfl-8109u/boot.html Possible fixes * boot: - bat-arls-3: [FAIL][4] ([i915#10234]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][6] ([i915#9318]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-arls-2: NOTRUN -> [SKIP][7] ([i915#9318]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#10213]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][9] ([i915#10213]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][10] ([i915#4083]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-2/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][12] ([i915#10196] / [i915#4077]) +2 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][13] ([i915#10197] / [i915#10211] / [i915#4079]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-2/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10197] / [i915#10211] / [i915#4079]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10196] / [i915#4077]) +2 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10206] / [i915#4079]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-3/igt@gem_tiled_pread_basic.html - bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10206] / [i915#4079]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-2: NOTRUN -> [SKIP][18] ([i915#10209]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-2/igt@i915_pm_...@basic-api.html - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10209]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v6/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@workarounds: - bat-dg2-14:
✗ Fi.CI.SPARSE: warning for VBT read cleanup (rev6)
== Series Details == Series: VBT read cleanup (rev6) URL : https://patchwork.freedesktop.org/series/130528/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
RE: [RFC 2/3] drm/i915/alpm: Add compute config for lobf
> -Original Message-
> From: Jani Nikula
> Sent: Monday, March 4, 2024 11:03 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Hogander, Jouni ; Murthy, Arun R
> ; Manna, Animesh
> Subject: Re: [RFC 2/3] drm/i915/alpm: Add compute config for lobf
>
> On Mon, 04 Mar 2024, Animesh Manna
> wrote:
> > Link Off Between Active Frames, is a new feature for eDP that allows
> > the panel to go to lower power state after transmission of data. This
> > is a feature on top of ALPM, AS SDP.
> > Add compute config during atomic-check phase.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > .../drm/i915/display/intel_display_types.h| 3 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 45 +++
> > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > 4 files changed, 52 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index d473d8dca90a..4d2161eeb686 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1851,6 +1851,9 @@ struct intel_dp {
> > u8 silence_period_sym_clocks;
> > u8 lfps_half_cycle_num_of_syms;
> > } alpm_parameters;
> > +
> > + /* LOBF flags*/
> > + bool lobf_supported;
> > };
> >
> > enum lspcon_vendor {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8304ef912767..e34b70d88b9a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2979,6 +2979,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> > intel_vrr_compute_config(pipe_config, conn_state);
> > intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
> > intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> > + intel_psr_lobf_compute_config(intel_dp, pipe_config, conn_state);
> > intel_dp_drrs_compute_config(connector, pipe_config,
> link_bpp_x16);
> > intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> > intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp,
> pipe_config,
> > conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 4adcddba69c1..c08bffc2921a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -436,6 +436,16 @@ static bool intel_dp_get_alpm_status(struct
> intel_dp *intel_dp)
> > return alpm_caps & DP_ALPM_CAP;
> > }
> >
> > +static bool intel_dp_get_aux_less_alpm_status(struct intel_dp
> > +*intel_dp) {
> > + u8 alpm_caps = 0;
> > +
> > + if (drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP,
> > + _caps) != 1)
>
> The compute config path must not access the hardware.
Sure, will put in init_connector() and store in a variable.
Regards,
Animesh
>
> BR,
> Jani.
>
> > + return false;
> > + return alpm_caps & DP_ALPM_AUX_LESS_CAP; }
> > +
> > static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1569,6
> > +1579,41 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> > crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> > crtc_state); }
> >
> > +void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state,
> > + struct drm_connector_state *conn_state) {
> > + struct drm_display_mode *adjusted_mode = _state-
> >hw.adjusted_mode;
> > + int waketime_in_lines, first_sdp_position;
> > + int context_latency, guardband;
> > + bool auxless_alpm;
> > +
> > + intel_dp->lobf_supported = false;
> > +
> > + if (!intel_dp_is_edp(intel_dp))
> > + return;
> > +
> > + if (!intel_dp_as_sdp_supported(intel_dp))
> > + return;
> > +
> > + if (CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))
> > + return;
> > +
> > + if (_compute_alpm_params(intel_dp, crtc_state)) {
> > + context_latency = adjusted_mode->crtc_vblank_start -
> adjusted_mode->crtc_vdisplay;
> > + guardband = adjusted_mode->crtc_vtotal - adjusted_mode-
> >crtc_vdisplay - context_latency;
> > + first_sdp_position = adjusted_mode->crtc_vtotal -
> adjusted_mode->crtc_vsync_start;
> > + auxless_alpm =
> intel_dp_get_aux_less_alpm_status(intel_dp);
> > + if (auxless_alpm)
> > + waketime_in_lines = intel_dp-
> >alpm_parameters.io_wake_lines;
> > + else
> > + waketime_in_lines = intel_dp-
> >alpm_parameters.aux_less_wake_lines;
> > +
> > + if ((context_latency + guardband) > (first_sdp_position +
> waketime_in_lines))
> > +
✗ Fi.CI.BAT: failure for drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev3)
== Series Details == Series: drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev3) URL : https://patchwork.freedesktop.org/series/130643/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130643v3 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_130643v3 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_130643v3, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/index.html Participating hosts (41 -> 40) -- Additional (1): fi-glk-j4005 Missing(2): bat-kbl-2 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_130643v3: ### IGT changes ### Possible regressions * igt@i915_selftest@live@migrate: - bat-dg2-9: NOTRUN -> [ABORT][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-dg2-9/igt@i915_selftest@l...@migrate.html Known issues Here are the changes found in Patchwork_130643v3 that come from known issues: ### CI changes ### Issues hit * boot: - fi-apl-guc: [PASS][2] -> [FAIL][3] ([i915#8293]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-apl-guc/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/fi-apl-guc/boot.html Possible fixes * boot: - bat-arls-3: [FAIL][4] ([i915#10234]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][6] ([i915#9318]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-arls-2: NOTRUN -> [SKIP][7] ([i915#9318]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10213]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][11] ([i915#10213]) +3 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][12] ([i915#4083]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-2/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#4083]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10196] / [i915#4077]) +2 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10197] / [i915#10211] / [i915#4079]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-2/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10197] / [i915#10211] / [i915#4079]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10196] / [i915#4077]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10206] / [i915#4079]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v3/bat-arls-3/igt@gem_tiled_pread_basic.html - bat-arls-2: NOTRUN -> [SKIP][19] ([i915#10206] / [i915#4079]) [19]:
RE: Regression on linux-next (next-20240228)
Hello Mathew,
> -Original Message-
> From: Borah, Chaitanya Kumar
> Sent: Monday, March 4, 2024 8:18 PM
> To: Matthew Wilcox
> Cc: intel-gfx@lists.freedesktop.org; Kurmi, Suresh Kumar
> ; Saarinen, Jani
> Subject: RE: Regression on linux-next (next-20240228)
>
> Hello Mathew,
>
> > -Original Message-
> > From: Matthew Wilcox
> > Sent: Monday, March 4, 2024 6:52 PM
> > To: Borah, Chaitanya Kumar
> > Cc: intel-gfx@lists.freedesktop.org; Kurmi, Suresh Kumar
> > ; Saarinen, Jani
> >
> > Subject: Re: Regression on linux-next (next-20240228)
> >
> > On Mon, Mar 04, 2024 at 10:03:13AM +, Borah, Chaitanya Kumar
> > wrote:
> > > > Could you try putting the two:
> > > >
> > > > - list_del(>lru);
> > > >
> > > > statements back in and see if that fixes it?
> > >
> > > That seems to fix it.
> > >
> > > if (!folio_put_testzero(folio))
> > > + list_del(>lru);
> > > continue;
> >
> > Ummm ... did you put { and } around this? Otherwise the indentation
> > is misleading and what you're actually done is:
> >
> > if (!folio_put_testzero(folio))
> > list_del(>lru);
> > continue;
> >
> > which will simply leak memory.
> >
>
> Oops look like a miss on our side. Let us re-do this and get back to you.
>
Issue is still seen with the following changes
void put_pages_list(struct list_head *pages)
folio_batch_init();
list_for_each_entry(folio, pages, lru) {
- if (!folio_put_testzero(folio))
+ if (!folio_put_testzero(folio)) {
+ list_del(>lru);
continue;
+ }
if (folio_test_large(folio)) {
__folio_put_large(folio);
+ list_del(>lru);
continue;
}
Regards
Chaitanya
> Regards
>
> Chaitanya
>
> > > if (folio_test_large(folio)) {
> > > __folio_put_large(folio);
> > > + list_del(>lru);
> > > continue;
> > > }
> > > Regards
> > >
> > > Chaitanya
✓ Fi.CI.BAT: success for drm/i915/mtl: Update workaround 14018575942 (rev4)
== Series Details == Series: drm/i915/mtl: Update workaround 14018575942 (rev4) URL : https://patchwork.freedesktop.org/series/130490/ State : success == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130490v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/index.html Participating hosts (41 -> 40) -- Additional (1): fi-glk-j4005 Missing(2): bat-mtlp-8 fi-snb-2520m Known issues Here are the changes found in Patchwork_130490v4 that come from known issues: ### CI changes ### Issues hit * boot: - bat-arls-2: [PASS][1] -> [FAIL][2] ([i915#10234]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-2/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-2/boot.html - bat-jsl-1: [PASS][3] -> [FAIL][4] ([i915#8293]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-jsl-1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-jsl-1/boot.html - fi-apl-guc: [PASS][5] -> [FAIL][6] ([i915#8293]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-apl-guc/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/fi-apl-guc/boot.html Possible fixes * boot: - bat-arls-3: [FAIL][7] ([i915#10234]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#9318]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#2190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10213]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#4083]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10197] / [i915#10211] / [i915#4079]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10196] / [i915#4077]) +2 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10206] / [i915#4079]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10209]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10200]) +9 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-glk-j4005: NOTRUN -> [SKIP][19] ([fdo#109271]) +10 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - bat-arls-3: NOTRUN -> [SKIP][20] ([i915#10202]) +1 other test skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-arls-3: NOTRUN -> [SKIP][21] ([i915#9886]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v4/bat-arls-3/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-arls-3: NOTRUN -> [SKIP][22] ([i915#10207]) [22]:
[PATCH] drm/i915/dp: Fix the computation for compressed_bpp for DISPLAY < 13
For DISPLAY < 13, compressed bpp is chosen from a list of
supported compressed bpps. Fix the condition to choose the
appropriate compressed bpp from the list.
Fixes: 1c56e9a39833 ("drm/i915/dp: Get optimal link config to have best
compressed bpp")
Cc: Ankit Nautiyal
Cc: Stanislav Lisovskiy
Cc: Jani Nikula
Cc: # v6.7+
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10162
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index e13121dc3a03..d579195f84ee 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1918,8 +1918,9 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
- if (valid_dsc_bpp[i] < dsc_min_bpp ||
- valid_dsc_bpp[i] > dsc_max_bpp)
+ if (valid_dsc_bpp[i] < dsc_min_bpp)
+ continue;
+ if (valid_dsc_bpp[i] > dsc_max_bpp)
break;
ret = dsc_compute_link_config(intel_dp,
--
2.40.1
✓ Fi.CI.BAT: success for drm/i915/guc: Use context hints for GT frequency
== Series Details == Series: drm/i915/guc: Use context hints for GT frequency URL : https://patchwork.freedesktop.org/series/130698/ State : success == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130698v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/index.html Participating hosts (41 -> 38) -- Missing(3): bat-mtlp-8 bat-dg1-7 fi-snb-2520m Known issues Here are the changes found in Patchwork_130698v1 that come from known issues: ### CI changes ### Possible fixes * boot: - bat-arls-3: [FAIL][1] ([i915#10234]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-arls-2: NOTRUN -> [SKIP][4] ([i915#9318]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][5] ([i915#10213]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][6] ([i915#10213]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-2/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#4083]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][9] ([i915#10196] / [i915#4077]) +2 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][10] ([i915#10197] / [i915#10211] / [i915#4079]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-2/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10197] / [i915#10211] / [i915#4079]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10196] / [i915#4077]) +2 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10206] / [i915#4079]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-3/igt@gem_tiled_pread_basic.html - bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10206] / [i915#4079]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rpm@module-reload: - fi-kbl-7567u: [PASS][15] -> [CRASH][16] ([i915#9947]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-kbl-7567u/igt@i915_pm_...@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/fi-kbl-7567u/igt@i915_pm_...@module-reload.html * igt@i915_pm_rps@basic-api: - bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10209]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-2/igt@i915_pm_...@basic-api.html - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10209]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@workarounds: - bat-dg2-14: [PASS][19] -> [DMESG-FAIL][20] ([i915#9500]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-dg2-14/igt@i915_selftest@l...@workarounds.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-dg2-14/igt@i915_selftest@l...@workarounds.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][21] ([i915#10200]) +9 other tests skip [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130698v1/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-arls-2: NOTRUN ->
✗ Fi.CI.SPARSE: warning for drm/i915/guc: Use context hints for GT frequency
== Series Details == Series: drm/i915/guc: Use context hints for GT frequency URL : https://patchwork.freedesktop.org/series/130698/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
RE: ✗ Fi.CI.IGT: failure for drm/i915/selftest_hangcheck: Check sanity with more patience
Hi, https://patchwork.freedesktop.org/series/130512/ - Re-reported. Thanks, Tejasree -Original Message- From: Janusz Krzysztofik Sent: Friday, March 1, 2024 6:55 PM To: LGCI Bug Filing Cc: intel-gfx@lists.freedesktop.org; Andi Shyti ; Janusz Krzysztofik Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/selftest_hangcheck: Check sanity with more patience On Thursday, 29 February 2024 23:16:22 CET Patchwork wrote: > == Series Details == > > Series: drm/i915/selftest_hangcheck: Check sanity with more patience > URL : https://patchwork.freedesktop.org/series/130512/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_14362_full -> Patchwork_130512v1_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_130512v1_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_130512v1_full, please notify your bug team > (i915-ci-in...@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v1/index.html > > Participating hosts (8 -> 9) > -- > > Additional (1): shard-snb-0 > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_130512v1_full: > > ### IGT changes ### > > Possible regressions > > * igt@gem_softpin@allocator-evict@vecs0: > - shard-rkl: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/shard-rkl-4/igt@gem_softpin@allocator-ev...@vecs0.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v1/shard-rkl-3/igt@gem_softpin@allocator-ev...@vecs0.html > > * igt@kms_flip@2x-plain-flip-ts-check@ac-hdmi-a1-hdmi-a2: > - shard-glk: [PASS][3] -> [INCOMPLETE][4] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/shard-glk2/igt@kms_flip@2x-plain-flip-ts-ch...@ac-hdmi-a1-hdmi-a2.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v1/shard-glk7/igt@kms_flip@2x-plain-flip-ts-ch...@ac-hdmi-a1-hdmi-a2.html None of the two is related to the change in igt@i915_selftest@live@hangcheck. @BUG Filing, please update filters and re-report. Thanks, Janusz > > > New tests > - > > New tests have been introduced between CI_DRM_14362_full and > Patchwork_130512v1_full: > > ### New IGT tests (7) ### > > * igt@kms_cursor_edge_walk@128x128-right-edge@pipe-a-dp-4: > - Statuses : 1 pass(s) > - Exec time: [3.46] s > > * igt@kms_cursor_edge_walk@128x128-right-edge@pipe-d-dp-4: > - Statuses : 1 pass(s) > - Exec time: [3.31] s > > * igt@kms_plane_alpha_blend@constant-alpha-min@pipe-d-dp-4: > - Statuses : 1 pass(s) > - Exec time: [0.74] s > > * > igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-dp-4: > - Statuses : 1 skip(s) > - Exec time: [0.01] s > > * > igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-b-dp-4: > - Statuses : 1 skip(s) > - Exec time: [0.03] s > > * > igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-dp-4: > - Statuses : 1 skip(s) > - Exec time: [0.03] s > > * > igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-dp-4: > - Statuses : 1 skip(s) > - Exec time: [0.03] s > > > > Known issues > > > Here are the changes found in Patchwork_130512v1_full that come from known > issues: > > ### CI changes ### > > Issues hit > > * boot: > - shard-snb: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], > [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], > [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], > [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], > [PASS][27], [PASS][28], [PASS][29]) -> ([PASS][30], [PASS][31], [PASS][32], > [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], > [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], > [PASS][45], [PASS][46], [FAIL][47], [PASS][48], [PASS][49], [PASS][50], > [PASS][51], [PASS][52], [PASS][53], [PASS][54]) ([i915#8293]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/shard-snb2/boot.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/shard-snb2/boot.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/shard-snb2/boot.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/shard-snb2/boot.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14362/shard-snb2/boot.html >[10]: >
✓ Fi.CI.BAT: success for drm/i915/selftest_hangcheck: Check sanity with more patience (rev3)
== Series Details == Series: drm/i915/selftest_hangcheck: Check sanity with more patience (rev3) URL : https://patchwork.freedesktop.org/series/130512/ State : success == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130512v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/index.html Participating hosts (41 -> 40) -- Additional (1): fi-glk-j4005 Missing(2): bat-mtlp-8 fi-snb-2520m Known issues Here are the changes found in Patchwork_130512v3 that come from known issues: ### CI changes ### Issues hit * boot: - fi-bsw-n3050: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-bsw-n3050/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-bsw-n3050/boot.html Possible fixes * boot: - bat-arls-3: [FAIL][3] ([i915#10234]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][5] ([i915#9318]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-arls-2: NOTRUN -> [SKIP][6] ([i915#9318]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#10213]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][10] ([i915#10213]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#4083]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][13] ([i915#10196] / [i915#4077]) +2 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10197] / [i915#10211] / [i915#4079]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10197] / [i915#10211] / [i915#4079]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10196] / [i915#4077]) +2 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10206] / [i915#4079]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_tiled_pread_basic.html - bat-arls-2: NOTRUN -> [SKIP][18] ([i915#10206] / [i915#4079]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-2: NOTRUN -> [SKIP][19] ([i915#10209]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@i915_pm_...@basic-api.html - bat-arls-3: NOTRUN -> [SKIP][20] ([i915#10209]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@client: - bat-arls-1: [PASS][21] -> [DMESG-WARN][22] ([i915#10341]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-1/igt@i915_selftest@l...@client.html [22]:
✗ Fi.CI.BAT: failure for VBT read cleanup (rev5)
== Series Details == Series: VBT read cleanup (rev5) URL : https://patchwork.freedesktop.org/series/130528/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130528v5 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_130528v5 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_130528v5, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/index.html Participating hosts (41 -> 37) -- Missing(4): bat-mtlp-8 bat-kbl-2 bat-jsl-1 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_130528v5: ### IGT changes ### Possible regressions * igt@gem_tiled_fence_blits@basic: - bat-arls-2: NOTRUN -> [FAIL][1] +1 other test fail [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-2/igt@gem_tiled_fence_bl...@basic.html * igt@i915_selftest@live@gt_heartbeat: - bat-arls-2: NOTRUN -> [ABORT][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-2/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@memory_region: - bat-atsm-1: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-atsm-1/igt@i915_selftest@live@memory_region.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-atsm-1/igt@i915_selftest@live@memory_region.html * igt@kms_pm_rpm@basic-rte: - bat-dg1-7: [PASS][5] -> [ABORT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-dg1-7/igt@kms_pm_...@basic-rte.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-dg1-7/igt@kms_pm_...@basic-rte.html Known issues Here are the changes found in Patchwork_130528v5 that come from known issues: ### CI changes ### Possible fixes * boot: - bat-arls-3: [FAIL][7] ([i915#10234]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#9318]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-arls-2: NOTRUN -> [SKIP][10] ([i915#9318]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10213]) +3 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][12] ([i915#10213]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][13] ([i915#4083]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-2/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#4083]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10196] / [i915#4077]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10197] / [i915#10211] / [i915#4079]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-2/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10197] / [i915#10211] / [i915#4079]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10196] / [i915#4077]) +2 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10206] / [i915#4079]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130528v5/bat-arls-3/igt@gem_tiled_pread_basic.html - bat-arls-2: NOTRUN ->
✗ Fi.CI.SPARSE: warning for VBT read cleanup (rev5)
== Series Details == Series: VBT read cleanup (rev5) URL : https://patchwork.freedesktop.org/series/130528/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.BAT: failure for drm/i915/selftest_hangcheck: Check sanity with more patience (rev3)
== Series Details == Series: drm/i915/selftest_hangcheck: Check sanity with more patience (rev3) URL : https://patchwork.freedesktop.org/series/130512/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130512v3 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_130512v3 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_130512v3, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/index.html Participating hosts (41 -> 40) -- Additional (1): fi-glk-j4005 Missing(2): bat-mtlp-8 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_130512v3: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gtt: - fi-elk-e7500: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-elk-e7500/igt@i915_selftest@l...@gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-elk-e7500/igt@i915_selftest@l...@gtt.html Known issues Here are the changes found in Patchwork_130512v3 that come from known issues: ### CI changes ### Issues hit * boot: - fi-bsw-n3050: [PASS][3] -> [FAIL][4] ([i915#8293]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-bsw-n3050/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-bsw-n3050/boot.html Possible fixes * boot: - bat-arls-3: [FAIL][5] ([i915#10234]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][7] ([i915#9318]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-arls-2: NOTRUN -> [SKIP][8] ([i915#9318]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10213]) +3 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][12] ([i915#10213]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][13] ([i915#4083]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#4083]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10196] / [i915#4077]) +2 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10197] / [i915#10211] / [i915#4079]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10197] / [i915#10211] / [i915#4079]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10196] / [i915#4077]) +2 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10206] / [i915#4079]) [19]:
Re: [PATCH v2 3/3] drm/i915/bios: abstract child device expected size
On 2/26/2024 23:28, Jani Nikula wrote:
Add a function to return the expected child device size. Flip the if
ladder around and use the same versions as in documentation to make it
easier to verify. Return an error for unknown versions. No functional
changes.
v2: Move BUILD_BUG_ON() next to the expected sizes
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 40 ++-
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index c0f41bd1f946..343726de9aa7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2699,27 +2699,35 @@ static void parse_ddi_ports(struct drm_i915_private
*i915)
print_ddi_port(devdata);
}
+static int child_device_expected_size(u16 version)
+{
+ BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
+
+ if (version > 256)
+ return -ENOENT;
+ else if (version >= 256)
Correct me if I'm wrong, but isn't version >= 256, a bit cryptic after
the first check?
Would it be wise to make it version > 256, return -ENOENT and if version
== 256, return 40?
+ return 40;
+ else if (version >= 216)
+ return 39;
+ else if (version >= 196)
+ return 38;
+ else if (version >= 195)
+ return 37;
+ else if (version >= 111)
+ return LEGACY_CHILD_DEVICE_CONFIG_SIZE;
+ else if (version >= 106)
+ return 27;
+ else
+ return 22;
+}
+
static bool child_device_size_valid(struct drm_i915_private *i915, int size)
{
int expected_size;
- if (i915->display.vbt.version < 106) {
- expected_size = 22;
- } else if (i915->display.vbt.version < 111) {
- expected_size = 27;
- } else if (i915->display.vbt.version < 195) {
- expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
- } else if (i915->display.vbt.version == 195) {
- expected_size = 37;
- } else if (i915->display.vbt.version <= 215) {
- expected_size = 38;
- } else if (i915->display.vbt.version <= 255) {
- expected_size = 39;
- } else if (i915->display.vbt.version <= 256) {
- expected_size = 40;
- } else {
+ expected_size = child_device_expected_size(i915->display.vbt.version);
+ if (expected_size < 0) {
expected_size = sizeof(struct child_device_config);
- BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
drm_dbg(>drm,
"Expected child device config size for VBT version %u not
known; assuming %d\n",
i915->display.vbt.version, expected_size);
--
-shekhar
✓ Fi.CI.BAT: success for Enable Wa_14019159160 and Wa_16019325821 for MTL (rev3)
== Series Details == Series: Enable Wa_14019159160 and Wa_16019325821 for MTL (rev3) URL : https://patchwork.freedesktop.org/series/130335/ State : success == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130335v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/index.html Participating hosts (41 -> 39) -- Additional (1): fi-glk-j4005 Missing(3): bat-mtlp-8 bat-dg1-7 fi-snb-2520m Known issues Here are the changes found in Patchwork_130335v3 that come from known issues: ### CI changes ### Issues hit * boot: - bat-jsl-1: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-jsl-1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-jsl-1/boot.html - fi-apl-guc: [PASS][3] -> [FAIL][4] ([i915#8293]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-apl-guc/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/fi-apl-guc/boot.html - fi-cfl-8109u: [PASS][5] -> [FAIL][6] ([i915#8293]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-cfl-8109u/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/fi-cfl-8109u/boot.html Possible fixes * boot: - bat-arls-3: [FAIL][7] ([i915#10234]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#9318]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-arls-2: NOTRUN -> [SKIP][10] ([i915#9318]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10213]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10213]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][15] ([i915#4083]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-2/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#4083]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10196] / [i915#4077]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][18] ([i915#10197] / [i915#10211] / [i915#4079]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-2/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10197] / [i915#10211] / [i915#4079]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][20] ([i915#10196] / [i915#4077]) +2 other tests skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][21] ([i915#10206] / [i915#4079]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-3/igt@gem_tiled_pread_basic.html - bat-arls-2: NOTRUN -> [SKIP][22] ([i915#10206] / [i915#4079]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130335v3/bat-arls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-2: NOTRUN -> [SKIP][23] ([i915#10209]) [23]:
✗ Fi.CI.SPARSE: warning for Enable Wa_14019159160 and Wa_16019325821 for MTL (rev3)
== Series Details == Series: Enable Wa_14019159160 and Wa_16019325821 for MTL (rev3) URL : https://patchwork.freedesktop.org/series/130335/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for Enable Wa_14019159160 and Wa_16019325821 for MTL (rev3)
== Series Details == Series: Enable Wa_14019159160 and Wa_16019325821 for MTL (rev3) URL : https://patchwork.freedesktop.org/series/130335/ State : warning == Summary == Error: dim checkpatch failed 0900ae5c7da2 drm/i915: Enable Wa_16019325821 f4c1b0cad70c drm/i915/guc: Add support for w/a KLVs -:105: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #105: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:829: + GEM_BUG_ON(iosys_map_is_null(>ads_map)); total: 0 errors, 1 warnings, 0 checks, 159 lines checked a368163da728 drm/i915/guc: Enable Wa_14019159160 -:101: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #101: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:830: + GEM_BUG_ON(remain < size); total: 0 errors, 1 warnings, 0 checks, 99 lines checked
[PATCH v4] drm/i915/dp: Increase idle pattern wait timeout to 2ms
The driver currently waits 1ms for idle patterns, but for LNL and later platforms, it requires a 1640us (rounded up to 2ms) timeout whilst waiting for idle patterns for MST streams. To simplify the code, the timeout is uniformly increased by 1ms across all platforms. v1: Introduced the 2ms wait timeout. v2: Segregated the wait timeout for platforms before & after LNL. v3: Fixed 2 cosmetic changes. v4: Revert to v2 design with commit message enhancements. BSpec: 68849 Signed-off-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index bea441590204..05ba3642d486 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3680,7 +3680,7 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, if (intel_de_wait_for_set(dev_priv, dp_tp_status_reg(encoder, crtc_state), - DP_TP_STATUS_IDLE_DONE, 1)) + DP_TP_STATUS_IDLE_DONE, 2)) drm_err(_priv->drm, "Timed out waiting for DP idle patterns\n"); } -- 2.34.1
✗ Fi.CI.BAT: failure for Enable LNL display
== Series Details == Series: Enable LNL display URL : https://patchwork.freedesktop.org/series/130689/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130689v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_130689v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_130689v1, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/index.html Participating hosts (41 -> 40) -- Additional (1): fi-glk-j4005 Missing(2): bat-arls-4 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_130689v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gem_contexts: - bat-arls-2: NOTRUN -> [ABORT][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@i915_selftest@live@gem_contexts.html Known issues Here are the changes found in Patchwork_130689v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-2: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][5] ([i915#10213]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][6] ([i915#4083]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][7] ([i915#10196] / [i915#4077]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][8] ([i915#10197] / [i915#10211] / [i915#4079]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-2: NOTRUN -> [SKIP][9] ([i915#10206] / [i915#4079]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-2: NOTRUN -> [SKIP][10] ([i915#10209]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-arls-2: NOTRUN -> [SKIP][11] ([i915#10200]) +9 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-glk-j4005: NOTRUN -> [SKIP][12] ([fdo#109271]) +10 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-arls-2: NOTRUN -> [SKIP][13] ([i915#10202]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-arls-2: NOTRUN -> [SKIP][14] ([i915#9886]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10207]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v1/bat-arls-2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@psr-primary-mmap-gtt@edp-1: - bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10196] / [i915#4077] / [i915#9688]) [16]:
✗ Fi.CI.CHECKPATCH: warning for Enable LNL display
== Series Details == Series: Enable LNL display URL : https://patchwork.freedesktop.org/series/130689/ State : warning == Summary == Error: dim checkpatch failed 52ce7e3a93e7 drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_table 3f9ed6439f1f drm/i915/cdclk: Add and use xe2lpd_mdclk_source_sel() 7071a46e9b9d drm/i915/cdclk: Only compute squash waveform when necessary f17882210bdb drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update() 60c6197de41a drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state d26865441ec6 drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changes -:264: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #264: FILE: drivers/gpu/drm/i915/display/skl_watermark_regs.h:44: +#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) total: 0 errors, 1 warnings, 0 checks, 195 lines checked f4c6b4816724 drm/i915/xe2lpd: Load DMC b3ff3350eb2d drm/xe/lnl: Enable display support
✗ Fi.CI.SPARSE: warning for Enable LNL display
== Series Details == Series: Enable LNL display URL : https://patchwork.freedesktop.org/series/130689/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✓ Fi.CI.BAT: success for drm/i915: Fix VMA UAF on destroy against deactivate race (rev4)
== Series Details ==
Series: drm/i915: Fix VMA UAF on destroy against deactivate race (rev4)
URL : https://patchwork.freedesktop.org/series/129026/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14383 -> Patchwork_129026v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/index.html
Participating hosts (41 -> 40)
--
Additional (1): fi-glk-j4005
Missing(2): bat-mtlp-8 fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_129026v4:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@perf:
- {bat-arls-4}: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-4/igt@i915_selftest@l...@perf.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-4/igt@i915_selftest@l...@perf.html
Known issues
Here are the changes found in Patchwork_129026v4 that come from known issues:
### CI changes ###
Issues hit
* boot:
- bat-arls-1: [PASS][3] -> [FAIL][4] ([i915#10234])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-1/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-1/boot.html
- bat-jsl-1: [PASS][5] -> [FAIL][6] ([i915#8293])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-jsl-1/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-jsl-1/boot.html
Possible fixes
* boot:
- bat-arls-3: [FAIL][7] ([i915#10234]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-3/boot.html
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-arls-3: NOTRUN -> [SKIP][9] ([i915#9318])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-3/igt@debugfs_t...@basic-hwmon.html
- bat-arls-2: NOTRUN -> [SKIP][10] ([i915#9318])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-2/igt@debugfs_t...@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- fi-glk-j4005: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-glk-j4005: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3
other tests skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10213]) +3 other tests
skip
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10213]) +3 other tests
skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_mmap@basic:
- bat-arls-2: NOTRUN -> [SKIP][15] ([i915#4083])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-2/igt@gem_m...@basic.html
- bat-arls-3: NOTRUN -> [SKIP][16] ([i915#4083])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-3/igt@gem_m...@basic.html
* igt@gem_mmap_gtt@basic:
- bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10196] / [i915#4077]) +2
other tests skip
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-2/igt@gem_mmap_...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-arls-2: NOTRUN -> [SKIP][18] ([i915#10197] / [i915#10211] /
[i915#4079])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-2/igt@gem_render_tiled_bl...@basic.html
- bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10197] / [i915#10211] /
[i915#4079])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-3/igt@gem_render_tiled_bl...@basic.html
* igt@gem_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][20] ([i915#10196] / [i915#4077]) +2
other tests skip
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129026v4/bat-arls-3/igt@gem_tiled_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-arls-3: NOTRUN -> [SKIP][21] ([i915#10206] / [i915#4079])
[21]:
✗ Fi.CI.BUILD: failure for series starting with [v8,1/3] drm/buddy: Implement tracking clear page feature
== Series Details == Series: series starting with [v8,1/3] drm/buddy: Implement tracking clear page feature URL : https://patchwork.freedesktop.org/series/130680/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool INSTALL libsubcmd_headers AR drivers/gpu/drm/panel/built-in.a AR drivers/gpu/drm/bridge/analogix/built-in.a AR drivers/gpu/drm/bridge/cadence/built-in.a AR drivers/gpu/drm/bridge/imx/built-in.a AR drivers/gpu/drm/bridge/synopsys/built-in.a AR drivers/gpu/drm/bridge/built-in.a AR drivers/gpu/drm/hisilicon/built-in.a AR drivers/gpu/drm/mxsfb/built-in.a AR drivers/gpu/drm/tiny/built-in.a AR drivers/gpu/drm/xlnx/built-in.a AR drivers/gpu/drm/gud/built-in.a AR drivers/gpu/drm/solomon/built-in.a CC [M] drivers/gpu/drm/tests/drm_buddy_test.o drivers/gpu/drm/tests/drm_buddy_test.c: In function ‘drm_test_buddy_alloc_range_bias’: drivers/gpu/drm/tests/drm_buddy_test.c:106:3: error: too few arguments to function ‘drm_buddy_free_list’ 106 | drm_buddy_free_list(, ); | ^~~ In file included from drivers/gpu/drm/tests/drm_buddy_test.c:13: ./include/drm/drm_buddy.h:166:6: note: declared here 166 | void drm_buddy_free_list(struct drm_buddy *mm, | ^~~ drivers/gpu/drm/tests/drm_buddy_test.c:116:3: error: too few arguments to function ‘drm_buddy_free_list’ 116 | drm_buddy_free_list(, ); | ^~~ In file included from drivers/gpu/drm/tests/drm_buddy_test.c:13: ./include/drm/drm_buddy.h:166:6: note: declared here 166 | void drm_buddy_free_list(struct drm_buddy *mm, | ^~~ drivers/gpu/drm/tests/drm_buddy_test.c:156:4: error: too few arguments to function ‘drm_buddy_free_list’ 156 |drm_buddy_free_list(, ); |^~~ In file included from drivers/gpu/drm/tests/drm_buddy_test.c:13: ./include/drm/drm_buddy.h:166:6: note: declared here 166 | void drm_buddy_free_list(struct drm_buddy *mm, | ^~~ drivers/gpu/drm/tests/drm_buddy_test.c:163:2: error: too few arguments to function ‘drm_buddy_free_list’ 163 | drm_buddy_free_list(, ); | ^~~ In file included from drivers/gpu/drm/tests/drm_buddy_test.c:13: ./include/drm/drm_buddy.h:166:6: note: declared here 166 | void drm_buddy_free_list(struct drm_buddy *mm, | ^~~ drivers/gpu/drm/tests/drm_buddy_test.c:223:2: error: too few arguments to function ‘drm_buddy_free_list’ 223 | drm_buddy_free_list(, ); | ^~~ In file included from drivers/gpu/drm/tests/drm_buddy_test.c:13: ./include/drm/drm_buddy.h:166:6: note: declared here 166 | void drm_buddy_free_list(struct drm_buddy *mm, | ^~~ make[6]: *** [scripts/Makefile.build:243: drivers/gpu/drm/tests/drm_buddy_test.o] Error 1 make[5]: *** [scripts/Makefile.build:481: drivers/gpu/drm/tests] Error 2 make[4]: *** [scripts/Makefile.build:481: drivers/gpu/drm] Error 2 make[3]: *** [scripts/Makefile.build:481: drivers/gpu] Error 2 make[2]: *** [scripts/Makefile.build:481: drivers] Error 2 make[1]: *** [/home/kbuild2/kernel/Makefile:1921: .] Error 2 make: *** [Makefile:240: __sub-make] Error 2 Build failed, no error log produced
✗ Fi.CI.SPARSE: warning for drm/i915: Fix VMA UAF on destroy against deactivate race (rev4)
== Series Details == Series: drm/i915: Fix VMA UAF on destroy against deactivate race (rev4) URL : https://patchwork.freedesktop.org/series/129026/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/uaccess_64.h:88:24: warning: cast removes address space '__user' of expression +./arch/x86/include/asm/uaccess_64.h:88:24: warning: cast removes address space '__user' of expression +./arch/x86/include/asm/uaccess_64.h:88:24: warning: cast removes address space '__user' of expression +./arch/x86/include/asm/uaccess_64.h:88:24: warning: cast removes address space '__user' of expression +./arch/x86/include/asm/uaccess_64.h:88:24: warning: cast removes address space '__user' of expression +./arch/x86/include/asm/uaccess_64.h:88:24: warning: cast removes address space '__user' of expression +./arch/x86/include/asm/uaccess_64.h:88:24: warning: cast removes address space '__user' of expression +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
✗ Fi.CI.BAT: failure for drm/i915/selftest_hangcheck: Check sanity with more patience (rev3)
== Series Details == Series: drm/i915/selftest_hangcheck: Check sanity with more patience (rev3) URL : https://patchwork.freedesktop.org/series/130512/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130512v3 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_130512v3 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_130512v3, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/index.html Participating hosts (41 -> 39) -- Additional (1): fi-glk-j4005 Missing(3): bat-mtlp-8 fi-snb-2520m fi-elk-e7500 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_130512v3: ### IGT changes ### Possible regressions * igt@i915_selftest@live@client: - bat-arls-1: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-1/igt@i915_selftest@l...@client.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-1/igt@i915_selftest@l...@client.html * igt@i915_selftest@live@slpc: - bat-dg2-11: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-dg2-11/igt@i915_selftest@l...@slpc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-dg2-11/igt@i915_selftest@l...@slpc.html Known issues Here are the changes found in Patchwork_130512v3 that come from known issues: ### CI changes ### Issues hit * boot: - fi-bsw-n3050: [PASS][5] -> [FAIL][6] ([i915#8293]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/fi-bsw-n3050/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-bsw-n3050/boot.html Possible fixes * boot: - bat-arls-3: [FAIL][7] ([i915#10234]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#9318]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-arls-2: NOTRUN -> [SKIP][10] ([i915#9318]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10213]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10213]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][15] ([i915#4083]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#4083]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10196] / [i915#4077]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][18] ([i915#10197] / [i915#10211] / [i915#4079]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-2/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10197] / [i915#10211] / [i915#4079]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130512v3/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][20] ([i915#10196] /
✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftest_hangcheck: Check sanity with more patience (rev3)
== Series Details == Series: drm/i915/selftest_hangcheck: Check sanity with more patience (rev3) URL : https://patchwork.freedesktop.org/series/130512/ State : warning == Summary == Error: dim checkpatch failed 3db5d21fbc6b drm/i915/selftest_hangcheck: Check sanity with more patience -:11: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #11: Feb 22 19:49:06 DUT1394ACMR kernel: calling mei_gsc_driver_init+0x0/0xff0 [mei_gsc] @ 121074 total: 0 errors, 1 warnings, 0 checks, 8 lines checked
✓ Fi.CI.BAT: success for drm/i915/selftests: Fix dependency of some timeouts on HZ (rev3)
== Series Details == Series: drm/i915/selftests: Fix dependency of some timeouts on HZ (rev3) URL : https://patchwork.freedesktop.org/series/130249/ State : success == Summary == CI Bug Log - changes from CI_DRM_14383 -> Patchwork_130249v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/index.html Participating hosts (41 -> 40) -- Additional (1): fi-glk-j4005 Missing(2): bat-dg1-7 fi-snb-2520m Known issues Here are the changes found in Patchwork_130249v3 that come from known issues: ### CI changes ### Possible fixes * boot: - bat-arls-3: [FAIL][1] ([i915#10234]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14383/bat-arls-3/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-3/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-arls-2: NOTRUN -> [SKIP][4] ([i915#9318]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-2/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][7] ([i915#10213]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-arls-2: NOTRUN -> [SKIP][8] ([i915#10213]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-2: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-2/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#4083]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-arls-2: NOTRUN -> [SKIP][11] ([i915#10196] / [i915#4077]) +2 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-2/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-2: NOTRUN -> [SKIP][12] ([i915#10197] / [i915#10211] / [i915#4079]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-2/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10197] / [i915#10211] / [i915#4079]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10196] / [i915#4077]) +2 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10206] / [i915#4079]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-3/igt@gem_tiled_pread_basic.html - bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10206] / [i915#4079]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-2/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10209]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-2/igt@i915_pm_...@basic-api.html - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10209]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10200]) +9 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130249v3/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-arls-2: NOTRUN -> [SKIP][20] ([i915#10200]) +9 other tests skip [20]:
✗ Fi.CI.BUILD: failure for drm/i915: Remove unneeded double drm_rect_visible call in check_overlay_dst
== Series Details == Series: drm/i915: Remove unneeded double drm_rect_visible call in check_overlay_dst URL : https://patchwork.freedesktop.org/series/130669/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/130669/revisions/1/mbox/ not applied Applying: drm/i915: Remove unneeded double drm_rect_visible call in check_overlay_dst error: git diff header lacks filename information when removing 1 leading pathname component (line 6) error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915: Remove unneeded double drm_rect_visible call in check_overlay_dst When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
✗ Fi.CI.BAT: failure for drm/i915/mtl: Update workaround 14018575942 (rev3)
== Series Details == Series: drm/i915/mtl: Update workaround 14018575942 (rev3) URL : https://patchwork.freedesktop.org/series/130490/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14382 -> Patchwork_130490v3 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_130490v3 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_130490v3, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/index.html Participating hosts (41 -> 39) -- Missing(2): bat-mtlp-8 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_130490v3: ### IGT changes ### Possible regressions * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-11: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html * igt@i915_selftest@live@gem_contexts: - bat-arls-2: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/bat-arls-2/igt@i915_selftest@live@gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/bat-arls-2/igt@i915_selftest@live@gem_contexts.html Known issues Here are the changes found in Patchwork_130490v3 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-tgl-1115g4: [FAIL][5] ([i915#8293]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/fi-tgl-1115g4/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#9318]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@evict: - bat-dg2-14: [PASS][10] -> [ABORT][11] ([i915#10366]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/bat-dg2-14/igt@i915_selftest@l...@evict.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/bat-dg2-14/igt@i915_selftest@l...@evict.html * igt@i915_selftest@live@hugepages: - bat-dg2-9: [PASS][12] -> [ABORT][13] ([i915#10366]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/bat-dg2-9/igt@i915_selftest@l...@hugepages.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/bat-dg2-9/igt@i915_selftest@l...@hugepages.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#4103]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#3840]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([fdo#109285]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#9812]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/igt@kms_pm_backli...@basic-brightness.html * igt@kms_psr@psr-sprite-plane-onoff: - fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([i915#9732]) +3 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/igt@kms_...@psr-sprite-plane-onoff.html * igt@kms_setmode@basic-clone-single-crtc: - fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#3555]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130490v3/fi-tgl-1115g4/igt@kms_setm...@basic-clone-single-crtc.html
✓ Fi.CI.BAT: success for drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev2)
== Series Details == Series: drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev2) URL : https://patchwork.freedesktop.org/series/130643/ State : success == Summary == CI Bug Log - changes from CI_DRM_14382 -> Patchwork_130643v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/index.html Participating hosts (41 -> 41) -- Additional (1): bat-kbl-2 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_130643v2 that come from known issues: ### CI changes ### Issues hit * boot: - fi-bsw-n3050: [PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/fi-bsw-n3050/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-bsw-n3050/boot.html - bat-arls-3: [PASS][3] -> [FAIL][4] ([i915#10234]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/bat-arls-3/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/bat-arls-3/boot.html - fi-cfl-8109u: [PASS][5] -> [FAIL][6] ([i915#8293]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/fi-cfl-8109u/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-cfl-8109u/boot.html Possible fixes * boot: - fi-tgl-1115g4: [FAIL][7] ([i915#8293]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/fi-tgl-1115g4/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-tgl-1115g4/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#9318]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-tgl-1115g4/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-kbl-2: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1849]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/bat-kbl-2/igt@fb...@info.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-kbl-2: NOTRUN -> [SKIP][12] ([fdo#109271]) +39 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#4613]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-tgl-1115g4/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@hangcheck: - fi-skl-guc: [PASS][14] -> [DMESG-FAIL][15] ([i915#10112]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@ring_submission: - bat-arls-2: [PASS][16] -> [DMESG-FAIL][17] ([i915#10262]) +12 other tests dmesg-fail [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14382/bat-arls-2/igt@i915_selftest@live@ring_submission.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/bat-arls-2/igt@i915_selftest@live@ring_submission.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([i915#4103]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#3840]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-tgl-1115g4/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([fdo#109285]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][21] ([i915#9812]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-tgl-1115g4/igt@kms_pm_backli...@basic-brightness.html * igt@kms_psr@psr-sprite-plane-onoff: - fi-tgl-1115g4: NOTRUN -> [SKIP][22] ([i915#9732]) +3 other tests skip [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v2/fi-tgl-1115g4/igt@kms_...@psr-sprite-plane-onoff.html * igt@kms_setmode@basic-clone-single-crtc: - fi-tgl-1115g4: NOTRUN -> [SKIP][23] ([i915#3555]) [23]:
✗ Fi.CI.BUILD: failure for Link off between frames for edp
== Series Details == Series: Link off between frames for edp URL : https://patchwork.freedesktop.org/series/130650/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/130650/revisions/1/mbox/ not applied Applying: drm/i915/alpm: Move alpm parameters from intel_psr error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_display_types.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915/alpm: Move alpm parameters from intel_psr When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
[PATCH v3] drm/i915/guc: Use context hints for GT frequency
Allow user to provide a low latency context hint. When set, KMD
sends a hint to GuC which results in special handling for this
context. SLPC will ramp the GT frequency aggressively every time
it switches to this context. The down freq threshold will also be
lower so GuC will ramp down the GT freq for this context more slowly.
We also disable waitboost for this context as that will interfere with
the strategy.
We need to enable the use of SLPC Compute strategy during init, but
it will apply only to contexts that set this bit during context
creation.
Userland can check whether this feature is supported using a new param-
I915_PARAM_HAS_CONTEXT_FREQ_HINTS. This flag is true for all guc submission
enabled platforms as they use SLPC for frequency management.
The Mesa usage model for this flag is here -
https://gitlab.freedesktop.org/sushmave/mesa/-/commits/compute_hint
v2: Rename flags as per review suggestions (Rodrigo, Tvrtko).
Also, use flag bits in intel_context as it allows finer control for
toggling per engine if needed (Tvrtko).
v3: Minor review comments (Tvrtko)
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Sushma Venkatesh Reddy
Acked-by: Rodrigo Vivi
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 16 --
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_rps.c | 4
.../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 21 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 17 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 ++
drivers/gpu/drm/i915/i915_getparam.c | 6 ++
include/uapi/drm/i915_drm.h | 15 +
10 files changed, 86 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index dcbfe32fd30c..81f65cab1330 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -879,6 +879,7 @@ static int set_proto_ctx_param(struct drm_i915_file_private
*fpriv,
struct i915_gem_proto_context *pc,
struct drm_i915_gem_context_param *args)
{
+ struct drm_i915_private *i915 = fpriv->i915;
int ret = 0;
switch (args->param) {
@@ -904,6 +905,13 @@ static int set_proto_ctx_param(struct
drm_i915_file_private *fpriv,
pc->user_flags &= ~BIT(UCONTEXT_BANNABLE);
break;
+ case I915_CONTEXT_PARAM_LOW_LATENCY:
+ if (intel_uc_uses_guc_submission(_gt(i915)->uc))
+ pc->user_flags |= BIT(UCONTEXT_LOW_LATENCY);
+ else
+ ret = -EINVAL;
+ break;
+
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
@@ -992,6 +1000,9 @@ static int intel_context_set_gem(struct intel_context *ce,
if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))
ret = intel_context_reconfigure_sseu(ce, sseu);
+ if (test_bit(UCONTEXT_LOW_LATENCY, >user_flags))
+ __set_bit(CONTEXT_LOW_LATENCY, >flags);
+
return ret;
}
@@ -1630,6 +1641,9 @@ i915_gem_create_context(struct drm_i915_private *i915,
if (vm)
ctx->vm = vm;
+ /* Assign early so intel_context_set_gem can access these flags */
+ ctx->user_flags = pc->user_flags;
+
mutex_init(>engines_mutex);
if (pc->num_user_engines >= 0) {
i915_gem_context_set_user_engines(ctx);
@@ -1652,8 +1666,6 @@ i915_gem_create_context(struct drm_i915_private *i915,
* is no remap info, it will be a NOP. */
ctx->remap_slice = ALL_L3_SLICES(i915);
- ctx->user_flags = pc->user_flags;
-
for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 03bc7f9d191b..b6d97da63d1f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -338,6 +338,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
+#define UCONTEXT_LOW_LATENCY 5
/**
* @flags: small set of booleans
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 7eccbd70d89f..ed95a7b57cbb 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -130,6 +130,7 @@ struct intel_context {
#define CONTEXT_PERMA_PIN 11
Re: [PATCH 5/8] drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state
On Mon, Mar 04, 2024 at 03:30:24PM -0300, Gustavo Sousa wrote:
> CDCLK programming Xe2LPD always selects the CDCLK PLL as source for the
I think something got a bit muddled while rewriting this sentence.
Maybe the first two words were supposed to be dropped?
Otherwise,
Reviewed-by: Matt Roper
> MDCLK. Because of that, the ratio between MDCLK and CDCLK is not be
> constant anymore. As such, make sure to have the current ratio available
> in intel_dbuf_state so that it can be used during dbuf programming.
>
> Note that we write-lock the global state instead of serializing to a
> hardware commit because a change in the ratio should be rather handled
> in the CDCLK change sequence, which will need to take care of updating
> the necessary registers in that case. We will implement that in upcoming
> changes.
>
> That said, changes in the MBus joining state should be handled by the
> DBUF/MBUS logic, just like it is already done, but the logic will need
> to know the ratio to properly update the registers.
>
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 26
> drivers/gpu/drm/i915/display/intel_cdclk.h | 2 ++
> drivers/gpu/drm/i915/display/skl_watermark.c | 18 +-
> drivers/gpu/drm/i915/display/skl_watermark.h | 3 +++
> 4 files changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index cdf3ae766f9e..04a6e9806254 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -39,6 +39,7 @@
> #include "intel_pcode.h"
> #include "intel_psr.h"
> #include "intel_vdsc.h"
> +#include "skl_watermark.h"
> #include "vlv_sideband.h"
>
> /**
> @@ -1891,6 +1892,22 @@ static u32 xe2lpd_mdclk_source_sel(struct
> drm_i915_private *i915)
> return MDCLK_SOURCE_SEL_CD2XCLK;
> }
>
> +u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +const struct intel_cdclk_config *cdclk_config)
> +{
> + u32 source_sel = xe2lpd_mdclk_source_sel(i915);
> +
> + switch (source_sel) {
> + case MDCLK_SOURCE_SEL_CD2XCLK:
> + return 2;
> + case MDCLK_SOURCE_SEL_CDCLK_PLL:
> + return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
> + default:
> + MISSING_CASE(source_sel);
> + return 2;
> + }
> +}
> +
> static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private
> *i915,
> const struct
> intel_cdclk_config *old_cdclk_config,
> const struct
> intel_cdclk_config *new_cdclk_config,
> @@ -3281,6 +3298,15 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
> *state)
> "Modeset required for cdclk change\n");
> }
>
> + if (intel_mdclk_cdclk_ratio(dev_priv, _cdclk_state->actual) !=
> + intel_mdclk_cdclk_ratio(dev_priv, _cdclk_state->actual)) {
> + u8 ratio = intel_mdclk_cdclk_ratio(dev_priv,
> _cdclk_state->actual);
> +
> + ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
> + if (ret)
> + return ret;
> + }
> +
> drm_dbg_kms(_priv->drm,
> "New cdclk calculated to be logical %u kHz, actual %u
> kHz\n",
> new_cdclk_state->logical.cdclk,
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index fa301495e7f1..8e6e302bd599 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -62,6 +62,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
> u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b);
> +u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> +const struct intel_cdclk_config *cdclk_config);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> void intel_cdclk_dump_config(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index d9e49cd60d3a..4410e21888ad 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3057,6 +3057,8 @@ static void skl_wm_get_hw_state(struct drm_i915_private
> *i915)
> if (HAS_MBUS_JOINING(i915))
> dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) &
> MBUS_JOIN;
>
> + dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(i915,
> >display.cdclk.hw);
> +
> for_each_intel_crtc(>drm, crtc) {
>
✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev2)
== Series Details == Series: drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev2) URL : https://patchwork.freedesktop.org/series/130643/ State : warning == Summary == Error: dim checkpatch failed 3a67ec8f2461 drm/i915/dp: Increase idle pattern wait timeout to 2ms -:31: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (16, 16) #31: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3682: + if (intel_de_wait_for_set(dev_priv, [...] + drm_err(_priv->drm, -:32: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #32: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3683: + if (intel_de_wait_for_set(dev_priv, + dp_tp_status_reg(encoder, crtc_state), -:37: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (16, 16) #37: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3688: + if (intel_de_wait_for_set(dev_priv, [...] drm_err(_priv->drm, -:38: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #38: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3689: + if (intel_de_wait_for_set(dev_priv, + dp_tp_status_reg(encoder, crtc_state), total: 0 errors, 2 warnings, 2 checks, 23 lines checked
Re: [PATCH 4/8] drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()
On Mon, Mar 04, 2024 at 03:30:23PM -0300, Gustavo Sousa wrote:
> As of Xe2LPD, it is now possible to select the source of the MDCLK
> as either the CD2XCLK or the CDCLK PLL.
>
> Previous display IPs were hardcoded to use the CD2XCLK. For those, the
> ratio between MDCLK and CDCLK remained constant, namely 2. For Xe2LPD,
> when we select the CDCLK PLL as the source, the ratio will vary
> according to the squashing configuration (since the cd2x divisor is
> fixed for all supported configurations).
>
> To help the transition to supporting changes in the ratio, extract the
> function intel_dbuf_mdclk_cdclk_ratio_update() from the existing logic
> and call it using 2 as hardcoded ratio. Upcoming changes will use that
> function for updates in the ratio due to CDCLK changes.
>
> Bspec: 50057, 69445, 49213, 68868
> Signed-off-by: Gustavo Sousa
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 30 +---
> 1 file changed, 19 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index c6b9be80d83c..d9e49cd60d3a 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3530,6 +3530,21 @@ int intel_dbuf_init(struct drm_i915_private *i915)
> return 0;
> }
>
> +static void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private
> *i915,
> + u8 ratio,
> + bool joined_mbus)
> +{
> + enum dbuf_slice slice;
> +
> + if (joined_mbus)
> + ratio *= 2;
> +
> + for_each_dbuf_slice(i915, slice)
> + intel_de_rmw(i915, DBUF_CTL_S(slice),
> + DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> + DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> +}
> +
> /*
> * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state
> before
> * update the request state of all DBUS slices.
> @@ -3537,8 +3552,7 @@ int intel_dbuf_init(struct drm_i915_private *i915)
> static void update_mbus_pre_enable(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> - u32 mbus_ctl, dbuf_min_tracker_val;
> - enum dbuf_slice slice;
> + u32 mbus_ctl;
> const struct intel_dbuf_state *dbuf_state =
> intel_atomic_get_new_dbuf_state(state);
>
> @@ -3549,24 +3563,18 @@ static void update_mbus_pre_enable(struct
> intel_atomic_state *state)
>* TODO: Implement vblank synchronized MBUS joining changes.
>* Must be properly coordinated with dbuf reprogramming.
>*/
> - if (dbuf_state->joined_mbus) {
> + if (dbuf_state->joined_mbus)
> mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
> MBUS_JOIN_PIPE_SELECT_NONE;
> - dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
> - } else {
> + else
> mbus_ctl = MBUS_HASHING_MODE_2x2 |
> MBUS_JOIN_PIPE_SELECT_NONE;
> - dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
> - }
>
> intel_de_rmw(i915, MBUS_CTL,
>MBUS_HASHING_MODE_MASK | MBUS_JOIN |
>MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
>
> - for_each_dbuf_slice(i915, slice)
> - intel_de_rmw(i915, DBUF_CTL_S(slice),
> - DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> - dbuf_min_tracker_val);
> + intel_dbuf_mdclk_cdclk_ratio_update(i915, 2, dbuf_state->joined_mbus);
> }
>
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> --
> 2.44.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH 3/8] drm/i915/cdclk: Only compute squash waveform when necessary
On Mon, Mar 04, 2024 at 03:30:22PM -0300, Gustavo Sousa wrote:
> It is no use computing the squash waveform if we are not going to use
> it. Move the call to cdclk_squash_waveform() inside the block guarded by
> HAS_CDCLK_SQUASH(dev_priv).
>
> Signed-off-by: Gustavo Sousa
You could also move the 'u32 waveform' declaration from the top of the
function inside the block too to help prevent any future mistakes of
using it unitialized.
Either way,
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index bf84bf27213f..cdf3ae766f9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2023,10 +2023,11 @@ static void _bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> } else
> bxt_cdclk_pll_update(dev_priv, vco);
>
> - waveform = cdclk_squash_waveform(dev_priv, cdclk);
> + if (HAS_CDCLK_SQUASH(dev_priv)) {
> + waveform = cdclk_squash_waveform(dev_priv, cdclk);
>
> - if (HAS_CDCLK_SQUASH(dev_priv))
> dg2_cdclk_squash_program(dev_priv, waveform);
> + }
>
> intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv,
> cdclk_config, pipe));
>
> --
> 2.44.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH 2/8] drm/i915/cdclk: Add and use xe2lpd_mdclk_source_sel()
On Mon, Mar 04, 2024 at 03:30:21PM -0300, Gustavo Sousa wrote:
> There will be future changes that rely on the source of the MDCLK. Let's
> have xe2lpd_mdclk_source_sel() as the function responsible for reporting
> that information.
>
> Bspec: 69090
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 17 -
> drivers/gpu/drm/i915/i915_reg.h| 4 +++-
> 2 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 407bd541eb46..bf84bf27213f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1876,6 +1876,21 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
> return vco == ~0;
> }
>
> +static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
> +{
> + if (DISPLAY_VER(i915) >= 20)
> + return MDCLK_SOURCE_SEL_CDCLK_PLL;
> +
> + /*
> + * Earlier display IPs do not provide means of selecting the
> + * MDCLK source, but MDCLK_SOURCE_SEL_CD2XCLK is a nice default,
> + * since it reflects the source used for those and allows
> + * xe2lpd_mdclk_source_sel() to be used in logic that depends on
> + * it.
> + */
> + return MDCLK_SOURCE_SEL_CD2XCLK;
At the moment this function only gets called on Xe2 and beyond where the
register field exists; if that's going to change soon, then wouldn't it
be more natural to just use an early exit to highlight that there's
nothing we need to OR into the CDCLK_CTL for earlier platforms?
/* Not configurable for older platforms; they always use CD2XCLK */
if (DISPLAY_VER(i915) < 20)
return 0;
Functionally it's the same, but it feels more intuitive to me.
If we aren't expecting to call this from common codepaths that aren't
already protected by a display version check, then we could make this a
drm_WARN_ON() to assert that we haven't deviated from expected behavior.
Matt
> +}
> +
> static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private
> *i915,
> const struct
> intel_cdclk_config *old_cdclk_config,
> const struct
> intel_cdclk_config *new_cdclk_config,
> @@ -1980,7 +1995,7 @@ static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
> val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
>
> if (DISPLAY_VER(i915) >= 20)
> - val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
> + val |= xe2lpd_mdclk_source_sel(i915);
> else
> val |= skl_cdclk_decimal(cdclk);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e00557e1a57f..eb953ed1f113 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5900,7 +5900,9 @@ enum skl_power_gate {
> #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
> #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
> #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
> -#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_BIT(25)
> +#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
> +#define MDCLK_SOURCE_SEL_CD2XCLKREG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
> +#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
> #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
> #define BXT_CDCLK_CD2X_DIV_SEL_1
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
> #define BXT_CDCLK_CD2X_DIV_SEL_1_5
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
> --
> 2.44.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH 1/8] drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_table
On Mon, Mar 04, 2024 at 03:30:20PM -0300, Gustavo Sousa wrote:
> The CDCLK table is tied to Xe2LPD display and not to the platform. Let's
> rename lnl_cdclk_table to xe2lpd_cdclk_table in order to reflect that.
>
> Signed-off-by: Gustavo Sousa
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 22473c55b899..407bd541eb46 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1417,7 +1417,7 @@ static const struct intel_cdclk_vals mtl_cdclk_table[]
> = {
> {}
> };
>
> -static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> +static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = {
> { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0x },
> { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> @@ -3710,7 +3710,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
> {
> if (DISPLAY_VER(dev_priv) >= 20) {
> dev_priv->display.funcs.cdclk = _cdclk_funcs;
> - dev_priv->display.cdclk.table = lnl_cdclk_table;
> + dev_priv->display.cdclk.table = xe2lpd_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) >= 14) {
> dev_priv->display.funcs.cdclk = _cdclk_funcs;
> dev_priv->display.cdclk.table = mtl_cdclk_table;
> --
> 2.44.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH v2] drm/i915/guc: Use context hints for GT freq
On Wed, Feb 28, 2024 at 11:58:06AM -0800, Belgaumkar, Vinay wrote:
>
> On 2/28/2024 4:54 AM, Tvrtko Ursulin wrote:
> >
> > On 27/02/2024 23:51, Vinay Belgaumkar wrote:
> > > Allow user to provide a low latency context hint. When set, KMD
> > > sends a hint to GuC which results in special handling for this
> > > context. SLPC will ramp the GT frequency aggressively every time
> > > it switches to this context. The down freq threshold will also be
> > > lower so GuC will ramp down the GT freq for this context more slowly.
> > > We also disable waitboost for this context as that will interfere with
> > > the strategy.
> > >
> > > We need to enable the use of SLPC Compute strategy during init, but
> > > it will apply only to contexts that set this bit during context
> > > creation.
> > >
> > > Userland can check whether this feature is supported using a new param-
> > > I915_PARAM_HAS_CONTEXT_FREQ_HINTS. This flag is true for all guc
> > > submission
> > > enabled platforms as they use SLPC for frequency management.
> > >
> > > The Mesa usage model for this flag is here -
> > > https://gitlab.freedesktop.org/sushmave/mesa/-/commits/compute_hint
> > >
> > > v2: Rename flags as per review suggestions (Rodrigo, Tvrtko).
> > > Also, use flag bits in intel_context as it allows finer control for
> > > toggling per engine if needed (Tvrtko).
> > >
> > > Cc: Rodrigo Vivi
> > > Cc: Tvrtko Ursulin
> > > Cc: Sushma Venkatesh Reddy
> > > Signed-off-by: Vinay Belgaumkar
> > > ---
> > > drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +++--
> > > .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
> > > drivers/gpu/drm/i915/gt/intel_context_types.h | 1 +
> > > drivers/gpu/drm/i915/gt/intel_rps.c | 5 +
> > > .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 21 +++
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 17 +++
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 1 +
> > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 ++
> > > drivers/gpu/drm/i915/i915_getparam.c | 12 +++
> > > include/uapi/drm/i915_drm.h | 15 +
> > > 10 files changed, 92 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > index dcbfe32fd30c..0799cb0b2803 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > @@ -879,6 +879,7 @@ static int set_proto_ctx_param(struct
> > > drm_i915_file_private *fpriv,
> > > struct i915_gem_proto_context *pc,
> > > struct drm_i915_gem_context_param *args)
> > > {
> > > + struct drm_i915_private *i915 = fpriv->i915;
> > > int ret = 0;
> > > switch (args->param) {
> > > @@ -904,6 +905,13 @@ static int set_proto_ctx_param(struct
> > > drm_i915_file_private *fpriv,
> > > pc->user_flags &= ~BIT(UCONTEXT_BANNABLE);
> > > break;
> > > + case I915_CONTEXT_PARAM_LOW_LATENCY:
> > > + if (intel_uc_uses_guc_submission(_gt(i915)->uc))
> > > + pc->user_flags |= BIT(UCONTEXT_LOW_LATENCY);
> > > + else
> > > + ret = -EINVAL;
> > > + break;
> > > +
> > > case I915_CONTEXT_PARAM_RECOVERABLE:
> > > if (args->size)
> > > ret = -EINVAL;
> > > @@ -992,6 +1000,9 @@ static int intel_context_set_gem(struct
> > > intel_context *ce,
> > > if (sseu.slice_mask && !WARN_ON(ce->engine->class !=
> > > RENDER_CLASS))
> > > ret = intel_context_reconfigure_sseu(ce, sseu);
> > > + if (test_bit(UCONTEXT_LOW_LATENCY, >user_flags))
> > > + set_bit(CONTEXT_LOW_LATENCY, >flags);
> >
> > Does not need to be atomic so can use __set_bit as higher up in the
> > function.
> ok.
> >
> > > +
> > > return ret;
> > > }
> > > @@ -1630,6 +1641,8 @@ i915_gem_create_context(struct
> > > drm_i915_private *i915,
> > > if (vm)
> > > ctx->vm = vm;
> > > + ctx->user_flags = pc->user_flags;
> > > +
> >
> > Given how most ctx->something assignments are at the bottom of the
> > function I would stick a comment here saying along the lines of "assign
> > early for intel_context_set_gem called when creating engines".
> ok.
> >
> > > mutex_init(>engines_mutex);
> > > if (pc->num_user_engines >= 0) {
> > > i915_gem_context_set_user_engines(ctx);
> > > @@ -1652,8 +1665,6 @@ i915_gem_create_context(struct
> > > drm_i915_private *i915,
> > > * is no remap info, it will be a NOP. */
> > > ctx->remap_slice = ALL_L3_SLICES(i915);
> > > - ctx->user_flags = pc->user_flags;
> > > -
> > > for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
> > > ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> > >
[PATCH v6] drm/i915: Show bios vbt when read from firmware/spi/oprom
Make debugfs vbt only shows valid vbt when read from ACPI opregion.
Make it work when read from firmware/spi/pci oprom cases. In the cases
where VBT needs to be read from spi/pci oprom, take the wakeref to
prevent WARN while reading DE registers during debugfs vbt dump.
v2: Extract getting vbt from different sources to its own function.
Protect sysfs write with vbt check(Jani)
v3: Fix CI error by probing bios vbt with runtime_pm wakeref
v4: Update commit message and skip waking up runtime while accessing
vbt from opregion/firmware(Jani)
v5: Skip grabbing unnecessary wakeref(Jani)
Cc: Jani Nikula
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_bios.c | 62 ---
1 file changed, 33 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 44c9dfe86a00..9e1be997a359 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3135,6 +3135,32 @@ static struct vbt_header *oprom_get_vbt(struct
drm_i915_private *i915,
return NULL;
}
+static const struct vbt_header *intel_bios_get_vbt(struct drm_i915_private
*i915,
+ size_t *sizep)
+{
+ const struct vbt_header *vbt = NULL;
+ intel_wakeref_t wakeref;
+
+ vbt = firmware_get_vbt(i915, sizep);
+
+ if (!vbt)
+ vbt = intel_opregion_get_vbt(i915, sizep);
+
+ /*
+* If the OpRegion does not have VBT, look in SPI flash
+* through MMIO or PCI mapping
+*/
+ if (!vbt && IS_DGFX(i915))
+ with_intel_runtime_pm(>runtime_pm, wakeref)
+ vbt = spi_oprom_get_vbt(i915, sizep);
+
+ if (!vbt)
+ with_intel_runtime_pm(>runtime_pm, wakeref)
+ vbt = oprom_get_vbt(i915, sizep);
+
+ return vbt;
+}
+
/**
* intel_bios_init - find VBT and initialize settings from the BIOS
* @i915: i915 device instance
@@ -3146,7 +3172,6 @@ static struct vbt_header *oprom_get_vbt(struct
drm_i915_private *i915,
void intel_bios_init(struct drm_i915_private *i915)
{
const struct vbt_header *vbt;
- struct vbt_header *oprom_vbt = NULL;
const struct bdb_header *bdb;
INIT_LIST_HEAD(>display.vbt.display_devices);
@@ -3160,27 +3185,7 @@ void intel_bios_init(struct drm_i915_private *i915)
init_vbt_defaults(i915);
- oprom_vbt = firmware_get_vbt(i915, NULL);
- vbt = oprom_vbt;
-
- if (!vbt) {
- oprom_vbt = intel_opregion_get_vbt(i915, NULL);
- vbt = oprom_vbt;
- }
-
- /*
-* If the OpRegion does not have VBT, look in SPI flash through MMIO or
-* PCI mapping
-*/
- if (!vbt && IS_DGFX(i915)) {
- oprom_vbt = spi_oprom_get_vbt(i915, NULL);
- vbt = oprom_vbt;
- }
-
- if (!vbt) {
- oprom_vbt = oprom_get_vbt(i915, NULL);
- vbt = oprom_vbt;
- }
+ vbt = intel_bios_get_vbt(i915, NULL);
if (!vbt)
goto out;
@@ -3213,7 +3218,7 @@ void intel_bios_init(struct drm_i915_private *i915)
parse_sdvo_device_mapping(i915);
parse_ddi_ports(i915);
- kfree(oprom_vbt);
+ kfree(vbt);
}
static void intel_bios_init_panel(struct drm_i915_private *i915,
@@ -3743,13 +3748,12 @@ static int intel_bios_vbt_show(struct seq_file *m, void
*unused)
const void *vbt;
size_t vbt_size;
- /*
-* FIXME: VBT might originate from other places than opregion, and then
-* this would be incorrect.
-*/
- vbt = intel_opregion_get_vbt(i915, _size);
- if (vbt)
+ vbt = intel_bios_get_vbt(i915, _size);
+
+ if (vbt) {
seq_write(m, vbt, vbt_size);
+ kfree(vbt);
+ }
return 0;
}
--
2.34.1
Re: [PATCH 7/8] drm/i915/xe2lpd: Load DMC
Quoting Lucas De Marchi (2024-03-04 16:50:49-03:00)
>On Mon, Mar 04, 2024 at 03:30:26PM -0300, Gustavo Sousa wrote:
>>From: Balasubramani Vivekanandan
>>
>>Load DMC for Xe2LPD. The value 0x8000 is the maximum payload size for
>>any Xe2LPD DMC firmware.
>>
>>Signed-off-by: Balasubramani Vivekanandan
>>
>>Signed-off-by: Dnyaneshwar Bhadane
>>Signed-off-by: Gustavo Sousa
>>---
>> drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
>> 1 file changed, 8 insertions(+), 1 deletion(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
>>b/drivers/gpu/drm/i915/display/intel_dmc.c
>>index 835781624482..54c5909de293 100644
>>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>>@@ -89,10 +89,14 @@ static struct intel_dmc *i915_to_dmc(struct
>>drm_i915_private *i915)
>> __stringify(major) "_"\
>> __stringify(minor) ".bin"
>>
>>+#define XE2LPD_MAX_FW_SIZE0x8000
>
> ^ missing DMC_ here to be like the other macros below?
Oh, yeah. That went unnoticed. Thanks!
--
Gustavo
>
>other than that, Reviewed-by: Lucas De Marchi
>
>Lucas De Marchi
>
>> #define XELPDP_DMC_MAX_FW_SIZE0x7000
>> #define DISPLAY_VER13_DMC_MAX_FW_SIZE0x2
>> #define DISPLAY_VER12_DMC_MAX_FW_SIZEICL_DMC_MAX_FW_SIZE
>>
>>+#define XE2LPD_DMC_PATHDMC_PATH(xe2lpd)
>>+MODULE_FIRMWARE(XE2LPD_DMC_PATH);
>>+
>> #define MTL_DMC_PATHDMC_PATH(mtl)
>> MODULE_FIRMWARE(MTL_DMC_PATH);
>>
>>@@ -987,7 +991,10 @@ void intel_dmc_init(struct drm_i915_private *i915)
>>
>> INIT_WORK(>work, dmc_load_work_fn);
>>
>>-if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
>>+if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) {
>>+dmc->fw_path = XE2LPD_DMC_PATH;
>>+dmc->max_fw_size = XE2LPD_MAX_FW_SIZE;
>>+} else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
>> dmc->fw_path = MTL_DMC_PATH;
>> dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
>> } else if (IS_DG2(i915)) {
>>--
>>2.44.0
>>
Re: [PATCH 8/8] drm/xe/lnl: Enable display support
On Mon, Mar 04, 2024 at 03:30:27PM -0300, Gustavo Sousa wrote:
From: Balasubramani Vivekanandan
Enable display support for Lunar Lake.
Signed-off-by: Balasubramani Vivekanandan
Signed-off-by: Lucas De Marchi
Signed-off-by: Gustavo Sousa
Reviewed-by: Lucas De Marchi
No need to merge this through drm-xe. Since we require all the other
patches in this series on the i915 side, let's just make our lives
easier and merge this one through drm-intel.
Lucas De Marchi
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 5b5c29761c5d..42ba2ea62c1e 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -333,6 +333,7 @@ static const struct xe_device_desc mtl_desc = {
static const struct xe_device_desc lnl_desc = {
PLATFORM(XE_LUNARLAKE),
+ .has_display = true,
.require_force_probe = true,
};
--
2.44.0
Re: [PATCH 7/8] drm/i915/xe2lpd: Load DMC
On Mon, Mar 04, 2024 at 03:30:26PM -0300, Gustavo Sousa wrote:
From: Balasubramani Vivekanandan
Load DMC for Xe2LPD. The value 0x8000 is the maximum payload size for
any Xe2LPD DMC firmware.
Signed-off-by: Balasubramani Vivekanandan
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 835781624482..54c5909de293 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -89,10 +89,14 @@ static struct intel_dmc *i915_to_dmc(struct
drm_i915_private *i915)
__stringify(major) "_"\
__stringify(minor) ".bin"
+#define XE2LPD_MAX_FW_SIZE 0x8000
^ missing DMC_ here to be like the other macros below?
other than that, Reviewed-by: Lucas De Marchi
Lucas De Marchi
#define XELPDP_DMC_MAX_FW_SIZE 0x7000
#define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x2
#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define XE2LPD_DMC_PATHDMC_PATH(xe2lpd)
+MODULE_FIRMWARE(XE2LPD_DMC_PATH);
+
#define MTL_DMC_PATHDMC_PATH(mtl)
MODULE_FIRMWARE(MTL_DMC_PATH);
@@ -987,7 +991,10 @@ void intel_dmc_init(struct drm_i915_private *i915)
INIT_WORK(>work, dmc_load_work_fn);
- if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
+ if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) {
+ dmc->fw_path = XE2LPD_DMC_PATH;
+ dmc->max_fw_size = XE2LPD_MAX_FW_SIZE;
+ } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
dmc->fw_path = MTL_DMC_PATH;
dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
} else if (IS_DG2(i915)) {
--
2.44.0
Re: [PATCH v1 0/6] LNL display
Quoting Govindapillai, Vinod (2024-02-22 14:18:53-03:00) >Hi. > > > >On Thu, 2024-02-22 at 13:04 -0300, Gustavo Sousa wrote: >> Hi, guys. >> >> (This is a re-send, because I *think* my MUA badly formed the address to >> the mailing list.) >> >> Quoting Govindapillai, Vinod (2024-02-22 11:39:32-03:00) >> > Hi, >> > >> > Well.. sorry.. I didn't know Gustavo is already working on this! >> > @Gustavo, pls ignore this series if you are arealdy working on this. >> > Please let me know >> >> Yeah. I have a couple of local fixes to apply to those commits, but I'm >> not finished yet. If you are okay with that, I can finish what I've >> already started and send a fresh new series (considering that this >> series has no modifications to what we already have). > >Yes! Please do so! It turns out that I ended up rewriting our logic and, as such, created new patches as a result. Series is available at https://patchwork.freedesktop.org/series/130689/ -- Gustavo Sousa > > >Vinod >> >> -- >> Gustavo Sousa >> >> > >> > On Thu, 2024-02-22 at 08:02 -0600, Lucas De Marchi wrote: >> > > +Gustavo as he was looking at upstreaming these patches. >> > > >> > > Were the issues with mdclk handling pointed out at latest attempt fixed? >> > > From the changelog it doesn't seem so. >> > > >> > > https://lore.kernel.org/all/20230908224303.gx2706...@mdroper-desk1.amr.corp.intel.com/ >> > >> > Yeah.. i did not notice these comments! Lets wait for Gustavo's reply >> > >> > BR >> > vinod >> > >> > > >> > > and also worth taking a look at previous versions: >> > > https://lore.kernel.org/all/?q=s%3A%22Introduce+MDCLK_CDCLK+ratio+to+DBuf%22 >> > > >> > > Lucas De Marchi >> > > >> > > On Thu, Feb 22, 2024 at 02:56:28PM +0200, Vinod Govindapillai wrote: >> > > > Rest of the cdclk patches as well as the patches to enable the display >> > > > in LNL >> > > > >> > > > Balasubramani Vivekanandan (2): >> > > > drm/i915/xe2lpd: Load DMC >> > > > drm/xe/lnl: Enable the display support >> > > > >> > > > Ravi Kumar Vodapalli (1): >> > > > drm/i915/lnl: Add programming for CDCLK change >> > > > >> > > > Stanislav Lisovskiy (3): >> > > > drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf >> > > > drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane >> > > > drm/i915/xe2lpd: Update mbus on post plane updates >> > > > >> > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 74 ++- >> > > > drivers/gpu/drm/i915/display/intel_display.c | 5 +- >> > > > drivers/gpu/drm/i915/display/intel_dmc.c | 9 ++- >> > > > drivers/gpu/drm/i915/display/skl_watermark.c | 35 +++-- >> > > > drivers/gpu/drm/i915/display/skl_watermark.h | 1 + >> > > > .../gpu/drm/i915/display/skl_watermark_regs.h | 2 + >> > > > drivers/gpu/drm/xe/xe_pci.c | 1 + >> > > > 7 files changed, 118 insertions(+), 9 deletions(-) >> > > > >> > > > -- >> > > > 2.34.1 >> > > > >> > >
[PATCH 7/8] drm/i915/xe2lpd: Load DMC
From: Balasubramani Vivekanandan
Load DMC for Xe2LPD. The value 0x8000 is the maximum payload size for
any Xe2LPD DMC firmware.
Signed-off-by: Balasubramani Vivekanandan
Signed-off-by: Dnyaneshwar Bhadane
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 835781624482..54c5909de293 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -89,10 +89,14 @@ static struct intel_dmc *i915_to_dmc(struct
drm_i915_private *i915)
__stringify(major) "_" \
__stringify(minor) ".bin"
+#define XE2LPD_MAX_FW_SIZE 0x8000
#define XELPDP_DMC_MAX_FW_SIZE 0x7000
#define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x2
#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define XE2LPD_DMC_PATHDMC_PATH(xe2lpd)
+MODULE_FIRMWARE(XE2LPD_DMC_PATH);
+
#define MTL_DMC_PATH DMC_PATH(mtl)
MODULE_FIRMWARE(MTL_DMC_PATH);
@@ -987,7 +991,10 @@ void intel_dmc_init(struct drm_i915_private *i915)
INIT_WORK(>work, dmc_load_work_fn);
- if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
+ if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) {
+ dmc->fw_path = XE2LPD_DMC_PATH;
+ dmc->max_fw_size = XE2LPD_MAX_FW_SIZE;
+ } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
dmc->fw_path = MTL_DMC_PATH;
dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
} else if (IS_DG2(i915)) {
--
2.44.0
[PATCH 8/8] drm/xe/lnl: Enable display support
From: Balasubramani Vivekanandan
Enable display support for Lunar Lake.
Signed-off-by: Balasubramani Vivekanandan
Signed-off-by: Lucas De Marchi
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 5b5c29761c5d..42ba2ea62c1e 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -333,6 +333,7 @@ static const struct xe_device_desc mtl_desc = {
static const struct xe_device_desc lnl_desc = {
PLATFORM(XE_LUNARLAKE),
+ .has_display = true,
.require_force_probe = true,
};
--
2.44.0
[PATCH 6/8] drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changes
Commit 394b4b7df9f7 ("drm/i915/lnl: Add CDCLK table") and commit
3d3696c0fed1 ("drm/i915/lnl: Start using CDCLK through PLL") started
adding support for CDCLK programming support for Xe2LPD. One final piece
is missing, which is the programming necessary for changed in the ratio
between MDCLK and CDCLK. Let's do that now.
BSpec instructs us to update MBUS_CTL and DBUF_CTL_S* registers when the
ratio between MDCLK and CDCLK changes. The updates must be done before
changing the CDCLK when decreasing the frequency; or after it when
increasing the frequency.
Ratio-related updates to MBUS_CTL also depend on the state of MBus
joining, so they are performed by either CDCLK change sequence or by
changes in MBus joining. Since one might happen independently of the
other, we need to make sure that both logics see the necessary state
values when programming that register. MBus joining logic needs to know
the MDCLK:CDCLK ratio and that's already provided via mdclk_cdclk_ratio
field of struct intel_dbuf_state.
For the CDCLK logic, we need to have something similar: we need to
propagate the status of MBus joining to struct intel_cdclk_state. Do
that by adding the field joined_mbus to struct intel_cdclk_config.
(Preferably, that field would be added to intel_cdclk_state, however
currently only intel_cdclk_config is passed down to the functions that
do the register programming. We might revisit this decision if we find
that refactoring the code to pass the whole intel_cdclk_state is worth
it.)
Bspec: 68864, 68868, 69090, 69482
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cdclk.c| 31 ++
drivers/gpu/drm/i915/display/intel_cdclk.h| 3 ++
drivers/gpu/drm/i915/display/skl_watermark.c | 40 +++
drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
.../gpu/drm/i915/display/skl_watermark_regs.h | 18 +
5 files changed, 77 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 04a6e9806254..12753589072d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -40,6 +40,7 @@
#include "intel_psr.h"
#include "intel_vdsc.h"
#include "skl_watermark.h"
+#include "skl_watermark_regs.h"
#include "vlv_sideband.h"
/**
@@ -1683,6 +1684,8 @@ static void bxt_get_cdclk(struct drm_i915_private
*dev_priv,
}
out:
+ if (DISPLAY_VER(dev_priv) >= 20)
+ cdclk_config->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) &
MBUS_JOIN;
/*
* Can't read this out :( Let's assume it's
* at least what the CDCLK frequency requires.
@@ -1908,6 +1911,14 @@ u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
}
}
+static void xe2lpd_mdclk_cdclk_ratio_program(struct drm_i915_private *i915,
+const struct intel_cdclk_config
*cdclk_config)
+{
+ intel_dbuf_mdclk_cdclk_ratio_update(i915,
+ intel_mdclk_cdclk_ratio(i915,
cdclk_config),
+ cdclk_config->joined_mbus);
+}
+
static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private
*i915,
const struct
intel_cdclk_config *old_cdclk_config,
const struct
intel_cdclk_config *new_cdclk_config,
@@ -2089,6 +2100,9 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
return;
}
+ if (DISPLAY_VER(dev_priv) >= 20 && cdclk <
dev_priv->display.cdclk.hw.cdclk)
+ xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config);
+
if (cdclk_compute_crawl_and_squash_midpoint(dev_priv,
_priv->display.cdclk.hw,
cdclk_config,
_cdclk_config)) {
_bxt_set_cdclk(dev_priv, _cdclk_config, pipe);
@@ -2097,6 +2111,9 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
_bxt_set_cdclk(dev_priv, cdclk_config, pipe);
}
+ if (DISPLAY_VER(dev_priv) >= 20 && cdclk >
dev_priv->display.cdclk.hw.cdclk)
+ xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config);
+
if (DISPLAY_VER(dev_priv) >= 14)
/*
* NOOP - No Pcode communication needed for
@@ -3179,6 +3196,20 @@ int intel_cdclk_atomic_check(struct intel_atomic_state
*state,
return 0;
}
+int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool
joined_mbus)
+{
+ struct intel_cdclk_state *cdclk_state;
+
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
+
+ cdclk_state->actual.joined_mbus = joined_mbus;
+ cdclk_state->logical.joined_mbus = joined_mbus;
+
+ return intel_atomic_lock_global_state(_state->base);
[PATCH 5/8] drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state
CDCLK programming Xe2LPD always selects the CDCLK PLL as source for the
MDCLK. Because of that, the ratio between MDCLK and CDCLK is not be
constant anymore. As such, make sure to have the current ratio available
in intel_dbuf_state so that it can be used during dbuf programming.
Note that we write-lock the global state instead of serializing to a
hardware commit because a change in the ratio should be rather handled
in the CDCLK change sequence, which will need to take care of updating
the necessary registers in that case. We will implement that in upcoming
changes.
That said, changes in the MBus joining state should be handled by the
DBUF/MBUS logic, just like it is already done, but the logic will need
to know the ratio to properly update the registers.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 26
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 ++
drivers/gpu/drm/i915/display/skl_watermark.c | 18 +-
drivers/gpu/drm/i915/display/skl_watermark.h | 3 +++
4 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cdf3ae766f9e..04a6e9806254 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -39,6 +39,7 @@
#include "intel_pcode.h"
#include "intel_psr.h"
#include "intel_vdsc.h"
+#include "skl_watermark.h"
#include "vlv_sideband.h"
/**
@@ -1891,6 +1892,22 @@ static u32 xe2lpd_mdclk_source_sel(struct
drm_i915_private *i915)
return MDCLK_SOURCE_SEL_CD2XCLK;
}
+u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config)
+{
+ u32 source_sel = xe2lpd_mdclk_source_sel(i915);
+
+ switch (source_sel) {
+ case MDCLK_SOURCE_SEL_CD2XCLK:
+ return 2;
+ case MDCLK_SOURCE_SEL_CDCLK_PLL:
+ return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
+ default:
+ MISSING_CASE(source_sel);
+ return 2;
+ }
+}
+
static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private
*i915,
const struct
intel_cdclk_config *old_cdclk_config,
const struct
intel_cdclk_config *new_cdclk_config,
@@ -3281,6 +3298,15 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
"Modeset required for cdclk change\n");
}
+ if (intel_mdclk_cdclk_ratio(dev_priv, _cdclk_state->actual) !=
+ intel_mdclk_cdclk_ratio(dev_priv, _cdclk_state->actual)) {
+ u8 ratio = intel_mdclk_cdclk_ratio(dev_priv,
_cdclk_state->actual);
+
+ ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
+ if (ret)
+ return ret;
+ }
+
drm_dbg_kms(_priv->drm,
"New cdclk calculated to be logical %u kHz, actual %u
kHz\n",
new_cdclk_state->logical.cdclk,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
b/drivers/gpu/drm/i915/display/intel_cdclk.h
index fa301495e7f1..8e6e302bd599 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -62,6 +62,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b);
+u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config);
void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
void intel_cdclk_dump_config(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index d9e49cd60d3a..4410e21888ad 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3057,6 +3057,8 @@ static void skl_wm_get_hw_state(struct drm_i915_private
*i915)
if (HAS_MBUS_JOINING(i915))
dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) &
MBUS_JOIN;
+ dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(i915,
>display.cdclk.hw);
+
for_each_intel_crtc(>drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -3530,6 +3532,19 @@ int intel_dbuf_init(struct drm_i915_private *i915)
return 0;
}
+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
u8 ratio)
+{
+ struct intel_dbuf_state *dbuf_state;
+
+ dbuf_state =
[PATCH 4/8] drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()
As of Xe2LPD, it is now possible to select the source of the MDCLK
as either the CD2XCLK or the CDCLK PLL.
Previous display IPs were hardcoded to use the CD2XCLK. For those, the
ratio between MDCLK and CDCLK remained constant, namely 2. For Xe2LPD,
when we select the CDCLK PLL as the source, the ratio will vary
according to the squashing configuration (since the cd2x divisor is
fixed for all supported configurations).
To help the transition to supporting changes in the ratio, extract the
function intel_dbuf_mdclk_cdclk_ratio_update() from the existing logic
and call it using 2 as hardcoded ratio. Upcoming changes will use that
function for updates in the ratio due to CDCLK changes.
Bspec: 50057, 69445, 49213, 68868
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/skl_watermark.c | 30 +---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index c6b9be80d83c..d9e49cd60d3a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3530,6 +3530,21 @@ int intel_dbuf_init(struct drm_i915_private *i915)
return 0;
}
+static void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
+ u8 ratio,
+ bool joined_mbus)
+{
+ enum dbuf_slice slice;
+
+ if (joined_mbus)
+ ratio *= 2;
+
+ for_each_dbuf_slice(i915, slice)
+ intel_de_rmw(i915, DBUF_CTL_S(slice),
+DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
+}
+
/*
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state
before
* update the request state of all DBUS slices.
@@ -3537,8 +3552,7 @@ int intel_dbuf_init(struct drm_i915_private *i915)
static void update_mbus_pre_enable(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
- u32 mbus_ctl, dbuf_min_tracker_val;
- enum dbuf_slice slice;
+ u32 mbus_ctl;
const struct intel_dbuf_state *dbuf_state =
intel_atomic_get_new_dbuf_state(state);
@@ -3549,24 +3563,18 @@ static void update_mbus_pre_enable(struct
intel_atomic_state *state)
* TODO: Implement vblank synchronized MBUS joining changes.
* Must be properly coordinated with dbuf reprogramming.
*/
- if (dbuf_state->joined_mbus) {
+ if (dbuf_state->joined_mbus)
mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_NONE;
- dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
- } else {
+ else
mbus_ctl = MBUS_HASHING_MODE_2x2 |
MBUS_JOIN_PIPE_SELECT_NONE;
- dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
- }
intel_de_rmw(i915, MBUS_CTL,
MBUS_HASHING_MODE_MASK | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
- for_each_dbuf_slice(i915, slice)
- intel_de_rmw(i915, DBUF_CTL_S(slice),
-DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
-dbuf_min_tracker_val);
+ intel_dbuf_mdclk_cdclk_ratio_update(i915, 2, dbuf_state->joined_mbus);
}
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
--
2.44.0
[PATCH 3/8] drm/i915/cdclk: Only compute squash waveform when necessary
It is no use computing the squash waveform if we are not going to use
it. Move the call to cdclk_squash_waveform() inside the block guarded by
HAS_CDCLK_SQUASH(dev_priv).
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index bf84bf27213f..cdf3ae766f9e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2023,10 +2023,11 @@ static void _bxt_set_cdclk(struct drm_i915_private
*dev_priv,
} else
bxt_cdclk_pll_update(dev_priv, vco);
- waveform = cdclk_squash_waveform(dev_priv, cdclk);
+ if (HAS_CDCLK_SQUASH(dev_priv)) {
+ waveform = cdclk_squash_waveform(dev_priv, cdclk);
- if (HAS_CDCLK_SQUASH(dev_priv))
dg2_cdclk_squash_program(dev_priv, waveform);
+ }
intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv,
cdclk_config, pipe));
--
2.44.0
[PATCH 2/8] drm/i915/cdclk: Add and use xe2lpd_mdclk_source_sel()
There will be future changes that rely on the source of the MDCLK. Let's
have xe2lpd_mdclk_source_sel() as the function responsible for reporting
that information.
Bspec: 69090
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 17 -
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 407bd541eb46..bf84bf27213f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1876,6 +1876,21 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
return vco == ~0;
}
+static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
+{
+ if (DISPLAY_VER(i915) >= 20)
+ return MDCLK_SOURCE_SEL_CDCLK_PLL;
+
+ /*
+* Earlier display IPs do not provide means of selecting the
+* MDCLK source, but MDCLK_SOURCE_SEL_CD2XCLK is a nice default,
+* since it reflects the source used for those and allows
+* xe2lpd_mdclk_source_sel() to be used in logic that depends on
+* it.
+*/
+ return MDCLK_SOURCE_SEL_CD2XCLK;
+}
+
static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private
*i915,
const struct
intel_cdclk_config *old_cdclk_config,
const struct
intel_cdclk_config *new_cdclk_config,
@@ -1980,7 +1995,7 @@ static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
if (DISPLAY_VER(i915) >= 20)
- val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
+ val |= xe2lpd_mdclk_source_sel(i915);
else
val |= skl_cdclk_decimal(cdclk);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e00557e1a57f..eb953ed1f113 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5900,7 +5900,9 @@ enum skl_power_gate {
#define CDCLK_FREQ_540REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
#define CDCLK_FREQ_337_308REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
#define CDCLK_FREQ_675_617REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
-#define MDCLK_SOURCE_SEL_CDCLK_PLLREG_BIT(25)
+#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
+#define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
+#define MDCLK_SOURCE_SEL_CDCLK_PLLREG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
#define BXT_CDCLK_CD2X_DIV_SEL_1
REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
#define BXT_CDCLK_CD2X_DIV_SEL_1_5
REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
--
2.44.0
[PATCH 1/8] drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_table
The CDCLK table is tied to Xe2LPD display and not to the platform. Let's
rename lnl_cdclk_table to xe2lpd_cdclk_table in order to reflect that.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 22473c55b899..407bd541eb46 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1417,7 +1417,7 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
{}
};
-static const struct intel_cdclk_vals lnl_cdclk_table[] = {
+static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = {
{ .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0x },
{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
@@ -3710,7 +3710,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 20) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
- dev_priv->display.cdclk.table = lnl_cdclk_table;
+ dev_priv->display.cdclk.table = xe2lpd_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 14) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
--
2.44.0
[PATCH 0/8] Enable LNL display
This series aims at providing the remaining patches for enabling display on Lunar Lake, which used Xe2LPD display IP. The first set of patches contains fixes and extra stuff required for supporting CDCLK on Xe2LPD: drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_table drm/i915/cdclk: Add and use xe2lpd_mdclk_source_sel() drm/i915/cdclk: Only compute squash waveform when necessary drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update() drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changes Then we have a single patch that enables loading Xe2LPD DMC, which is already available in linux-firmware: drm/i915/xe2lpd: Load DMC Finally, we have the last patch, which enables display for LNL: drm/xe/lnl: Enable display support I believe this last one is supposed to be merged via drm-xe-next. -- Gustavo Sousa Balasubramani Vivekanandan (2): drm/i915/xe2lpd: Load DMC drm/xe/lnl: Enable display support Gustavo Sousa (6): drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_table drm/i915/cdclk: Add and use xe2lpd_mdclk_source_sel() drm/i915/cdclk: Only compute squash waveform when necessary drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update() drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changes drivers/gpu/drm/i915/display/intel_cdclk.c| 83 +-- drivers/gpu/drm/i915/display/intel_cdclk.h| 5 ++ drivers/gpu/drm/i915/display/intel_dmc.c | 9 +- drivers/gpu/drm/i915/display/skl_watermark.c | 74 ++--- drivers/gpu/drm/i915/display/skl_watermark.h | 4 + .../gpu/drm/i915/display/skl_watermark_regs.h | 18 ++-- drivers/gpu/drm/i915/i915_reg.h | 4 +- drivers/gpu/drm/xe/xe_pci.c | 1 + 8 files changed, 170 insertions(+), 28 deletions(-) -- 2.44.0
Re: [RFC 2/3] drm/i915/alpm: Add compute config for lobf
On Mon, 04 Mar 2024, Animesh Manna wrote:
> Link Off Between Active Frames, is a new feature for eDP
> that allows the panel to go to lower power state after
> transmission of data. This is a feature on top of ALPM, AS SDP.
> Add compute config during atomic-check phase.
>
> Signed-off-by: Animesh Manna
> ---
> .../drm/i915/display/intel_display_types.h| 3 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 45 +++
> drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> 4 files changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d473d8dca90a..4d2161eeb686 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1851,6 +1851,9 @@ struct intel_dp {
> u8 silence_period_sym_clocks;
> u8 lfps_half_cycle_num_of_syms;
> } alpm_parameters;
> +
> + /* LOBF flags*/
> + bool lobf_supported;
> };
>
> enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8304ef912767..e34b70d88b9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2979,6 +2979,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> intel_vrr_compute_config(pipe_config, conn_state);
> intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
> intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> + intel_psr_lobf_compute_config(intel_dp, pipe_config, conn_state);
> intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
> intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config,
> conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4adcddba69c1..c08bffc2921a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -436,6 +436,16 @@ static bool intel_dp_get_alpm_status(struct intel_dp
> *intel_dp)
> return alpm_caps & DP_ALPM_CAP;
> }
>
> +static bool intel_dp_get_aux_less_alpm_status(struct intel_dp *intel_dp)
> +{
> + u8 alpm_caps = 0;
> +
> + if (drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP,
> + _caps) != 1)
The compute config path must not access the hardware.
BR,
Jani.
> + return false;
> + return alpm_caps & DP_ALPM_AUX_LESS_CAP;
> +}
> +
> static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> @@ -1569,6 +1579,41 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> }
>
> +void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
> +struct intel_crtc_state *crtc_state,
> +struct drm_connector_state *conn_state)
> +{
> + struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
> + int waketime_in_lines, first_sdp_position;
> + int context_latency, guardband;
> + bool auxless_alpm;
> +
> + intel_dp->lobf_supported = false;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + if (!intel_dp_as_sdp_supported(intel_dp))
> + return;
> +
> + if (CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))
> + return;
> +
> + if (_compute_alpm_params(intel_dp, crtc_state)) {
> + context_latency = adjusted_mode->crtc_vblank_start -
> adjusted_mode->crtc_vdisplay;
> + guardband = adjusted_mode->crtc_vtotal -
> adjusted_mode->crtc_vdisplay - context_latency;
> + first_sdp_position = adjusted_mode->crtc_vtotal -
> adjusted_mode->crtc_vsync_start;
> + auxless_alpm = intel_dp_get_aux_less_alpm_status(intel_dp);
> + if (auxless_alpm)
> + waketime_in_lines =
> intel_dp->alpm_parameters.io_wake_lines;
> + else
> + waketime_in_lines =
> intel_dp->alpm_parameters.aux_less_wake_lines;
> +
> + if ((context_latency + guardband) > (first_sdp_position +
> waketime_in_lines))
> + intel_dp->lobf_supported = true;
> + }
> +}
> +
> void intel_psr_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index cde781df84d5..4bb77295288f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -40,6 +40,9 @@ void intel_psr_init(struct intel_dp
Re: [PATCH v8 3/3] drm/buddy: Add user for defragmentation
Am 04.03.24 um 17:32 schrieb Arunpravin Paneer Selvam:
Add amdgpu driver as user for the drm buddy
defragmentation.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 17 +++--
drivers/gpu/drm/drm_buddy.c | 1 +
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index e494f5bf136a..cff8a526c622 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -533,8 +533,21 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
min_block_size,
>blocks,
vres->flags);
- if (unlikely(r))
- goto error_free_blocks;
+ if (unlikely(r)) {
+ if (r == -ENOSPC) {
+ drm_buddy_defrag(mm, min_block_size);
+ r = drm_buddy_alloc_blocks(mm, fpfn,
+ lpfn,
+ size,
+ min_block_size,
+ >blocks,
+ vres->flags);
That doesn't looks like something we should do.
We might fallback when contiguous memory is requested, but certainly not
on normal allocation failure.
Regards,
Christian.
+ if (unlikely(r))
+ goto error_free_blocks;
+ } else {
+ goto error_free_blocks;
+ }
+ }
if (size > remaining_size)
remaining_size = 0;
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 40131ed9b0cd..19440f8caec0 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -396,6 +396,7 @@ void drm_buddy_defrag(struct drm_buddy *mm,
}
}
}
+EXPORT_SYMBOL(drm_buddy_defrag);
/**
* drm_buddy_free_block - free a block
[PATCH v8 3/3] drm/buddy: Add user for defragmentation
Add amdgpu driver as user for the drm buddy
defragmentation.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 17 +++--
drivers/gpu/drm/drm_buddy.c | 1 +
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index e494f5bf136a..cff8a526c622 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -533,8 +533,21 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
min_block_size,
>blocks,
vres->flags);
- if (unlikely(r))
- goto error_free_blocks;
+ if (unlikely(r)) {
+ if (r == -ENOSPC) {
+ drm_buddy_defrag(mm, min_block_size);
+ r = drm_buddy_alloc_blocks(mm, fpfn,
+ lpfn,
+ size,
+ min_block_size,
+ >blocks,
+ vres->flags);
+ if (unlikely(r))
+ goto error_free_blocks;
+ } else {
+ goto error_free_blocks;
+ }
+ }
if (size > remaining_size)
remaining_size = 0;
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 40131ed9b0cd..19440f8caec0 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -396,6 +396,7 @@ void drm_buddy_defrag(struct drm_buddy *mm,
}
}
}
+EXPORT_SYMBOL(drm_buddy_defrag);
/**
* drm_buddy_free_block - free a block
--
2.25.1
[PATCH v8 2/3] drm/amdgpu: Enable clear page functionality
Add clear page support in vram memory region.
v1(Christian):
- Dont handle clear page as TTM flag since when moving the BO back
in from GTT again we don't need that.
- Make a specialized version of amdgpu_fill_buffer() which only
clears the VRAM areas which are not already cleared
- Drop the TTM_PL_FLAG_WIPE_ON_RELEASE check in
amdgpu_object.c
v2:
- Modify the function name amdgpu_ttm_* (Alex)
- Drop the delayed parameter (Christian)
- handle amdgpu_res_cleared() just above the size
calculation (Christian)
- Use AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE for clearing the buffers
in the free path to properly wait for fences etc.. (Christian)
v3(Christian):
- Remove buffer clear code in VRAM manager instead change the
AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE handling to set
the DRM_BUDDY_CLEARED flag.
- Remove ! from amdgpu_res_cleared() check.
Signed-off-by: Arunpravin Paneer Selvam
Suggested-by: Christian König
Acked-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 22 ---
.../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h| 25
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 61 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 5 ++
6 files changed, 111 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 8bc79924d171..c92d92b28a57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -39,6 +39,7 @@
#include "amdgpu.h"
#include "amdgpu_trace.h"
#include "amdgpu_amdkfd.h"
+#include "amdgpu_vram_mgr.h"
/**
* DOC: amdgpu_object
@@ -601,8 +602,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
if (!amdgpu_bo_support_uswc(bo->flags))
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- if (adev->ras_enabled)
- bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
+ bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
bo->tbo.bdev = >mman.bdev;
if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
@@ -632,15 +632,17 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
bo->tbo.resource->mem_type == TTM_PL_VRAM) {
- struct dma_fence *fence;
+ struct dma_fence *fence = NULL;
- r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, , true);
+ r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, );
if (unlikely(r))
goto fail_unreserve;
- dma_resv_add_fence(bo->tbo.base.resv, fence,
- DMA_RESV_USAGE_KERNEL);
- dma_fence_put(fence);
+ if (fence) {
+ dma_resv_add_fence(bo->tbo.base.resv, fence,
+ DMA_RESV_USAGE_KERNEL);
+ dma_fence_put(fence);
+ }
}
if (!bp->resv)
amdgpu_bo_unreserve(bo);
@@ -1365,8 +1367,12 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object
*bo)
if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
return;
- r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, , true);
+ r = amdgpu_fill_buffer(abo, 0, bo->base.resv, , true);
if (!WARN_ON(r)) {
+ struct amdgpu_vram_mgr_resource *vres;
+
+ vres = to_amdgpu_vram_mgr_resource(bo->resource);
+ vres->flags |= DRM_BUDDY_CLEARED;
amdgpu_bo_fence(abo, fence, false);
dma_fence_put(fence);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index 381101d2bf05..50fcd86e1033 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -164,4 +164,29 @@ static inline void amdgpu_res_next(struct
amdgpu_res_cursor *cur, uint64_t size)
}
}
+/**
+ * amdgpu_res_cleared - check if blocks are cleared
+ *
+ * @cur: the cursor to extract the block
+ *
+ * Check if the @cur block is cleared
+ */
+static inline bool amdgpu_res_cleared(struct amdgpu_res_cursor *cur)
+{
+ struct drm_buddy_block *block;
+
+ switch (cur->mem_type) {
+ case TTM_PL_VRAM:
+ block = cur->node;
+
+ if (!amdgpu_vram_mgr_is_cleared(block))
+ return false;
+ break;
+ default:
+ return false;
+ }
+
+ return true;
+}
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 8722beba494e..bcbffe909b47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++
[PATCH v8 1/3] drm/buddy: Implement tracking clear page feature
- Add tracking clear page feature.
- Driver should enable the DRM_BUDDY_CLEARED flag if it
successfully clears the blocks in the free path. On the otherhand,
DRM buddy marks each block as cleared.
- Track the available cleared pages size
- If driver requests cleared memory we prefer cleared memory
but fallback to uncleared if we can't find the cleared blocks.
when driver requests uncleared memory we try to use uncleared but
fallback to cleared memory if necessary.
- When a block gets freed we clear it and mark the freed block as cleared,
when there are buddies which are cleared as well we can merge them.
Otherwise, we prefer to keep the blocks as separated.
- Add a function to support defragmentation.
v1:
- Depends on the flag check DRM_BUDDY_CLEARED, enable the block as
cleared. Else, reset the clear flag for each block in the list(Christian)
- For merging the 2 cleared blocks compare as below,
drm_buddy_is_clear(block) != drm_buddy_is_clear(buddy)(Christian)
- Defragment the memory beginning from min_order
till the required memory space is available.
v2: (Matthew)
- Add a wrapper drm_buddy_free_list_internal for the freeing of blocks
operation within drm buddy.
- Write a macro block_incompatible() to allocate the required blocks.
- Update the xe driver for the drm_buddy_free_list change in arguments.
- add a warning if the two blocks are incompatible on
defragmentation
- call full defragmentation in the fini() function
- place a condition to test if min_order is equal to 0
- replace the list with safe_reverse() variant as we might
remove the block from the list.
v3:
- fix Gitlab user reported lockup issue.
- Keep DRM_BUDDY_HEADER_CLEAR define sorted(Matthew)
- modify to pass the root order instead max_order in fini()
function(Matthew)
- change bool 1 to true(Matthew)
- add check if min_block_size is power of 2(Matthew)
- modify the min_block_size datatype to u64(Matthew)
Signed-off-by: Arunpravin Paneer Selvam
Signed-off-by: Matthew Auld
Suggested-by: Christian König
Suggested-by: Matthew Auld
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 6 +-
drivers/gpu/drm/drm_buddy.c | 294 +++---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 6 +-
drivers/gpu/drm/tests/drm_buddy_test.c| 18 +-
drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 4 +-
include/drm/drm_buddy.h | 22 +-
6 files changed, 290 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 8db880244324..c0c851409241 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -571,7 +571,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
return 0;
error_free_blocks:
- drm_buddy_free_list(mm, >blocks);
+ drm_buddy_free_list(mm, >blocks, 0);
mutex_unlock(>lock);
error_fini:
ttm_resource_fini(man, >base);
@@ -604,7 +604,7 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager
*man,
amdgpu_vram_mgr_do_reserve(man);
- drm_buddy_free_list(mm, >blocks);
+ drm_buddy_free_list(mm, >blocks, 0);
mutex_unlock(>lock);
atomic64_sub(vis_usage, >vis_usage);
@@ -912,7 +912,7 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev)
kfree(rsv);
list_for_each_entry_safe(rsv, temp, >reserved_pages, blocks) {
- drm_buddy_free_list(>mm, >allocated);
+ drm_buddy_free_list(>mm, >allocated, 0);
kfree(rsv);
}
if (!adev->gmc.is_app_apu)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index c4222b886db7..40131ed9b0cd 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -57,6 +57,16 @@ static void list_insert_sorted(struct drm_buddy *mm,
__list_add(>link, node->link.prev, >link);
}
+static void clear_reset(struct drm_buddy_block *block)
+{
+ block->header &= ~DRM_BUDDY_HEADER_CLEAR;
+}
+
+static void mark_cleared(struct drm_buddy_block *block)
+{
+ block->header |= DRM_BUDDY_HEADER_CLEAR;
+}
+
static void mark_allocated(struct drm_buddy_block *block)
{
block->header &= ~DRM_BUDDY_HEADER_STATE;
@@ -186,11 +196,21 @@ EXPORT_SYMBOL(drm_buddy_init);
*/
void drm_buddy_fini(struct drm_buddy *mm)
{
+ u64 root_size, size;
+ unsigned int order;
int i;
+ size = mm->size;
+
for (i = 0; i < mm->n_roots; ++i) {
+ order = ilog2(size) - ilog2(mm->chunk_size);
+ root_size = mm->chunk_size << order;
+ drm_buddy_defrag(mm, root_size);
+
WARN_ON(!drm_buddy_block_is_free(mm->roots[i]));
drm_block_free(mm, mm->roots[i]);
+
+ size -= root_size;
}
WARN_ON(mm->avail != mm->size);
@@ -223,6
[PULL] drm-xe-next-fixes
Hi Dave and Sima, A few xe fixes for 6.9. drm-xe-next-fixes-2024-03-04: Driver Changes: - Fix kunit link failure with built-in xe - Fix one more 32-bit build failure with ARM compiler - Fix initialization order of topology struct - Cleanup unused fields in struct xe_vm - Fix xe_vm leak when handling page fault on a VM not in fault mode - Drop use of "grouped target" feature in Makefile since that's only available in make >= 4.3 thanks, Lucas De Marchi The following changes since commit c6d6a82d8a9f8f9326b760accaa532b839b80140: Merge tag 'drm-misc-next-fixes-2024-02-29' of https://anongit.freedesktop.org/git/drm/drm-misc into drm-next (2024-03-01 19:38:13 +1000) are available in the Git repository at: ssh://g...@gitlab.freedesktop.org/drm/xe/kernel.git tags/drm-xe-next-fixes-2024-03-04 for you to fetch changes up to e62d2e00780b4a465c77d2229837495fcbc480d3: drm/xe: Replace 'grouped target' in Makefile with pattern rule (2024-03-04 08:41:28 -0600) Driver Changes: - Fix kunit link failure with built-in xe - Fix one more 32-bit build failure with ARM compiler - Fix initialization order of topology struct - Cleanup unused fields in struct xe_vm - Fix xe_vm leak when handling page fault on a VM not in fault mode - Drop use of "grouped target" feature in Makefile since that's only available in make >= 4.3 Arnd Bergmann (2): drm/xe/kunit: fix link failure with built-in xe drm/xe/xe2: fix 64-bit division in pte_update_size Dafna Hirschfeld (1): drm/xe: Replace 'grouped target' in Makefile with pattern rule Matthew Brost (1): drm/xe: Fix ref counting leak on page fault Mika Kuoppala (1): drm/xe: Remove obsolete async_ops from struct xe_vm Zhanjun Dong (1): drm/xe/guc: Fix missing topology init drivers/gpu/drm/xe/Kconfig | 1 + drivers/gpu/drm/xe/Kconfig.debug | 1 - drivers/gpu/drm/xe/Makefile | 9 ++--- drivers/gpu/drm/xe/xe_gt.c | 3 +-- drivers/gpu/drm/xe/xe_gt_pagefault.c | 6 -- drivers/gpu/drm/xe/xe_migrate.c | 2 +- drivers/gpu/drm/xe/xe_vm_types.h | 24 7 files changed, 13 insertions(+), 33 deletions(-)
Re: [PATCH 1/4] drm/i915/hdcp: Move intel_hdcp_gsc_message def away from header file
On Tue, 27 Feb 2024, Suraj Kandpal wrote:
> Move intel_hdcp_gsc_message definition into intel_hdcp_gsc.h
> so that intel_hdcp_gsc_message can be redefined for xe as needed.
>
> --v2
> -Correct commit message to reflect what patch is actually doing [Arun]
>
> Signed-off-by: Suraj Kandpal
Acked-by: Jani Nikula
for merging this patch via drm-xe-next.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 6 ++
> drivers/gpu/drm/i915/display/intel_hdcp_gsc.h | 7 +--
> 2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
> b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
> index 302bff75b06c..35823e1f65d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
> @@ -13,6 +13,12 @@
> #include "intel_hdcp_gsc.h"
> #include "intel_hdcp_gsc_message.h"
>
> +struct intel_hdcp_gsc_message {
> + struct i915_vma *vma;
> + void *hdcp_cmd_in;
> + void *hdcp_cmd_out;
> +};
> +
> bool intel_hdcp_gsc_cs_required(struct drm_i915_private *i915)
> {
> return DISPLAY_VER(i915) >= 14;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
> b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
> index eba2057c5a9e..5f610df61cc9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
> @@ -10,12 +10,7 @@
> #include
>
> struct drm_i915_private;
> -
> -struct intel_hdcp_gsc_message {
> - struct i915_vma *vma;
> - void *hdcp_cmd_in;
> - void *hdcp_cmd_out;
> -};
> +struct intel_hdcp_gsc_message;
>
> bool intel_hdcp_gsc_cs_required(struct drm_i915_private *i915);
> ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in,
--
Jani Nikula, Intel
Re: [PATCH v6 1/3] drm/i915/vma: Fix UAF on destroy against retire race
On 3/1/2024 8:29 AM, Janusz Krzysztofik wrote:
Object debugging tools were sporadically reporting illegal attempts to
free a still active i915 VMA object when parking a GT believed to be idle.
[161.359441] ODEBUG: free active (active state 0) object: 88811643b958
object type: i915_active hint: __i915_vma_active+0x0/0x50 [i915]
[161.360082] WARNING: CPU: 5 PID: 276 at lib/debugobjects.c:514
debug_print_object+0x80/0xb0
...
[161.360304] CPU: 5 PID: 276 Comm: kworker/5:2 Not tainted
6.5.0-rc1-CI_DRM_13375-g003f860e5577+ #1
[161.360314] Hardware name: Intel Corporation Rocket Lake Client
Platform/RocketLake S UDIMM 6L RVP, BIOS RKLSFWI1.R00.3173.A03.2204210138
04/21/2022
[161.360322] Workqueue: i915-unordered __intel_wakeref_put_work [i915]
[161.360592] RIP: 0010:debug_print_object+0x80/0xb0
...
[161.361347] debug_object_free+0xeb/0x110
[161.361362] i915_active_fini+0x14/0x130 [i915]
[161.361866] release_references+0xfe/0x1f0 [i915]
[161.362543] i915_vma_parked+0x1db/0x380 [i915]
[161.363129] __gt_park+0x121/0x230 [i915]
[161.363515] intel_wakeref_put_last+0x1f/0x70 [i915]
That has been tracked down to be happening when another thread is
deactivating the VMA inside __active_retire() helper, after the VMA's
active counter has been already decremented to 0, but before deactivation
of the VMA's object is reported to the object debugging tool.
We could prevent from that race by serializing i915_active_fini() with
__active_retire() via ref->tree_lock, but that wouldn't stop the VMA from
being used, e.g. from __i915_vma_retire() called at the end of
__active_retire(), after that VMA has been already freed by a concurrent
i915_vma_destroy() on return from the i915_active_fini(). Then, we should
rather fix the issue at the VMA level, not in i915_active.
Since __i915_vma_parked() is called from __gt_park() on last put of the
GT's wakeref, the issue could be addressed by holding the GT wakeref long
enough for __active_retire() to complete before that wakeref is released
and the GT parked.
I believe the issue was introduced by commit d93939730347 ("drm/i915:
Remove the vma refcount") which moved a call to i915_active_fini() from
a dropped i915_vma_release(), called on last put of the removed VMA kref,
to i915_vma_parked() processing path called on last put of a GT wakeref.
However, its visibility to the object debugging tool was suppressed by a
bug in i915_active that was fixed two weeks later with commit e92eb246feb9
("drm/i915/active: Fix missing debug object activation").
A VMA associated with a request doesn't acquire a GT wakeref by itself.
Instead, it depends on a wakeref held directly by the request's active
intel_context for a GT associated with its VM, and indirectly on that
intel_context's engine wakeref if the engine belongs to the same GT as the
VMA's VM. Those wakerefs are released asynchronously to VMA deactivation.
Fix the issue by getting a wakeref for the VMA's GT when activating it,
and putting that wakeref only after the VMA is deactivated. However,
exclude global GTT from that processing path, otherwise the GPU never goes
idle. Since __i915_vma_retire() may be called from atomic contexts, use
async variant of wakeref put. Also, to avoid circular locking dependency,
take care of acquiring the wakeref before VM mutex when both are needed.
v6: Since __i915_vma_active/retire() callbacks are not serialized, storing
a wakeref tracking handle inside struct i915_vma is not safe, and
there is no other good place for that. Use untracked variants of
intel_gt_pm_get/put_async().
v5: Replace "tile" with "GT" across commit description (Rodrigo),
- avoid mentioning multi-GT case in commit description (Rodrigo),
- explain why we need to take a temporary wakeref unconditionally inside
i915_vma_pin_ww() (Rodrigo).
v4: Refresh on top of commit 5e4e06e4087e ("drm/i915: Track gt pm
wakerefs") (Andi),
- for more easy backporting, split out removal of former insufficient
workarounds and move them to separate patches (Nirmoy).
- clean up commit message and description a bit.
v3: Identify root cause more precisely, and a commit to blame,
- identify and drop former workarounds,
- update commit message and description.
v2: Get the wakeref before VM mutex to avoid circular locking dependency,
- drop questionable Fixes: tag.
Fixes: d93939730347 ("drm/i915: Remove the vma refcount")
Closes: https://gitlab.freedesktop.org/drm/intel/issues/8875
Signed-off-by: Janusz Krzysztofik
Cc: Thomas Hellström
Cc: Nirmoy Das
Cc: Andi Shyti
Cc: Rodrigo Vivi
Cc: sta...@vger.kernel.org # v5.19+
---
drivers/gpu/drm/i915/i915_vma.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index d09aad34ba37f..ffe81fe338f7e 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -34,6 +34,7 @@
#include "gt/intel_engine.h"
RE: Regression on linux-next (next-20240228)
Hello Mathew,
> -Original Message-
> From: Matthew Wilcox
> Sent: Monday, March 4, 2024 6:52 PM
> To: Borah, Chaitanya Kumar
> Cc: intel-gfx@lists.freedesktop.org; Kurmi, Suresh Kumar
> ; Saarinen, Jani
> Subject: Re: Regression on linux-next (next-20240228)
>
> On Mon, Mar 04, 2024 at 10:03:13AM +, Borah, Chaitanya Kumar
> wrote:
> > > Could you try putting the two:
> > >
> > > - list_del(>lru);
> > >
> > > statements back in and see if that fixes it?
> >
> > That seems to fix it.
> >
> > if (!folio_put_testzero(folio))
> > + list_del(>lru);
> > continue;
>
> Ummm ... did you put { and } around this? Otherwise the indentation is
> misleading and what you're actually done is:
>
> if (!folio_put_testzero(folio))
> list_del(>lru);
> continue;
>
> which will simply leak memory.
>
Oops look like a miss on our side. Let us re-do this and get back to you.
Regards
Chaitanya
> > if (folio_test_large(folio)) {
> > __folio_put_large(folio);
> > + list_del(>lru);
> > continue;
> > }
> > Regards
> >
> > Chaitanya
RE: [RFC 0/5] Introduce drm sharpening property
On Monday, March 4th, 2024 at 15:04, Garg, Nemesa wrote: > This is generic as sharpness effect is applied post blending. Depending > on the color gamut, pixel format and other inputs the image gets > blended and once we get blended output it can be sharpened based on > strength value provided by the user. It would really help if you could provide the exact mathematical formula applied by this KMS property.
Re: GuC issue
Michał has helped me a lot - no action is required! Thank you for your time and help, I really appreciate it! Maksym środa, 28 lutego 2024 1:43 PM, mak...@wezdecki.pl napisał(a): > > > Hello, > > Thanks again for reply. > > I have implemented __uc_sanitize() function in my code for resetting a GuC > just before uploading a HuC firmware blob. > > My current setup is as follows: I have TGL and Safety Critiical OS. I load > GuC and authenticate HuC successfully. Then I kill my Safety Critical KMD > driver. I load it once again, which triggers GuC reset/HuC loading/GuC > loading/Enable communication etc. > > Unfortunately, when I try to enable communication for the second time > (without cold reset), then guc_action_control_ctb(), especially > intel_guc_send_mmio() returns GUC_HXG_TYPE_RESPONSE_FAILURE with error 774 or > 0x306. > > I'm not sure what it means. > > The log buffer just after guc_action_control_ctb() is attached to this email. > > Could anybody look into it? > > I really appreciate you help, > Maksym > > > > > wtorek, 27 lutego 2024 9:03 PM, John Harrison john.c.harri...@intel.com > napisał(a): > > > On 2/26/2024 08:30, mak...@wezdecki.pl wrote: > > > > > Hello, > > > > > > Thank you for your help. > > > > > > Is there a possibility to load GuC, then "unload" it and load it again > > > without cold reset? > > > > You need to reset the GuC at least - bit 3 of GDRST. The GuC cannot be > > reloaded 'live'. It must be put into reset first. The last line of > > __uc_sanitize() is a call to reset the GuC, so yes that would be an > > option. Note that fini is more about cleaning up to unload the driver. > > Whereas the sanitise functions are about resets with the potential to > > restart again. > > > > John. > > > > > By loading I mean HuC firmware upload, GuC ADS/log init, GuC firmware > > > upload, CT init, HuC authentication by GuC. > > > > > > I'm asking because I need to perform severe testing on the target for > > > safety purposes without GPU cold reset. > > > What should be done in order to "unload" the GuC? Is it __uc_sanitize() > > > and __uc_fini()? > > > > > > Maksym > > > > > > czwartek, 22 lutego 2024 20:31, Harrison, John C > > > john.c.harri...@intel.com napisał(a): > > > > > > > Hello, > > > > > > > > That worked better. The complaint is that the engine mapping table is > > > > invalid. See the i915 code in guc_mapping_table_init () in > > > > gt/uc/intel_guc_ads.c for an example of how to initialise the table. > > > > > > > > John. > > > > > > > > -Original Message- > > > > From: mak...@wezdecki.pl mak...@wezdecki.pl > > > > > > > > Sent: Wednesday, February 21, 2024 07:15 > > > > To: Harrison, John C john.c.harri...@intel.com > > > > > > > > Cc: mak...@wezdecki.pl; Wajdeczko, Michal michal.wajdec...@intel.com; > > > > intel-gfx@lists.freedesktop.org > > > > > > > > Subject: Re: GuC issue > > > > > > > > Ah, I dumped them with Windows new line characters. > > > > > > > > Here is a new log binary dump. > > > > > > > > I moved to the newest TGL GuC firmware from linux-firmware repo. > > > > > > > > środa, 21 lutego 2024 12:16 AM, John Harrison john.c.harri...@intel.com > > > > napisał(a): > > > > > > > > > Hello, > > > > > > > > > > Something is very corrupted with that GuC log. The log consists of a > > > > > header page and then a stream of log entry structures. The structure > > > > > is supposed to be 20 bytes long and starts with a four byte time > > > > > stamp. But I am seeing what is conceivably a 32bit timestamp appearing > > > > > at 21 byte increments through the log. Even more curiously, the time > > > > > stamp seems to have an 0x0D, 0x0A after it. Are you doing any printf > > > > > type operation in order to write the log out from memory to disk? > > > > > > > > > > INTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID means that the GuC did not > > > > > like the initialisation data passed in. Most likely, something in the > > > > > ADS structure is not valid. If you try with the latest GuC version, > > > > > that might give you more information as to what is the incorrect. More > > > > > status codes have been added since 70.1.1. > > > > > > > > > > John. > > > > > > > > > > On 2/20/2024 05:03, mak...@wezdecki.pl wrote: > > > > > > > > > > > Hi, > > > > > > > > > > > > Please see GuC log attached to this email. > > > > > > > > > > > > Log size is "PAGE_SIZE+Debug Log(64KB) + Crash Log (8KB) + Capture > > > > > > Log (1M)" > > > > > > > > > > > > Can anybody from Intel decode this log buffer? Thanks. > > > > > > > > > > > > What am I doing wrong? > > > > > > > > > > > > Maksym > > > > > > > > > > > > poniedziałek, 19 lutego 2024 09:44, mak...@wezdecki.pl > > > > > > mak...@wezdecki.pl napisał(a): > > > > > > > > > > > > > Hi, > > > > > > > > > > > > > > I fixed one issue in my driver. Log address was set incorrectly. > > > > > > > > > > > > > > Right now, after GuC uploading, GUC_STATUS changed. > > >
Re: [PATCH] drm/i915: Remove unneeded double drm_rect_visible call in check_overlay_dst
On 2/29/24 15:30, Ville Syrjälä wrote: I prefer the current way where we have no side effects in the if statement. This seem like a valid concern from readability and maintainability standpoint. My patch was aimed mostly at performance and maintainability using tools: some more pedantic analyzers are sensitive to non-checked return values (as of now, drm_rect_intersect is ignored). Would it be a better idea to make an update to the patch with second drm_rect_visible call changed to an appropriately named state flag set with drm_rect_intersect result? BTW, the original patch somehow got mangled while it made its way to the patchwork: source list line in patch got broken, which permits the patch from being applied (the original version did not have that line break). Any ideas how to prevent this happening with the second version of patch (in case the idea is viable)?
Re: linux-next: build failure after merge of the kunit-next tree
Hi Stephen,
On 2/28/24 21:26, Stephen Rothwell wrote:
Hi all,
After merging the kunit-next tree, today's linux-next build (x86_64
allmodconfig) failed like this:
In file included from drivers/gpu/drm/tests/drm_buddy_test.c:7:
drivers/gpu/drm/tests/drm_buddy_test.c: In function
'drm_test_buddy_alloc_range_bias':
drivers/gpu/drm/tests/drm_buddy_test.c:191:40: error: format '%u' expects a
matching 'unsigned int' argument [-Werror=format=]
191 |"buddy_alloc failed with
bias(%x-%x), size=%u, ps=%u\n",
|
^~~
include/kunit/test.h:597:37: note: in definition of macro '_KUNIT_FAILED'
597 | fmt,
\
| ^~~
include/kunit/test.h:662:9: note: in expansion of macro 'KUNIT_UNARY_ASSERTION'
662 | KUNIT_UNARY_ASSERTION(test,
\
| ^
include/kunit/test.h:1233:9: note: in expansion of macro
'KUNIT_FALSE_MSG_ASSERTION'
1233 | KUNIT_FALSE_MSG_ASSERTION(test,
\
| ^
drivers/gpu/drm/tests/drm_buddy_test.c:186:17: note: in expansion of macro
'KUNIT_ASSERT_FALSE_MSG'
186 | KUNIT_ASSERT_FALSE_MSG(test,
| ^~
drivers/gpu/drm/tests/drm_buddy_test.c:191:91: note: format string is defined
here
191 |"buddy_alloc failed with
bias(%x-%x), size=%u, ps=%u\n",
|
~^
|
|
|
unsigned int
cc1: all warnings being treated as errors
Caused by commit
806cb2270237 ("kunit: Annotate _MSG assertion variants with gnu printf
specifiers")
Thank you. I did allmodconfig build on kselftest kunit branch to make
sure all is well, before I pushed the commits.
interacting with commit
c70703320e55 ("drm/tests/drm_buddy: add alloc_range_bias test")
>
from the drm-misc-fixes tree.
I have applied the following patch for today (this should probably
actually be fixed in the drm-misc-fixes tree).
Danial, David,
I can carry the fix through kselftest kunit if it works
for all.
From: Stephen Rothwell
Date: Thu, 29 Feb 2024 15:18:36 +1100
Subject: [PATCH] fix up for "drm/tests/drm_buddy: add alloc_range_bias test"
Signed-off-by: Stephen Rothwell
---
drivers/gpu/drm/tests/drm_buddy_test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tests/drm_buddy_test.c
b/drivers/gpu/drm/tests/drm_buddy_test.c
index 1e73e3f0d278..369edf587b44 100644
--- a/drivers/gpu/drm/tests/drm_buddy_test.c
+++ b/drivers/gpu/drm/tests/drm_buddy_test.c
@@ -188,7 +188,7 @@ static void drm_test_buddy_alloc_range_bias(struct kunit
*test)
bias_end, size,
ps,
,
DRM_BUDDY_RANGE_ALLOCATION),
- "buddy_alloc failed with bias(%x-%x),
size=%u, ps=%u\n",
+ "buddy_alloc failed with bias(%x-%x),
size=%u\n",
bias_start, bias_end, size);
bias_rem -= size;
thanks,
-- Shuah
Re: linux-next: build failure after merge of the kunit-next tree
Hi Stephen, On 3/1/24 13:46, Stephen Rothwell wrote: Hi Shuah, On Fri, 1 Mar 2024 09:05:57 -0700 Shuah Khan wrote: On 3/1/24 03:43, Stephen Rothwell wrote: Hi all, On Fri, 1 Mar 2024 15:15:02 +0800 David Gow wrote: On Thu, 29 Feb 2024 at 23:07, Shuah Khan wrote: I can carry the fix through kselftest kunit if it works for all. I'm happy for this to go in with the KUnit changes if that's the best way to keep all of the printk formatting fixes together. Unfortunately you can't fix this in the kunit-next tree without pulling in Linus' tree (or the drm-fixes tree) - which seems excessive. I am pretty sure that the proper fix has been applied to the drm-fixes tree today (in the merge of the drm-misc-fixes tree). What's the commit id for this fix? I Would like to include the details in my pull request to Linus. My mistake, I misread the merge commit. It has not been fixed in the drm-misc-fixes tree or the drm-fixes tree (or Linus' tree since the drm-fixes tree has been merged there) :-( The problem in this case is not with the format string types, but with a missing argument i.e. there is another argument required by the format string. It really should be fixed in the drm-misc-fixes tree and sent to Linus post haste. At least the change in the kunit-next tree will stop this happening in the future. Thank you for looking into it. David, please send a fix in as you suggested earlier. I will apply it to avoid compile errors. thanks, -- Shuah
Re: linux-next: build failure after merge of the kunit-next tree
On 3/1/24 03:43, Stephen Rothwell wrote: Hi all, On Fri, 1 Mar 2024 15:15:02 +0800 David Gow wrote: On Thu, 29 Feb 2024 at 23:07, Shuah Khan wrote: I can carry the fix through kselftest kunit if it works for all. I'm happy for this to go in with the KUnit changes if that's the best way to keep all of the printk formatting fixes together. I am pretty sure that the proper fix has been applied to the drm-fixes tree today (in the merge of the drm-misc-fixes tree). What's the commit id for this fix? I Would like to include the details in my pull request to Linus. If this fix is going before the merge window - we are all set. thanks, -- Shuah
RE: GuC issue
Hello, Thank you for your help. Is there a possibility to load GuC, then "unload" it and load it again without cold reset? By loading I mean HuC firmware upload, GuC ADS/log init, GuC firmware upload, CT init, HuC authentication by GuC. I'm asking because I need to perform severe testing on the target for safety purposes without GPU cold reset. What should be done in order to "unload" the GuC? Is it __uc_sanitize() and __uc_fini()? Maksym czwartek, 22 lutego 2024 20:31, Harrison, John C napisał(a): > > > Hello, > > That worked better. The complaint is that the engine mapping table is > invalid. See the i915 code in guc_mapping_table_init () in > gt/uc/intel_guc_ads.c for an example of how to initialise the table. > > John. > > > -Original Message- > From: mak...@wezdecki.pl mak...@wezdecki.pl > > Sent: Wednesday, February 21, 2024 07:15 > To: Harrison, John C john.c.harri...@intel.com > > Cc: mak...@wezdecki.pl; Wajdeczko, Michal michal.wajdec...@intel.com; > intel-gfx@lists.freedesktop.org > > Subject: Re: GuC issue > > Ah, I dumped them with Windows new line characters. > > Here is a new log binary dump. > > I moved to the newest TGL GuC firmware from linux-firmware repo. > > > środa, 21 lutego 2024 12:16 AM, John Harrison john.c.harri...@intel.com > napisał(a): > > > Hello, > > > > Something is very corrupted with that GuC log. The log consists of a > > header page and then a stream of log entry structures. The structure > > is supposed to be 20 bytes long and starts with a four byte time > > stamp. But I am seeing what is conceivably a 32bit timestamp appearing > > at 21 byte increments through the log. Even more curiously, the time > > stamp seems to have an 0x0D, 0x0A after it. Are you doing any printf > > type operation in order to write the log out from memory to disk? > > > > INTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID means that the GuC did not > > like the initialisation data passed in. Most likely, something in the > > ADS structure is not valid. If you try with the latest GuC version, > > that might give you more information as to what is the incorrect. More > > status codes have been added since 70.1.1. > > > > John. > > > > On 2/20/2024 05:03, mak...@wezdecki.pl wrote: > > > > > Hi, > > > > > > Please see GuC log attached to this email. > > > > > > Log size is "PAGE_SIZE+Debug Log(64KB) + Crash Log (8KB) + Capture Log > > > (1M)" > > > > > > Can anybody from Intel decode this log buffer? Thanks. > > > > > > What am I doing wrong? > > > > > > Maksym > > > > > > poniedziałek, 19 lutego 2024 09:44, mak...@wezdecki.pl mak...@wezdecki.pl > > > napisał(a): > > > > > > > Hi, > > > > > > > > I fixed one issue in my driver. Log address was set incorrectly. > > > > > > > > Right now, after GuC uploading, GUC_STATUS changed. > > > > Right now, intel_guc_load_status is > > > > INTEL_GUC_LOAD_STATUS_INIT_DATA_INVALID = 0x71. > > > > > > > > What does it mean? > > > > Could you please help me with this? > > > > > > > > Thanks, > > > > Maksym > > > > > > > > piątek, 9 lutego 2024 08:42, natur.prod...@pm.me natur.prod...@pm.me > > > > napisał(a): > > > > > > > > > Hello, > > > > > > > > > > Please see my comments below. > > > > > > > > > > piątek, 9 lutego 2024 2:45 AM, John Harrison > > > > > john.c.harri...@intel.com napisał(a): > > > > > > > > > > > Hello, > > > > > > > > > > > > What platform is this on? And which GuC firmware version are you > > > > > > using? > > > > > > It's TGL. I'm using tgl_guc_70.1.1.bin firmware blob. > > > > > > > > > > > One thing you made need to do is force maximum GT frequency > > > > > > during GuC load. That is something the i915 driver does. If > > > > > > the system decides the GPU is idle and drops the frequency to > > > > > > minimum then it can take multiple seconds for the GuC > > > > > > initialisation to complete. > > > > > > Thanks for the hint. I'm not doing that at all in my code. How am I > > > > > > supposed to do this? Is there a specific register for that? > > > > > > > > > > > Did the status change at all during that second of waiting? Or > > > > > > was it still reading LAPIC_DONE? > > > > > > It's always LAPIC_DONE. > > > > > > > > > > > For ADS documentation, I'm afraid that the best we currently > > > > > > have publicly available is the i915 driver code. If you are > > > > > > not intending to use GuC submission then most of the ADS can be > > > > > > ignored. > > > > > > Ok, that great. Which part of ADS is must-have then? > > > > > > > > > > > If you can share the GuC log, that might provide some clues as > > > > > > to what is happening. For just logging the boot process, you > > > > > > shouldn't need to allocate a large log. The default size of > > > > > > i915 for release builds is 64KB. That should be plenty. > > > > > > I'll collect GuC log as soon as possible. Is it something that can > > > > > > be understood without a knowledge of GuC internals? Or is it simply > > > >
[PATCH] drm/i915: Remove unneeded double drm_rect_visible call in check_overlay_dst
check_overlay_dst for clipped is called 2 times: in drm_rect_intersect
and than directly. Change second call for check of drm_rect_intersect
result to save some time (in locked code section).
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 8d8b2dd3995f ("drm/i915: Make the PIPESRC rect relative to the
entire bigjoiner area")
Signed-off-by: Nikita Kiryushin
---
drivers/gpu/drm/i915/display/intel_overlay.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 2b1392d5a902..1cda1c163a92 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -972,9 +972,8 @@ static int check_overlay_dst(struct intel_overlay
*overlay,
rec->dst_width, rec->dst_height);
clipped = req;
- drm_rect_intersect(, _state->pipe_src);
- if (!drm_rect_visible() ||
+ if (!drm_rect_intersect(, _state->pipe_src) ||
!drm_rect_equals(, ))
return -EINVAL;
-- 2.34.1
GuC WOPCM question
Hi, I understand that GuC is 32bit uController, so it has access only to 4GB GTT. I don't understand WOPCM and GTT conjunction. >From i915 doc we can see that: +===> ++ <== _ ^ | Reserved | | ++ <== GUC_GGTT_TOP | || | |DRAM| GuC|| Address+===> ++ <== GuC ggtt_pin_bias Space ^ || | | || | GuC|GuC | | WOPCM | WOPCM| | Size || | | || v v || +===+===> ++ <== _ Can the range of (from 0x_ to "GuC ggtt_pin_bias") be used by other parts of the KMD? Or this range is reserved only for GuC WOPCM and shouldn't be used by KMD driver for other allocations? Thanks for reply, Maksym
RE: [RFC 0/5] Introduce drm sharpening property
This is generic as sharpness effect is applied post blending. Depending on the color gamut, pixel format and other inputs the image gets blended and once we get blended output it can be sharpened based on strength value provided by the user. On intel platform it is implemented through pipe scaler. Pipe scaler can be used as either scaler or sharpness filter. As mentioned earlier the client can provide any strength value between 0-255 or any other scale based on discussions. Perhaps userspace can have provide options like low-med-high sharpness or in percentage form or steps which is mapped to 0-255. I will add the documentation regarding property. > -Original Message- > From: dri-devel On Behalf Of Pekka > Paalanen > Sent: Friday, February 16, 2024 2:06 PM > To: Garg, Nemesa > Cc: Simon Ser ; intel-gfx@lists.freedesktop.org; dri- > de...@lists.freedesktop.org; G M, Adarsh > Subject: Re: [RFC 0/5] Introduce drm sharpening property > > On Fri, 16 Feb 2024 04:28:41 + > "Garg, Nemesa" wrote: > > > It is not intel specific and the goal is to have a generic API for > > configuring Sharpness, accessible to various vendors. Intel currently > > offers sharpness support through the Display Engine, while other > > vendors seem to support Sharpness through the GPU using GL shaders > > (Vulcan/Open GL based). > > Do you mean that all vendors use the exact same mathematical algorithm (with > only differences in operation precision at most)? > > If yes, good. > > If not, then we need to know where exactly in the virtual KMS color pipeline > the > operation happens, whether this can be generic or not. > > Does this also work the same regardless of pixel formats, dynamic range, color > gamut, transfer functions etc. on both plane input and connector output > configurations? > > > In terms of sharpness intensity adjustment, the plan is to provide > > users with the ability to customize and regulate sharpness levels. We > > suggest setting a minimum and maximum strength range from 1 to 255, > > where a value of 0 signifies that the sharpness feature is disabled, > > indicated by a u8 data type. For now we have mapped the strength value > > 0.0 to 14.9375 to 0-239 but as the datatype is u8 user can give value > > upto 255 which is gets clamped to 239. > > Naturally you will need to document all that, so that all drivers and vendors > do the > exact same thing. > > I did not see any actual documentation in the patch series yet, e.g. a > reference to > a specific algorithm. > > As Ville pointed out, there was also no specification at which point of the > virtual > color pipeline this operation will apply. Before/after > DEGAMMA/CTM/GAMMA/scaling in plane/blending/CRTC? > > Is the property being added to the list in > https://dri.freedesktop.org/docs/drm/gpu/drm-kms.html#standard-crtc- > properties > or where-ever it belongs? > > > Thanks, > pq > > > We are also open to have alternative scales, such as 1-100 or 1-10, as > > long as a general consensus is reached within the community comprising > > OEMs and vendors. > > > > > -Original Message- > > > From: Simon Ser > > > Sent: Thursday, February 15, 2024 2:03 PM > > > To: Garg, Nemesa > > > Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org > > > Subject: Re: [RFC 0/5] Introduce drm sharpening property > > > > > > How much of this is Intel-specific? Are there any hardware vendors > > > with a similar feature? How much is the "sharpness" knob tied to > > > Intel hardware?
Re: Regression on linux-next (next-20240228)
On Mon, Mar 04, 2024 at 10:03:13AM +, Borah, Chaitanya Kumar wrote:
> > Could you try putting the two:
> >
> > - list_del(>lru);
> >
> > statements back in and see if that fixes it?
>
> That seems to fix it.
>
> if (!folio_put_testzero(folio))
> + list_del(>lru);
> continue;
Ummm ... did you put { and } around this? Otherwise the indentation
is misleading and what you're actually done is:
if (!folio_put_testzero(folio))
list_del(>lru);
continue;
which will simply leak memory.
> if (folio_test_large(folio)) {
> __folio_put_large(folio);
> + list_del(>lru);
> continue;
> }
> Regards
>
> Chaitanya
Re: [PATCH v7 3/3] drm/buddy: Add defragmentation support
On 04/03/2024 12:22, Paneer Selvam, Arunpravin wrote:
Hi Matthew,
On 2/22/2024 12:12 AM, Matthew Auld wrote:
On 21/02/2024 12:18, Arunpravin Paneer Selvam wrote:
Add a function to support defragmentation.
v1:
- Defragment the memory beginning from min_order
till the required memory space is available.
v2(Matthew):
- add amdgpu user for defragmentation
- add a warning if the two blocks are incompatible on
defragmentation
- call full defragmentation in the fini() function
- place a condition to test if min_order is equal to 0
- replace the list with safe_reverse() variant as we might
remove the block from the list.
Signed-off-by: Arunpravin Paneer Selvam
Suggested-by: Matthew Auld
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 17 +++-
drivers/gpu/drm/drm_buddy.c | 93 +---
include/drm/drm_buddy.h | 3 +
3 files changed, 97 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index e494f5bf136a..cff8a526c622 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -533,8 +533,21 @@ static int amdgpu_vram_mgr_new(struct
ttm_resource_manager *man,
min_block_size,
>blocks,
vres->flags);
- if (unlikely(r))
- goto error_free_blocks;
+ if (unlikely(r)) {
+ if (r == -ENOSPC) {
+ drm_buddy_defrag(mm, min_block_size);
+ r = drm_buddy_alloc_blocks(mm, fpfn,
+ lpfn,
+ size,
+ min_block_size,
+ >blocks,
+ vres->flags);
+ if (unlikely(r))
+ goto error_free_blocks;
+ } else {
+ goto error_free_blocks;
+ }
+ }
if (size > remaining_size)
remaining_size = 0;
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 18e004fa39d3..56bd1560fbcd 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -203,6 +203,8 @@ void drm_buddy_fini(struct drm_buddy *mm)
drm_block_free(mm, mm->roots[i]);
}
+ drm_buddy_defrag(mm, mm->chunk_size << mm->max_order);
I think this needs to be called higher up, otherwise we blow up with
the WARN, plus we just freed the root(s). There is also the case with
non-power-of-two VRAM size, in which case you get multiple roots and
max_order is just the largest root and not entire address space. I
guess do this in the loop above and use the root order instead?
Also this should be done as part of the first patch and then in this
patch it is just a case of exporting it. Every commit should ideally
be functional by itself.
You mean we move the above change in drm_buddy_fini function and
drm_buddy_defrag function as part of first patch.
And just we add export function and add amdgpu user in this patch. Is my
understanding correct?
Yeah, I think that makes sense.
Thanks,
Arun.
+
WARN_ON(mm->avail != mm->size);
kfree(mm->roots);
@@ -276,25 +278,39 @@ drm_get_buddy(struct drm_buddy_block *block)
}
EXPORT_SYMBOL(drm_get_buddy);
-static void __drm_buddy_free(struct drm_buddy *mm,
- struct drm_buddy_block *block)
+static unsigned int __drm_buddy_free(struct drm_buddy *mm,
+ struct drm_buddy_block *block,
+ bool defrag)
{
+ unsigned int order, block_order;
struct drm_buddy_block *parent;
+ block_order = drm_buddy_block_order(block);
+
while ((parent = block->parent)) {
- struct drm_buddy_block *buddy;
+ struct drm_buddy_block *buddy = NULL;
buddy = __get_buddy(block);
if (!drm_buddy_block_is_free(buddy))
break;
- if (drm_buddy_block_is_clear(block) !=
- drm_buddy_block_is_clear(buddy))
- break;
+ if (!defrag) {
+ /*
+ * Check the block and its buddy clear state and exit
+ * the loop if they both have the dissimilar state.
+ */
+ if (drm_buddy_block_is_clear(block) !=
+ drm_buddy_block_is_clear(buddy))
+ break;
- if (drm_buddy_block_is_clear(block))
- mark_cleared(parent);
+ if (drm_buddy_block_is_clear(block))
+ mark_cleared(parent);
+ }
+
+ WARN_ON(defrag &&
+ (drm_buddy_block_is_clear(block) ==
+ drm_buddy_block_is_clear(buddy)));
list_del(>link);
@@ -304,8 +320,57 @@ static void __drm_buddy_free(struct drm_buddy
*mm,
block = parent;
}
- mark_free(mm, block);
+ order = drm_buddy_block_order(block);
+ if
Re: [PATCH v7 3/3] drm/buddy: Add defragmentation support
Hi Matthew,
On 2/22/2024 12:12 AM, Matthew Auld wrote:
On 21/02/2024 12:18, Arunpravin Paneer Selvam wrote:
Add a function to support defragmentation.
v1:
- Defragment the memory beginning from min_order
till the required memory space is available.
v2(Matthew):
- add amdgpu user for defragmentation
- add a warning if the two blocks are incompatible on
defragmentation
- call full defragmentation in the fini() function
- place a condition to test if min_order is equal to 0
- replace the list with safe_reverse() variant as we might
remove the block from the list.
Signed-off-by: Arunpravin Paneer Selvam
Suggested-by: Matthew Auld
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 17 +++-
drivers/gpu/drm/drm_buddy.c | 93 +---
include/drm/drm_buddy.h | 3 +
3 files changed, 97 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index e494f5bf136a..cff8a526c622 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -533,8 +533,21 @@ static int amdgpu_vram_mgr_new(struct
ttm_resource_manager *man,
min_block_size,
>blocks,
vres->flags);
- if (unlikely(r))
- goto error_free_blocks;
+ if (unlikely(r)) {
+ if (r == -ENOSPC) {
+ drm_buddy_defrag(mm, min_block_size);
+ r = drm_buddy_alloc_blocks(mm, fpfn,
+ lpfn,
+ size,
+ min_block_size,
+ >blocks,
+ vres->flags);
+ if (unlikely(r))
+ goto error_free_blocks;
+ } else {
+ goto error_free_blocks;
+ }
+ }
if (size > remaining_size)
remaining_size = 0;
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 18e004fa39d3..56bd1560fbcd 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -203,6 +203,8 @@ void drm_buddy_fini(struct drm_buddy *mm)
drm_block_free(mm, mm->roots[i]);
}
+ drm_buddy_defrag(mm, mm->chunk_size << mm->max_order);
I think this needs to be called higher up, otherwise we blow up with
the WARN, plus we just freed the root(s). There is also the case with
non-power-of-two VRAM size, in which case you get multiple roots and
max_order is just the largest root and not entire address space. I
guess do this in the loop above and use the root order instead?
Also this should be done as part of the first patch and then in this
patch it is just a case of exporting it. Every commit should ideally
be functional by itself.
You mean we move the above change in drm_buddy_fini function and
drm_buddy_defrag function as part of first patch.
And just we add export function and add amdgpu user in this patch. Is my
understanding correct?
Thanks,
Arun.
+
WARN_ON(mm->avail != mm->size);
kfree(mm->roots);
@@ -276,25 +278,39 @@ drm_get_buddy(struct drm_buddy_block *block)
}
EXPORT_SYMBOL(drm_get_buddy);
-static void __drm_buddy_free(struct drm_buddy *mm,
- struct drm_buddy_block *block)
+static unsigned int __drm_buddy_free(struct drm_buddy *mm,
+ struct drm_buddy_block *block,
+ bool defrag)
{
+ unsigned int order, block_order;
struct drm_buddy_block *parent;
+ block_order = drm_buddy_block_order(block);
+
while ((parent = block->parent)) {
- struct drm_buddy_block *buddy;
+ struct drm_buddy_block *buddy = NULL;
buddy = __get_buddy(block);
if (!drm_buddy_block_is_free(buddy))
break;
- if (drm_buddy_block_is_clear(block) !=
- drm_buddy_block_is_clear(buddy))
- break;
+ if (!defrag) {
+ /*
+ * Check the block and its buddy clear state and exit
+ * the loop if they both have the dissimilar state.
+ */
+ if (drm_buddy_block_is_clear(block) !=
+ drm_buddy_block_is_clear(buddy))
+ break;
- if (drm_buddy_block_is_clear(block))
- mark_cleared(parent);
+ if (drm_buddy_block_is_clear(block))
+ mark_cleared(parent);
+ }
+
+ WARN_ON(defrag &&
+ (drm_buddy_block_is_clear(block) ==
+ drm_buddy_block_is_clear(buddy)));
list_del(>link);
@@ -304,8 +320,57 @@ static void __drm_buddy_free(struct drm_buddy
*mm,
block = parent;
}
- mark_free(mm, block);
+ order = drm_buddy_block_order(block);
+ if (block_order != order)
+ mark_free(mm, block);
+
+ return order;
+}
+
+/**
+ *
Re: [PATCH v3] drm/i915/dp: Increase idle pattern wait timeout to 2ms
On Mon, 04 Mar 2024, "Chauhan, Shekhar" wrote: > On 3/4/2024 14:16, Jani Nikula wrote: >> I did not ask for this. I would rather all platforms used 2 ms. I even >> said the original change looked fine. But I'd like it to be explained in >> the commit message. > I felt that when you said "why bump for non lnl platforms", I felt that > I should be segregating them. > But, as discussed offline, I'll revert back to the original design with > a change in the commit message. Thanks. Communication is hard. :) BR, Jani. -- Jani Nikula, Intel
Re: [PATCH v3] drm/i915/dp: Increase idle pattern wait timeout to 2ms
On 3/4/2024 14:16, Jani Nikula wrote:
On Mon, 04 Mar 2024, Shekhar Chauhan wrote:
Currently, the driver is only waiting for 1ms for
idle patterns. But starting from LNL and beyond,
the MST wants the driver to wait for 1640us before
What does it mean that "the MST wants"?
I wanted to convey that MST streams require the driver to wait for 2ms.
I'll rephrase.
timing out (which we round up to 2ms).
v1: Introduced the 2ms wait timeout.
v2: Segregated the wait timeout for platforms before & after LNL.
I did not ask for this. I would rather all platforms used 2 ms. I even
said the original change looked fine. But I'd like it to be explained in
the commit message.
I felt that when you said "why bump for non lnl platforms", I felt that
I should be segregating them.
But, as discussed offline, I'll revert back to the original design with
a change in the commit message.
v3: Fixed 2 cosmetic changes.
BSpec: 68849
Signed-off-by: Shekhar Chauhan
---
drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..b59adb7685b8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3677,12 +3677,19 @@ static void intel_ddi_set_idle_link_train(struct
intel_dp *intel_dp,
*/
if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
return;
-
- if (intel_de_wait_for_set(dev_priv,
- dp_tp_status_reg(encoder, crtc_state),
- DP_TP_STATUS_IDLE_DONE, 1))
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ if (intel_de_wait_for_set(dev_priv,
+ dp_tp_status_reg(encoder, crtc_state),
+ DP_TP_STATUS_IDLE_DONE, 2))
+ drm_err(_priv->drm,
+ "Timed out waiting for DP idle patterns\n");
+ } else {
+ if (intel_de_wait_for_set(dev_priv,
+ dp_tp_status_reg(encoder, crtc_state),
+ DP_TP_STATUS_IDLE_DONE, 1))
drm_err(_priv->drm,
"Timed out waiting for DP idle patterns\n");
+ }
So I'd like you to go back to how it was originally.
}
static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
--
-shekhar
Re: [PATCH v2] drm/i915/overlay: Remove redundant drm_rect_visible() use
On Sat, Mar 25, 2023 at 02:27:19PM -0300, Arthur Grillo wrote: > The drm_rect_intersect() already returns if the intersection is visible > or not, so the use of drm_rect_visible() is duplicate. > > Signed-off-by: Arthur Grillo Sorry, looks like I completely missed this. Now push the drm-intel-next. Thanks. > --- > v1->v2: > https://lore.kernel.org/all/20230324142533.6357-1-arthurgri...@riseup.net/ > - Split the if condition. > --- > drivers/gpu/drm/i915/display/intel_overlay.c | 7 --- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c > b/drivers/gpu/drm/i915/display/intel_overlay.c > index c12bdca8da9b..d55153587cae 100644 > --- a/drivers/gpu/drm/i915/display/intel_overlay.c > +++ b/drivers/gpu/drm/i915/display/intel_overlay.c > @@ -966,10 +966,11 @@ static int check_overlay_dst(struct intel_overlay > *overlay, > rec->dst_width, rec->dst_height); > > clipped = req; > - drm_rect_intersect(, _state->pipe_src); > > - if (!drm_rect_visible() || > - !drm_rect_equals(, )) > + if (!drm_rect_intersect(, _state->pipe_src)) > + return -EINVAL; > + > + if (!drm_rect_equals(, )) > return -EINVAL; > > return 0; > -- > 2.39.2 -- Ville Syrjälä Intel
Re: [PATCH] drm/i915: Remove unneeded double drm_rect_visible call in check_overlay_dst
On Fri, Mar 01, 2024 at 09:56:41PM +0300, Nikita Kiryushin wrote: > On 2/29/24 15:30, Ville Syrjälä wrote: > > I prefer the current way where we have no side effects in > > the if statement. > > > > This seem like a valid concern from readability and maintainability > standpoint. My patch was aimed mostly at performance and maintainability > using tools: some more pedantic analyzers are sensitive to non-checked > return values (as of now, drm_rect_intersect is ignored). > > Would it be a better idea to make an update to the patch with second > drm_rect_visible call changed to an appropriately named state flag set > with drm_rect_intersect result? I was thinking of maybe removing that drm_rect_visible() from drm_rect_intersect() entirely, but looks like it's used fairly extensively, so would require a bunch of work. But now that I though about this I recalled that there was an earlier patch trying to do exactly what you suggested in this patch. And looks like there was a second version posted which I completely missed: https://patchwork.freedesktop.org/series/115605/ While that does still have drm_rect_intersect() with its side effects inside the if() I don't find it quite as objectionable since it's the only thing in there. So it's a bit more obvious what is happening. I've gone and merged that one. Thanks for the patch regardless. At least I reminded me to look at the earlier attempt ;) > > BTW, the original patch somehow got mangled while it made its way to the > patchwork: source list line in patch got broken, which permits the patch > from being applied (the original version did not have that line break). > Any ideas how to prevent this happening with the second version of patch > (in case the idea is viable)? -- Ville Syrjälä Intel
Re: [PATCH v15 9/9] drm/i915/display: Read/Write AS sdp only when sink/source has enabled
On 3/1/2024 2:15 PM, Mitul Golani wrote: Write/Read Adaptive sync SDP only when Sink and Source is enabled for the same. Also along with write TRANS_VRR_VSYNC values. The subject line and commit message need to be updated. Now we are just enabling Adaptive sync SDP. Regards, Ankit Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index c587a8efeafc..f164020a4773 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3972,6 +3972,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); intel_audio_codec_get_config(encoder, pipe_config); } diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ef1543205ee9..9abe245ac1ee 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4332,6 +4332,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, return; intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); }
Re: [PATCH v15 8/9] drm/i915/display: Compute vrr_vsync params
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START/END. (Ankit)
--v3:
- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
- Read/write vrr_vsync params only when we intend to send
adaptive_sync sdp.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 29 +--
drivers/gpu/drm/i915/i915_reg.h | 7 +
4 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 88158f06bf82..f62c3ae7f0fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5377,6 +5377,8 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+ PIPE_CONF_CHECK_I(vrr.vsync_start);
+ PIPE_CONF_CHECK_I(vrr.vsync_end);
}
#undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 098957cea25b..e8ba3c077569 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1423,6 +1423,7 @@ struct intel_crtc_state {
bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
+ u32 vsync_end, vsync_start;
} vrr;
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..d24a42902e69 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_vrr.h"
+#include "intel_dp.h"
bool intel_vrr_is_capable(struct intel_connector *connector)
{
@@ -113,6 +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
const struct drm_display_info *info = >base.display_info;
int vmin, vmax;
@@ -165,6 +167,15 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
if (crtc_state->uapi.vrr_enabled) {
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+ if (intel_dp_as_sdp_supported(intel_dp)) {
+ crtc_state->vrr.vsync_start =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+
VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start));
+ crtc_state->vrr.vsync_end =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+
(VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16));
I think you are using the VRR_SYNC_START/END macros incorrectly.
We dont need to use these macros here.
+ }
}
}
@@ -203,6 +214,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder),
crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder),
crtc_state->vrr.flipline - 1);
+
+ if (crtc_state->vrr.vsync_end && crtc_state->vrr.vsync_start)
+ intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+ crtc_state->vrr.vsync_end << 16 |
crtc_state->vrr.vsync_start);
Here is where the macros should be used.
VRR_SYNC_END(crtc_state->vrr.vsync_end) |
VRR_SYNC_START(crtc_state->vrr.vsync_start);
}
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
@@ -263,7 +278,7 @@ void intel_vrr_get_config(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- u32 trans_vrr_ctl;
+ u32 trans_vrr_ctl, trans_vrr_vsync;
trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
@@ -283,6
Re: [PATCH v2 8/8] drm/i915: Handle joined pipes inside hsw_crtc_disable()
On Mon, Mar 04, 2024 at 08:44:35AM +0200, Srinivas, Vidya wrote:
> Thank you very much Ville and Stan.
> With https://patchwork.freedesktop.org/series/130619/ and
> https://patchwork.freedesktop.org/series/130449/ tested that 6K works
> Tested-by: Vidya Srinivas
The thing is that we still don't handle crtc enable(i.e actual enabling of
displays)
here at all, only disabling part. So fact that it works could be also related
to this.
Ville, should I use your series, plus the things we had discussed in my series
to implement
hsw_crtc_enable on top of your series?
Of course things related to transcoder have to be clarified still.
Or do you plan to do it yourself?
Stan
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Ville
> > Syrjala
> > Sent: Friday, March 1, 2024 10:54 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Lisovskiy, Stanislav
> > Subject: [PATCH v2 8/8] drm/i915: Handle joined pipes inside
> > hsw_crtc_disable()
> >
> > From: Ville Syrjälä
> >
> > Reorganize the crtc disable path to only deal with the master
> > pipes/transcoders in intel_old_crtc_state_disables() and offload the
> > handling
> > of joined pipes to hsw_crtc_disable().
> > This makes the whole thing much more sensible since we can actually control
> > the order in which we do the per-pipe vs.
> > per-transcoder modeset steps.
> >
> > v2: Pass the correct crtc pointer to .crtc_disable()
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 66
> > 1 file changed, 39 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 1df3923cc30d..e01536983303 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1793,29 +1793,27 @@ static void hsw_crtc_disable(struct
> > intel_atomic_state *state,
> > const struct intel_crtc_state *old_master_crtc_state =
> > intel_atomic_get_old_crtc_state(state, master_crtc);
> > struct drm_i915_private *i915 = to_i915(master_crtc->base.dev);
> > + u8 pipe_mask = intel_crtc_joined_pipe_mask(old_master_crtc_state);
> > + struct intel_crtc *crtc;
> >
> > /*
> > * FIXME collapse everything to one hook.
> > * Need care with mst->ddi interactions.
> > */
> > - if (!intel_crtc_is_bigjoiner_slave(old_master_crtc_state)) {
> > - intel_encoders_disable(state, master_crtc);
> > - intel_encoders_post_disable(state, master_crtc);
> > - }
> > -
> > - intel_disable_shared_dpll(old_master_crtc_state);
> > + intel_encoders_disable(state, master_crtc);
> > + intel_encoders_post_disable(state, master_crtc);
> >
> > - if (!intel_crtc_is_bigjoiner_slave(old_master_crtc_state)) {
> > - struct intel_crtc *slave_crtc;
> > + for_each_intel_crtc_in_pipe_mask(>drm, crtc, pipe_mask) {
> > + const struct intel_crtc_state *old_crtc_state =
> > + intel_atomic_get_old_crtc_state(state, crtc);
> >
> > - intel_encoders_post_pll_disable(state, master_crtc);
> > + intel_disable_shared_dpll(old_crtc_state);
> > + }
> >
> > - intel_dmc_disable_pipe(i915, master_crtc->pipe);
> > + intel_encoders_post_pll_disable(state, master_crtc);
> >
> > - for_each_intel_crtc_in_pipe_mask(>drm, slave_crtc,
> > -
> > intel_crtc_bigjoiner_slave_pipes(old_master_crtc_state))
> > - intel_dmc_disable_pipe(i915, slave_crtc->pipe);
> > - }
> > + for_each_intel_crtc_in_pipe_mask(>drm, crtc, pipe_mask)
> > + intel_dmc_disable_pipe(i915, crtc->pipe);
> > }
> >
> > static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) @@
> > -
> > 6753,24 +6751,33 @@ static void intel_update_crtc(struct intel_atomic_state
> > *state, }
> >
> > static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc)
> > + struct intel_crtc *master_crtc)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > - const struct intel_crtc_state *new_crtc_state =
> > - intel_atomic_get_new_crtc_state(state, crtc);
> > + const struct intel_crtc_state *old_master_crtc_state =
> > + intel_atomic_get_old_crtc_state(state, master_crtc);
> > + u8 pipe_mask = intel_crtc_joined_pipe_mask(old_master_crtc_state);
> > + struct intel_crtc *crtc;
> >
> > /*
> > * We need to disable pipe CRC before disabling the pipe,
> > * or we race against vblank off.
> > */
> > - intel_crtc_disable_pipe_crc(crtc);
> > + for_each_intel_crtc_in_pipe_mask(_priv->drm, crtc, pipe_mask)
> > + intel_crtc_disable_pipe_crc(crtc);
> >
> > - dev_priv->display.funcs.display->crtc_disable(state, crtc);
> > - crtc->active = false;
> > -
Re: [PATCH v15 7/9] drm/i915/display: Add state checker for Adaptive Sync SDP
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Enable infoframe and add state checker for Adaptive Sync
SDP enablement.
--v1:
- crtc_state->infoframes.enable, to add on correct place holder.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 46
1 file changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ab2f52d21bad..88158f06bf82 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4791,6 +4791,17 @@ intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
a->content_type == b->content_type;
}
+static bool
+intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
+ const struct drm_dp_as_sdp *b)
+{
+ return a->vtotal == b->vtotal &&
+ a->target_rr == b->target_rr &&
+ a->duration_incr_ms == b->duration_incr_ms &&
+ a->duration_decr_ms == b->duration_decr_ms &&
+ a->mode == b->mode;
+}
+
static bool
intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
{
@@ -4846,6 +4857,30 @@ pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private
*i915,
drm_dp_vsc_sdp_log(, b);
}
+static void
+pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915,
+ bool fastset, const char *name,
+ const struct drm_dp_as_sdp *a,
+ const struct drm_dp_as_sdp *b)
+{
+ struct drm_printer p;
+
+ if (fastset) {
+ p = drm_dbg_printer(>drm, DRM_UT_KMS, NULL);
+
+ drm_printf(, "fastset requirement not met in %s dp sdp\n",
name);
+ } else {
+ p = drm_err_printer(>drm, NULL);
+
+ drm_printf(, "mismatch in %s dp sdp\n", name);
+ }
+
+ drm_printf(, "expected:\n");
+ drm_dp_as_sdp_log(, a);
+ drm_printf(, "found:\n");
+ drm_dp_as_sdp_log(, b);
+}
+
/* Returns the length up to and including the last differing byte */
static size_t
memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
@@ -5099,6 +5134,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
+ if (!intel_compare_dp_as_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+ pipe_config_dp_as_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
_config->infoframes.name, \
+ _config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BUFFER(name, len) do { \
BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
@@ -5280,6 +5325,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
+ PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
Re: [PATCH v15 6/9] drm/i915/display: Compute AS SDP parameters
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Add necessary function definitions to compute AS SDP data.
The new intel_dp_compute_as_sdp function computes AS SDP
values based on the display configuration, ensuring proper
handling of Variable Refresh Rate (VRR).
--v2:
- Added DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx(). [Ankit]
- Separated patch for intel_read/write_dp_sdp. [Ankit]
- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit]
- Fixed indentation issues. [Ankit]
--v3:
- Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.
--v4:
- Added HAS_VRR check before writing AS SDP.
--v5:
Added missed HAS_VRR check before reading AS SDP.
--v6:
- Used Adaptive Sync sink status as a check for read/write SDP. (Ankit)
--v7:
- Remove as_sdp_enable from crtc_state.
- Add a comment mentioning current support of
DP_AS_SDP_AVT_FIXED_VTOTAL.
- Add state checker for AS_SDP infoframe enable.
--v8:
- Drop conn_state from intel_dp_compute_as_sdp, as not used.
- Remove fullstop in subject line.
--v9:
- Add vrr.enable instead of is_in_vrr_range.
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 26 +
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1b3e7ae3dd76..ef1543205ee9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2620,6 +2620,31 @@ static void intel_dp_compute_vsc_colorimetry(const
struct intel_crtc_state *crtc
vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
}
+static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_dp_as_sdp *as_sdp = _state->infoframes.as_sdp;
+ struct intel_connector *connector = intel_dp->attached_connector;
+ const struct drm_display_mode *adjusted_mode =
+ _state->hw.adjusted_mode;
+ int vrefresh = drm_mode_vrefresh(adjusted_mode);
I think you missed to remove vrefresh and connector, as they are no
longer required.
Regards,
Ankit
+
+ if (!crtc_state->vrr.enable ||
+ !intel_dp_as_sdp_supported(intel_dp))
+ return;
+
+ crtc_state->infoframes.enable |=
intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
+
+ /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
+ as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+ as_sdp->length = 0x9;
+ as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+ as_sdp->target_rr = 0;
+ as_sdp->duration_incr_ms = 0;
+ as_sdp->duration_incr_ms = 0;
+}
+
static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -2980,6 +3005,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
g4x_dp_set_clock(encoder, pipe_config);
intel_vrr_compute_config(pipe_config, conn_state);
+ intel_dp_compute_as_sdp(intel_dp, pipe_config);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
Re: [PATCH v15 5/9] drm/i915/dp: Add wrapper function to check AS SDP
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add a wrapper function to check if both the source and
sink support Adaptive Sync SDP.
--v1:
Just use drm/i915/dp in subject line.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 99732ac1475d..1b3e7ae3dd76 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -122,6 +122,14 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
return dig_port->base.type == INTEL_OUTPUT_EDP;
}
+bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ return HAS_AS_SDP(i915) &&
+ drm_dp_as_sdp_supported(_dp->aux, intel_dp->dpcd);
+}
+
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 564a587e2d01..0b15fd4750ee 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -86,6 +86,7 @@ void intel_dp_audio_compute_config(struct intel_encoder
*encoder,
struct drm_connector_state *conn_state);
bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
bool intel_dp_is_edp(struct intel_dp *intel_dp);
+bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp);
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
int intel_dp_link_symbol_size(int rate);
int intel_dp_link_symbol_clock(int rate);
Re: [PATCH v15 4/9] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
--v4:
- Remove as_sdp_mode from crtc_state.
- Drop metadata keyword.
- For consistency, update ADL_ prefix or post fix as required.
--v5:
- Check if AS_SDP bit is set in crtc_state->infoframes.enable. If not
return.
- Check for HAS_AS_SDP() before setting VIDEO_DIP_ENABLE_AS_ADL mask.
--v6:
- Rename intel_read_dp_infoframe_as_sdp to intel_read_dp_as_sdp.
-
Signed-off-by: Mitul Golani
---
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 91 +++
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++
include/drm/display/drm_dp_helper.h | 2 +-
5 files changed, 114 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..6399fbc6c738 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
#define HAS_TRANSCODER(i915, trans)
((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
+#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
#define INTEL_NUM_PIPES(i915)
(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915)
(DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915)
(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6ece2c563c7a..99732ac1475d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4127,6 +4127,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
*crtc_state,
return false;
}
+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
+ struct dp_sdp *sdp, size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ /* Prepare AS (Adaptive Sync) SDP Header */
+ sdp->sdp_header.HB0 = 0;
+ sdp->sdp_header.HB1 = as_sdp->sdp_type;
+ sdp->sdp_header.HB2 = 0x02;
+ sdp->sdp_header.HB3 = as_sdp->length;
+
+ /* Fill AS (Adaptive Sync) SDP Payload */
+ sdp->db[0] = as_sdp->mode;
+ sdp->db[1] = as_sdp->vtotal & 0xFF;
+ sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
+ sdp->db[3] = as_sdp->target_rr;
Use as_sdp->target_rr & 0xFF;
+ sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
+
+ return length;
+}
+
static ssize_t
intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
const struct hdmi_drm_infoframe
*drm_infoframe,
@@ -4226,6 +4252,10 @@ static void intel_write_dp_sdp(struct intel_encoder
*encoder,
_state->infoframes.drm.drm,
,
sizeof(sdp));
break;
+ case DP_SDP_ADAPTIVE_SYNC:
+ len = intel_dp_as_sdp_pack(_state->infoframes.as_sdp, ,
+ sizeof(sdp));
+ break;
default:
MISSING_CASE(type);
return;
@@ -4247,6 +4277,10 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+
+ if (HAS_AS_SDP(dev_priv))
+ dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
+
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
@@ -4268,6 +4302,36 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
intel_write_dp_sdp(encoder, crtc_state,
HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static
+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+
RE: Regression on linux-next (next-20240228)
Hello Mathew,
> -Original Message-
> From: Matthew Wilcox
> Sent: Monday, March 4, 2024 11:27 AM
> To: Borah, Chaitanya Kumar
> Cc: intel-gfx@lists.freedesktop.org; Kurmi, Suresh Kumar
> ; Saarinen, Jani
> Subject: Re: Regression on linux-next (next-20240228)
>
> On Mon, Mar 04, 2024 at 04:49:47AM +, Borah, Chaitanya Kumar
> wrote:
> > After bisecting the tree, the following patch [4] seems to be the first
> > "bad"
> > commit
> >
> > ``
> > ```
> > commit ac7130117e8860081be88149061b5abb654d5759
> > Author: Matthew Wilcox (Oracle) mailto:wi...@infradead.org
> > Date: Tue Feb 27 17:42:41 2024 +
> >
> > mm: use free_unref_folios() in put_pages_list()
> >
> > Break up the list of folios into batches here so that the folios
> > are more
> > likely to be cache hot when doing the rest of the processing.
> >
> > Link:
> > https://lkml.kernel.org/r/20240227174254.710559-8-wi...@infradead.org
> > Signed-off-by: Matthew Wilcox (Oracle) mailto:wi...@infradead.org
> > ``
> > ```
> >
> > We could not revert the patch because of a build errors but resetting
> > to the parent of the commit seems to fix the issue
> >
> > Could you please check why the patch causes this regression and provide a
> fix if necessary?
>
> Could you try putting the two:
>
> - list_del(>lru);
>
> statements back in and see if that fixes it?
That seems to fix it.
if (!folio_put_testzero(folio))
+ list_del(>lru);
continue;
if (folio_test_large(folio)) {
__folio_put_large(folio);
+ list_del(>lru);
continue;
}
Regards
Chaitanya
Re: [PATCH v5] drm/i915: Show bios vbt when read from firmware/spi/oprom
On Fri, 01 Mar 2024, Radhakrishna Sripada
wrote:
> Make debugfs vbt only shows valid vbt when read from ACPI opregion.
> Make it work when read from firmware/spi/pci oprom cases. In the cases
> where VBT needs to be read from spi/pci oprom, take the wakeref to
> prevent WARN while reading DE registers during debugfs vbt dump.
>
> v2: Extract getting vbt from different sources to its own function.
> Protect sysfs write with vbt check(Jani)
> v3: Fix CI error by probing bios vbt with runtime_pm wakeref
> v4: Update commit message and skip waking up runtime while accessing
> vbt from opregion/firmware(Jani)
>
> Cc: Jani Nikula
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 62 ---
> 1 file changed, 33 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 44c9dfe86a00..9a8c7fe381b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -3135,6 +3135,32 @@ static struct vbt_header *oprom_get_vbt(struct
> drm_i915_private *i915,
> return NULL;
> }
>
> +static const struct vbt_header *intel_bios_get_vbt(struct drm_i915_private
> *i915,
> +size_t *sizep)
> +{
> + const struct vbt_header *vbt = NULL;
> + intel_wakeref_t wakeref;
> +
> + vbt = firmware_get_vbt(i915, sizep);
> +
> + if (!vbt)
> + vbt = intel_opregion_get_vbt(i915, sizep);
> +
> + /*
> + * If the OpRegion does not have VBT, look in SPI flash
> + * through MMIO or PCI mapping
> + */
> + with_intel_runtime_pm(>runtime_pm, wakeref) {
> + if (!vbt && IS_DGFX(i915))
> + vbt = spi_oprom_get_vbt(i915, sizep);
> +
> + if (!vbt)
> + vbt = oprom_get_vbt(i915, sizep);
> + }
This will still enable power even if intel_opregion_get_vbt() returned a
non-NULL pointer.
BR,
Jani.
> +
> + return vbt;
> +}
> +
> /**
> * intel_bios_init - find VBT and initialize settings from the BIOS
> * @i915: i915 device instance
> @@ -3146,7 +3172,6 @@ static struct vbt_header *oprom_get_vbt(struct
> drm_i915_private *i915,
> void intel_bios_init(struct drm_i915_private *i915)
> {
> const struct vbt_header *vbt;
> - struct vbt_header *oprom_vbt = NULL;
> const struct bdb_header *bdb;
>
> INIT_LIST_HEAD(>display.vbt.display_devices);
> @@ -3160,27 +3185,7 @@ void intel_bios_init(struct drm_i915_private *i915)
>
> init_vbt_defaults(i915);
>
> - oprom_vbt = firmware_get_vbt(i915, NULL);
> - vbt = oprom_vbt;
> -
> - if (!vbt) {
> - oprom_vbt = intel_opregion_get_vbt(i915, NULL);
> - vbt = oprom_vbt;
> - }
> -
> - /*
> - * If the OpRegion does not have VBT, look in SPI flash through MMIO or
> - * PCI mapping
> - */
> - if (!vbt && IS_DGFX(i915)) {
> - oprom_vbt = spi_oprom_get_vbt(i915, NULL);
> - vbt = oprom_vbt;
> - }
> -
> - if (!vbt) {
> - oprom_vbt = oprom_get_vbt(i915, NULL);
> - vbt = oprom_vbt;
> - }
> + vbt = intel_bios_get_vbt(i915, NULL);
>
> if (!vbt)
> goto out;
> @@ -3213,7 +3218,7 @@ void intel_bios_init(struct drm_i915_private *i915)
> parse_sdvo_device_mapping(i915);
> parse_ddi_ports(i915);
>
> - kfree(oprom_vbt);
> + kfree(vbt);
> }
>
> static void intel_bios_init_panel(struct drm_i915_private *i915,
> @@ -3743,13 +3748,12 @@ static int intel_bios_vbt_show(struct seq_file *m,
> void *unused)
> const void *vbt;
> size_t vbt_size;
>
> - /*
> - * FIXME: VBT might originate from other places than opregion, and then
> - * this would be incorrect.
> - */
> - vbt = intel_opregion_get_vbt(i915, _size);
> - if (vbt)
> + vbt = intel_bios_get_vbt(i915, _size);
> +
> + if (vbt) {
> seq_write(m, vbt, vbt_size);
> + kfree(vbt);
> + }
>
> return 0;
> }
--
Jani Nikula, Intel
Re: [PATCH v15 3/9] drm: Add crtc state dump for Adaptive Sync SDP
Add drm/i915/display in subject line.
With that fixed this is:
Reviewed-by: Ankit Nautiyal
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add crtc state dump for Adaptive Sync SDP to know which
crtc specifically caused the failure.
Signed-off-by: Mitul Golani
---
.../gpu/drm/i915/display/intel_crtc_state_dump.c| 13 +
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4bcf446c75f4..1e4618271156 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -51,6 +51,15 @@ intel_dump_infoframe(struct drm_i915_private *i915,
hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame);
}
+static void
+intel_dump_dp_as_sdp(struct drm_i915_private *i915,
+const struct drm_dp_as_sdp *as_sdp)
+{
+ struct drm_printer p = drm_dbg_printer(>drm, DRM_UT_KMS,
"AS_SDP");
+
+ drm_dp_as_sdp_log(, as_sdp);
+}
+
static void
intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
const struct drm_dp_vsc_sdp *vsc)
@@ -302,6 +311,10 @@ void intel_crtc_state_dump(const struct intel_crtc_state
*pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(DP_SDP_VSC))
intel_dump_dp_vsc_sdp(i915, _config->infoframes.vsc);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+ intel_dump_dp_as_sdp(i915, _config->infoframes.as_sdp);
+
if (pipe_config->has_audio)
intel_dump_buffer(i915, "ELD: ", pipe_config->eld,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 860e867586f4..098957cea25b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1338,6 +1338,7 @@ struct intel_crtc_state {
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
struct drm_dp_vsc_sdp vsc;
+ struct drm_dp_as_sdp as_sdp;
} infoframes;
u8 eld[MAX_ELD_BYTES];
Re: [PATCH 8/8] drm/i915: Handle joined pipes inside hsw_crtc_disable()
On Fri, Mar 01, 2024 at 06:47:54PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 01, 2024 at 06:22:19PM +0200, Lisovskiy, Stanislav wrote:
> > On Fri, Mar 01, 2024 at 06:10:25PM +0200, Ville Syrjälä wrote:
> > > On Fri, Mar 01, 2024 at 06:04:27PM +0200, Lisovskiy, Stanislav wrote:
> > > > On Fri, Mar 01, 2024 at 04:36:00PM +0200, Ville Syrjala wrote:
> > > > > From: Ville Syrjälä
> > > > >
> > > > > Reorganize the crtc disable path to only deal with the
> > > > > master pipes/transcoders in intel_old_crtc_state_disables()
> > > > > and offload the handling of joined pipes to hsw_crtc_disable().
> > > > > This makes the whole thing much more sensible since we can
> > > > > actually control the order in which we do the per-pipe vs.
> > > > > per-transcoder modeset steps.
> > > > >
> > > > > Signed-off-by: Ville Syrjälä
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 64
> > > > >
> > > > > 1 file changed, 38 insertions(+), 26 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 1df3923cc30d..07239c1ce9df 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -1793,29 +1793,27 @@ static void hsw_crtc_disable(struct
> > > > > intel_atomic_state *state,
> > > > > const struct intel_crtc_state *old_master_crtc_state =
> > > > > intel_atomic_get_old_crtc_state(state, master_crtc);
> > > > > struct drm_i915_private *i915 = to_i915(master_crtc->base.dev);
> > > > > + u8 pipe_mask =
> > > > > intel_crtc_joined_pipe_mask(old_master_crtc_state);
> > > > > + struct intel_crtc *crtc;
> > > > >
> > > > > /*
> > > > >* FIXME collapse everything to one hook.
> > > > >* Need care with mst->ddi interactions.
> > > > >*/
> > > > > - if (!intel_crtc_is_bigjoiner_slave(old_master_crtc_state)) {
> > > > > - intel_encoders_disable(state, master_crtc);
> > > > > - intel_encoders_post_disable(state, master_crtc);
> > > > > - }
> > > > > -
> > > > > - intel_disable_shared_dpll(old_master_crtc_state);
> > > > > + intel_encoders_disable(state, master_crtc);
> > > > > + intel_encoders_post_disable(state, master_crtc);
> > > > >
> > > > > - if (!intel_crtc_is_bigjoiner_slave(old_master_crtc_state)) {
> > > > > - struct intel_crtc *slave_crtc;
> > > > > + for_each_intel_crtc_in_pipe_mask(>drm, crtc, pipe_mask) {
> > > > > + const struct intel_crtc_state *old_crtc_state =
> > > > > + intel_atomic_get_old_crtc_state(state, crtc);
> > > > >
> > > > > - intel_encoders_post_pll_disable(state, master_crtc);
> > > > > + intel_disable_shared_dpll(old_crtc_state);
> > > > > + }
> > > > >
> > > > > - intel_dmc_disable_pipe(i915, master_crtc->pipe);
> > > > > + intel_encoders_post_pll_disable(state, master_crtc);
> > > > >
> > > > > - for_each_intel_crtc_in_pipe_mask(>drm, slave_crtc,
> > > > > -
> > > > > intel_crtc_bigjoiner_slave_pipes(old_master_crtc_state))
> > > > > - intel_dmc_disable_pipe(i915, slave_crtc->pipe);
> > > > > - }
> > > > > + for_each_intel_crtc_in_pipe_mask(>drm, crtc, pipe_mask)
> > > > > + intel_dmc_disable_pipe(i915, crtc->pipe);
> > > > > }
> > > >
> > > > Okay the only difference from hsw_crtc_disable part from my patch is
> > > > that
> > > > I don't have intel_crtc_joined_pipe_mask and encoder calls are outside
> > > > the pipe
> > > > loop. Ok. You could of course just communicate this to me, it is quite
> > > > a small
> > > > thing to change.
> > > >
> > > > And still there is a question about how to handle the crtc enable side,
> > > > since
> > > > extracting transcoder programming from the pipe loop, will break the
> > > > sequence,
> > > > as I described. Either it is ok that we will partly program
> > > > slave/master pipe, then
> > > > program transcoder then again program slave/master pipes or it has to be
> > > > in a pipe loop.
> > >
> > > Transcoder stuff shouldn't be in pipe loops. That's what
> > > I've been saying all along.
> >
> > Yep, I realize you kept saying this and I described you the problem what
> > happens if
> > we extract it from there.
> > Either it is ok to have 2 loops and have transcoder programming in between
> > or you
> > first program pipes then program the transcoder - in both cases that would
> > change
> > the sequence of how it is done now.
> > My question was if this is ok or not.
>
> Well, that's pretty much it's supposed to be done. As mentioned
> I think the current code kinda works more by luck.
>
> I suppose the only reason it works at all is that we do try to order
> at least some of the steps via the
Re: [PATCH v15 2/9] drm: Add Adaptive Sync SDP logging
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add structure representing Adaptive Sync Secondary Data Packet (AS SDP).
Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate
debugging.
--v2:
- Update logging. [Jani, Ankit]
- Use 'as_sdp' instead of 'async' [Ankit]
- Correct define placeholders to where they are actually used. [Jani]
- Update members in 'as_sdp' structure to make it uniform. [Jani]
--v3:
- Added changes to dri-devel mailing list. No code changes.
--v4:
- Instead of directly using operation mode, use an enum to accommodate
all operation modes (Ankit).
--v5:
Nit-pick changes to commit message.
--v6:
- Add correct place holder and name change for AS_SDP_OP_MODE.
- Separate i915 changes from drm changes.
- Remove extra lines.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/display/drm_dp_helper.c | 12 ++
include/drm/display/drm_dp.h| 10 +
include/drm/display/drm_dp_helper.h | 29 +
3 files changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index f2fabb673aa4..f880bc7b2153 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2948,6 +2948,18 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const
struct drm_dp_vsc_sdp *vsc)
}
EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
+void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp)
+{
+ drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
+ as_sdp->revision, as_sdp->length);
+ drm_printf(p, "vtotal: %d\n", as_sdp->vtotal);
+ drm_printf(p, "target_rr: %d\n", as_sdp->target_rr);
+ drm_printf(p, "duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
+ drm_printf(p, "duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
+ drm_printf(p, "operation_mode: %d\n", as_sdp->mode);
+}
+EXPORT_SYMBOL(drm_dp_as_sdp_log);
+
/**
* drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
* @aux: DisplayPort AUX channel
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 4891bd916d26..e39a22a714e2 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1150,6 +1150,7 @@
#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */
# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED(1 << 0)
+# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0)
I am wondering if GENMASK can be used here, without including linux/bits.h
I might be wrong though.
Other than patch looks good to me.
Regards,
Ankit
# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1
<< 1)
# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4)
@@ -1639,10 +1640,12 @@ enum drm_dp_phy {
#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
#define DP_SDP_ISRC 0x06 /* DP 1.2 */
#define DP_SDP_VSC0x07 /* DP 1.2 */
+#define DP_SDP_ADAPTIVE_SYNC 0x22 /* DP 1.4 */
#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
#define DP_SDP_PPS0x10 /* DP 1.4 */
#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
#define DP_SDP_VSC_EXT_CEA0x21 /* DP 1.4 */
+
/* 0x80+ CEA-861 infoframe types */
#define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
@@ -1798,4 +1801,11 @@ enum dp_content_type {
DP_CONTENT_TYPE_GAME = 0x04,
};
+enum operation_mode {
+ DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
+ DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
+ DP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02,
+ DP_AS_SDP_FAVT_TRR_REACHED = 0x03
+};
+
#endif /* _DRM_DP_H_ */
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index 7df19acdc790..10147ae96326 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -98,6 +98,35 @@ struct drm_dp_vsc_sdp {
enum dp_content_type content_type;
};
+/**
+ * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP
+ *
+ * This structure represents a DP AS SDP of drm
+ * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes]
and
+ * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]
+ *
+ * @sdp_type: Secondary-data packet type
+ * @revision: Revision Number
+ * @length: Number of valid data bytes
+ * @vtotal: Minimum Vertical Vtotal
+ * @target_rr: Target Refresh
+ * @duration_incr_ms: Successive frame duration increase
+ * @duration_decr_ms: Successive frame duration decrease
+ * @operation_mode: Adaptive Sync Operation Mode
+ */
+struct drm_dp_as_sdp {
+ unsigned char sdp_type;
+ unsigned char revision;
+ unsigned char length;
+ int vtotal;
+ int target_rr;
+ int duration_incr_ms;
+ int duration_decr_ms;
+ enum operation_mode mode;
+};
+
+void drm_dp_as_sdp_log(struct drm_printer *p,
Re: [PATCH v3] drm/i915/dp: Increase idle pattern wait timeout to 2ms
On Mon, 04 Mar 2024, Shekhar Chauhan wrote:
> Currently, the driver is only waiting for 1ms for
> idle patterns. But starting from LNL and beyond,
> the MST wants the driver to wait for 1640us before
What does it mean that "the MST wants"?
> timing out (which we round up to 2ms).
>
> v1: Introduced the 2ms wait timeout.
> v2: Segregated the wait timeout for platforms before & after LNL.
I did not ask for this. I would rather all platforms used 2 ms. I even
said the original change looked fine. But I'd like it to be explained in
the commit message.
> v3: Fixed 2 cosmetic changes.
>
> BSpec: 68849
> Signed-off-by: Shekhar Chauhan
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bea441590204..b59adb7685b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3677,12 +3677,19 @@ static void intel_ddi_set_idle_link_train(struct
> intel_dp *intel_dp,
>*/
> if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
> return;
> -
> - if (intel_de_wait_for_set(dev_priv,
> - dp_tp_status_reg(encoder, crtc_state),
> - DP_TP_STATUS_IDLE_DONE, 1))
> + if (DISPLAY_VER(dev_priv) >= 20) {
> + if (intel_de_wait_for_set(dev_priv,
> + dp_tp_status_reg(encoder, crtc_state),
> + DP_TP_STATUS_IDLE_DONE, 2))
> + drm_err(_priv->drm,
> + "Timed out waiting for DP idle patterns\n");
> + } else {
> + if (intel_de_wait_for_set(dev_priv,
> + dp_tp_status_reg(encoder, crtc_state),
> + DP_TP_STATUS_IDLE_DONE, 1))
> drm_err(_priv->drm,
> "Timed out waiting for DP idle patterns\n");
> + }
So I'd like you to go back to how it was originally.
> }
>
> static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
--
Jani Nikula, Intel
Re: [PATCH v15 1/9] drm/dp: Add support to indicate if sink supports AS SDP
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add an API that indicates support for Adaptive Sync SDP in
the sink, which can be utilized by the rest of the DP programming.
--v1:
- Format commit message properly.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/display/drm_dp_helper.c | 25 +
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index 266826eac4a7..f2fabb673aa4 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2948,6 +2948,31 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const
struct drm_dp_vsc_sdp *vsc)
}
EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
+/**
+ * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
+ * @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
+ *
+ * Returns true if adaptive sync sdp is supported, else returns false
+ */
+bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8
dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ u8 rx_feature;
+
+ if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
+ return false;
+
+ if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
+ _feature) != 1) {
+ drm_dbg_dp(aux->drm_dev,
+ "Failed to read
DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
+ return false;
+ }
+
+ return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED);
+}
+EXPORT_SYMBOL(drm_dp_as_sdp_supported);
+
/**
* drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
* @aux: DisplayPort AUX channel
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index a62fcd051d4d..7df19acdc790 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -101,6 +101,7 @@ struct drm_dp_vsc_sdp {
void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp
*vsc);
bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8
dpcd[DP_RECEIVER_CAP_SIZE]);
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
Re: [PATCH v3 0/5] ALSA/ASoC: Conditionally skip i915 init and cleanups
On Mon, 26 Feb 2024 13:44:27 +0100,
Cezary Rojewski wrote:
>
> A small set of changes to improve initialization of the audio stack on
> HDAudio devices and pair of cleanups.
>
> As the first change is the most important one here, following is the
> technical background for it:
>
> Commit 78f613ba1efb ("drm/i915: finish removal of CNL") and its friends
> removed support for i915 for all CNL-based platforms. HDAudio library,
> however, still treats such platforms as valid candidates for i915
> binding. Update query mechanism to reflect changes made in drm tree.
>
> At the same time, i915 support for LKF-based platforms has not been
> provided so remove them from valid binding candidates.
>
> The snd_soc_hda change is a follow up for the above and the cleanup
> patches do not bring any functional changes.
>
> Changes in v3:
> - snd_soc_hda_codec now returns -ENODEV on attach() if i915 is not
> present
> - denylist now const
> - added new patch for the avs-driver to address -ENODEV during
> probe_codec()
> - note: retained reviewed-by for patch 1/4 as changes are minimal
>
> Changes in v2:
> - list of problematic VGA devices is now declared locally, no more
> touching drm stuff
>
> Cezary Rojewski (5):
> ALSA: hda: Skip i915 initialization on CNL/LKF-based platforms
> ASoC: codecs: hda: Skip HDMI/DP registration if i915 is missing
> ASoC: Intel: avs: Ignore codecs with no suppoting driver
> ASoC: codecs: hda: Cleanup error messages
> ALSA: hda: Reuse for_each_pcm_streams()
Applied to for-next branch now. Thanks.
Takashi
