Re: [PATCH 6/8] drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changes

[Lisovskiy, Stanislav]

On Mon, Mar 11, 2024 at 06:13:29PM -0300, Gustavo Sousa wrote:
> Quoting Lisovskiy, Stanislav (2024-03-11 18:01:04-03:00)
> >On Mon, Mar 04, 2024 at 03:30:25PM -0300, Gustavo Sousa wrote:
> >> Commit 394b4b7df9f7 ("drm/i915/lnl: Add CDCLK table") and commit
> >> 3d3696c0fed1 ("drm/i915/lnl: Start using CDCLK through PLL") started
> >> adding support for CDCLK programming support for Xe2LPD. One final piece
> >> is missing, which is the programming necessary for changed in the ratio
> >> between MDCLK and CDCLK. Let's do that now.
> >> 
> >> BSpec instructs us to update MBUS_CTL and DBUF_CTL_S* registers when the
> >> ratio between MDCLK and CDCLK changes. The updates must be done before
> >> changing the CDCLK when decreasing the frequency; or after it when
> >> increasing the frequency.
> >> 
> >> Ratio-related updates to MBUS_CTL also depend on the state of MBus
> >> joining, so they are performed by either CDCLK change sequence or by
> >> changes in MBus joining. Since one might happen independently of the
> >> other, we need to make sure that both logics see the necessary state
> >> values when programming that register. MBus joining logic needs to know
> >> the MDCLK:CDCLK ratio and that's already provided via mdclk_cdclk_ratio
> >> field of struct intel_dbuf_state.
> >> 
> >> For the CDCLK logic, we need to have something similar: we need to
> >> propagate the status of MBus joining to struct intel_cdclk_state. Do
> >> that by adding the field joined_mbus to struct intel_cdclk_config.
> >> (Preferably, that field would be added to intel_cdclk_state, however
> >> currently only intel_cdclk_config is passed down to the functions that
> >> do the register programming. We might revisit this decision if we find
> >> that refactoring the code to pass the whole intel_cdclk_state is worth
> >> it.)
> >> 
> >> Bspec: 68864, 68868, 69090, 69482
> >> Signed-off-by: Gustavo Sousa 
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_cdclk.c| 31 ++
> >>  drivers/gpu/drm/i915/display/intel_cdclk.h|  3 ++
> >>  drivers/gpu/drm/i915/display/skl_watermark.c  | 40 +++
> >>  drivers/gpu/drm/i915/display/skl_watermark.h  |  1 +
> >>  .../gpu/drm/i915/display/skl_watermark_regs.h | 18 +
> >>  5 files changed, 77 insertions(+), 16 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> >> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> index 04a6e9806254..12753589072d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> @@ -40,6 +40,7 @@
> >>  #include "intel_psr.h"
> >>  #include "intel_vdsc.h"
> >>  #include "skl_watermark.h"
> >> +#include "skl_watermark_regs.h"
> >>  #include "vlv_sideband.h"
> >>  
> >>  /**
> >> @@ -1683,6 +1684,8 @@ static void bxt_get_cdclk(struct drm_i915_private 
> >> *dev_priv,
> >>  }
> >>  
> >>   out:
> >> +if (DISPLAY_VER(dev_priv) >= 20)
> >> +cdclk_config->joined_mbus = intel_de_read(dev_priv, 
> >> MBUS_CTL) & MBUS_JOIN;
> >>  /*
> >>   * Can't read this out :( Let's assume it's
> >>   * at least what the CDCLK frequency requires.
> >> @@ -1908,6 +1911,14 @@ u8 intel_mdclk_cdclk_ratio(struct drm_i915_private 
> >> *i915,
> >>  }
> >>  }
> >>  
> >> +static void xe2lpd_mdclk_cdclk_ratio_program(struct drm_i915_private 
> >> *i915,
> >> + const struct 
> >> intel_cdclk_config *cdclk_config)
> >> +{
> >> +intel_dbuf_mdclk_cdclk_ratio_update(i915,
> >> +intel_mdclk_cdclk_ratio(i915, 
> >> cdclk_config),
> >> +cdclk_config->joined_mbus);
> >> +}
> >> +
> >>  static bool cdclk_compute_crawl_and_squash_midpoint(struct 
> >> drm_i915_private *i915,
> >>  const struct 
> >> intel_cdclk_config *old_cdclk_config,
> >>  const struct 
> >> intel_cdclk_config *new_cdclk_config,
> >> @@ -2089,6 +2100,9 @@ static void bxt_set_cdclk(struct drm_i915_private 
> >> *dev_priv,
> >>  return;
> >>  }
> >>  
> >> +if (DISPLAY_VER(dev_priv) >= 20 && cdclk < 
> >> dev_priv->display.cdclk.hw.cdclk)
> >> +xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config);
> >> +
> >>  if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, 
> >> &dev_priv->display.cdclk.hw,
> >>  cdclk_config, 
> >> &mid_cdclk_config)) {
> >>  _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
> >> @@ -2097,6 +2111,9 @@ static void bxt_set_cdclk(struct drm_i915_private 
> >> *dev_priv,
> >>  _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> >>  }
> >>  
> >> +if (DISPLAY_VER(dev_priv) >= 20 && cdclk > 
> >> dev_priv->display.cdclk.hw.cdclk)
> >> + 

RE: [RFC 0/5] Introduce drm sharpening property

[Garg, Nemesa]

This  KMS property is not implementing any formula and the values that are 
being used are based on empirical analysis and certain experiments done on the 
hardware. These values are fixed and is not expected to change and this can 
change from vendor to vendor. 
The client can choose any sharpness value on the scale and on the basis of it 
the sharpness will be set. The sharpness effect can be changed from content to 
content and from display to display so user needs to adjust the optimum 
intensity value so as to get good experience on the screen.

> -Original Message-
> From: dri-devel  On Behalf Of Simon
> Ser
> Sent: Monday, March 4, 2024 7:46 PM
> To: Garg, Nemesa 
> Cc: Pekka Paalanen ; intel-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; G M, Adarsh
> 
> Subject: RE: [RFC 0/5] Introduce drm sharpening property
> 
> On Monday, March 4th, 2024 at 15:04, Garg, Nemesa 
> wrote:
> 
> > This is generic as sharpness effect is applied post blending.
> > Depending on the color gamut, pixel format and other inputs the image
> > gets blended and once we get blended output it can be sharpened based
> > on strength value provided by the user.
> 
> It would really help if you could provide the exact mathematical formula 
> applied
> by this KMS property.

Re: [PATCH 06/11] drm/xe: Remove useless mem_access during probe

[Matthew Auld]

On 11/03/2024 19:22, Rodrigo Vivi wrote:

xe_pm_init is the very last thing during the xe_pci_probe(),
hence these protections are useless from the point of view
of ensuring that the device is awake.

Let's remove it so we continue towards the goal of killing
xe_device_mem_access.

v2: Adding more cases
v3: Provide a separate fix for xe_tile_init_noalloc return (Matt)
 Adding a new case where display HDCP init calls which
 are also called at display probe time.

Cc: Matthew Auld 
Signed-off-by: Rodrigo Vivi 

Reviewed-by: Matthew Auld 

Re: [PATCH 0/5] drm/i915: cleanup dead code

[Tvrtko Ursulin]

On 11/03/2024 19:27, Lucas De Marchi wrote:

On Mon, Mar 11, 2024 at 05:43:00PM +, Tvrtko Ursulin wrote:


On 06/03/2024 19:36, Lucas De Marchi wrote:

Remove platforms that never had their PCI IDs added to the driver and
are of course marked with requiring force_probe. Note that most of the
code for those platforms is actually used by subsequent ones, so it's
not a huge amount of code being removed.


I had PVC and xehpsdv back in October but could not collect all acks. :(

Last two patches from https://patchwork.freedesktop.org/series/124705/.


oh... I was actually surprised we still had xehpsdv while removing a
WA for PVC, which made me look into removing these platforms.

rebasing your series and comparing yours..my-v2, where my-v2 only has
patches 2 and 4, I have the diff below. I think it's small enough that I
can just take your commits and squash delta. Is that ok to you?

my version is a little bit more aggressive, also doing some renames
s/xehpsdv/xehp/ and dropping some more code
(engine_mask_apply_copy_fuses(), unused registers, default ctx, fw
ranges).


Right, yeah I see I missed some case combos in the comments when 
grepping and more.


 diff --git a/Documentation/gpu/rfc/i915_vm_bind.h 
b/Documentation/gpu/rfc/i915_vm_bind.h

 index 8a8fcd4fceac..bc26dc126104 100644
 --- a/Documentation/gpu/rfc/i915_vm_bind.h
 +++ b/Documentation/gpu/rfc/i915_vm_bind.h
 @@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
   * Multiple VA mappings can be created to the same section of the 
object

   * (aliasing).
   *
 - * The @start, @offset and @length must be 4K page aligned. 
However the DG2
 - * and XEHPSDV has 64K page size for device local memory and has 
compact page
 - * table. On those platforms, for binding device local-memory 
objects, the
 - * @start, @offset and @length must be 64K aligned. Also, UMDs 
should not mix
 - * the local memory 64K page and the system memory 4K page 
bindings in the same

 - * 2M range.
 + * The @start, @offset and @length must be 4K page aligned. 
However the DG2 has
 + * 64K page size for device local memory and has compact page 
table. On that
 + * platform, for binding device local-memory objects, the @start, 
@offset and
 + * @length must be 64K aligned. Also, UMDs should not mix the 
local memory 64K

 + * page and the system memory 4K page bindings in the same 2M range.
   *
   * Error code -EINVAL will be returned if @start, @offset and 
@length are not
   * properly aligned. In version 1 (See 
I915_PARAM_VM_BIND_VERSION), error code
 diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h

 index 1495b6074492..d3300ae3053f 100644
 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
 +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
 @@ -386,7 +386,7 @@ struct drm_i915_gem_object {
  * and kernel mode driver for caching policy control after GEN12.
  * In the meantime platform specific tables are created to 
translate
  * i915_cache_level into pat index, for more details check the 
macros

 - * defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.
 + * defined i915/i915_pci.c, e.g. MTL_CACHELEVEL.


Why this?

  * For backward compatibility, this field contains values 
exactly match
  * the entries of enum i915_cache_level for pre-GEN12 platforms 
(See

  * LEGACY_CACHELEVEL), so that the PTE encode functions for these
 diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c

 index fa46d2308b0e..1bd0e041e15c 100644
 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
 +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
 @@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
  }
  static void
 -xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
 -  struct i915_vma_resource *vma_res,
 -  struct sgt_dma *iter,
 -  unsigned int pat_index,
 -  u32 flags)
 +xehp_ppgtt_insert_huge(struct i915_address_space *vm,
 +   struct i915_vma_resource *vma_res,
 +   struct sgt_dma *iter,
 +   unsigned int pat_index,
 +   u32 flags)
  {
     const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
     unsigned int rem = sg_dma_len(iter->sg);
 @@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct 
i915_address_space *vm,

     struct sgt_dma iter = sgt_dma(vma_res);
     if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 -    if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
 -    xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, 
pat_index, flags);

 +    if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
 +    xehp_ppgtt_insert_huge(vm, vma_res, &iter, pat_index,

RE: [PATCH 1/5] drm: Introduce sharpness mode property

[Garg, Nemesa]

> -Original Message-
> From: dri-devel  On Behalf Of Pekka
> Paalanen
> Sent: Friday, March 8, 2024 2:18 PM
> To: Garg, Nemesa 
> Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 1/5] drm: Introduce sharpness mode property
> 
> On Thu,  7 Mar 2024 14:02:33 +0530
> Nemesa Garg  wrote:
> 
> > This allows the user to set the intensity so as to get the sharpness
> > effect.
> >
> > It is useful in scenario when the output is blurry and user want to
> > sharpen the pixels.
> >
> > Signed-off-by: Nemesa Garg 
> > ---
> >  drivers/gpu/drm/drm_atomic_uapi.c |  4 
> >  drivers/gpu/drm/drm_crtc.c| 17 +
> >  include/drm/drm_crtc.h| 17 +
> >  3 files changed, 38 insertions(+)
> 
> Hi,
> 
> the UAPI documentation is completely missing. This cannot be discussed until 
> the
> UAPI contract is drafted. It needs to end up in the appropriate "Properties"
> section under https://dri.freedesktop.org/docs/drm/gpu/drm-kms.html#kms-
> properties
> when documentation is built.
> 
> I also do not see any of the previous review comments being addressed that I
> recall.
> 
> The typo "sharpeness" is very common in these patches, and it is even in the 
> UAPI
> as the property name. Also doc comments use different spelling than actual 
> code.
> And sometimes you use even "sharpening"
> instead of "sharpness". Which one is it?

Thank you for pointing it out. I'll change it to sharpness to make it 
consistent everywhere and will add document in next revision. It seems I have 
missed some queries I will try to address it.

Thanks,
Nemesa

> 
> 
> Thanks,
> pq
> 
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > b/drivers/gpu/drm/drm_atomic_uapi.c
> > index 29d4940188d4..773873726b87 100644
> > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > @@ -417,6 +417,8 @@ static int drm_atomic_crtc_set_property(struct
> drm_crtc *crtc,
> > set_out_fence_for_crtc(state->state, crtc, fence_ptr);
> > } else if (property == crtc->scaling_filter_property) {
> > state->scaling_filter = val;
> > +   } else if (property == crtc->sharpening_strength_prop) {
> > +   state->sharpeness_strength = val;
> > } else if (crtc->funcs->atomic_set_property) {
> > return crtc->funcs->atomic_set_property(crtc, state, property,
> val);
> > } else {
> > @@ -454,6 +456,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
> > *val = 0;
> > else if (property == crtc->scaling_filter_property)
> > *val = state->scaling_filter;
> > +   else if (property == crtc->sharpening_strength_prop)
> > +   *val = state->sharpeness_strength;
> > else if (crtc->funcs->atomic_get_property)
> > return crtc->funcs->atomic_get_property(crtc, state, property,
> val);
> > else {
> > diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> > index cb90e70d85e8..d01ab76a719f 100644
> > --- a/drivers/gpu/drm/drm_crtc.c
> > +++ b/drivers/gpu/drm/drm_crtc.c
> > @@ -955,3 +955,20 @@ int drm_crtc_create_scaling_filter_property(struct
> drm_crtc *crtc,
> > return 0;
> >  }
> >  EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property);
> > +
> > +int drm_crtc_create_sharpening_strength_property(struct drm_crtc
> > +*crtc) {
> > +   struct drm_device *dev = crtc->dev;
> > +
> > +   struct drm_property *prop =
> > +   drm_property_create_range(dev, 0, "SHARPENESS_STRENGTH",
> 0, 255);
> > +
> > +   if (!prop)
> > +   return -ENOMEM;
> > +
> > +   crtc->sharpening_strength_prop = prop;
> > +   drm_object_attach_property(&crtc->base, prop, 0);
> > +
> > +   return 0;
> > +}
> > +EXPORT_SYMBOL(drm_crtc_create_sharpening_strength_property);
> > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index
> > 8b48a1974da3..241514fc3eea 100644
> > --- a/include/drm/drm_crtc.h
> > +++ b/include/drm/drm_crtc.h
> > @@ -317,6 +317,16 @@ struct drm_crtc_state {
> >  */
> > enum drm_scaling_filter scaling_filter;
> >
> > +   /**
> > +* @sharpness_strength
> > +*
> > +* Used by the user to set the sharpness intensity.
> > +* The value ranges from 0-255.
> > +* Any value greater than 0 means enabling the featuring
> > +* along with setting the value for sharpness.
> > +*/
> > +   u8 sharpeness_strength;
> > +
> > /**
> >  * @event:
> >  *
> > @@ -1088,6 +1098,12 @@ struct drm_crtc {
> >  */
> > struct drm_property *scaling_filter_property;
> >
> > +   /**
> > +* @sharpening_strength_prop: property to apply
> > +* the intensity of the sharpness requested.
> > +*/
> > +   struct drm_property *sharpening_strength_prop;
> > +
> > /**
> >  * @state:
> >  *
> > @@ -1324,4 +1340,5 @@ static inline struct drm_crtc
> > *drm_crtc_find(struct drm_device *dev,  int
> drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc,
> >  

[PATCH] drm/xe/display: fix potential overflow when multiplying 2 u32

[Arun R Murthy]

Multiplying XE_PAGE_SIZE with another u32 and the product stored in
u64 can potentially lead to overflow. Change one of the value to u64 so
as to perform 64 bit arithmetic operation as the product is u64.

Signed-off-by: Arun R Murthy 
---
 drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c 
b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 722c84a56607..c9d26345ae6e 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -29,7 +29,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, 
u32 *dpt_ofs, u32 bo_
u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
 
for (row = 0; row < height; row++) {
-   u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * 
XE_PAGE_SIZE,
+   u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * 
(u64)XE_PAGE_SIZE,
  
xe->pat.idx[XE_CACHE_WB]);
 
iosys_map_wr(map, *dpt_ofs, u64, pte);
@@ -61,7 +61,7 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, 
u32 *dpt_ofs,
 
for (column = 0; column < width; column++) {
iosys_map_wr(map, *dpt_ofs, u64,
-pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
+pte_encode_bo(bo, src_idx * 
(u64)XE_PAGE_SIZE,
 xe->pat.idx[XE_CACHE_WB]));
 
*dpt_ofs += 8;
@@ -118,7 +118,7 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
u32 x;
 
for (x = 0; x < size / XE_PAGE_SIZE; x++) {
-   u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x * 
XE_PAGE_SIZE,
+   u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x * 
(u64)XE_PAGE_SIZE,
  
xe->pat.idx[XE_CACHE_WB]);
 
iosys_map_wr(&dpt->vmap, x * 8, u64, pte);
@@ -164,7 +164,7 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt, 
u32 *ggtt_ofs, u32 bo
u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
 
for (row = 0; row < height; row++) {
-   u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * 
XE_PAGE_SIZE,
+   u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * 
(u64)XE_PAGE_SIZE,
  
xe->pat.idx[XE_CACHE_WB]);
 
xe_ggtt_set_pte(ggtt, *ggtt_ofs, pte);
@@ -381,4 +381,4 @@ struct i915_address_space *intel_dpt_create(struct 
intel_framebuffer *fb)
 void intel_dpt_destroy(struct i915_address_space *vm)
 {
return;
-}
\ No newline at end of file
+}
-- 
2.25.1

Re: [PATCH v5 4/5] drm/i915/psr: Add IO buffer wake times for LunarLake and beyond

[Hogander, Jouni]

On Fri, 2024-03-08 at 16:56 +0200, Ville Syrjälä wrote:
> On Fri, Mar 08, 2024 at 04:39:55PM +0200, Ville Syrjälä wrote:
> > On Fri, Mar 08, 2024 at 01:00:38PM +0200, Jouni Högander wrote:
> > > IO buffer wake time used for IO wake calculation is dependent on
> > > port clock
> > > on LunarLake and beyond. Take this into account in
> > > get_io_buffer_wake_time.
> > > 
> > > Bspec: 65450
> > > 
> > > v2: add own io_wake_time helper for LunarLake
> > > 
> > > Signed-off-by: Jouni Högander 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 14 +-
> > >  1 file changed, 13 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 747761efa4be..e3daaf05d640 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1165,11 +1165,23 @@ static int tgl_io_buffer_wake_time(void)
> > > return 10;
> > >  }
> > >  
> > > +static int lnl_io_buffer_wake_time(int port_clock)
> > > +{
> > > +   if (port_clock > 27)
> > > +   return 10;
> > > +   else if (port_clock > 162000)
> > > +   return 11;
> > > +   else
> > > +   return 15;
> > > +}
> > 
> > These numbers are only listed in the MTL section of bspec. There
> > is nothing like this in the LNL PHY power section AFAICS.
> 
> Windows appears to use fixed 12us here.

Referring our offline discussion with HW folks: It seems 10 us is ok
for LNL as well. What do you think if we just drop this patch as it
seems to be incorrect?

Can you also provide you rb to patch 5 in this set?

BR,

Jouni Högander

> 
> > 
> > > +
> > >  static int io_buffer_wake_time(const struct intel_crtc_state
> > > *crtc_state)
> > >  {
> > > struct drm_i915_private *i915 = to_i915(crtc_state-
> > > >uapi.crtc->dev);
> > >  
> > > -   if (DISPLAY_VER(i915) >= 12)
> > > +   if (DISPLAY_VER(i915) >= 20)
> > > +   return lnl_io_buffer_wake_time(crtc_state-
> > > >port_clock);
> > > +   else if (DISPLAY_VER(i915) >= 12)
> > > return tgl_io_buffer_wake_time();
> > > else
> > > return skl_io_buffer_wake_time();
> > > -- 
> > > 2.34.1
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 

[PATCH] drm/i915/selftests: Pick correct caching mode.

[Nirmoy Das]

Caching mode is HW dependent so pick a correct one using
intel_gt_coherent_map_type().

Cc: Andi Shyti 
Cc: Janusz Krzysztofik 
Cc: Jonathan Cavitt 
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10249
Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
index d684a70f2c04..65a931ea80e9 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
@@ -7,6 +7,7 @@
 #include "i915_drv.h"
 #include "i915_selftest.h"
 #include "gem/i915_gem_context.h"
+#include "gt/intel_gt.h"
 
 #include "mock_context.h"
 #include "mock_dmabuf.h"
@@ -155,6 +156,7 @@ static int verify_access(struct drm_i915_private *i915,
struct file *file;
u32 *vaddr;
int err = 0, i;
+   unsigned int mode;
 
file = mock_file(i915);
if (IS_ERR(file))
@@ -194,7 +196,8 @@ static int verify_access(struct drm_i915_private *i915,
if (err)
goto out_file;
 
-   vaddr = i915_gem_object_pin_map_unlocked(native_obj, I915_MAP_WB);
+   mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true);
+   vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode);
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
goto out_file;
-- 
2.42.0

✗ Fi.CI.IGT: failure for Fix divide-by-zero regression on DP MST unplug with nouveau

[Patchwork]

== Series Details ==

Series: Fix divide-by-zero regression on DP MST unplug with nouveau
URL   : https://patchwork.freedesktop.org/series/131002/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14420_full -> Patchwork_131002v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_131002v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_131002v1_full, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/index.html

Participating hosts (8 -> 9)
--

  Additional (1): shard-snb-0 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_131002v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_eio@context-create:
- shard-dg2:  NOTRUN -> [ABORT][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-dg2-6/igt@gem_...@context-create.html
- shard-dg1:  NOTRUN -> [ABORT][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-dg1-15/igt@gem_...@context-create.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1:
- shard-rkl:  [PASS][3] -> [FAIL][4] +1 other test fail
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-rkl-4/igt@kms_flip@flip-vs-absolute-wf_vbl...@b-hdmi-a1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vbl...@b-hdmi-a1.html

  
Known issues


  Here are the changes found in Patchwork_131002v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg2:  NOTRUN -> [SKIP][5] ([i915#8411])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-dg2-2/igt@api_intel...@blit-reloc-purge-cache.html

  * igt@device_reset@cold-reset-bound:
- shard-dg1:  NOTRUN -> [SKIP][6] ([i915#7701])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-dg1-19/igt@device_re...@cold-reset-bound.html

  * igt@drm_fdinfo@busy-idle-check-all@vcs1:
- shard-dg1:  NOTRUN -> [SKIP][7] ([i915#8414]) +6 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-dg1-14/igt@drm_fdinfo@busy-idle-check-...@vcs1.html

  * igt@drm_fdinfo@busy@bcs0:
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#8414]) +6 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-mtlp-8/igt@drm_fdinfo@b...@bcs0.html

  * igt@drm_fdinfo@context-close-stress:
- shard-rkl:  [PASS][9] -> [ABORT][10] ([i915#10154])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-rkl-5/igt@drm_fdi...@context-close-stress.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-rkl-1/igt@drm_fdi...@context-close-stress.html

  * igt@drm_fdinfo@virtual-idle:
- shard-rkl:  [PASS][11] -> [FAIL][12] ([i915#7742])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-rkl-5/igt@drm_fdi...@virtual-idle.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-rkl-5/igt@drm_fdi...@virtual-idle.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#9323])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-mtlp-8/igt@gem_...@ctrl-surf-copy-new-ctx.html

  * igt@gem_ccs@suspend-resume:
- shard-dg1:  NOTRUN -> [SKIP][14] ([i915#9323])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-dg1-14/igt@gem_...@suspend-resume.html

  * igt@gem_create@create-ext-cpu-access-big:
- shard-dg2:  NOTRUN -> [INCOMPLETE][15] ([i915#9364])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-dg2-2/igt@gem_cre...@create-ext-cpu-access-big.html

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl:  [PASS][16] -> [FAIL][17] ([i915#6268])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-rkl-5/igt@gem_ctx_e...@basic-nohangcheck.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-rkl-5/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_ctx_persistence@hang:
- shard-dg1:  NOTRUN -> [SKIP][18] ([i915#8555])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-dg1-19/igt@gem_ctx_persiste...@hang.html

  * igt@gem_ctx_sseu@invalid-args:
- shard-dg1:  NOTRUN -> [SKIP][19] ([i915#280])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131002v1/shard-dg1-12/

✗ Fi.CI.CHECKPATCH: warning for drm/xe/display: fix potential overflow when multiplying 2 u32

[Patchwork]

== Series Details ==

Series: drm/xe/display: fix potential overflow when multiplying 2 u32
URL   : https://patchwork.freedesktop.org/series/131014/
State : warning

== Summary ==

Error: dim checkpatch failed
6fef8a077711 drm/xe/display: fix potential overflow when multiplying 2 u32
-:31: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#31: FILE: drivers/gpu/drm/xe/display/xe_fb_pin.c:65:
+pte_encode_bo(bo, src_idx * 
(u64)XE_PAGE_SIZE,
 xe->pat.idx[XE_CACHE_WB]));

total: 0 errors, 0 warnings, 1 checks, 38 lines checked

✓ Fi.CI.BAT: success for drm/xe/display: fix potential overflow when multiplying 2 u32

[Patchwork]

== Series Details ==

Series: drm/xe/display: fix potential overflow when multiplying 2 u32
URL   : https://patchwork.freedesktop.org/series/131014/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14420 -> Patchwork_131014v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/index.html

Participating hosts (34 -> 36)
--

  Additional (4): bat-kbl-2 bat-dg2-11 fi-glk-j4005 bat-mtlp-8 
  Missing(2): bat-rpls-3 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_131014v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-cfl-8109u:   [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/fi-cfl-8109u/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/fi-cfl-8109u/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][4] ([i915#1849])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-kbl-2/igt@fb...@info.html

  * igt@gem_exec_parallel@engines@basic:
- bat-arls-2: [PASS][5] -> [ABORT][6] ([i915#10233])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/bat-arls-2/igt@gem_exec_parallel@engi...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-arls-2/igt@gem_exec_parallel@engi...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-glk-j4005:   NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-glk-j4005:   NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][9] +39 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
- bat-adlm-1: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-adlm-1/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4613]) +3 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#4083])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-dg2-11/igt@gem_m...@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#4083])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-mtlp-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4077]) +2 other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-mtlp-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#4079]) +1 other test skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#4077]) +2 other tests skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#4079]) +1 other test skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-dg2-11/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#6621])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-dg2-11/igt@i915_pm_...@basic-api.html
- bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#6621])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html
- bat-adlm-1: NOTRUN -> [SKIP][20] ([i915#6621])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-adlm-1/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][21] ([i915#4212]) +7 other tests skip
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131014v1/bat-dg2-11/igt@kms_addfb_ba...

Re: [PATCH v3 4/6] drm/i915: Extract opregion vbt presence check

[Thomas Weißschuh]

On Wed, Feb 28, 2024 at 01:32:33PM -0800, Radhakrishna Sripada wrote:
> We want to later change intel_opregion_get_vbt to duplicate the vbt
> memory if present, which would be an overkill when we just want to
> peek into the presence of opregion vbt. Carve out the presence check
> into its own function to use in places where only the presence of vbt
> is required.

This doesn't compile when CONFIG_ACPI is not enabled:

  CC [M]  drivers/gpu/drm/xe/i915-display/intel_bios.o
drivers/gpu/drm/i915/display/intel_bios.c: In function 
'intel_bios_is_lvds_present':
drivers/gpu/drm/i915/display/intel_bios.c:3425:24: error: implicit declaration 
of function 'intel_opregion_vbt_present'; did you mean
 'intel_opregion_asle_present'? [-Werror=implicit-function-declaration]
 3425 | return intel_opregion_vbt_present(i915);
  |^~
  |intel_opregion_asle_present
cc1: all warnings being treated as errors

Seen on next-20240312.

> 
> Suggested-by: Jani Nikula 
> Signed-off-by: Radhakrishna Sripada 
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c |  3 +--
>  drivers/gpu/drm/i915/display/intel_opregion.c | 10 ++
>  drivers/gpu/drm/i915/display/intel_opregion.h |  1 +
>  3 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index a66fc79466bd..c283a5a07010 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -3364,8 +3364,7 @@ bool intel_bios_is_lvds_present(struct drm_i915_private 
> *i915, u8 *i2c_pin)
>* additional data.  Trust that if the VBT was written into
>* the OpRegion then they have validated the LVDS's existence.
>*/
> - if (intel_opregion_get_vbt(i915, NULL))
> - return true;
> + return intel_opregion_vbt_present(i915);
>   }
>  
>   return false;
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
> b/drivers/gpu/drm/i915/display/intel_opregion.c
> index 5d07a002edaa..58dfecb617b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -1131,6 +1131,16 @@ const struct drm_edid *intel_opregion_get_edid(struct 
> intel_connector *intel_con
>   return drm_edid;
>  }
>  
> +bool intel_opregion_vbt_present(struct drm_i915_private *i915)
> +{
> + struct intel_opregion *opregion = i915->display.opregion;
> +
> + if (!opregion || !opregion->vbt)
> + return false;
> +
> + return true;
> +}
> +
>  const void *intel_opregion_get_vbt(struct drm_i915_private *i915, size_t 
> *size)
>  {
>   struct intel_opregion *opregion = i915->display.opregion;
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h 
> b/drivers/gpu/drm/i915/display/intel_opregion.h
> index 0bec224f711f..63573c38d735 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> @@ -53,6 +53,7 @@ int intel_opregion_notify_adapter(struct drm_i915_private 
> *dev_priv,
>  int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
>  const struct drm_edid *intel_opregion_get_edid(struct intel_connector 
> *connector);
>  
> +bool intel_opregion_vbt_present(struct drm_i915_private *i915);

This declaration is in a #ifdef CONFIG_ACPI block.

>  const void *intel_opregion_get_vbt(struct drm_i915_private *i915, size_t 
> *size);
>  
>  bool intel_opregion_headless_sku(struct drm_i915_private *i915);
> -- 
> 2.34.1
> 

[PATCH] drm/i915/opregion: add intel_opregion_vbt_present() stub for ACPI=n

[Jani Nikula]

The opregion code needs stubs for ACPI=n. Add the missing stub for
intel_opregion_vbt_present().

Reported-by: Thomas Weißschuh 
Closes: 
https://lore.kernel.org/r/20240312120240-afdb1b83-8517-434b-be79-06f41bafd...@linutronix.de
Fixes: 9d9bb71f3e11 ("drm/i915: Extract opregion vbt presence check")
Cc: Radhakrishna Sripada 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_opregion.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h 
b/drivers/gpu/drm/i915/display/intel_opregion.h
index 63573c38d735..4b2b8e752632 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -120,6 +120,11 @@ intel_opregion_get_edid(struct intel_connector *connector)
return NULL;
 }
 
+static inline bool intel_opregion_vbt_present(struct drm_i915_private *i915)
+{
+   return false;
+}
+
 static inline const void *
 intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size)
 {
-- 
2.39.2

Re: [PATCH v3 4/6] drm/i915: Extract opregion vbt presence check

[Jani Nikula]

On Tue, 12 Mar 2024, Thomas Weißschuh  wrote:
> On Wed, Feb 28, 2024 at 01:32:33PM -0800, Radhakrishna Sripada wrote:
>> We want to later change intel_opregion_get_vbt to duplicate the vbt
>> memory if present, which would be an overkill when we just want to
>> peek into the presence of opregion vbt. Carve out the presence check
>> into its own function to use in places where only the presence of vbt
>> is required.
>
> This doesn't compile when CONFIG_ACPI is not enabled:
>
>   CC [M]  drivers/gpu/drm/xe/i915-display/intel_bios.o
> drivers/gpu/drm/i915/display/intel_bios.c: In function 
> 'intel_bios_is_lvds_present':
> drivers/gpu/drm/i915/display/intel_bios.c:3425:24: error: implicit 
> declaration of function 'intel_opregion_vbt_present'; did you mean
>  'intel_opregion_asle_present'? [-Werror=implicit-function-declaration]
>  3425 | return intel_opregion_vbt_present(i915);
>   |^~
>   |    intel_opregion_asle_present
> cc1: all warnings being treated as errors
>
> Seen on next-20240312.

Thanks for the report, fix at 

https://lore.kernel.org/r/20240312115757.683584-1-jani.nik...@intel.com

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 0/5] drm/i915: cleanup dead code

[Lucas De Marchi]

On Tue, Mar 12, 2024 at 09:54:41AM +, Tvrtko Ursulin wrote:


On 11/03/2024 19:27, Lucas De Marchi wrote:

On Mon, Mar 11, 2024 at 05:43:00PM +, Tvrtko Ursulin wrote:


On 06/03/2024 19:36, Lucas De Marchi wrote:

Remove platforms that never had their PCI IDs added to the driver and
are of course marked with requiring force_probe. Note that most of the
code for those platforms is actually used by subsequent ones, so it's
not a huge amount of code being removed.


I had PVC and xehpsdv back in October but could not collect all acks. :(

Last two patches from https://patchwork.freedesktop.org/series/124705/.


oh... I was actually surprised we still had xehpsdv while removing a
WA for PVC, which made me look into removing these platforms.

rebasing your series and comparing yours..my-v2, where my-v2 only has
patches 2 and 4, I have the diff below. I think it's small enough that I
can just take your commits and squash delta. Is that ok to you?

my version is a little bit more aggressive, also doing some renames
s/xehpsdv/xehp/ and dropping some more code
(engine_mask_apply_copy_fuses(), unused registers, default ctx, fw
ranges).


Right, yeah I see I missed some case combos in the comments when 
grepping and more.


diff --git a/Documentation/gpu/rfc/i915_vm_bind.h 
b/Documentation/gpu/rfc/i915_vm_bind.h

index 8a8fcd4fceac..bc26dc126104 100644
--- a/Documentation/gpu/rfc/i915_vm_bind.h
+++ b/Documentation/gpu/rfc/i915_vm_bind.h
@@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
  * Multiple VA mappings can be created to the same section of 
the object

  * (aliasing).
  *
- * The @start, @offset and @length must be 4K page aligned. 
However the DG2
- * and XEHPSDV has 64K page size for device local memory and 
has compact page
- * table. On those platforms, for binding device local-memory 
objects, the
- * @start, @offset and @length must be 64K aligned. Also, UMDs 
should not mix
- * the local memory 64K page and the system memory 4K page 
bindings in the same

- * 2M range.
+ * The @start, @offset and @length must be 4K page aligned. 
However the DG2 has
+ * 64K page size for device local memory and has compact page 
table. On that
+ * platform, for binding device local-memory objects, the 
@start, @offset and
+ * @length must be 64K aligned. Also, UMDs should not mix the 
local memory 64K

+ * page and the system memory 4K page bindings in the same 2M range.
  *
  * Error code -EINVAL will be returned if @start, @offset and 
@length are not
  * properly aligned. In version 1 (See 
I915_PARAM_VM_BIND_VERSION), error code
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h

index 1495b6074492..d3300ae3053f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -386,7 +386,7 @@ struct drm_i915_gem_object {
 * and kernel mode driver for caching policy control after GEN12.
 * In the meantime platform specific tables are created to 
translate
 * i915_cache_level into pat index, for more details check 
the macros

- * defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.
+ * defined i915/i915_pci.c, e.g. MTL_CACHELEVEL.


Why this?



it was just our different choices while doing the search-and-replace.
It's not that I changed yours, it's that my choice was to go with MTL
and yours to go with TGL. Any of them fit the role here.




 * For backward compatibility, this field contains values 
exactly match
 * the entries of enum i915_cache_level for pre-GEN12 
platforms (See

 * LEGACY_CACHELEVEL), so that the PTE encode functions for these
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c

index fa46d2308b0e..1bd0e041e15c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
 }
 static void
-xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
-  struct i915_vma_resource *vma_res,
-  struct sgt_dma *iter,
-  unsigned int pat_index,
-  u32 flags)
+xehp_ppgtt_insert_huge(struct i915_address_space *vm,
+   struct i915_vma_resource *vma_res,
+   struct sgt_dma *iter,
+   unsigned int pat_index,
+   u32 flags)
 {
    const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
    unsigned int rem = sg_dma_len(iter->sg);
@@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct 
i915_address_space *vm,

    struct sgt_dma iter = sgt_dma(vma_res);
    if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
-    if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
-

✓ Fi.CI.BAT: success for drm/i915/selftests: Pick correct caching mode.

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Pick correct caching mode.
URL   : https://patchwork.freedesktop.org/series/131019/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14420 -> Patchwork_131019v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/index.html

Participating hosts (34 -> 34)
--

  Additional (2): bat-dg2-11 bat-mtlp-8 
  Missing(2): bat-dg1-7 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_131019v1 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-cfl-8109u:   [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/fi-cfl-8109u/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/fi-cfl-8109u/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlm-1: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-adlm-1/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#4083])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-dg2-11/igt@gem_m...@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4083])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-mtlp-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-mtlp-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-dg2-11/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#6621])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-dg2-11/igt@i915_pm_...@basic-api.html
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html
- bat-adlm-1: NOTRUN -> [SKIP][14] ([i915#6621])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-adlm-1/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][15] -> [ABORT][16] ([i915#9662])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#4212]) +7 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#5190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
- bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#5190])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][20] ([i915#4212]) +8 other tests skip
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
- bat-dg2-11: NOTRUN -> [SKIP][21] ([i915#4215] / [i915#5190])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/

Re: [PATCH v2] Fix divide-by-zero regression on DP MST unplug with nouveau

[Imre Deak]

On Mon, Mar 11, 2024 at 11:10:55PM +, Chris Bainbridge wrote:
> Fix a regression when using nouveau and unplugging a StarTech MSTDP122DP
> DisplaypPort 1.2 MST hub (the same regression does not appear when using
> a Cable Matters DisplayPort 1.4 MST hub). Trace:
> 
>  divide error:  [#1] PREEMPT SMP PTI
>  CPU: 7 PID: 2962 Comm: Xorg Not tainted 6.8.0-rc3+ #744
>  Hardware name: Razer Blade/DANA_MB, BIOS 01.01 08/31/2018
>  RIP: 0010:drm_dp_bw_overhead+0xb4/0x110 [drm_display_helper]
>  Code: c6 b8 01 00 00 00 75 61 01 c6 41 0f af f3 41 0f af f1 c1 e1 04 48 63 
> c7 31 d2 89 ff 48 8b 5d f8 c9 48 0f af f1 48 8d 44 06 ff <48> f7 f7 31 d2 31 
> c9 31 f6 31 ff 45 31 c0 45 31 c9 45 31 d2 45 31
>  RSP: 0018:b2c5c211fa30 EFLAGS: 00010206
>  RAX:  RBX:  RCX: 00f59b00
>  RDX:  RSI:  RDI: 
>  RBP: b2c5c211fa48 R08: 0001 R09: 0020
>  R10: 0004 R11:  R12: 00023b4a
>  R13: 91d37d165800 R14: 91d36fac6d80 R15: 91d34a764010
>  FS:  7f4a1ca3fa80() GS:91d6edbc() knlGS:
>  CS:  0010 DS:  ES:  CR0: 80050033
>  CR2: 559491d49000 CR3: 00011d180002 CR4: 003706f0
>  Call Trace:
>   
>   ? show_regs+0x6d/0x80
>   ? die+0x37/0xa0
>   ? do_trap+0xd4/0xf0
>   ? do_error_trap+0x71/0xb0
>   ? drm_dp_bw_overhead+0xb4/0x110 [drm_display_helper]
>   ? exc_divide_error+0x3a/0x70
>   ? drm_dp_bw_overhead+0xb4/0x110 [drm_display_helper]
>   ? asm_exc_divide_error+0x1b/0x20
>   ? drm_dp_bw_overhead+0xb4/0x110 [drm_display_helper]
>   ? drm_dp_calc_pbn_mode+0x2e/0x70 [drm_display_helper]
>   nv50_msto_atomic_check+0xda/0x120 [nouveau]
>   drm_atomic_helper_check_modeset+0xa87/0xdf0 [drm_kms_helper]
>   drm_atomic_helper_check+0x19/0xa0 [drm_kms_helper]
>   nv50_disp_atomic_check+0x13f/0x2f0 [nouveau]
>   drm_atomic_check_only+0x668/0xb20 [drm]
>   ? drm_connector_list_iter_next+0x86/0xc0 [drm]
>   drm_atomic_commit+0x58/0xd0 [drm]
>   ? __pfx___drm_printfn_info+0x10/0x10 [drm]
>   drm_atomic_connector_commit_dpms+0xd7/0x100 [drm]
>   drm_mode_obj_set_property_ioctl+0x1c5/0x450 [drm]
>   ? __pfx_drm_connector_property_set_ioctl+0x10/0x10 [drm]
>   drm_connector_property_set_ioctl+0x3b/0x60 [drm]
>   drm_ioctl_kernel+0xb9/0x120 [drm]
>   drm_ioctl+0x2d0/0x550 [drm]
>   ? __pfx_drm_connector_property_set_ioctl+0x10/0x10 [drm]
>   nouveau_drm_ioctl+0x61/0xc0 [nouveau]
>   __x64_sys_ioctl+0xa0/0xf0
>   do_syscall_64+0x76/0x140
>   ? do_syscall_64+0x85/0x140
>   ? do_syscall_64+0x85/0x140
>   entry_SYSCALL_64_after_hwframe+0x6e/0x76
>  RIP: 0033:0x7f4a1cd1a94f
>  Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 
> 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 c0 3d 00 f0 
> ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00
>  RSP: 002b:7ffd2f1df520 EFLAGS: 0246 ORIG_RAX: 0010
>  RAX: ffda RBX: 7ffd2f1df5b0 RCX: 7f4a1cd1a94f
>  RDX: 7ffd2f1df5b0 RSI: c01064ab RDI: 000f
>  RBP: c01064ab R08: 56347932deb8 R09: 56347a7d99c0
>  R10:  R11: 0246 R12: 56347938a220
>  R13: 000f R14: 563479d9f3f0 R15: 
>   
>  Modules linked in: rfcomm xt_conntrack nft_chain_nat xt_MASQUERADE nf_nat 
> nf_conntrack_netlink nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 xfrm_user 
> xfrm_algo xt_addrtype nft_compat nf_tables nfnetlink br_netfilter bridge stp 
> llc ccm cmac algif_hash overlay algif_skcipher af_alg bnep binfmt_misc 
> snd_sof_pci_intel_cnl snd_sof_intel_hda_common snd_soc_hdac_hda snd_sof_pci 
> snd_sof_xtensa_dsp snd_sof_intel_hda snd_sof snd_sof_utils 
> snd_soc_acpi_intel_match snd_soc_acpi snd_soc_core snd_compress 
> snd_sof_intel_hda_mlink snd_hda_ext_core iwlmvm intel_rapl_msr 
> intel_rapl_common intel_tcc_cooling x86_pkg_temp_thermal intel_powerclamp 
> mac80211 coretemp kvm_intel snd_hda_codec_hdmi kvm snd_hda_codec_realtek 
> snd_hda_codec_generic uvcvideo libarc4 snd_hda_intel snd_intel_dspcfg 
> snd_hda_codec iwlwifi videobuf2_vmalloc videobuf2_memops uvc irqbypass btusb 
> videobuf2_v4l2 snd_seq_midi crct10dif_pclmul hid_multitouch crc32_pclmul 
> snd_seq_midi_event btrtl snd_hwdep videodev polyval_clmulni polyval_generic 
> snd_rawmidi
>   ghash_clmulni_intel aesni_intel btintel crypto_simd snd_hda_core cryptd 
> snd_seq btbcm ee1004 8250_dw videobuf2_common btmtk rapl nls_iso8859_1 
> mei_hdcp thunderbolt bluetooth intel_cstate wmi_bmof intel_wmi_thunderbolt 
> cfg80211 snd_pcm mc snd_seq_device i2c_i801 r8169 ecdh_generic snd_timer 
> i2c_smbus ecc snd mei_me intel_lpss_pci mei ahci intel_lpss soundcore realtek 
> libahci idma64 intel_pch_thermal i2c_hid_acpi i2c_hid acpi_pad sch_fq_codel 
> msr parport_pc ppdev lp parport efi_pstore ip_tables x_tables autofs4 
> dm_crypt raid10 raid456 libcrc32c async_raid6_recov async_memcp

Re: [PATCH v2] Fix divide-by-zero regression on DP MST unplug with nouveau

[Jani Nikula]

On Tue, 12 Mar 2024, Imre Deak  wrote:
> On Mon, Mar 11, 2024 at 11:10:55PM +, Chris Bainbridge wrote:
>> Fix a regression when using nouveau and unplugging a StarTech MSTDP122DP
>> DisplaypPort 1.2 MST hub (the same regression does not appear when using
>> a Cable Matters DisplayPort 1.4 MST hub). Trace:
>> 
>>  divide error:  [#1] PREEMPT SMP PTI
>>  CPU: 7 PID: 2962 Comm: Xorg Not tainted 6.8.0-rc3+ #744
>>  Hardware name: Razer Blade/DANA_MB, BIOS 01.01 08/31/2018
>>  RIP: 0010:drm_dp_bw_overhead+0xb4/0x110 [drm_display_helper]
>>  Code: c6 b8 01 00 00 00 75 61 01 c6 41 0f af f3 41 0f af f1 c1 e1 04 48 63 
>> c7 31 d2 89 ff 48 8b 5d f8 c9 48 0f af f1 48 8d 44 06 ff <48> f7 f7 31 d2 31 
>> c9 31 f6 31 ff 45 31 c0 45 31 c9 45 31 d2 45 31
>>  RSP: 0018:b2c5c211fa30 EFLAGS: 00010206
>>  RAX:  RBX:  RCX: 00f59b00
>>  RDX:  RSI:  RDI: 
>>  RBP: b2c5c211fa48 R08: 0001 R09: 0020
>>  R10: 0004 R11:  R12: 00023b4a
>>  R13: 91d37d165800 R14: 91d36fac6d80 R15: 91d34a764010
>>  FS:  7f4a1ca3fa80() GS:91d6edbc() knlGS:
>>  CS:  0010 DS:  ES:  CR0: 80050033
>>  CR2: 559491d49000 CR3: 00011d180002 CR4: 003706f0
>>  Call Trace:
>>   
>>   ? show_regs+0x6d/0x80
>>   ? die+0x37/0xa0
>>   ? do_trap+0xd4/0xf0
>>   ? do_error_trap+0x71/0xb0
>>   ? drm_dp_bw_overhead+0xb4/0x110 [drm_display_helper]
>>   ? exc_divide_error+0x3a/0x70
>>   ? drm_dp_bw_overhead+0xb4/0x110 [drm_display_helper]
>>   ? asm_exc_divide_error+0x1b/0x20
>>   ? drm_dp_bw_overhead+0xb4/0x110 [drm_display_helper]
>>   ? drm_dp_calc_pbn_mode+0x2e/0x70 [drm_display_helper]
>>   nv50_msto_atomic_check+0xda/0x120 [nouveau]
>>   drm_atomic_helper_check_modeset+0xa87/0xdf0 [drm_kms_helper]
>>   drm_atomic_helper_check+0x19/0xa0 [drm_kms_helper]
>>   nv50_disp_atomic_check+0x13f/0x2f0 [nouveau]
>>   drm_atomic_check_only+0x668/0xb20 [drm]
>>   ? drm_connector_list_iter_next+0x86/0xc0 [drm]
>>   drm_atomic_commit+0x58/0xd0 [drm]
>>   ? __pfx___drm_printfn_info+0x10/0x10 [drm]
>>   drm_atomic_connector_commit_dpms+0xd7/0x100 [drm]
>>   drm_mode_obj_set_property_ioctl+0x1c5/0x450 [drm]
>>   ? __pfx_drm_connector_property_set_ioctl+0x10/0x10 [drm]
>>   drm_connector_property_set_ioctl+0x3b/0x60 [drm]
>>   drm_ioctl_kernel+0xb9/0x120 [drm]
>>   drm_ioctl+0x2d0/0x550 [drm]
>>   ? __pfx_drm_connector_property_set_ioctl+0x10/0x10 [drm]
>>   nouveau_drm_ioctl+0x61/0xc0 [nouveau]
>>   __x64_sys_ioctl+0xa0/0xf0
>>   do_syscall_64+0x76/0x140
>>   ? do_syscall_64+0x85/0x140
>>   ? do_syscall_64+0x85/0x140
>>   entry_SYSCALL_64_after_hwframe+0x6e/0x76
>>  RIP: 0033:0x7f4a1cd1a94f
>>  Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 
>> 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 c0 3d 00 f0 
>> ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00
>>  RSP: 002b:7ffd2f1df520 EFLAGS: 0246 ORIG_RAX: 0010
>>  RAX: ffda RBX: 7ffd2f1df5b0 RCX: 7f4a1cd1a94f
>>  RDX: 7ffd2f1df5b0 RSI: c01064ab RDI: 000f
>>  RBP: c01064ab R08: 56347932deb8 R09: 56347a7d99c0
>>  R10:  R11: 0246 R12: 56347938a220
>>  R13: 000f R14: 563479d9f3f0 R15: 
>>   
>>  Modules linked in: rfcomm xt_conntrack nft_chain_nat xt_MASQUERADE nf_nat 
>> nf_conntrack_netlink nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 xfrm_user 
>> xfrm_algo xt_addrtype nft_compat nf_tables nfnetlink br_netfilter bridge stp 
>> llc ccm cmac algif_hash overlay algif_skcipher af_alg bnep binfmt_misc 
>> snd_sof_pci_intel_cnl snd_sof_intel_hda_common snd_soc_hdac_hda snd_sof_pci 
>> snd_sof_xtensa_dsp snd_sof_intel_hda snd_sof snd_sof_utils 
>> snd_soc_acpi_intel_match snd_soc_acpi snd_soc_core snd_compress 
>> snd_sof_intel_hda_mlink snd_hda_ext_core iwlmvm intel_rapl_msr 
>> intel_rapl_common intel_tcc_cooling x86_pkg_temp_thermal intel_powerclamp 
>> mac80211 coretemp kvm_intel snd_hda_codec_hdmi kvm snd_hda_codec_realtek 
>> snd_hda_codec_generic uvcvideo libarc4 snd_hda_intel snd_intel_dspcfg 
>> snd_hda_codec iwlwifi videobuf2_vmalloc videobuf2_memops uvc irqbypass btusb 
>> videobuf2_v4l2 snd_seq_midi crct10dif_pclmul hid_multitouch crc32_pclmul 
>> snd_seq_midi_event btrtl snd_hwdep videodev polyval_clmulni polyval_generic 
>> snd_rawmidi
>>   ghash_clmulni_intel aesni_intel btintel crypto_simd snd_hda_core cryptd 
>> snd_seq btbcm ee1004 8250_dw videobuf2_common btmtk rapl nls_iso8859_1 
>> mei_hdcp thunderbolt bluetooth intel_cstate wmi_bmof intel_wmi_thunderbolt 
>> cfg80211 snd_pcm mc snd_seq_device i2c_i801 r8169 ecdh_generic snd_timer 
>> i2c_smbus ecc snd mei_me intel_lpss_pci mei ahci intel_lpss soundcore 
>> realtek libahci idma64 intel_pch_thermal i2c_hid_acpi i2c_hid acpi_pad 
>> sch_fq_codel msr parpo

RE: [PATCH] drm/i915/selftests: Pick correct caching mode.

[Cavitt, Jonathan]

-Original Message-
From: Das, Nirmoy  
Sent: Tuesday, March 12, 2024 4:18 AM
To: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org; Das, Nirmoy ; Andi 
Shyti ; Janusz Krzysztofik 
; Cavitt, Jonathan 

Subject: [PATCH] drm/i915/selftests: Pick correct caching mode.
> 
> Caching mode is HW dependent so pick a correct one using
> intel_gt_coherent_map_type().
> 
> Cc: Andi Shyti 
> Cc: Janusz Krzysztofik 
> Cc: Jonathan Cavitt 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10249
> Signed-off-by: Nirmoy Das 

LGTM
Acked-by: Jonathan Cavitt 
-Jonathan Cavitt

> ---
>  drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c 
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> index d684a70f2c04..65a931ea80e9 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> @@ -7,6 +7,7 @@
>  #include "i915_drv.h"
>  #include "i915_selftest.h"
>  #include "gem/i915_gem_context.h"
> +#include "gt/intel_gt.h"
>  
>  #include "mock_context.h"
>  #include "mock_dmabuf.h"
> @@ -155,6 +156,7 @@ static int verify_access(struct drm_i915_private *i915,
>   struct file *file;
>   u32 *vaddr;
>   int err = 0, i;
> + unsigned int mode;
>  
>   file = mock_file(i915);
>   if (IS_ERR(file))
> @@ -194,7 +196,8 @@ static int verify_access(struct drm_i915_private *i915,
>   if (err)
>   goto out_file;
>  
> - vaddr = i915_gem_object_pin_map_unlocked(native_obj, I915_MAP_WB);
> + mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true);
> + vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode);
>   if (IS_ERR(vaddr)) {
>   err = PTR_ERR(vaddr);
>   goto out_file;
> -- 
> 2.42.0
> 
> 

Re: [RFC 0/5] Introduce drm sharpening property

[Pekka Paalanen]

On Tue, 12 Mar 2024 08:30:34 +
"Garg, Nemesa"  wrote:

> This  KMS property is not implementing any formula

Sure it is. Maybe Intel just does not want to tell what the algorithm
is, or maybe it's even patented.

> and the values
> that are being used are based on empirical analysis and certain
> experiments done on the hardware. These values are fixed and is not
> expected to change and this can change from vendor to vendor. The
> client can choose any sharpness value on the scale and on the basis
> of it the sharpness will be set. The sharpness effect can be changed
> from content to content and from display to display so user needs to
> adjust the optimum intensity value so as to get good experience on
> the screen.
> 

IOW, it's an opaque box operation, and there is no way to reproduce its
results without the specific Intel hardware. Definitely no way to
reproduce its results in free open source software alone.

Such opaque box operations can only occur after KMS blending, at the
CRTC or later stage. They cannot appear before blending, not in the new
KMS color pipeline design at least. The reason is that the modern way
to use KMS planes is opportunistic composition off-loading.
Opportunistic means that userspace decides from time to time whether it
composes the final picture using KMS or some other rendering method
(usually GPU and shaders). Since userspace will arbitrarily switch
between KMS and render composition, both must result in the exact same
image, or end users will observe unwanted flicker.

Such opaque box operations are fine after blending, because there they
can be configured once and remain on forever. No switching, no flicker.

Where does "sharpeness" operation occur in the Intel color processing
chain? Is it before or after blending?

What kind of transfer characteristics does it expect from the image,
and can those be realized with KMS CRTC properties if KMS is configured
such that the blending happens using some other characteristics (e.g.
blending in optical space)?

What about SDR vs. HDR imagery?


Thanks,
pq

> > -Original Message-
> > From: dri-devel  On Behalf Of Simon
> > Ser
> > Sent: Monday, March 4, 2024 7:46 PM
> > To: Garg, Nemesa 
> > Cc: Pekka Paalanen ; intel-
> > g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; G M, Adarsh
> > 
> > Subject: RE: [RFC 0/5] Introduce drm sharpening property
> > 
> > On Monday, March 4th, 2024 at 15:04, Garg, Nemesa 
> > wrote:
> >   
> > > This is generic as sharpness effect is applied post blending.
> > > Depending on the color gamut, pixel format and other inputs the image
> > > gets blended and once we get blended output it can be sharpened based
> > > on strength value provided by the user.  
> > 
> > It would really help if you could provide the exact mathematical formula 
> > applied
> > by this KMS property.  



pgptrYTGwkIr1.pgp
Description: OpenPGP digital signature

Re: [PATCH] drm/i915/selftests: Pick correct caching mode.

[Andi Shyti]

Hi Nirmoy,

On Tue, Mar 12, 2024 at 12:18:15PM +0100, Nirmoy Das wrote:
> Caching mode is HW dependent so pick a correct one using
> intel_gt_coherent_map_type().
> 
> Cc: Andi Shyti 
> Cc: Janusz Krzysztofik 
> Cc: Jonathan Cavitt 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10249
> Signed-off-by: Nirmoy Das 

I think it's a good choice not to have the Fixes tag here either.

Reviewed-by: Andi Shyti 

Thanks,
Andi

[RFC 0/7] drm/i915: pass encoder around more for port/phy checks

[Jani Nikula]

Based on my ideas at [1], pass the encoder around more instead of i915,
port pair. Look up phy and TC port based on encoder.

This could be later extended to e.g. cache the info to encoder and/or
look up data from encoder->devdata.

I know relying solely on encoder has its drawbacks, namely not being
able to do stuff unless you have that encoder for that specific
port/phy. And have a reference to it.

Thoughts?

BR,
Jani.


[1] https://lore.kernel.org/r/87y1dnswgo@intel.com

Jani Nikula (7):
  drm/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin()
  drm/i915/ddi: pass encoder to intel_wait_ddi_buf_active()
  drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state()
  drm/i915/display: add intel_encoder_is_*() and _to_*() functions
  drm/i915/display: use intel_encoder_is/to_* functions
  drm/i915/cx0: remove intel_is_c10phy()
  drm/i915/cx0: pass encoder instead of i915 and port around

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 299 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c  | 127 
 .../drm/i915/display/intel_ddi_buf_trans.c|  14 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  40 +++
 drivers/gpu/drm/i915/display/intel_display.h  |   7 +
 .../i915/display/intel_display_power_well.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |  15 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  22 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c |  80 ++---
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  14 +-
 drivers/gpu/drm/i915/display/intel_psr.c  |   7 +-
 drivers/gpu/drm/i915/display/intel_snps_phy.c |  16 +-
 drivers/gpu/drm/i915/display/intel_snps_phy.h |   4 +-
 drivers/gpu/drm/i915/display/intel_tc.c   |  33 +-
 15 files changed, 339 insertions(+), 344 deletions(-)

-- 
2.39.2

[RFC 1/7] drm/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin()

[Jani Nikula]

Pass encoder to the _port_to_ddc_pin() functions, and rename to
_encoder_to_ddc_pin().

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 60 ++-
 1 file changed, 37 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 90d2236fede3..f1fc9669238f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2664,8 +2664,9 @@ bool intel_hdmi_handle_sink_scrambling(struct 
intel_encoder *encoder,
drm_scdc_set_scrambling(connector, scrambling);
 }
 
-static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port 
port)
+static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   enum port port = encoder->port;
u8 ddc_pin;
 
switch (port) {
@@ -2686,8 +2687,9 @@ static u8 chv_port_to_ddc_pin(struct drm_i915_private 
*dev_priv, enum port port)
return ddc_pin;
 }
 
-static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port 
port)
+static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   enum port port = encoder->port;
u8 ddc_pin;
 
switch (port) {
@@ -2705,9 +2707,9 @@ static u8 bxt_port_to_ddc_pin(struct drm_i915_private 
*dev_priv, enum port port)
return ddc_pin;
 }
 
-static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
- enum port port)
+static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   enum port port = encoder->port;
u8 ddc_pin;
 
switch (port) {
@@ -2731,8 +2733,10 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private 
*dev_priv,
return ddc_pin;
 }
 
-static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port 
port)
+static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
 
if (intel_phy_is_combo(dev_priv, phy))
@@ -2744,8 +2748,10 @@ static u8 icl_port_to_ddc_pin(struct drm_i915_private 
*dev_priv, enum port port)
return GMBUS_PIN_2_BXT;
 }
 
-static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port 
port)
+static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
u8 ddc_pin;
 
@@ -2767,8 +2773,10 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private 
*dev_priv, enum port port)
return ddc_pin;
 }
 
-static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port 
port)
+static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
 
WARN_ON(port == PORT_C);
@@ -2785,8 +2793,10 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private 
*dev_priv, enum port port)
return GMBUS_PIN_1_BXT + phy;
 }
 
-static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port 
port)
+static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
enum phy phy = intel_port_to_phy(i915, port);
 
drm_WARN_ON(&i915->drm, port == PORT_A);
@@ -2803,13 +2813,18 @@ static u8 gen9bc_tgp_port_to_ddc_pin(struct 
drm_i915_private *i915, enum port po
return GMBUS_PIN_1_BXT + phy;
 }
 
-static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port 
port)
+static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
+
return intel_port_to_phy(dev_priv, port) + 1;
 }
 
-static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port 
port)
+static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
 
WARN_ON(port == PORT_B || port == PORT_C);
@@ -2824,9 +2839,9 @@ static u8 adls_port_to_ddc_pin(struct drm_i915_private 
*dev_priv, enum port port
return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
 }
 
-static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
- enum port port)
+static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder)
 {
+   enum port port = encoder->port;
u8 ddc_pin;
 
switch (port) {
@@ -2850,30 +2865,29 @@ static u8 g4x_port_to_ddc_pin(struct drm_i915_private 
*dev_priv,
 s

[RFC 2/7] drm/i915/ddi: pass encoder to intel_wait_ddi_buf_active()

[Jani Nikula]

Pass encoder to intel_wait_ddi_buf_active().

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c587a8efeafc..fe00c34b5127 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -200,9 +200,10 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private 
*dev_priv,
port_name(port));
 }
 
-static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
- enum port port)
+static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
 {
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
int timeout_us;
int ret;
@@ -3354,7 +3355,7 @@ static void intel_enable_ddi_hdmi(struct 
intel_atomic_state *state,
 
intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
 
-   intel_wait_ddi_buf_active(dev_priv, port);
+   intel_wait_ddi_buf_active(encoder);
 }
 
 static void intel_enable_ddi(struct intel_atomic_state *state,
@@ -3574,7 +3575,7 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp 
*intel_dp,
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 
/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
-   intel_wait_ddi_buf_active(dev_priv, port);
+   intel_wait_ddi_buf_active(encoder);
 }
 
 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
@@ -3624,7 +3625,7 @@ static void intel_ddi_prepare_link_retrain(struct 
intel_dp *intel_dp,
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 
-   intel_wait_ddi_buf_active(dev_priv, port);
+   intel_wait_ddi_buf_active(encoder);
 }
 
 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
-- 
2.39.2

[RFC 3/7] drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state()

[Jani Nikula]

Pass encoder to intel_snps_phy_update_psr_power_state().

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_psr.c  | 7 ++-
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 6 --
 drivers/gpu/drm/i915/display/intel_snps_phy.h | 4 ++--
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 6927785fd6ff..9d28ca0c630c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1700,7 +1700,6 @@ static void intel_psr_enable_locked(struct intel_dp 
*intel_dp,
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-   enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
u32 val;
 
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
@@ -1728,7 +1727,7 @@ static void intel_psr_enable_locked(struct intel_dp 
*intel_dp,
drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
intel_dp->psr.psr2_enabled ? "2" : "1");
 
-   intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
+   intel_snps_phy_update_psr_power_state(&dig_port->base, true);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state);
intel_dp->psr.enabled = true;
@@ -1799,8 +1798,6 @@ static void intel_psr_disable_locked(struct intel_dp 
*intel_dp)
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
-   enum phy phy = intel_port_to_phy(dev_priv,
-dp_to_dig_port(intel_dp)->base.port);
 
lockdep_assert_held(&intel_dp->psr.lock);
 
@@ -1835,7 +1832,7 @@ static void intel_psr_disable_locked(struct intel_dp 
*intel_dp)
 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
}
 
-   intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
+   intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, 
false);
 
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c 
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index bc61e736f9b3..7fc002268482 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -44,9 +44,11 @@ void intel_snps_phy_wait_for_calibration(struct 
drm_i915_private *i915)
}
 }
 
-void intel_snps_phy_update_psr_power_state(struct drm_i915_private *i915,
-  enum phy phy, bool enable)
+void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,
+  bool enable)
 {
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   enum phy phy = intel_port_to_phy(i915, encoder->port);
u32 val;
 
if (!intel_phy_is_snps(i915, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h 
b/drivers/gpu/drm/i915/display/intel_snps_phy.h
index 515abf7c5902..bc08b92a7cd9 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h
@@ -17,8 +17,8 @@ struct intel_mpllb_state;
 enum phy;
 
 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv);
-void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
-  enum phy phy, bool enable);
+void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,
+  bool enable);
 
 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
   struct intel_encoder *encoder);
-- 
2.39.2

[RFC 4/7] drm/i915/display: add intel_encoder_is_*() and _to_*() functions

[Jani Nikula]

Add a number of encoder based functions to check if the port/phy of the
encoder is of a certain type, or to convert to phy or tc_port. Initially
these are just wrappers around the existing functions, but they can be
improved to use VBT data or use some cached info in the future.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  9 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 +
 drivers/gpu/drm/i915/display/intel_display.c | 40 
 drivers/gpu/drm/i915/display/intel_display.h |  7 
 4 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 64e0f820a789..f0ae2fe70c41 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -29,6 +29,7 @@
 #define INTEL_CX0_LANE1BIT(1)
 #define INTEL_CX0_BOTH_LANES   (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
 
+/* Prefer intel_encoder_is_c10phy() */
 bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
 {
if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
@@ -37,6 +38,14 @@ bool intel_is_c10phy(struct drm_i915_private *i915, enum phy 
phy)
return false;
 }
 
+bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
+{
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   enum phy phy = intel_encoder_to_phy(encoder);
+
+   return intel_is_c10phy(i915, phy);
+}
+
 static int lane_mask_to_lane(u8 lane_mask)
 {
if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) ||
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c6682677253a..2be474877fdc 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -23,6 +23,7 @@ struct intel_encoder;
 struct intel_hdmi;
 
 bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
+bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
  const struct intel_crtc_state *crtc_state);
 void intel_mtl_pll_disable(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index b88f214e111a..9911aebb37fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1836,6 +1836,7 @@ static void i9xx_pfit_enable(const struct 
intel_crtc_state *crtc_state)
intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
 }
 
+/* Prefer intel_encoder_is_combo() */
 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
if (phy == PHY_NONE)
@@ -1857,6 +1858,7 @@ bool intel_phy_is_combo(struct drm_i915_private 
*dev_priv, enum phy phy)
return false;
 }
 
+/* Prefer intel_encoder_is_tc() */
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
/*
@@ -1877,6 +1879,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, 
enum phy phy)
return false;
 }
 
+/* Prefer intel_encoder_is_snps() */
 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
 {
/*
@@ -1886,6 +1889,7 @@ bool intel_phy_is_snps(struct drm_i915_private *dev_priv, 
enum phy phy)
return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E;
 }
 
+/* Prefer intel_encoder_to_phy() */
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
@@ -1903,6 +1907,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, 
enum port port)
return PHY_A + port - PORT_A;
 }
 
+/* Prefer intel_encoder_to_tc() */
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port 
port)
 {
if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
@@ -1914,6 +1919,41 @@ enum tc_port intel_port_to_tc(struct drm_i915_private 
*dev_priv, enum port port)
return TC_PORT_1 + port - PORT_C;
 }
 
+enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
+{
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+   return intel_port_to_phy(i915, encoder->port);
+}
+
+bool intel_encoder_is_combo(struct intel_encoder *encoder)
+{
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+   return intel_phy_is_combo(i915, intel_encoder_to_phy(encoder));
+}
+
+bool intel_encoder_is_snps(struct intel_encoder *encoder)
+{
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+   return intel_phy_is_snps(i915, intel_encoder_to_phy(encoder));
+}
+
+bool intel_encoder_is_tc(struct intel_encoder *encoder)
+{
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+   return intel_phy_is_tc(i915, intel_encoder_to_phy(encoder));
+}
+
+enum tc_port intel_encoder_to_tc(struct intel_encoder 

[RFC 5/7] drm/i915/display: use intel_encoder_is/to_* functions

[Jani Nikula]

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  36 ++
 drivers/gpu/drm/i915/display/intel_ddi.c  | 116 +++---
 .../drm/i915/display/intel_ddi_buf_trans.c|  14 +--
 .../i915/display/intel_display_power_well.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |  15 +--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  22 ++--
 drivers/gpu/drm/i915/display/intel_hdmi.c |  38 +++---
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  14 +--
 drivers/gpu/drm/i915/display/intel_snps_phy.c |  12 +-
 drivers/gpu/drm/i915/display/intel_tc.c   |  33 ++---
 10 files changed, 110 insertions(+), 192 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f0ae2fe70c41..f893db353f91 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -423,7 +423,6 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_ddi_buf_trans *trans;
-   enum phy phy = intel_port_to_phy(i915, encoder->port);
u8 owned_lane_mask;
intel_wakeref_t wakeref;
int n_entries, ln;
@@ -442,7 +441,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder 
*encoder,
return;
}
 
-   if (intel_is_c10phy(i915, phy)) {
+   if (intel_encoder_is_c10phy(encoder)) {
intel_cx0_rmw(i915, encoder->port, owned_lane_mask, 
PHY_C10_VDR_CONTROL(1),
  0, C10_VDR_CTRL_MSGBUS_ACCESS, 
MB_WRITE_COMMITTED);
intel_cx0_rmw(i915, encoder->port, owned_lane_mask, 
PHY_C10_VDR_CMN(3),
@@ -483,7 +482,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder 
*encoder,
  0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
  MB_WRITE_COMMITTED);
 
-   if (intel_is_c10phy(i915, phy))
+   if (intel_encoder_is_c10phy(encoder))
intel_cx0_rmw(i915, encoder->port, owned_lane_mask, 
PHY_C10_VDR_CONTROL(1),
  0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
 
@@ -2046,10 +2045,8 @@ static int intel_c20_phy_check_hdmi_link_rate(int clock)
 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
 {
struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
-   struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);
-   enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
-   if (intel_is_c10phy(i915, phy))
+   if (intel_encoder_is_c10phy(&dig_port->base))
return intel_c10_phy_check_hdmi_link_rate(clock);
return intel_c20_phy_check_hdmi_link_rate(clock);
 }
@@ -2097,10 +2094,7 @@ static int intel_c20pll_calc_state(struct 
intel_crtc_state *crtc_state,
 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
 {
-   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-   enum phy phy = intel_port_to_phy(i915, encoder->port);
-
-   if (intel_is_c10phy(i915, phy))
+   if (intel_encoder_is_c10phy(encoder))
return intel_c10pll_calc_state(crtc_state, encoder);
return intel_c20pll_calc_state(crtc_state, encoder);
 }
@@ -2652,7 +2646,7 @@ static void intel_cx0_program_phy_lane(struct 
drm_i915_private *i915,
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
enum port port = encoder->port;
 
-   if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
+   if (intel_encoder_is_c10phy(encoder))
intel_cx0_rmw(i915, port, owned_lane_mask,
  PHY_C10_VDR_CONTROL(1), 0,
  C10_VDR_CTRL_MSGBUS_ACCESS,
@@ -2681,7 +2675,7 @@ static void intel_cx0_program_phy_lane(struct 
drm_i915_private *i915,
  MB_WRITE_COMMITTED);
}
 
-   if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
+   if (intel_encoder_is_c10phy(encoder))
intel_cx0_rmw(i915, port, owned_lane_mask,
  PHY_C10_VDR_CONTROL(1), 0,
  C10_VDR_CTRL_UPDATE_CFG,
@@ -2744,7 +2738,7 @@ static void intel_cx0pll_enable(struct intel_encoder 
*encoder,
 */
 
/* 5. Program PHY internal PLL internal registers. */
-   if (intel_is_c10phy(i915, phy))
+   if (intel_encoder_is_c10phy(encoder))
intel_c10_pll_program(i915, crtc_state, encoder);
else
intel_c20_pll_program(i915, crtc_state, encoder);
@@ -2902,7 +2896,7 @@ static void intel_cx0pll_disable(struct intel_encoder 
*encoder)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
-   bool is_c10 = intel_is_c10phy(i915, phy);
+

[RFC 6/7] drm/i915/cx0: remove intel_is_c10phy()

[Jani Nikula]

Unused.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 --
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 --
 2 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f893db353f91..b88ffc75cf4a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -29,21 +29,15 @@
 #define INTEL_CX0_LANE1BIT(1)
 #define INTEL_CX0_BOTH_LANES   (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
 
-/* Prefer intel_encoder_is_c10phy() */
-bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
-{
-   if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
-   return true;
-
-   return false;
-}
-
 bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_encoder_to_phy(encoder);
 
-   return intel_is_c10phy(i915, phy);
+   if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
+   return true;
+
+   return false;
 }
 
 static int lane_mask_to_lane(u8 lane_mask)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 2be474877fdc..3e03af3e006c 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -11,7 +11,6 @@
 #include 
 
 enum icl_port_dpll_id;
-enum phy;
 struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_c10pll_state;
@@ -22,7 +21,6 @@ struct intel_crtc_state;
 struct intel_encoder;
 struct intel_hdmi;
 
-bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
 bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
  const struct intel_crtc_state *crtc_state);
-- 
2.39.2

[RFC 7/7] drm/i915/cx0: pass encoder instead of i915 and port around

[Jani Nikula]

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 258 ++-
 1 file changed, 136 insertions(+), 122 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b88ffc75cf4a..d2e4439562e3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -49,8 +49,7 @@ static int lane_mask_to_lane(u8 lane_mask)
return ilog2(lane_mask);
 }
 
-static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
-   struct intel_encoder *encoder)
+static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)
 {
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
@@ -117,16 +116,20 @@ static void intel_cx0_phy_transaction_end(struct 
intel_encoder *encoder, intel_w
intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref);
 }
 
-static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
-   enum port port, int lane)
+static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
+   int lane)
 {
-   intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+   intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, 
lane),
 0, XELPDP_PORT_P2M_RESPONSE_READY | 
XELPDP_PORT_P2M_ERROR_SET);
 }
 
-static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, 
int lane)
+static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
 {
-   enum phy phy = intel_port_to_phy(i915, port);
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
+   enum phy phy = intel_encoder_to_phy(encoder);
 
intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
   XELPDP_PORT_M2P_TRANSACTION_RESET);
@@ -138,13 +141,15 @@ static void intel_cx0_bus_reset(struct drm_i915_private 
*i915, enum port port, i
return;
}
 
-   intel_clear_response_ready_flag(i915, port, lane);
+   intel_clear_response_ready_flag(encoder, lane);
 }
 
-static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port 
port,
+static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
  int command, int lane, u32 *val)
 {
-   enum phy phy = intel_port_to_phy(i915, port);
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
+   enum phy phy = intel_encoder_to_phy(encoder);
 
if (__intel_de_wait_for_register(i915,
 XELPDP_PORT_P2M_MSGBUS_STATUS(i915, 
port, lane),
@@ -161,31 +166,33 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private 
*i915, enum port port,
"PHY %c Hardware did not detect a 
timeout\n",
phy_name(phy));
 
-   intel_cx0_bus_reset(i915, port, lane);
+   intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
}
 
if (*val & XELPDP_PORT_P2M_ERROR_SET) {
drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s 
command. Status: 0x%x\n", phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? 
"read" : "write", *val);
-   intel_cx0_bus_reset(i915, port, lane);
+   intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
}
 
if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {
drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS 
Status: 0x%x.\n", phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? 
"read" : "write", *val);
-   intel_cx0_bus_reset(i915, port, lane);
+   intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
}
 
return 0;
 }
 
-static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
+static int __intel_cx0_read_once(struct intel_encoder *encoder,
 int lane, u16 addr)
 {
-   enum phy phy = intel_port_to_phy(i915, port);
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   enum port port = encoder->port;
+   enum phy phy = intel_encoder_to_phy(encoder);
int ack;
u32 val;
 
@@ -194,7 +201,7 @@ static int __intel_cx0_read_once(struct drm_i915_private 
*i915, enum port port,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
"PHY %c Timeout waiting for previous transaction to 
complete. Reset the bus and retry.\n", phy_name(phy)

Re: ✗ Fi.CI.IGT: failure for drm/i915/dp: Fix DSC state HW readout for SST connectors

[Imre Deak]

On Tue, Mar 12, 2024 at 09:03:03AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/dp: Fix DSC state HW readout for SST connectors
> URL   : https://patchwork.freedesktop.org/series/130986/
> State : failure

Thanks for the review, pushed to drm-intel-next with the Closes: gitlab
issue line added. The failures are unrelated see below.

> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_14420_full -> Patchwork_130986v1_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_130986v1_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_130986v1_full, please notify your bug team 
> (i915-ci-in...@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (8 -> 8)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_130986v1_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@gem_eio@context-create:
> - shard-dg2:  NOTRUN -> [ABORT][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130986v1/shard-dg2-5/igt@gem_...@context-create.html
> - shard-dg1:  NOTRUN -> [ABORT][2]
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130986v1/shard-dg1-19/igt@gem_...@context-create.html

<4> [237.045073] ==
<4> [237.045078] WARNING: possible circular locking dependency detected
<4> [237.045083] 6.8.0-Patchwork_130986v1-g61fa386186cb+ #1 Tainted: G U

<4> [237.045089] --
<4> [237.045094] gem_eio/937 is trying to acquire lock:
<4> [237.045098] 88812d46b640 (&hwmon->hwmon_lock){+.+.}-{3:3}, at: 
i915_hwmon_power_max_disable+0x43/0xb0 [i915]
<4> [237.045255] 
but task is already holding lock:
<4> [237.045260] 88810de2d8f0 (>->reset.mutex){+.+.}-{3:3}, at: 
intel_gt_reset+0x181/0x480 [i915]

No DP connectors on the above DG1, where the patch would make a difference.
The issue is already filed at:
https://gitlab.freedesktop.org/drm/intel/-/issues/10404
and
https://gitlab.freedesktop.org/drm/intel/-/issues/10367

>   * igt@gem_exec_await@wide-contexts:
> - shard-dg2:  NOTRUN -> [INCOMPLETE][3]
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130986v1/shard-dg2-6/igt@gem_exec_aw...@wide-contexts.html

Connection lost after a series of GEM tests, no DP connector on the machine.

>   * igt@gem_exec_capture@capture@ccs0-smem:
> - shard-dg2:  [PASS][4] -> [INCOMPLETE][5]
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-dg2-2/igt@gem_exec_capture@capt...@ccs0-smem.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130986v1/shard-dg2-2/igt@gem_exec_capture@capt...@ccs0-smem.html

Connection lost after a series of GEM tests, no DP connector on the machine.

>   * igt@i915_module_load@reload-with-fault-injection:
> - shard-tglu: [PASS][6] -> [INCOMPLETE][7]
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-tglu-3/igt@i915_module_l...@reload-with-fault-injection.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130986v1/shard-tglu-9/igt@i915_module_l...@reload-with-fault-injection.html

<6>[  129.204916] i915 :00:02.0: [drm:__i915_inject_probe_error [i915]] 
Injecting failure -19 at checkpoint 15 [intel_connector_register:121]
...
<4>[  129.209885] i915 :00:02.0: drm_WARN_ON(power_domains->init_wakeref)

No DP connectors. The issue is missing error handling during DRM connector
registration, filed at:
https://gitlab.freedesktop.org/drm/intel/-/issues/10047

>   * igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1:
> - shard-rkl:  [PASS][8] -> [FAIL][9] +1 other test fail
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-rkl-4/igt@kms_flip@flip-vs-absolute-wf_vbl...@b-hdmi-a1.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130986v1/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vbl...@b-hdmi-a1.html

No DP connectors on the machine.

> 
>   * igt@kms_pm_rpm@cursor-dpms:
> - shard-dg2:  [PASS][10] -> [ABORT][11]
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-dg2-6/igt@kms_pm_...@cursor-dpms.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130986v1/shard-dg2-7/igt@kms_pm_...@cursor-dpms.html

<4> [384.860378] ==
<4> [384.860381] WARNING: possible circular locking dependency detected
<4> [384.860384] 6.8.0-Patchwork_130986v1-g61fa386186cb+ #1 Not tainted
<4> [384.860389] 

Re: [PATCH] drm/i915/selftests: Pick correct caching mode.

[Nirmoy Das]

On 3/12/2024 3:28 PM, Andi Shyti wrote:

Hi Nirmoy,

On Tue, Mar 12, 2024 at 12:18:15PM +0100, Nirmoy Das wrote:

Caching mode is HW dependent so pick a correct one using
intel_gt_coherent_map_type().

Cc: Andi Shyti 
Cc: Janusz Krzysztofik 
Cc: Jonathan Cavitt 
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10249
Signed-off-by: Nirmoy Das 

I think it's a good choice not to have the Fixes tag here either.


Yes,  fixes tag isn't needed for selftests




Reviewed-by: Andi Shyti 


Thanks,

Nirmoy



Thanks,
Andi

[PATCH v2] drm/i915/gem: Execbuffer objects must have struct pages.

[Jonathan Cavitt]

We cannot write requests to objects without struct pages, so escape
early if the requests are bound to objects that lack them.

Signed-off-by: Jonathan Cavitt 
---

v2: s/vma-obj/vma->obj

 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3a771afb083e..adb4f9e78cb49 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -3313,6 +3313,13 @@ eb_requests_create(struct i915_execbuffer *eb, struct 
dma_fence *in_fence,
unsigned int i;
 
for_each_batch_create_order(eb, i) {
+   /* Do not write requests to objects without struct pages. */
+   if (eb->batches[i]->vma &&
+   !i915_gem_object_has_struct_page(eb->batches[i]->vma->obj)) 
{
+   out_fence = ERR_PTR(-EINVAL);
+   return out_fence;
+   }
+
/* Allocate a request for this batch buffer nice and early. */
eb->requests[i] = i915_request_create(eb_find_context(eb, i));
if (IS_ERR(eb->requests[i])) {
-- 
2.25.1

Re: ✗ Fi.CI.IGT: failure for drm/i915/hwmon: Fix locking inversion in sysfs getter (rev2)

[Janusz Krzysztofik]

Hi Bug Filing,

On Tuesday, 12 March 2024 11:02:19 CET Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/hwmon: Fix locking inversion in sysfs getter (rev2)
> URL   : https://patchwork.freedesktop.org/series/130966/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_14420_full -> Patchwork_130966v2_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_130966v2_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_130966v2_full, please notify your bug team 
> (i915-ci-in...@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (8 -> 9)
> --
> 
>   Additional (1): shard-snb-0 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_130966v2_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-a-hdmi-a-4:
> - shard-dg1:  [PASS][1] -> [INCOMPLETE][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-dg1-16/igt@kms_cursor_edge_walk@256x256-top-bot...@pipe-a-hdmi-a-4.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-dg1-14/igt@kms_cursor_edge_walk@256x256-top-bot...@pipe-a-hdmi-a-4.html

In CI buglog there are quite a few incompletes from kms_* tests executed on 
DG1 with no filters assigned yet, and one of them specifically from a very 
similar igt@kms_cursor_edge_walk@256x256-left-edge subtest.  Since kms_* tests 
are not related to i915 hwmon code touched by my patch, I think that's an 
unrelated issue reported here as a possible regression.  Please update CI 
buglog filters and re-report.

Thanks,
Janusz


> New tests
> -
> 
>   New tests have been introduced between CI_DRM_14420_full and 
> Patchwork_130966v2_full:
> 
> ### New IGT tests (1) ###
> 
>   * igt@kms_cursor_crc@cursor-rapid-movement-256x256@pipe-d-dp-4:
> - Statuses : 1 pass(s)
> - Exec time: [0.40] s
> 
>   
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_130966v2_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@api_intel_bb@blit-reloc-purge-cache:
> - shard-dg2:  NOTRUN -> [SKIP][3] ([i915#8411])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-dg2-11/igt@api_intel...@blit-reloc-purge-cache.html
> 
>   * igt@device_reset@cold-reset-bound:
> - shard-dg1:  NOTRUN -> [SKIP][4] ([i915#7701])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-dg1-18/igt@device_re...@cold-reset-bound.html
> 
>   * igt@drm_fdinfo@busy-hang@rcs0:
> - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#8414]) +12 other tests 
> skip
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-mtlp-7/igt@drm_fdinfo@busy-h...@rcs0.html
> 
>   * igt@drm_fdinfo@busy-idle-check-all@vcs1:
> - shard-dg1:  NOTRUN -> [SKIP][6] ([i915#8414]) +11 other tests 
> skip
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-dg1-17/igt@drm_fdinfo@busy-idle-check-...@vcs1.html
> 
>   * igt@drm_fdinfo@busy-idle@bcs0:
> - shard-dg2:  NOTRUN -> [SKIP][7] ([i915#8414]) +20 other tests 
> skip
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-dg2-7/igt@drm_fdinfo@busy-i...@bcs0.html
> 
>   * igt@drm_fdinfo@virtual-idle:
> - shard-rkl:  [PASS][8] -> [FAIL][9] ([i915#7742])
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-rkl-5/igt@drm_fdi...@virtual-idle.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-rkl-3/igt@drm_fdi...@virtual-idle.html
> 
>   * igt@gem_busy@semaphore:
> - shard-dg2:  NOTRUN -> [SKIP][10] ([i915#3936])
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-dg2-7/igt@gem_b...@semaphore.html
> - shard-dg1:  NOTRUN -> [SKIP][11] ([i915#3936])
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-dg1-19/igt@gem_b...@semaphore.html
> 
>   * igt@gem_ccs@block-copy-compressed:
> - shard-mtlp: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#9323])
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-mtlp-7/igt@gem_...@block-copy-compressed.html
> 
>   * igt@gem_ccs@ctrl-surf-copy-new-ctx:
> - shard-mtlp: NOTRUN -> [SKIP][13] ([i915#9323])
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130966v2/shard-mtlp-7/igt@gem_...@ctrl-surf-copy-new-ctx.html
> 
>   * igt@gem_ccs@suspend-resume:
> - shard-dg1:  NOTRUN -> [SKIP][14] ([i

RE: [PATCH] drm/i915/opregion: add intel_opregion_vbt_present() stub for ACPI=n

[Sripada, Radhakrishna]

LGTM,
Reviewed-by: Radhakrishna Sripada 

> -Original Message-
> From: Nikula, Jani 
> Sent: Tuesday, March 12, 2024 4:58 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Thomas Weißschuh
> ; Sripada, Radhakrishna
> 
> Subject: [PATCH] drm/i915/opregion: add intel_opregion_vbt_present() stub for
> ACPI=n
> 
> The opregion code needs stubs for ACPI=n. Add the missing stub for
> intel_opregion_vbt_present().
> 
> Reported-by: Thomas Weißschuh 
> Closes: https://lore.kernel.org/r/20240312120240-afdb1b83-8517-434b-be79-
> 06f41bafd...@linutronix.de
> Fixes: 9d9bb71f3e11 ("drm/i915: Extract opregion vbt presence check")
> Cc: Radhakrishna Sripada 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/intel_opregion.h | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h
> b/drivers/gpu/drm/i915/display/intel_opregion.h
> index 63573c38d735..4b2b8e752632 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> @@ -120,6 +120,11 @@ intel_opregion_get_edid(struct intel_connector
> *connector)
>   return NULL;
>  }
> 
> +static inline bool intel_opregion_vbt_present(struct drm_i915_private *i915)
> +{
> + return false;
> +}
> +
>  static inline const void *
>  intel_opregion_get_vbt(struct drm_i915_private *i915, size_t *size)
>  {
> --
> 2.39.2

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

[Matt Roper]

On Thu, Mar 07, 2024 at 06:01:29PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison 
> 
> An existing workaround has been extended in both platforms affected
> and implementation complexity.
> 
> Signed-off-by: John Harrison 
> ---
>  drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h |  3 ++-
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c|  3 ++-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 21 ++-
>  3 files changed, 15 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> index bebf28e3c4794..3e7060e859794 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> @@ -105,7 +105,8 @@ enum {
>   * Workaround keys:
>   */
>  enum {
> - GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
> 0x9001,
> + GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
> 0x9001,   /* Wa_14019159160 */
> + GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE = 
> 0x9006,   /* Wa_14019159160 */
>  };
>  
>  #endif /* _ABI_GUC_KLVS_ABI_H */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 0c67d674c94de..4c3dae98656af 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -296,7 +296,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>  
>   /* Wa_16019325821 */
>   /* Wa_14019159160 */
> - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
> + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||

>From what I can see, this workaround is also needed on Xe_LPG+ (12.74)
now.


Matt

> + IS_DG2(gt->i915))
>   flags |= GUC_WA_RCS_CCS_SWITCHOUT;
>  
>   /*
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 5c9908b56616e..00fe3c21a9b1c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -815,23 +815,23 @@ guc_capture_prep_lists(struct intel_guc *guc)
>   return PAGE_ALIGN(total_size);
>  }
>  
> -/* Wa_14019159160 */
> -static u32 guc_waklv_ra_mode(struct intel_guc *guc, u32 offset, u32 remain)
> +static void guc_waklv_enable_simple(struct intel_guc *guc, u32 *offset, u32 
> *remain, u32 klv_id)
>  {
>   u32 size;
>   u32 klv_entry[] = {
>   /* 16:16 key/length */
> - FIELD_PREP(GUC_KLV_0_KEY, 
> GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE) |
> + FIELD_PREP(GUC_KLV_0_KEY, klv_id) |
>   FIELD_PREP(GUC_KLV_0_LEN, 0),
>   /* 0 dwords data */
>   };
>  
>   size = sizeof(klv_entry);
> - GEM_BUG_ON(remain < size);
> + GEM_BUG_ON(*remain < size);
>  
> - iosys_map_memcpy_to(&guc->ads_map, offset, klv_entry, size);
> + iosys_map_memcpy_to(&guc->ads_map, *offset, klv_entry, size);
>  
> - return size;
> + *offset += size;
> + *remain -= size;
>  }
>  
>  static void guc_waklv_init(struct intel_guc *guc)
> @@ -850,10 +850,11 @@ static void guc_waklv_init(struct intel_guc *guc)
>   remain = guc_ads_waklv_size(guc);
>  
>   /* Wa_14019159160 */
> - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
> - size = guc_waklv_ra_mode(guc, offset, remain);
> - offset += size;
> - remain -= size;
> + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
> IS_DG2(gt->i915)) {
> + guc_waklv_enable_simple(guc, &offset, &remain,
> + GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE);
> + guc_waklv_enable_simple(guc, &offset, &remain,
> + 
> GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE);
>   }
>  
>   size = guc_ads_waklv_size(guc) - remain;
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2] drm/i915/hwmon: Fix locking inversion in sysfs getter

[Dixit, Ashutosh]

On Mon, 11 Mar 2024 13:34:58 -0700, Janusz Krzysztofik wrote:
>
> In i915 hwmon sysfs getter path we now take a hwmon_lock, then acquire an
> rpm wakeref.  That results in lock inversion:
>
> <4> [197.079335] ==
> <4> [197.085473] WARNING: possible circular locking dependency detected
> <4> [197.091611] 6.8.0-rc7-Patchwork_129026v7-gc4dc92fb1152+ #1 Not tainted
> <4> [197.098096] --
> <4> [197.104231] prometheus-node/839 is trying to acquire lock:
> <4> [197.109680] 82764d80 (fs_reclaim){+.+.}-{0:0}, at: 
> __kmalloc+0x9a/0x350
> <4> [197.116939]
> but task is already holding lock:
> <4> [197.122730] 88811b772a40 (&hwmon->hwmon_lock){+.+.}-{3:3}, at: 
> hwm_energy+0x4b/0x100 [i915]
> <4> [197.131543]
> which lock already depends on the new lock.
> ...
> <4> [197.507922] Chain exists of:
>   fs_reclaim --> >->reset.mutex --> &hwmon->hwmon_lock
> <4> [197.518528]  Possible unsafe locking scenario:
> <4> [197.524411]CPU0CPU1
> <4> [197.528916]
> <4> [197.533418]   lock(&hwmon->hwmon_lock);
> <4> [197.537237]lock(>->reset.mutex);
> <4> [197.543376]lock(&hwmon->hwmon_lock);
> <4> [197.549682]   lock(fs_reclaim);
> ...
> <4> [197.632548] Call Trace:
> <4> [197.634990]  
> <4> [197.637088]  dump_stack_lvl+0x64/0xb0
> <4> [197.640738]  check_noncircular+0x15e/0x180
> <4> [197.652968]  check_prev_add+0xe9/0xce0
> <4> [197.656705]  __lock_acquire+0x179f/0x2300
> <4> [197.660694]  lock_acquire+0xd8/0x2d0
> <4> [197.673009]  fs_reclaim_acquire+0xa1/0xd0
> <4> [197.680478]  __kmalloc+0x9a/0x350
> <4> [197.689063]  acpi_ns_internalize_name.part.0+0x4a/0xb0
> <4> [197.694170]  acpi_ns_get_node_unlocked+0x60/0xf0
> <4> [197.720608]  acpi_ns_get_node+0x3b/0x60
> <4> [197.724428]  acpi_get_handle+0x57/0xb0
> <4> [197.728164]  acpi_has_method+0x20/0x50
> <4> [197.731896]  acpi_pci_set_power_state+0x43/0x120
> <4> [197.736485]  pci_power_up+0x24/0x1c0
> <4> [197.740047]  pci_pm_default_resume_early+0x9/0x30
> <4> [197.744725]  pci_pm_runtime_resume+0x2d/0x90
> <4> [197.753911]  __rpm_callback+0x3c/0x110
> <4> [197.762586]  rpm_callback+0x58/0x70
> <4> [197.766064]  rpm_resume+0x51e/0x730
> <4> [197.769542]  rpm_resume+0x267/0x730
> <4> [197.773020]  rpm_resume+0x267/0x730
> <4> [197.776498]  rpm_resume+0x267/0x730
> <4> [197.779974]  __pm_runtime_resume+0x49/0x90
> <4> [197.784055]  __intel_runtime_pm_get+0x19/0xa0 [i915]
> <4> [197.789070]  hwm_energy+0x55/0x100 [i915]
> <4> [197.793183]  hwm_read+0x9a/0x310 [i915]
> <4> [197.797124]  hwmon_attr_show+0x36/0x120
> <4> [197.800946]  dev_attr_show+0x15/0x60
> <4> [197.804509]  sysfs_kf_seq_show+0xb5/0x100
>
> Acquire the wakeref before the lock and hold it as long as the lock is
> also held.  Follow that pattern across the whole source file where similar
> lock inversion can happen.
>
> v2: Keep hardware read under the lock so the whole operation of updating
> energy from hardware is still atomic (Guenter),
>   - instead, acquire the rpm wakeref before the lock and hold it as long
> as the lock is held,
>   - use the same aproach for other similar places across the i915_hwmon.c
> source file (Rodrigo).
>
> Fixes: c41b8bdcc297 ("drm/i915/hwmon: Show device level energy usage")

I would think that the lock inversion issue was introduced here:

1b44019a93e2 ("drm/i915/guc: Disable PL1 power limit when loading GuC firmware")

This is the commit which introduced this sequence:
lock(>->reset.mutex);
lock(&hwmon->hwmon_lock);

Before this, everything was fine. So perhaps the Fixes tag should reference
this commit?

Otherwise the patch LGTM:

Reviewed-by: Ashutosh Dixit 

Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv

[Lucas De Marchi]

On Mon, Mar 11, 2024 at 11:16:06AM -0400, Rodrigo Vivi wrote:

On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:

PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.

The registers not used anymore are also removed.

Signed-off-by: Lucas De Marchi 
---

Potential problem here that needs a deeper look, the changes in
__gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
I removed them, but it needs to be double checked with spec and CI
results.


I have checked the specs and your patch looks right because those
bits should be reserved for DG2.

But the main issue I see is that we were using that (wrongly?) for
DG2 so far. So it probably deserves a separate patch anyway.

With this patch only removing the comments and a separate patch
to remove that for DG2 (and standalone CI run on that patch by itself):


After double checking I think the main issue is that the changed table
became wrong since it poke holes. From the docs:

 * All platforms' forcewake tables below must be sorted by offset ranges.
 * Furthermore, new forcewake tables added should be "watertight" and hav
 * no gaps between ranges.


I *think* this would be the more correct change:

@@ -1533,21 +1533,16 @@ static const struct intel_forcewake_range 
__gen12_fw_ranges[] = {
0x12000 - 0x127ff: always on
\
0x12800 - 0x12fff: reserved */  
\
GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */  
\
-   GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /*  
\
+   GEN_FW_RANGE(0x13200, 0x147ff, FORCEWAKE_MEDIA_VDBOX2), /*  
\
0x13200 - 0x133ff: VD2 (DG2 only)   
\
-   0x13400 - 0x13fff: reserved */  
\
-   GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only 
*/  \
-   GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only 
*/  \
-   GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only 
*/  \
-   GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only 
*/  \
+   0x13400 - 0x147ff: reserved */  
\
GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),   
\
GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*
\
0x15000 - 0x15fff: gt (DG2 only)
\
0x16000 - 0x16dff: reserved */  
\
-   GEN_FW_RANGE(0x16e00, 0x1, FORCEWAKE_RENDER),   
\
-   GEN_FW_RANGE(0x2, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*  
\
-   0x2 - 0x20fff: VD0 (XEHPSDV only)   
\
-   0x21000 - 0x21fff: reserved */  
\
+   GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /*
\
+   0x16e00 - 0x1: render   
\
+   0x2 - 0x21fff: reserved */  
\
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),   
\
GEN_FW_RANGE(0x24000, 0x2417f, 0), /*   
\
0x24000 - 0x2407f: always on
\

did you find any access on DG2 within the reserved ranges?

Lucas De Marchi



Reviewed-by: Rodrigo Vivi 



 Documentation/gpu/rfc/i915_vm_bind.h  | 11 +--
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  | 40 
 drivers/gpu/drm/i915/gt/intel_gsc.c   | 15 ---
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 20 +---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 50 --
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   | 21 ++--
 drivers/gpu/drm/i915/gt/intel_lrc.c   | 43 -
 drivers/gpu/drm/i915/gt/intel_migrate.c   | 18 ++--
 drivers/gpu/drm/i915/gt/intel_mocs.c  | 31 --
 drivers/gpu/drm/i915/gt/intel_rps.c   |  2 -
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 95 ---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  4 +-
 drivers/gpu/drm/i915/i915_drv.h   |  4 -
 drivers/gpu/drm/i915/i915_hwmon.c |  6 --
 drivers/gpu/drm/i915/i915_pci.c   | 17 
 drivers/gpu/drm/i915/i915_perf.c  | 11 +--
 drivers/gpu/drm/i915/i915_reg.h   |  3 +-
 drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
 drivers/gpu/drm/i915/intel_device_info.c  |  1 -
 drivers/gpu/drm/i915/intel_device_info.h  |  1 -
 drivers/gpu/drm/i915/intel_step.c | 10 --
 drivers/gpu/drm/i915/intel_uncore.c   | 15 +--
 drivers/gpu

[PATCH v2 0/8] Enable LNL display

[Gustavo Sousa]

This series aims at providing the remaining patches for enabling display
on Lunar Lake, which used Xe2LPD display IP.

The first set of patches contains fixes and extra stuff required for
supporting CDCLK on Xe2LPD:

drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_table
drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()
drm/i915/cdclk: Only compute squash waveform when necessary
drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()
drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state
drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changes

Then we have a single patch that enables loading Xe2LPD DMC, which is
already available in linux-firmware:

drm/i915/xe2lpd: Load DMC

Finally, we have the last patch, which enables display for LNL:

drm/xe/lnl: Enable display support

v2:
 - Incorporated review feedback. Please see individual patches for details.

--
Gustavo Sousa

Balasubramani Vivekanandan (2):
  drm/i915/xe2lpd: Load DMC
  drm/xe/lnl: Enable display support

Gustavo Sousa (6):
  drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_table
  drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()
  drm/i915/cdclk: Only compute squash waveform when necessary
  drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()
  drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state
  drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changes

 drivers/gpu/drm/i915/display/intel_cdclk.c| 76 +--
 drivers/gpu/drm/i915/display/intel_cdclk.h|  5 ++
 drivers/gpu/drm/i915/display/intel_dmc.c  |  9 ++-
 drivers/gpu/drm/i915/display/skl_watermark.c  | 74 ++
 drivers/gpu/drm/i915/display/skl_watermark.h  |  4 +
 .../gpu/drm/i915/display/skl_watermark_regs.h | 18 +++--
 drivers/gpu/drm/i915/i915_reg.h   |  4 +-
 drivers/gpu/drm/xe/xe_pci.c   |  1 +
 8 files changed, 162 insertions(+), 29 deletions(-)

-- 
2.44.0

[PATCH v2 1/8] drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_table

[Gustavo Sousa]

The CDCLK table is tied to Xe2LPD display and not to the platform. Let's
rename lnl_cdclk_table to xe2lpd_cdclk_table in order to reflect that.

Reviewed-by: Matt Roper 
Signed-off-by: Gustavo Sousa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 5b2688d8c644..be268c6abe21 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1417,7 +1417,7 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
{}
 };
 
-static const struct intel_cdclk_vals lnl_cdclk_table[] = {
+static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = {
{ .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0x },
{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
@@ -3703,7 +3703,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
 {
if (DISPLAY_VER(dev_priv) >= 20) {
dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
-   dev_priv->display.cdclk.table = lnl_cdclk_table;
+   dev_priv->display.cdclk.table = xe2lpd_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 14) {
dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
-- 
2.44.0

[PATCH v2 2/8] drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()

[Gustavo Sousa]

Currently, only Xe2LPD uses CDCLK PLL as the source of MDCLK and
previous display IPs use the CD2XCLK. There will be changes in code
paths common to those platforms that will rely on which source is being
used. As such, let's make that information explicit with the addition of
the predicate function mdclk_source_is_cdclk_pll().

Arguably, an enum could be created, but using a boolean should suffice
here, since we there are only two possible sources and the logic that
will rely on it will be very localized.

In order to get the code into a more consistent state, let's also take
this opportunity to hook the selection of CDCLK_CTL's "MDCLK Source
Select" to that new function. Even though currently only
MDCLK_SOURCE_SEL_CDCLK_PLL will be returned, having this extra logic is
arguably better than keeping stuff untied and prone to bugs.

v2:
  - Extract mdclk_source_is_cdclk_pll() out of xe2lpd_mdclk_source_sel()
to make latter only about the register's field.

Bspec: 69090
Cc: Matt Roper 
Signed-off-by: Gustavo Sousa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 15 ++-
 drivers/gpu/drm/i915/i915_reg.h|  4 +++-
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index be268c6abe21..ad0f03e51e4a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1876,6 +1876,19 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
return vco == ~0;
 }
 
+static bool mdclk_source_is_cdclk_pll(struct drm_i915_private *i915)
+{
+   return DISPLAY_VER(i915) >= 20;
+}
+
+static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
+{
+   if (mdclk_source_is_cdclk_pll(i915))
+   return MDCLK_SOURCE_SEL_CDCLK_PLL;
+
+   return MDCLK_SOURCE_SEL_CD2XCLK;
+}
+
 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private 
*i915,
const struct 
intel_cdclk_config *old_cdclk_config,
const struct 
intel_cdclk_config *new_cdclk_config,
@@ -1980,7 +1993,7 @@ static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
 
if (DISPLAY_VER(i915) >= 20)
-   val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
+   val |= xe2lpd_mdclk_source_sel(i915);
else
val |= skl_cdclk_decimal(cdclk);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8823531b8770..d6193c858a74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5891,7 +5891,9 @@ enum skl_power_gate {
 #define  CDCLK_FREQ_540REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
 #define  CDCLK_FREQ_337_308REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
 #define  CDCLK_FREQ_675_617REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
-#define  MDCLK_SOURCE_SEL_CDCLK_PLLREG_BIT(25)
+#define  MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
+#define  MDCLK_SOURCE_SEL_CD2XCLK  REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
+#define  MDCLK_SOURCE_SEL_CDCLK_PLLREG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
 #define  BXT_CDCLK_CD2X_DIV_SEL_MASK   REG_GENMASK(23, 22)
 #define  BXT_CDCLK_CD2X_DIV_SEL_1  
REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
 #define  BXT_CDCLK_CD2X_DIV_SEL_1_5
REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
-- 
2.44.0

[PATCH v2 3/8] drm/i915/cdclk: Only compute squash waveform when necessary

[Gustavo Sousa]

It is no use computing the squash waveform if we are not going to use
it. Move the call to cdclk_squash_waveform() inside the block guarded by
HAS_CDCLK_SQUASH(dev_priv).

v2:
  - Move "u16 waveform" declaration to inside the block where it is
initialized and used. (Matt)

Reviewed-by: Matt Roper 
Signed-off-by: Gustavo Sousa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad0f03e51e4a..354a9dba6440 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2006,7 +2006,6 @@ static void _bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
 {
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
-   u16 waveform;
 
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && 
vco > 0 &&
!cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
@@ -2021,10 +2020,11 @@ static void _bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
} else
bxt_cdclk_pll_update(dev_priv, vco);
 
-   waveform = cdclk_squash_waveform(dev_priv, cdclk);
+   if (HAS_CDCLK_SQUASH(dev_priv)) {
+   u16 waveform = cdclk_squash_waveform(dev_priv, cdclk);
 
-   if (HAS_CDCLK_SQUASH(dev_priv))
dg2_cdclk_squash_program(dev_priv, waveform);
+   }
 
intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, 
cdclk_config, pipe));
 
-- 
2.44.0

[PATCH v2 4/8] drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()

[Gustavo Sousa]

As of Xe2LPD, it is now possible to select the source of the MDCLK
as either the CD2XCLK or the CDCLK PLL.

Previous display IPs were hardcoded to use the CD2XCLK. For those, the
ratio between MDCLK and CDCLK remained constant, namely 2. For Xe2LPD,
when we select the CDCLK PLL as the source, the ratio will vary
according to the squashing configuration (since the cd2x divisor is
fixed for all supported configurations).

To help the transition to supporting changes in the ratio, extract the
function intel_dbuf_mdclk_cdclk_ratio_update() from the existing logic
and call it using 2 as hardcoded ratio. Upcoming changes will use that
function for updates in the ratio due to CDCLK changes.

Bspec: 50057, 69445, 49213, 68868
Reviewed-by: Matt Roper 
Signed-off-by: Gustavo Sousa 
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 30 +---
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c 
b/drivers/gpu/drm/i915/display/skl_watermark.c
index c6b9be80d83c..d9e49cd60d3a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3530,6 +3530,21 @@ int intel_dbuf_init(struct drm_i915_private *i915)
return 0;
 }
 
+static void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915,
+   u8 ratio,
+   bool joined_mbus)
+{
+   enum dbuf_slice slice;
+
+   if (joined_mbus)
+   ratio *= 2;
+
+   for_each_dbuf_slice(i915, slice)
+   intel_de_rmw(i915, DBUF_CTL_S(slice),
+DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
+}
+
 /*
  * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state 
before
  * update the request state of all DBUS slices.
@@ -3537,8 +3552,7 @@ int intel_dbuf_init(struct drm_i915_private *i915)
 static void update_mbus_pre_enable(struct intel_atomic_state *state)
 {
struct drm_i915_private *i915 = to_i915(state->base.dev);
-   u32 mbus_ctl, dbuf_min_tracker_val;
-   enum dbuf_slice slice;
+   u32 mbus_ctl;
const struct intel_dbuf_state *dbuf_state =
intel_atomic_get_new_dbuf_state(state);
 
@@ -3549,24 +3563,18 @@ static void update_mbus_pre_enable(struct 
intel_atomic_state *state)
 * TODO: Implement vblank synchronized MBUS joining changes.
 * Must be properly coordinated with dbuf reprogramming.
 */
-   if (dbuf_state->joined_mbus) {
+   if (dbuf_state->joined_mbus)
mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_NONE;
-   dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
-   } else {
+   else
mbus_ctl = MBUS_HASHING_MODE_2x2 |
MBUS_JOIN_PIPE_SELECT_NONE;
-   dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
-   }
 
intel_de_rmw(i915, MBUS_CTL,
 MBUS_HASHING_MODE_MASK | MBUS_JOIN |
 MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
 
-   for_each_dbuf_slice(i915, slice)
-   intel_de_rmw(i915, DBUF_CTL_S(slice),
-DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
-dbuf_min_tracker_val);
+   intel_dbuf_mdclk_cdclk_ratio_update(i915, 2, dbuf_state->joined_mbus);
 }
 
 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
-- 
2.44.0

[PATCH v2 5/8] drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state

[Gustavo Sousa]

Xe2LPD always selects the CDCLK PLL as source for the MDCLK. Because of
that, the ratio between MDCLK and CDCLK is not be constant anymore. As
such, make sure to have the current ratio available in intel_dbuf_state
so that it can be used during dbuf programming.

Note that we write-lock the global state instead of serializing to a
hardware commit because a change in the ratio should be rather handled
in the CDCLK change sequence, which will need to take care of updating
the necessary registers in that case. We will implement that in upcoming
changes.

That said, changes in the MBus joining state should be handled by the
DBUF/MBUS logic, just like it is already done, but the logic will need
to know the ratio to properly update the registers.

v2:
  - Make first sentence of commit message more intelligible. (Matt)

Reviewed-by: Matt Roper 
Signed-off-by: Gustavo Sousa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c   | 20 
 drivers/gpu/drm/i915/display/intel_cdclk.h   |  2 ++
 drivers/gpu/drm/i915/display/skl_watermark.c | 18 +-
 drivers/gpu/drm/i915/display/skl_watermark.h |  3 +++
 4 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 354a9dba6440..4e143082dca1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -39,6 +39,7 @@
 #include "intel_pcode.h"
 #include "intel_psr.h"
 #include "intel_vdsc.h"
+#include "skl_watermark.h"
 #include "vlv_sideband.h"
 
 /**
@@ -1889,6 +1890,16 @@ static u32 xe2lpd_mdclk_source_sel(struct 
drm_i915_private *i915)
return MDCLK_SOURCE_SEL_CD2XCLK;
 }
 
+u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+  const struct intel_cdclk_config *cdclk_config)
+{
+   if (mdclk_source_is_cdclk_pll(i915))
+   return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
+
+   /* Otherwise, source for MDCLK is CD2XCLK. */
+   return 2;
+}
+
 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private 
*i915,
const struct 
intel_cdclk_config *old_cdclk_config,
const struct 
intel_cdclk_config *new_cdclk_config,
@@ -3278,6 +3289,15 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
*state)
"Modeset required for cdclk change\n");
}
 
+   if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
+   intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
+   u8 ratio = intel_mdclk_cdclk_ratio(dev_priv, 
&new_cdclk_state->actual);
+
+   ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
+   if (ret)
+   return ret;
+   }
+
drm_dbg_kms(&dev_priv->drm,
"New cdclk calculated to be logical %u kHz, actual %u 
kHz\n",
new_cdclk_state->logical.cdclk,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h 
b/drivers/gpu/drm/i915/display/intel_cdclk.h
index fa301495e7f1..8e6e302bd599 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -62,6 +62,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
 u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
   const struct intel_cdclk_config *b);
+u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+  const struct intel_cdclk_config *cdclk_config);
 void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
 void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
 void intel_cdclk_dump_config(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c 
b/drivers/gpu/drm/i915/display/skl_watermark.c
index d9e49cd60d3a..4410e21888ad 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3057,6 +3057,8 @@ static void skl_wm_get_hw_state(struct drm_i915_private 
*i915)
if (HAS_MBUS_JOINING(i915))
dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & 
MBUS_JOIN;
 
+   dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(i915, 
&i915->display.cdclk.hw);
+
for_each_intel_crtc(&i915->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -3530,6 +3532,19 @@ int intel_dbuf_init(struct drm_i915_private *i915)
return 0;
 }
 
+int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, 
u8 ratio)
+{
+   struct intel_dbuf_state *dbuf_state;
+
+   dbuf_state = intel_atomic_get_dbuf_state(state);
+   if (IS_ERR(dbuf_state))
+   retu

[PATCH v2 7/8] drm/i915/xe2lpd: Load DMC

[Gustavo Sousa]

From: Balasubramani Vivekanandan 

Load DMC for Xe2LPD. The value 0x8000 is the maximum payload size for
any Xe2LPD DMC firmware.

v2:
  - s/XE2LPD_MAX_FW_SIZE/XE2LPD_DMC_MAX_FW_SIZE/. (Lucas)

Signed-off-by: Balasubramani Vivekanandan 
Signed-off-by: Dnyaneshwar Bhadane 
Reviewed-by: Lucas De Marchi 
Signed-off-by: Gustavo Sousa 
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 835781624482..3fa851b5c7a6 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -89,10 +89,14 @@ static struct intel_dmc *i915_to_dmc(struct 
drm_i915_private *i915)
__stringify(major) "_"  \
__stringify(minor) ".bin"
 
+#define XE2LPD_DMC_MAX_FW_SIZE 0x8000
 #define XELPDP_DMC_MAX_FW_SIZE 0x7000
 #define DISPLAY_VER13_DMC_MAX_FW_SIZE  0x2
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE  ICL_DMC_MAX_FW_SIZE
 
+#define XE2LPD_DMC_PATHDMC_PATH(xe2lpd)
+MODULE_FIRMWARE(XE2LPD_DMC_PATH);
+
 #define MTL_DMC_PATH   DMC_PATH(mtl)
 MODULE_FIRMWARE(MTL_DMC_PATH);
 
@@ -987,7 +991,10 @@ void intel_dmc_init(struct drm_i915_private *i915)
 
INIT_WORK(&dmc->work, dmc_load_work_fn);
 
-   if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
+   if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) {
+   dmc->fw_path = XE2LPD_DMC_PATH;
+   dmc->max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
+   } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
dmc->fw_path = MTL_DMC_PATH;
dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
} else if (IS_DG2(i915)) {
-- 
2.44.0

[PATCH v2 6/8] drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changes

[Gustavo Sousa]

Commit 394b4b7df9f7 ("drm/i915/lnl: Add CDCLK table") and commit
3d3696c0fed1 ("drm/i915/lnl: Start using CDCLK through PLL") started
adding support for CDCLK programming support for Xe2LPD. One final piece
is missing, which is the programming necessary for changed in the ratio
between MDCLK and CDCLK. Let's do that now.

BSpec instructs us to update MBUS_CTL and DBUF_CTL_S* registers when the
ratio between MDCLK and CDCLK changes. The updates must be done before
changing the CDCLK when decreasing the frequency; or after it when
increasing the frequency.

Ratio-related updates to MBUS_CTL also depend on the state of MBus
joining, so they are performed by either CDCLK change sequence or by
changes in MBus joining. Since one might happen independently of the
other, we need to make sure that both logics see the necessary state
values when programming that register. MBus joining logic needs to know
the MDCLK:CDCLK ratio and that's already provided via mdclk_cdclk_ratio
field of struct intel_dbuf_state.

For the CDCLK logic, we need to have something similar: we need to
propagate the status of MBus joining to struct intel_cdclk_state. Do
that by adding the field joined_mbus to struct intel_cdclk_config.
(Preferably, that field would be added to intel_cdclk_state, however
currently only intel_cdclk_config is passed down to the functions that
do the register programming. We might revisit this decision if we find
that refactoring the code to pass the whole intel_cdclk_state is worth
it.)

Bspec: 68864, 68868, 69090, 69482
Reviewed-by: Stanislav Lisovskiy 
Signed-off-by: Gustavo Sousa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c| 31 ++
 drivers/gpu/drm/i915/display/intel_cdclk.h|  3 ++
 drivers/gpu/drm/i915/display/skl_watermark.c  | 40 +++
 drivers/gpu/drm/i915/display/skl_watermark.h  |  1 +
 .../gpu/drm/i915/display/skl_watermark_regs.h | 18 +
 5 files changed, 77 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4e143082dca1..31aaa9780dfc 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -40,6 +40,7 @@
 #include "intel_psr.h"
 #include "intel_vdsc.h"
 #include "skl_watermark.h"
+#include "skl_watermark_regs.h"
 #include "vlv_sideband.h"
 
 /**
@@ -1683,6 +1684,8 @@ static void bxt_get_cdclk(struct drm_i915_private 
*dev_priv,
}
 
  out:
+   if (DISPLAY_VER(dev_priv) >= 20)
+   cdclk_config->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & 
MBUS_JOIN;
/*
 * Can't read this out :( Let's assume it's
 * at least what the CDCLK frequency requires.
@@ -1900,6 +1903,14 @@ u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
return 2;
 }
 
+static void xe2lpd_mdclk_cdclk_ratio_program(struct drm_i915_private *i915,
+const struct intel_cdclk_config 
*cdclk_config)
+{
+   intel_dbuf_mdclk_cdclk_ratio_update(i915,
+   intel_mdclk_cdclk_ratio(i915, 
cdclk_config),
+   cdclk_config->joined_mbus);
+}
+
 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private 
*i915,
const struct 
intel_cdclk_config *old_cdclk_config,
const struct 
intel_cdclk_config *new_cdclk_config,
@@ -2080,6 +2091,9 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
return;
}
 
+   if (DISPLAY_VER(dev_priv) >= 20 && cdclk < 
dev_priv->display.cdclk.hw.cdclk)
+   xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config);
+
if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, 
&dev_priv->display.cdclk.hw,
cdclk_config, 
&mid_cdclk_config)) {
_bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
@@ -2088,6 +2102,9 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
_bxt_set_cdclk(dev_priv, cdclk_config, pipe);
}
 
+   if (DISPLAY_VER(dev_priv) >= 20 && cdclk > 
dev_priv->display.cdclk.hw.cdclk)
+   xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config);
+
if (DISPLAY_VER(dev_priv) >= 14)
/*
 * NOOP - No Pcode communication needed for
@@ -3170,6 +3187,20 @@ int intel_cdclk_atomic_check(struct intel_atomic_state 
*state,
return 0;
 }
 
+int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool 
joined_mbus)
+{
+   struct intel_cdclk_state *cdclk_state;
+
+   cdclk_state = intel_atomic_get_cdclk_state(state);
+   if (IS_ERR(cdclk_state))
+   return PTR_ERR(cdclk_state);
+
+   cdclk_state->actual.joined_mbus = joined_mbus;
+   cdclk_state->logical.joined_mbus = joined_mbus;
+
+   r

[PATCH v2 8/8] drm/xe/lnl: Enable display support

[Gustavo Sousa]

From: Balasubramani Vivekanandan 

Enable display support for Lunar Lake.

Signed-off-by: Balasubramani Vivekanandan 
Signed-off-by: Lucas De Marchi 
Reviewed-by: Lucas De Marchi 
Signed-off-by: Gustavo Sousa 
---
 drivers/gpu/drm/xe/xe_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 986c07d8b168..3c94154051a8 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -333,6 +333,7 @@ static const struct xe_device_desc mtl_desc = {
 
 static const struct xe_device_desc lnl_desc = {
PLATFORM(XE_LUNARLAKE),
+   .has_display = true,
.require_force_probe = true,
 };
 
-- 
2.44.0

Re: [PATCH v5 5/5] drm/i915/display: Increase number of fast wake precharge pulses

[Ville Syrjälä]

On Fri, Mar 08, 2024 at 01:00:39PM +0200, Jouni Högander wrote:
> Increasing number of fast wake sync pulses seem to fix problems with
> certain PSR panels. This should be ok for other panels as well as the eDP
> specification allows 10...16 precharge pulses and we are still within that
> range.
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9739
> Signed-off-by: Jouni Högander 
> ---
>  drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c 
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 7e69be100d90..5dff1bc85d61 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -145,7 +145,7 @@ static int intel_dp_aux_sync_len(void)
>  
>  int intel_dp_aux_fw_sync_len(void)
>  {
> - int precharge = 10; /* 10-16 */
> + int precharge = 12; /* 10-16 */

This is still giving me allergies because Windows doesn't have
anything like this. So the mystery is how does Windows work?
This was an actual production machine I take it?

Did we have look at the error bits in PSR2_DEBUG to see if there
is some difference between the working and non-working values?

Anyways, this at least needs a proper comment to explain why
we're not usign the standard value.

>   int preamble = 8;
>  
>   return precharge + preamble;
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

Re: [PATCH v2 5/8] drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state

[Gustavo Sousa]

Quoting Gustavo Sousa (2024-03-12 13:36:36-03:00)
>Xe2LPD always selects the CDCLK PLL as source for the MDCLK. Because of
>that, the ratio between MDCLK and CDCLK is not be constant anymore. As
>such, make sure to have the current ratio available in intel_dbuf_state
>so that it can be used during dbuf programming.
>
>Note that we write-lock the global state instead of serializing to a
>hardware commit because a change in the ratio should be rather handled
>in the CDCLK change sequence, which will need to take care of updating
>the necessary registers in that case. We will implement that in upcoming
>changes.
>
>That said, changes in the MBus joining state should be handled by the
>DBUF/MBUS logic, just like it is already done, but the logic will need
>to know the ratio to properly update the registers.
>
>v2:
>  - Make first sentence of commit message more intelligible. (Matt)
>
>Reviewed-by: Matt Roper 
>Signed-off-by: Gustavo Sousa 
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c   | 20 
> drivers/gpu/drm/i915/display/intel_cdclk.h   |  2 ++
> drivers/gpu/drm/i915/display/skl_watermark.c | 18 +-
> drivers/gpu/drm/i915/display/skl_watermark.h |  3 +++
> 4 files changed, 42 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
>b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 354a9dba6440..4e143082dca1 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -39,6 +39,7 @@
> #include "intel_pcode.h"
> #include "intel_psr.h"
> #include "intel_vdsc.h"
>+#include "skl_watermark.h"
> #include "vlv_sideband.h"
> 
> /**
>@@ -1889,6 +1890,16 @@ static u32 xe2lpd_mdclk_source_sel(struct 
>drm_i915_private *i915)
> return MDCLK_SOURCE_SEL_CD2XCLK;
> }
> 
>+u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>+   const struct intel_cdclk_config *cdclk_config)
>+{
>+if (mdclk_source_is_cdclk_pll(i915))
>+return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
>+
>+/* Otherwise, source for MDCLK is CD2XCLK. */
>+return 2;

Matt, this function was updated as a result of updating the second patch
(now "drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()").

Since the update here is functionally equivalent to v1, I took the
liberty of carrying your r-b over. Please let me know if you have
concerns here.

--
Gustavo Sousa

>+}
>+
> static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private 
> *i915,
> const struct 
> intel_cdclk_config *old_cdclk_config,
> const struct 
> intel_cdclk_config *new_cdclk_config,
>@@ -3278,6 +3289,15 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
>*state)
> "Modeset required for cdclk change\n");
> }
> 
>+if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
>+intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
>+u8 ratio = intel_mdclk_cdclk_ratio(dev_priv, 
>&new_cdclk_state->actual);
>+
>+ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
>+if (ret)
>+return ret;
>+}
>+
> drm_dbg_kms(&dev_priv->drm,
> "New cdclk calculated to be logical %u kHz, actual %u 
> kHz\n",
> new_cdclk_state->logical.cdclk,
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h 
>b/drivers/gpu/drm/i915/display/intel_cdclk.h
>index fa301495e7f1..8e6e302bd599 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>@@ -62,6 +62,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
> u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
>const struct intel_cdclk_config *b);
>+u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
>+   const struct intel_cdclk_config *cdclk_config);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> void intel_cdclk_dump_config(struct drm_i915_private *i915,
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c 
>b/drivers/gpu/drm/i915/display/skl_watermark.c
>index d9e49cd60d3a..4410e21888ad 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3057,6 +3057,8 @@ static void skl_wm_get_hw_state(struct drm_i915_private 
>*i915)
> if (HAS_MBUS_JOINING(i915))
> dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & 
> MBUS_JOIN;
> 
>+dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(i915, 
>&i915->display.cdclk.hw);
>+
> for_e

Re: [PATCH] drm/xe/display: fix potential overflow when multiplying 2 u32

[Ville Syrjälä]

On Tue, Mar 12, 2024 at 03:24:41PM +0530, Arun R Murthy wrote:
> Multiplying XE_PAGE_SIZE with another u32 and the product stored in
> u64 can potentially lead to overflow. Change one of the value to u64 so
> as to perform 64 bit arithmetic operation as the product is u64.

These should never get that big.

> 
> Signed-off-by: Arun R Murthy 
> ---
>  drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c 
> b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index 722c84a56607..c9d26345ae6e 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -29,7 +29,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, 
> u32 *dpt_ofs, u32 bo_
>   u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
>  
>   for (row = 0; row < height; row++) {
> - u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * 
> XE_PAGE_SIZE,
> + u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * 
> (u64)XE_PAGE_SIZE,

mul_u32_u32() may generate better code due to compiler fails.

> 
> xe->pat.idx[XE_CACHE_WB]);

Rather surprising to see WB in any display code.
Is this stuff actually working?

>  
>   iosys_map_wr(map, *dpt_ofs, u64, pte);
> @@ -61,7 +61,7 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, 
> u32 *dpt_ofs,
>  
>   for (column = 0; column < width; column++) {
>   iosys_map_wr(map, *dpt_ofs, u64,
> -  pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
> +  pte_encode_bo(bo, src_idx * 
> (u64)XE_PAGE_SIZE,
>xe->pat.idx[XE_CACHE_WB]));
>  
>   *dpt_ofs += 8;
> @@ -118,7 +118,7 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer 
> *fb,
>   u32 x;
>  
>   for (x = 0; x < size / XE_PAGE_SIZE; x++) {
> - u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x * 
> XE_PAGE_SIZE,
> + u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x * 
> (u64)XE_PAGE_SIZE,
> 
> xe->pat.idx[XE_CACHE_WB]);
>  
>   iosys_map_wr(&dpt->vmap, x * 8, u64, pte);
> @@ -164,7 +164,7 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt 
> *ggtt, u32 *ggtt_ofs, u32 bo
>   u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
>  
>   for (row = 0; row < height; row++) {
> - u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * 
> XE_PAGE_SIZE,
> + u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * 
> (u64)XE_PAGE_SIZE,
> 
> xe->pat.idx[XE_CACHE_WB]);
>  
>   xe_ggtt_set_pte(ggtt, *ggtt_ofs, pte);
> @@ -381,4 +381,4 @@ struct i915_address_space *intel_dpt_create(struct 
> intel_framebuffer *fb)
>  void intel_dpt_destroy(struct i915_address_space *vm)
>  {
>   return;
> -}
> \ No newline at end of file
> +}
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

Re: [PATCH v2 2/8] drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()

[Matt Roper]

On Tue, Mar 12, 2024 at 01:36:33PM -0300, Gustavo Sousa wrote:
> Currently, only Xe2LPD uses CDCLK PLL as the source of MDCLK and
> previous display IPs use the CD2XCLK. There will be changes in code
> paths common to those platforms that will rely on which source is being
> used. As such, let's make that information explicit with the addition of
> the predicate function mdclk_source_is_cdclk_pll().
> 
> Arguably, an enum could be created, but using a boolean should suffice
> here, since we there are only two possible sources and the logic that
> will rely on it will be very localized.
> 
> In order to get the code into a more consistent state, let's also take
> this opportunity to hook the selection of CDCLK_CTL's "MDCLK Source
> Select" to that new function. Even though currently only
> MDCLK_SOURCE_SEL_CDCLK_PLL will be returned, having this extra logic is
> arguably better than keeping stuff untied and prone to bugs.
> 
> v2:
>   - Extract mdclk_source_is_cdclk_pll() out of xe2lpd_mdclk_source_sel()
> to make latter only about the register's field.
> 
> Bspec: 69090

You might also add 68861 here since that's where we find out that Xe2
and beyond should always use the CDCLK PLL as the MDCLK source (rather
than the CD2X which would still be the register field's default value if
we didn't touch it).

Reviewed-by: Matt Roper 

> Cc: Matt Roper 
> Signed-off-by: Gustavo Sousa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 15 ++-
>  drivers/gpu/drm/i915/i915_reg.h|  4 +++-
>  2 files changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index be268c6abe21..ad0f03e51e4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1876,6 +1876,19 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
>   return vco == ~0;
>  }
>  
> +static bool mdclk_source_is_cdclk_pll(struct drm_i915_private *i915)
> +{
> + return DISPLAY_VER(i915) >= 20;
> +}
> +
> +static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
> +{
> + if (mdclk_source_is_cdclk_pll(i915))
> + return MDCLK_SOURCE_SEL_CDCLK_PLL;
> +
> + return MDCLK_SOURCE_SEL_CD2XCLK;
> +}
> +
>  static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private 
> *i915,
>   const struct 
> intel_cdclk_config *old_cdclk_config,
>   const struct 
> intel_cdclk_config *new_cdclk_config,
> @@ -1980,7 +1993,7 @@ static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
>   val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
>  
>   if (DISPLAY_VER(i915) >= 20)
> - val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
> + val |= xe2lpd_mdclk_source_sel(i915);
>   else
>   val |= skl_cdclk_decimal(cdclk);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8823531b8770..d6193c858a74 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5891,7 +5891,9 @@ enum skl_power_gate {
>  #define  CDCLK_FREQ_540  REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
>  #define  CDCLK_FREQ_337_308  REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
>  #define  CDCLK_FREQ_675_617  REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
> -#define  MDCLK_SOURCE_SEL_CDCLK_PLL  REG_BIT(25)
> +#define  MDCLK_SOURCE_SEL_MASK   REG_GENMASK(25, 25)
> +#define  MDCLK_SOURCE_SEL_CD2XCLKREG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
> +#define  MDCLK_SOURCE_SEL_CDCLK_PLL  REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_1
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_1_5  
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
> -- 
> 2.44.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 5/8] drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state

[Matt Roper]

On Tue, Mar 12, 2024 at 01:45:32PM -0300, Gustavo Sousa wrote:
> Quoting Gustavo Sousa (2024-03-12 13:36:36-03:00)
> >Xe2LPD always selects the CDCLK PLL as source for the MDCLK. Because of
> >that, the ratio between MDCLK and CDCLK is not be constant anymore. As
> >such, make sure to have the current ratio available in intel_dbuf_state
> >so that it can be used during dbuf programming.
> >
> >Note that we write-lock the global state instead of serializing to a
> >hardware commit because a change in the ratio should be rather handled
> >in the CDCLK change sequence, which will need to take care of updating
> >the necessary registers in that case. We will implement that in upcoming
> >changes.
> >
> >That said, changes in the MBus joining state should be handled by the
> >DBUF/MBUS logic, just like it is already done, but the logic will need
> >to know the ratio to properly update the registers.
> >
> >v2:
> >  - Make first sentence of commit message more intelligible. (Matt)
> >
> >Reviewed-by: Matt Roper 
> >Signed-off-by: Gustavo Sousa 
> >---
> > drivers/gpu/drm/i915/display/intel_cdclk.c   | 20 
> > drivers/gpu/drm/i915/display/intel_cdclk.h   |  2 ++
> > drivers/gpu/drm/i915/display/skl_watermark.c | 18 +-
> > drivers/gpu/drm/i915/display/skl_watermark.h |  3 +++
> > 4 files changed, 42 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> >b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >index 354a9dba6440..4e143082dca1 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >@@ -39,6 +39,7 @@
> > #include "intel_pcode.h"
> > #include "intel_psr.h"
> > #include "intel_vdsc.h"
> >+#include "skl_watermark.h"
> > #include "vlv_sideband.h"
> > 
> > /**
> >@@ -1889,6 +1890,16 @@ static u32 xe2lpd_mdclk_source_sel(struct 
> >drm_i915_private *i915)
> > return MDCLK_SOURCE_SEL_CD2XCLK;
> > }
> > 
> >+u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> >+   const struct intel_cdclk_config *cdclk_config)
> >+{
> >+if (mdclk_source_is_cdclk_pll(i915))
> >+return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
> >+
> >+/* Otherwise, source for MDCLK is CD2XCLK. */
> >+return 2;
> 
> Matt, this function was updated as a result of updating the second patch
> (now "drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()").
> 
> Since the update here is functionally equivalent to v1, I took the
> liberty of carrying your r-b over. Please let me know if you have
> concerns here.

No concerns; you can keep my r-b.


Matt

> 
> --
> Gustavo Sousa
> 
> >+}
> >+
> > static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private 
> > *i915,
> > const struct 
> > intel_cdclk_config *old_cdclk_config,
> > const struct 
> > intel_cdclk_config *new_cdclk_config,
> >@@ -3278,6 +3289,15 @@ int intel_modeset_calc_cdclk(struct 
> >intel_atomic_state *state)
> > "Modeset required for cdclk change\n");
> > }
> > 
> >+if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) !=
> >+intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) {
> >+u8 ratio = intel_mdclk_cdclk_ratio(dev_priv, 
> >&new_cdclk_state->actual);
> >+
> >+ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
> >+if (ret)
> >+return ret;
> >+}
> >+
> > drm_dbg_kms(&dev_priv->drm,
> > "New cdclk calculated to be logical %u kHz, actual %u 
> > kHz\n",
> > new_cdclk_state->logical.cdclk,
> >diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h 
> >b/drivers/gpu/drm/i915/display/intel_cdclk.h
> >index fa301495e7f1..8e6e302bd599 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> >+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> >@@ -62,6 +62,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> > bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> >const struct intel_cdclk_config *b);
> >+u8 intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> >+   const struct intel_cdclk_config *cdclk_config);
> > void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> > void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> > void intel_cdclk_dump_config(struct drm_i915_private *i915,
> >diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c 
> >b/drivers/gpu/drm/i915/display/skl_watermark.c
> >index d9e49cd60d3a..4410e21888ad 100644
> >--- a/drivers/gpu/drm/i915/display/skl_watermark.c
> >+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> >@@ -30

Re: [PATCH v5 1/4] drm/i915/gt: Disable HW load balancing for CCS

[Matt Roper]

On Fri, Mar 08, 2024 at 09:22:16PM +0100, Andi Shyti wrote:
> The hardware should not dynamically balance the load between CCS
> engines. Wa_14019159160 recommends disabling it across all
> platforms.
> 
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti 
> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Matt Roper 
> Cc:  # v6.2+
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h |  1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 +++--
>  2 files changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 50962cfd1353..cf709f6c05ae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1478,6 +1478,7 @@
>  
>  #define GEN12_RCU_MODE   _MMIO(0x14800)
>  #define   GEN12_RCU_MODE_CCS_ENABLE  REG_BIT(0)
> +#define   XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)

Nitpick: we usually order register bits in descending order.  Aside from
that,

Reviewed-by: Matt Roper 

although I still hope our architects will push through a formal
documentation update for this.


Matt

>  
>  #define CHV_FUSE_GT  _MMIO(VLV_GUNIT_BASE + 0x2168)
>  #define   CHV_FGT_DISABLE_SS0(1 << 10)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 25413809b9dc..4865eb5ca9c9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -51,7 +51,8 @@
>   *   registers belonging to BCS, VCS or VECS should be implemented in
>   *   xcs_engine_wa_init(). Workarounds for registers not belonging to a 
> specific
>   *   engine's MMIO range but that are part of of the common RCS/CCS reset 
> domain
> - *   should be implemented in general_render_compute_wa_init().
> + *   should be implemented in general_render_compute_wa_init(). The settings
> + *   about the CCS load balancing should be added in ccs_engine_wa_mode().
>   *
>   * - GT workarounds: the list of these WAs is applied whenever these 
> registers
>   *   revert to their default values: on GPU reset, suspend/resume [1]_, etc.
> @@ -2854,6 +2855,22 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
>   wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
>  }
>  
> +static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct 
> i915_wa_list *wal)
> +{
> + struct intel_gt *gt = engine->gt;
> +
> + if (!IS_DG2(gt->i915))
> + return;
> +
> + /*
> +  * Wa_14019159160: This workaround, along with others, leads to
> +  * significant challenges in utilizing load balancing among the
> +  * CCS slices. Consequently, an architectural decision has been
> +  * made to completely disable automatic CCS load balancing.
> +  */
> + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
> +}
> +
>  /*
>   * The workarounds in this function apply to shared registers in
>   * the general render reset domain that aren't tied to a
> @@ -3004,8 +3021,10 @@ engine_init_workarounds(struct intel_engine_cs 
> *engine, struct i915_wa_list *wal
>* to a single RCS/CCS engine's workaround list since
>* they're reset as part of the general render domain reset.
>*/
> - if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
> + if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) {
>   general_render_compute_wa_init(engine, wal);
> + ccs_engine_wa_mode(engine, wal);
> + }
>  
>   if (engine->class == COMPUTE_CLASS)
>   ccs_engine_wa_init(engine, wal);
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

✗ Fi.CI.SPARSE: warning for drm/i915/opregion: add intel_opregion_vbt_present() stub for ACPI=n

[Patchwork]

== Series Details ==

Series: drm/i915/opregion: add intel_opregion_vbt_present() stub for ACPI=n
URL   : https://patchwork.freedesktop.org/series/131021/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [PATCH v5 2/4] drm/i915/gt: Refactor uabi engine class/instance list creation

[Matt Roper]

On Fri, Mar 08, 2024 at 09:22:17PM +0100, Andi Shyti wrote:
> For the upcoming changes we need a cleaner way to build the list
> of uabi engines.
> 
> Suggested-by: Tvrtko Ursulin 
> Signed-off-by: Andi Shyti 
> Cc:  # v6.2+

I don't really see why we need patches 2 & 3 in this series.  If we want
to restrict the platform to a single CCS engine for now (and give that
single engine access to all of the cslices), it would be much simpler to
only create a single intel_engine_cs which which would then cause both
i915 and userspace to only consider a single engine, even if more than
one is physically present.  That could be done with a simple adjustment
to engine_mask_apply_compute_fuses() to mask off extra bits from the
engine mask such that only a single CCS can get returned rather than the
mask of all CCSs that are present.

Managing all of the engines in the KMD but only exposing one (some) of
them to userspace might be something we need if you want to add extra
functionality down to road to "hotplug" extra engines, or to allow
userspace to explicitly request multi-CCS mode.  But none of that seems
necessary for this series, especially for something you're backporting
to stable kernels.


Matt

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 -
>  1 file changed, 17 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
> b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 833987015b8b..11cc06c0c785 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -203,7 +203,7 @@ static void engine_rename(struct intel_engine_cs *engine, 
> const char *name, u16
>  
>  void intel_engines_driver_register(struct drm_i915_private *i915)
>  {
> - u16 name_instance, other_instance = 0;
> + u16 class_instance[I915_LAST_UABI_ENGINE_CLASS + 2] = { };
>   struct legacy_ring ring = {};
>   struct list_head *it, *next;
>   struct rb_node **p, *prev;
> @@ -214,6 +214,8 @@ void intel_engines_driver_register(struct 
> drm_i915_private *i915)
>   prev = NULL;
>   p = &i915->uabi_engines.rb_node;
>   list_for_each_safe(it, next, &engines) {
> + u16 uabi_class;
> +
>   struct intel_engine_cs *engine =
>   container_of(it, typeof(*engine), uabi_list);
>  
> @@ -222,15 +224,14 @@ void intel_engines_driver_register(struct 
> drm_i915_private *i915)
>  
>   GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
>   engine->uabi_class = uabi_classes[engine->class];
> - if (engine->uabi_class == I915_NO_UABI_CLASS) {
> - name_instance = other_instance++;
> - } else {
> - GEM_BUG_ON(engine->uabi_class >=
> -ARRAY_SIZE(i915->engine_uabi_class_count));
> - name_instance =
> - 
> i915->engine_uabi_class_count[engine->uabi_class]++;
> - }
> - engine->uabi_instance = name_instance;
> +
> + if (engine->uabi_class == I915_NO_UABI_CLASS)
> + uabi_class = I915_LAST_UABI_ENGINE_CLASS + 1;
> + else
> + uabi_class = engine->uabi_class;
> +
> + GEM_BUG_ON(uabi_class >= ARRAY_SIZE(class_instance));
> + engine->uabi_instance = class_instance[uabi_class]++;
>  
>   /*
>* Replace the internal name with the final user and log facing
> @@ -238,11 +239,15 @@ void intel_engines_driver_register(struct 
> drm_i915_private *i915)
>*/
>   engine_rename(engine,
> intel_engine_class_repr(engine->class),
> -   name_instance);
> +   engine->uabi_instance);
>  
> - if (engine->uabi_class == I915_NO_UABI_CLASS)
> + if (uabi_class > I915_LAST_UABI_ENGINE_CLASS)
>   continue;
>  
> + GEM_BUG_ON(uabi_class >=
> +ARRAY_SIZE(i915->engine_uabi_class_count));
> + i915->engine_uabi_class_count[uabi_class]++;
> +
>   rb_link_node(&engine->uabi_node, prev, p);
>   rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
>  
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2] drm/i915/hwmon: Fix locking inversion in sysfs getter

[Andi Shyti]

Hi Janusz,

On Mon, Mar 11, 2024 at 09:34:58PM +0100, Janusz Krzysztofik wrote:
> In i915 hwmon sysfs getter path we now take a hwmon_lock, then acquire an
> rpm wakeref.  That results in lock inversion:
> 
> <4> [197.079335] ==
> <4> [197.085473] WARNING: possible circular locking dependency detected
> <4> [197.091611] 6.8.0-rc7-Patchwork_129026v7-gc4dc92fb1152+ #1 Not tainted
> <4> [197.098096] --
> <4> [197.104231] prometheus-node/839 is trying to acquire lock:
> <4> [197.109680] 82764d80 (fs_reclaim){+.+.}-{0:0}, at: 
> __kmalloc+0x9a/0x350
> <4> [197.116939]
> but task is already holding lock:
> <4> [197.122730] 88811b772a40 (&hwmon->hwmon_lock){+.+.}-{3:3}, at: 
> hwm_energy+0x4b/0x100 [i915]
> <4> [197.131543]
> which lock already depends on the new lock.
> ...
> <4> [197.507922] Chain exists of:
>   fs_reclaim --> >->reset.mutex --> &hwmon->hwmon_lock
> <4> [197.518528]  Possible unsafe locking scenario:
> <4> [197.524411]CPU0CPU1
> <4> [197.528916]
> <4> [197.533418]   lock(&hwmon->hwmon_lock);
> <4> [197.537237]lock(>->reset.mutex);
> <4> [197.543376]lock(&hwmon->hwmon_lock);
> <4> [197.549682]   lock(fs_reclaim);
> ...
> <4> [197.632548] Call Trace:
> <4> [197.634990]  
> <4> [197.637088]  dump_stack_lvl+0x64/0xb0
> <4> [197.640738]  check_noncircular+0x15e/0x180
> <4> [197.652968]  check_prev_add+0xe9/0xce0
> <4> [197.656705]  __lock_acquire+0x179f/0x2300
> <4> [197.660694]  lock_acquire+0xd8/0x2d0
> <4> [197.673009]  fs_reclaim_acquire+0xa1/0xd0
> <4> [197.680478]  __kmalloc+0x9a/0x350
> <4> [197.689063]  acpi_ns_internalize_name.part.0+0x4a/0xb0
> <4> [197.694170]  acpi_ns_get_node_unlocked+0x60/0xf0
> <4> [197.720608]  acpi_ns_get_node+0x3b/0x60
> <4> [197.724428]  acpi_get_handle+0x57/0xb0
> <4> [197.728164]  acpi_has_method+0x20/0x50
> <4> [197.731896]  acpi_pci_set_power_state+0x43/0x120
> <4> [197.736485]  pci_power_up+0x24/0x1c0
> <4> [197.740047]  pci_pm_default_resume_early+0x9/0x30
> <4> [197.744725]  pci_pm_runtime_resume+0x2d/0x90
> <4> [197.753911]  __rpm_callback+0x3c/0x110
> <4> [197.762586]  rpm_callback+0x58/0x70
> <4> [197.766064]  rpm_resume+0x51e/0x730
> <4> [197.769542]  rpm_resume+0x267/0x730
> <4> [197.773020]  rpm_resume+0x267/0x730
> <4> [197.776498]  rpm_resume+0x267/0x730
> <4> [197.779974]  __pm_runtime_resume+0x49/0x90
> <4> [197.784055]  __intel_runtime_pm_get+0x19/0xa0 [i915]
> <4> [197.789070]  hwm_energy+0x55/0x100 [i915]
> <4> [197.793183]  hwm_read+0x9a/0x310 [i915]
> <4> [197.797124]  hwmon_attr_show+0x36/0x120
> <4> [197.800946]  dev_attr_show+0x15/0x60
> <4> [197.804509]  sysfs_kf_seq_show+0xb5/0x100
> 
> Acquire the wakeref before the lock and hold it as long as the lock is
> also held.  Follow that pattern across the whole source file where similar
> lock inversion can happen.
> 
> v2: Keep hardware read under the lock so the whole operation of updating
> energy from hardware is still atomic (Guenter),
>   - instead, acquire the rpm wakeref before the lock and hold it as long
> as the lock is held,
>   - use the same aproach for other similar places across the i915_hwmon.c
> source file (Rodrigo).
> 
> Fixes: c41b8bdcc297 ("drm/i915/hwmon: Show device level energy usage")
> Signed-off-by: Janusz Krzysztofik 
> Cc: Rodrigo Vivi 
> Cc: Guenter Roeck 
> Cc:  # v6.2+

Reviewed-by: Andi Shyti 

If you want I can change the Fixes tag as suggested by Ashutosh
before applying the patch before pushing the change.

Andi

✓ Fi.CI.BAT: success for drm/i915/opregion: add intel_opregion_vbt_present() stub for ACPI=n

[Patchwork]

== Series Details ==

Series: drm/i915/opregion: add intel_opregion_vbt_present() stub for ACPI=n
URL   : https://patchwork.freedesktop.org/series/131021/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14421 -> Patchwork_131021v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/index.html

Participating hosts (36 -> 35)
--

  Additional (1): fi-glk-j4005 
  Missing(2): bat-mtlp-8 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_131021v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-glk-j4005:   NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-glk-j4005:   NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- bat-arls-2: NOTRUN -> [SKIP][4] ([i915#10213]) +3 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-7:  NOTRUN -> [SKIP][5] ([i915#6621])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-dg1-7/igt@i915_pm_...@basic-api.html
- bat-arls-2: NOTRUN -> [SKIP][6] ([i915#10209])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-arls-2/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- fi-kbl-8809g:   NOTRUN -> [INCOMPLETE][7] ([i915#9527])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/fi-kbl-8809g/igt@i915_selftest@l...@hangcheck.html
- bat-rpls-3: [PASS][8] -> [DMESG-WARN][9] ([i915#5591])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-j4005:   NOTRUN -> [SKIP][10] +10 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
- bat-arls-2: NOTRUN -> [SKIP][11] ([i915#9886])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-arls-2/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-arls-2: NOTRUN -> [SKIP][12] ([i915#10207])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-arls-2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- bat-arls-2: NOTRUN -> [SKIP][13] ([i915#10196] / [i915#4077] / 
[i915#9688])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-arls-2/igt@kms_psr@psr-primary-mmap-...@edp-1.html

  * igt@kms_psr@psr-primary-page-flip:
- bat-dg1-7:  NOTRUN -> [SKIP][14] ([i915#9732]) +3 other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-dg1-7/igt@kms_...@psr-primary-page-flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10208] / [i915#8809])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-arls-2/igt@kms_setm...@basic-clone-single-crtc.html
- bat-dg1-7:  NOTRUN -> [SKIP][16] ([i915#3555])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-dg1-7/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
- bat-dg1-7:  NOTRUN -> [SKIP][17] ([i915#3708]) +3 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-dg1-7/igt@prime_v...@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
- bat-dg1-7:  NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4077]) +1 
other test skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-dg1-7/igt@prime_v...@basic-fence-mmap.html
- bat-arls-2: NOTRUN -> [SKIP][19] ([i915#10196] / [i915#3708] / 
[i915#4077]) +1 other test skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131021v1/bat-arls-2/igt@prime_v...@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
- bat-arls-2: NOTRUN -> [SKIP][20] ([i915#10212] / [i915#3708])
 

[linux-next:master] BUILD REGRESSION a1184cae56bcb96b86df3ee0377cec507a3f56e0

[kernel test robot]

tree/branch: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: a1184cae56bcb96b86df3ee0377cec507a3f56e0  Add linux-next specific 
files for 20240312

Error/Warning reports:

https://lore.kernel.org/oe-kbuild-all/202403121924.e3xrqdss-...@intel.com

Error/Warning: (recently discovered and may have been fixed)

drivers/gpu/drm/i915/display/intel_bios.c:3417:10: error: call to undeclared 
function 'intel_opregion_vbt_present'; ISO C99 and later do not support 
implicit function declarations [-Wimplicit-function-declaration]

Error/Warning ids grouped by kconfigs:

gcc_recent_errors
|-- alpha-allyesconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- arc-allmodconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- arc-allyesconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- arm-allmodconfig
|   |-- 
arch-arm-mach-omap2-prm33xx.c:warning:expecting-prototype-for-am33xx_prm_global_warm_sw_reset().-Prototype-was-for-am33xx_prm_global_sw_reset()-instead
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- arm-allyesconfig
|   |-- 
arch-arm-mach-omap2-prm33xx.c:warning:expecting-prototype-for-am33xx_prm_global_warm_sw_reset().-Prototype-was-for-am33xx_prm_global_sw_reset()-instead
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- arm-randconfig-002-20240312
|   |-- 
arch-arm-mach-omap2-prm33xx.c:warning:expecting-prototype-for-am33xx_prm_global_warm_sw_reset().-Prototype-was-for-am33xx_prm_global_sw_reset()-instead
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- arm-randconfig-003-20240312
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- arm64-defconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- arm64-randconfig-001-20240312
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- csky-allmodconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- csky-allyesconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- csky-randconfig-002-20240312
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- i386-allmodconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- i386-allyesconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- i386-randconfig-001-20240312
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- i386-randconfig-011-20240312
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- i386-randconfig-061-20240312
|   |-- io_uring-io_uring.c:sparse:sparse:cast-to-restricted-io_req_flags_t
|   |-- 
kernel-power-energy_model.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-em_perf_state-table-got-struct-em_perf_state-noderef-__rcu
|   |-- 
kernel-power-energy_model.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-struct-kref-kref-got-struct-kref-noderef-__rcu
|   |-- 
kernel-power-energy_model.c:sparse:sparse:incorrect-type-in-argument-(different-address-spaces)-expected-void-const-objp-got-struct-em_perf_table-noderef-__rcu-assigned-em_table
|   `-- 
kernel-power-energy_model.c:sparse:sparse:incorrect-type-in-assignment-(different-address-spaces)-expected-struct-em_perf_state-new_ps-got-struct-em_perf_state-noderef-__rcu
|-- i386-randconfig-063-20240312
|   `-- io_uring-io_uring.c:sparse:sparse:cast-to-restricted-io_req_flags_t
|-- loongarch-allmodconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- loongarch-defconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue()-instead
|-- m68k-allmodconfig
|   `-- 
fs-ubifs-journal.c:warning:expecting-prototype-for-wake_up_reservation().-Prototype-was-for-add_or_start_queue

✗ Fi.CI.CHECKPATCH: warning for drm/i915: pass encoder around more for port/phy checks

[Patchwork]

== Series Details ==

Series: drm/i915: pass encoder around more for port/phy checks
URL   : https://patchwork.freedesktop.org/series/131031/
State : warning

== Summary ==

Error: dim checkpatch failed
e1b7c8c052d0 drm/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin()
d4b8dffcc1db drm/i915/ddi: pass encoder to intel_wait_ddi_buf_active()
254a54ef205c drm/i915/snps: pass encoder to 
intel_snps_phy_update_psr_power_state()
4e620962b4b9 drm/i915/display: add intel_encoder_is_*() and _to_*() functions
e9fd125d155d drm/i915/display: use intel_encoder_is/to_* functions
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:643: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#643: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1696:
+   else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 
!(intel_encoder_is_c10phy(encoder)))

total: 0 errors, 2 warnings, 0 checks, 964 lines checked
0f16c202ad7c drm/i915/cx0: remove intel_is_c10phy()
6fadfbd31454 drm/i915/cx0: pass encoder instead of i915 and port around
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:201: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#201: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:295:
+   ack = intel_cx0_wait_for_ack(encoder, 
XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);

-:445: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#445: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1923:
+   intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), 
pll_state->cmn, MB_WRITE_COMMITTED);

-:446: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#446: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1924:
+   intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), 
pll_state->tx, MB_WRITE_COMMITTED);

-:466: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#466: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2168:
+   cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, 
PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;

-:531: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#531: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2358:
+   intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 
RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);

-:540: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#540: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2366:
+   intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 
PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);

-:543: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#543: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2368:
+   intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 
PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);

-:550: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#550: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2374:
+   intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 
PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);

-:553: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#553: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2376:
+   intel_c20_sram_write(encoder, INTEL_CX0_LANE0, 
PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);

total: 0 errors, 10 warnings, 0 checks, 730 lines checked

✗ Fi.CI.SPARSE: warning for drm/i915: pass encoder around more for port/phy checks

[Patchwork]

== Series Details ==

Series: drm/i915: pass encoder around more for port/phy checks
URL   : https://patchwork.freedesktop.org/series/131031/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/

✗ Fi.CI.BAT: failure for drm/i915: pass encoder around more for port/phy checks

[Patchwork]

== Series Details ==

Series: drm/i915: pass encoder around more for port/phy checks
URL   : https://patchwork.freedesktop.org/series/131031/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14421 -> Patchwork_131031v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_131031v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_131031v1, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/index.html

Participating hosts (36 -> 34)
--

  Missing(2): bat-dg1-7 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_131031v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hangcheck:
- bat-arls-2: NOTRUN -> [ABORT][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_force_connector_basic@force-edid:
- bat-dg2-8:  [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-dg2-8/igt@kms_force_connector_ba...@force-edid.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-dg2-8/igt@kms_force_connector_ba...@force-edid.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-hdmi-a-1:
- fi-kbl-8809g:   [PASS][4] -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/fi-kbl-8809g/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-hdmi-a-1.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/fi-kbl-8809g/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-hdmi-a-1.html

  
Known issues


  Here are the changes found in Patchwork_131031v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@verify-random:
- bat-arls-2: NOTRUN -> [SKIP][6] ([i915#10213]) +3 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_pm_rps@basic-api:
- bat-arls-2: NOTRUN -> [SKIP][7] ([i915#10209])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_contexts:
- bat-dg2-14: [PASS][8] -> [ABORT][9] ([i915#10366])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-dg2-14/igt@i915_selftest@live@gt_contexts.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-dg2-14/igt@i915_selftest@live@gt_contexts.html

  * igt@i915_selftest@live@hangcheck:
- bat-rpls-3: [PASS][10] -> [DMESG-WARN][11] ([i915#5591])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_dsc@dsc-basic:
- bat-arls-2: NOTRUN -> [SKIP][12] ([i915#9886])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-arls-2: NOTRUN -> [SKIP][13] ([i915#10207])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10196] / [i915#4077] / 
[i915#9688])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@kms_psr@psr-primary-mmap-...@edp-1.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10208] / [i915#8809])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
- bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10196] / [i915#3708] / 
[i915#4077]) +1 other test skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@prime_v...@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
- bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10212] / [i915#3708])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@prime_v...@basic-fence-read.html

  * igt@prime_vgem@basic-read:
- bat-arls-2: NOTRUN -> [SKIP][18] ([i915#10214] / [i915#3708])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131031v1/bat-arls-2/igt@prime_v...@ba

✗ Fi.CI.BAT: failure for drm/i915/gem: Execbuffer objects must have struct pages. (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Execbuffer objects must have struct pages. (rev2)
URL   : https://patchwork.freedesktop.org/series/131000/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14421 -> Patchwork_131000v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_131000v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_131000v2, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/index.html

Participating hosts (36 -> 33)
--

  Additional (1): fi-glk-j4005 
  Missing(4): bat-dg2-14 bat-mtlp-8 fi-snb-2520m fi-kbl-8809g 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_131000v2:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fence@basic-await@bcs0:
- bat-atsm-1: [PASS][1] -> [FAIL][2] +74 other tests fail
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-atsm-1/igt@gem_exec_fence@basic-aw...@bcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-atsm-1/igt@gem_exec_fence@basic-aw...@bcs0.html

  * igt@gem_exec_fence@basic-wait@vcs1:
- bat-dg2-8:  [PASS][3] -> [FAIL][4] +72 other tests fail
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-dg2-8/igt@gem_exec_fence@basic-w...@vcs1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-dg2-8/igt@gem_exec_fence@basic-w...@vcs1.html

  * igt@gem_softpin@safe-alignment:
- bat-dg2-9:  [PASS][5] -> [FAIL][6] +73 other tests fail
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-dg2-9/igt@gem_soft...@safe-alignment.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-dg2-9/igt@gem_soft...@safe-alignment.html

  * igt@i915_module_load@load:
- bat-dg2-13: [PASS][7] -> [FAIL][8] +1 other test fail
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-dg2-13/igt@i915_module_l...@load.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-dg2-13/igt@i915_module_l...@load.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a2:
- bat-dg1-7:  [PASS][9] -> [FAIL][10] +97 other tests fail
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-dg1-7/igt@kms_flip@basic-flip-vs-wf_vbl...@a-hdmi-a2.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-dg1-7/igt@kms_flip@basic-flip-vs-wf_vbl...@a-hdmi-a2.html

  * igt@kms_pm_rpm@basic-rte:
- bat-dg1-7:  NOTRUN -> [FAIL][11] +5 other tests fail
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-dg1-7/igt@kms_pm_...@basic-rte.html

  
 Warnings 

  * igt@kms_pm_rpm@basic-pci-d3-state:
- bat-dg1-7:  [ABORT][12] ([i915#10367]) -> [FAIL][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-dg1-7/igt@kms_pm_...@basic-pci-d3-state.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-dg1-7/igt@kms_pm_...@basic-pci-d3-state.html

  
Known issues


  Here are the changes found in Patchwork_131000v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-glk-j4005:   NOTRUN -> [SKIP][14] ([i915#2190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-glk-j4005:   NOTRUN -> [SKIP][15] ([i915#4613]) +3 other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@basic@lmem0:
- bat-dg1-7:  NOTRUN -> [FAIL][16] ([i915#10378])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-dg1-7/igt@gem_lmem_swapping@ba...@lmem0.html
- bat-dg2-9:  [PASS][17] -> [FAIL][18] ([i915#10378])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
- bat-dg2-8:  [PASS][19] -> [FAIL][20] ([i915#10378])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131000v2/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html

  * igt@gem_lmem_swapping@verify-random:
- bat-arls-2: NOTRUN -> [SKIP][21] ([i915#10213]) +3 other tests 
skip
   [21]: 
https://intel-gfx-ci.01.org/tree/d

✗ Fi.CI.CHECKPATCH: warning for Enable LNL display (rev2)

[Patchwork]

== Series Details ==

Series: Enable LNL display (rev2)
URL   : https://patchwork.freedesktop.org/series/130689/
State : warning

== Summary ==

Error: dim checkpatch failed
ba3eac026061 drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_table
3d99b83d61e5 drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()
217625bf4b87 drm/i915/cdclk: Only compute squash waveform when necessary
aff812f0faf8 drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()
9bd409c13e96 drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state
c0c0fa6f1105 drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changes
-:265: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#265: FILE: drivers/gpu/drm/i915/display/skl_watermark_regs.h:44:
+#define   MBUS_TRANSLATION_THROTTLE_MIN(val)   
REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)

total: 0 errors, 1 warnings, 0 checks, 195 lines checked
df51b8c0194d drm/i915/xe2lpd: Load DMC
192dbbe77799 drm/xe/lnl: Enable display support

✗ Fi.CI.SPARSE: warning for Enable LNL display (rev2)

[Patchwork]

== Series Details ==

Series: Enable LNL display (rev2)
URL   : https://patchwork.freedesktop.org/series/130689/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ Fi.CI.BAT: success for Enable LNL display (rev2)

[Patchwork]

== Series Details ==

Series: Enable LNL display (rev2)
URL   : https://patchwork.freedesktop.org/series/130689/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14421 -> Patchwork_130689v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/index.html

Participating hosts (36 -> 31)
--

  Additional (1): fi-glk-j4005 
  Missing(6): bat-dg1-7 bat-kbl-2 fi-snb-2520m fi-kbl-8809g bat-dg2-14 
bat-mtlp-8 

New tests
-

  New tests have been introduced between CI_DRM_14421 and Patchwork_130689v2:

### New IGT tests (1) ###

  * igt@kms_force_connector_basic:
- Statuses :
- Exec time: [None] s

  

Known issues


  Here are the changes found in Patchwork_130689v2 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- bat-jsl-1:  [FAIL][1] ([i915#8293]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-jsl-1/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-jsl-1/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-1:  NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-1:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-jsl-1/igt@gem_huc_c...@huc-copy.html
- fi-glk-j4005:   NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-glk-j4005:   NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- bat-arls-2: NOTRUN -> [SKIP][7] ([i915#10213]) +3 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html
- bat-jsl-1:  NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_pm_rps@basic-api:
- bat-arls-2: NOTRUN -> [SKIP][9] ([i915#10209])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-arls-2/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- bat-rpls-3: [PASS][10] -> [DMESG-WARN][11] ([i915#5591])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-j4005:   NOTRUN -> [SKIP][12] +10 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-1:  NOTRUN -> [SKIP][13] ([i915#4103]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-arls-2: NOTRUN -> [SKIP][14] ([i915#9886])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-arls-2/igt@kms_...@dsc-basic.html
- bat-jsl-1:  NOTRUN -> [SKIP][15] ([i915#3555] / [i915#9886])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-jsl-1/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10207])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-arls-2/igt@kms_force_connector_ba...@force-load-detect.html
- bat-jsl-1:  NOTRUN -> [SKIP][17]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-jsl-1/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- bat-arls-2: NOTRUN -> [SKIP][18] ([i915#10196] / [i915#4077] / 
[i915#9688])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-arls-2/igt@kms_psr@psr-primary-mmap-...@edp-1.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-arls-2: NOTRUN -> [SKIP][19] ([i915#10208] / [i915#8809])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/bat-arls-2/igt@kms_setm...@basic-clone-single-crtc.html
- bat-jsl-1:  NOTRUN -> [SKIP][20] ([i915#3555])
   

Re: [PATCH v2] drm/i915/hwmon: Fix locking inversion in sysfs getter

[Janusz Krzysztofik]

Hi Ashutosh,

On Tuesday, 12 March 2024 17:25:14 CET Dixit, Ashutosh wrote:
> On Mon, 11 Mar 2024 13:34:58 -0700, Janusz Krzysztofik wrote:
> >
> > In i915 hwmon sysfs getter path we now take a hwmon_lock, then acquire an
> > rpm wakeref.  That results in lock inversion:
> >
> > <4> [197.079335] ==
> > <4> [197.085473] WARNING: possible circular locking dependency detected
> > <4> [197.091611] 6.8.0-rc7-Patchwork_129026v7-gc4dc92fb1152+ #1 Not tainted
> > <4> [197.098096] --
> > <4> [197.104231] prometheus-node/839 is trying to acquire lock:
> > <4> [197.109680] 82764d80 (fs_reclaim){+.+.}-{0:0}, at: 
> > __kmalloc+0x9a/0x350
> > <4> [197.116939]
> > but task is already holding lock:
> > <4> [197.122730] 88811b772a40 (&hwmon->hwmon_lock){+.+.}-{3:3}, at: 
> > hwm_energy+0x4b/0x100 [i915]
> > <4> [197.131543]
> > which lock already depends on the new lock.
> > ...
> > <4> [197.507922] Chain exists of:
> >   fs_reclaim --> >->reset.mutex --> &hwmon->hwmon_lock
> > <4> [197.518528]  Possible unsafe locking scenario:
> > <4> [197.524411]CPU0CPU1
> > <4> [197.528916]
> > <4> [197.533418]   lock(&hwmon->hwmon_lock);
> > <4> [197.537237]lock(>->reset.mutex);
> > <4> [197.543376]lock(&hwmon->hwmon_lock);
> > <4> [197.549682]   lock(fs_reclaim);
> > ...
> > <4> [197.632548] Call Trace:
> > <4> [197.634990]  
> > <4> [197.637088]  dump_stack_lvl+0x64/0xb0
> > <4> [197.640738]  check_noncircular+0x15e/0x180
> > <4> [197.652968]  check_prev_add+0xe9/0xce0
> > <4> [197.656705]  __lock_acquire+0x179f/0x2300
> > <4> [197.660694]  lock_acquire+0xd8/0x2d0
> > <4> [197.673009]  fs_reclaim_acquire+0xa1/0xd0
> > <4> [197.680478]  __kmalloc+0x9a/0x350
> > <4> [197.689063]  acpi_ns_internalize_name.part.0+0x4a/0xb0
> > <4> [197.694170]  acpi_ns_get_node_unlocked+0x60/0xf0
> > <4> [197.720608]  acpi_ns_get_node+0x3b/0x60
> > <4> [197.724428]  acpi_get_handle+0x57/0xb0
> > <4> [197.728164]  acpi_has_method+0x20/0x50
> > <4> [197.731896]  acpi_pci_set_power_state+0x43/0x120
> > <4> [197.736485]  pci_power_up+0x24/0x1c0
> > <4> [197.740047]  pci_pm_default_resume_early+0x9/0x30
> > <4> [197.744725]  pci_pm_runtime_resume+0x2d/0x90
> > <4> [197.753911]  __rpm_callback+0x3c/0x110
> > <4> [197.762586]  rpm_callback+0x58/0x70
> > <4> [197.766064]  rpm_resume+0x51e/0x730
> > <4> [197.769542]  rpm_resume+0x267/0x730
> > <4> [197.773020]  rpm_resume+0x267/0x730
> > <4> [197.776498]  rpm_resume+0x267/0x730
> > <4> [197.779974]  __pm_runtime_resume+0x49/0x90
> > <4> [197.784055]  __intel_runtime_pm_get+0x19/0xa0 [i915]
> > <4> [197.789070]  hwm_energy+0x55/0x100 [i915]
> > <4> [197.793183]  hwm_read+0x9a/0x310 [i915]
> > <4> [197.797124]  hwmon_attr_show+0x36/0x120
> > <4> [197.800946]  dev_attr_show+0x15/0x60
> > <4> [197.804509]  sysfs_kf_seq_show+0xb5/0x100
> >
> > Acquire the wakeref before the lock and hold it as long as the lock is
> > also held.  Follow that pattern across the whole source file where similar
> > lock inversion can happen.
> >
> > v2: Keep hardware read under the lock so the whole operation of updating
> > energy from hardware is still atomic (Guenter),
> >   - instead, acquire the rpm wakeref before the lock and hold it as long
> > as the lock is held,
> >   - use the same aproach for other similar places across the i915_hwmon.c
> > source file (Rodrigo).
> >
> > Fixes: c41b8bdcc297 ("drm/i915/hwmon: Show device level energy usage")
> 
> I would think that the lock inversion issue was introduced here:
> 
> 1b44019a93e2 ("drm/i915/guc: Disable PL1 power limit when loading GuC 
> firmware")
> 
> This is the commit which introduced this sequence:
>   lock(>->reset.mutex);
>   lock(&hwmon->hwmon_lock);
> 
> Before this, everything was fine. So perhaps the Fixes tag should reference
> this commit?

OK, thanks for pointing that out.

> Otherwise the patch LGTM:
> 
> Reviewed-by: Ashutosh Dixit 

Thank you,
Janusz

Re: [PATCH v2] drm/i915/hwmon: Fix locking inversion in sysfs getter

[Janusz Krzysztofik]

On Tuesday, 12 March 2024 18:09:37 CET Andi Shyti wrote:
> Hi Janusz,
> 
> On Mon, Mar 11, 2024 at 09:34:58PM +0100, Janusz Krzysztofik wrote:
> > In i915 hwmon sysfs getter path we now take a hwmon_lock, then acquire an
> > rpm wakeref.  That results in lock inversion:
> > 
> > <4> [197.079335] ==
> > <4> [197.085473] WARNING: possible circular locking dependency detected
> > <4> [197.091611] 6.8.0-rc7-Patchwork_129026v7-gc4dc92fb1152+ #1 Not tainted
> > <4> [197.098096] --
> > <4> [197.104231] prometheus-node/839 is trying to acquire lock:
> > <4> [197.109680] 82764d80 (fs_reclaim){+.+.}-{0:0}, at: 
> > __kmalloc+0x9a/0x350
> > <4> [197.116939]
> > but task is already holding lock:
> > <4> [197.122730] 88811b772a40 (&hwmon->hwmon_lock){+.+.}-{3:3}, at: 
> > hwm_energy+0x4b/0x100 [i915]
> > <4> [197.131543]
> > which lock already depends on the new lock.
> > ...
> > <4> [197.507922] Chain exists of:
> >   fs_reclaim --> >->reset.mutex --> &hwmon->hwmon_lock
> > <4> [197.518528]  Possible unsafe locking scenario:
> > <4> [197.524411]CPU0CPU1
> > <4> [197.528916]
> > <4> [197.533418]   lock(&hwmon->hwmon_lock);
> > <4> [197.537237]lock(>->reset.mutex);
> > <4> [197.543376]lock(&hwmon->hwmon_lock);
> > <4> [197.549682]   lock(fs_reclaim);
> > ...
> > <4> [197.632548] Call Trace:
> > <4> [197.634990]  
> > <4> [197.637088]  dump_stack_lvl+0x64/0xb0
> > <4> [197.640738]  check_noncircular+0x15e/0x180
> > <4> [197.652968]  check_prev_add+0xe9/0xce0
> > <4> [197.656705]  __lock_acquire+0x179f/0x2300
> > <4> [197.660694]  lock_acquire+0xd8/0x2d0
> > <4> [197.673009]  fs_reclaim_acquire+0xa1/0xd0
> > <4> [197.680478]  __kmalloc+0x9a/0x350
> > <4> [197.689063]  acpi_ns_internalize_name.part.0+0x4a/0xb0
> > <4> [197.694170]  acpi_ns_get_node_unlocked+0x60/0xf0
> > <4> [197.720608]  acpi_ns_get_node+0x3b/0x60
> > <4> [197.724428]  acpi_get_handle+0x57/0xb0
> > <4> [197.728164]  acpi_has_method+0x20/0x50
> > <4> [197.731896]  acpi_pci_set_power_state+0x43/0x120
> > <4> [197.736485]  pci_power_up+0x24/0x1c0
> > <4> [197.740047]  pci_pm_default_resume_early+0x9/0x30
> > <4> [197.744725]  pci_pm_runtime_resume+0x2d/0x90
> > <4> [197.753911]  __rpm_callback+0x3c/0x110
> > <4> [197.762586]  rpm_callback+0x58/0x70
> > <4> [197.766064]  rpm_resume+0x51e/0x730
> > <4> [197.769542]  rpm_resume+0x267/0x730
> > <4> [197.773020]  rpm_resume+0x267/0x730
> > <4> [197.776498]  rpm_resume+0x267/0x730
> > <4> [197.779974]  __pm_runtime_resume+0x49/0x90
> > <4> [197.784055]  __intel_runtime_pm_get+0x19/0xa0 [i915]
> > <4> [197.789070]  hwm_energy+0x55/0x100 [i915]
> > <4> [197.793183]  hwm_read+0x9a/0x310 [i915]
> > <4> [197.797124]  hwmon_attr_show+0x36/0x120
> > <4> [197.800946]  dev_attr_show+0x15/0x60
> > <4> [197.804509]  sysfs_kf_seq_show+0xb5/0x100
> > 
> > Acquire the wakeref before the lock and hold it as long as the lock is
> > also held.  Follow that pattern across the whole source file where similar
> > lock inversion can happen.
> > 
> > v2: Keep hardware read under the lock so the whole operation of updating
> > energy from hardware is still atomic (Guenter),
> >   - instead, acquire the rpm wakeref before the lock and hold it as long
> > as the lock is held,
> >   - use the same aproach for other similar places across the i915_hwmon.c
> > source file (Rodrigo).
> > 
> > Fixes: c41b8bdcc297 ("drm/i915/hwmon: Show device level energy usage")
> > Signed-off-by: Janusz Krzysztofik 
> > Cc: Rodrigo Vivi 
> > Cc: Guenter Roeck 
> > Cc:  # v6.2+
> 
> Reviewed-by: Andi Shyti 
> 
> If you want I can change the Fixes tag as suggested by Ashutosh
> before applying the patch before pushing the change.

Yes, please do, and then also s/v6.2+/v6.5+/.

Thanks,
Janusz

> 
> Andi
> 

Re: [PATCH v5 1/4] drm/i915/gt: Disable HW load balancing for CCS

[Andi Shyti]

Hi Matt,

...

> >  #define GEN12_RCU_MODE _MMIO(0x14800)
> >  #define   GEN12_RCU_MODE_CCS_ENABLEREG_BIT(0)
> > +#define   XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE   REG_BIT(1)
> 
> Nitpick: we usually order register bits in descending order.  Aside from
> that,

I can take care of it.

> Reviewed-by: Matt Roper 

Thanks!
Andi

Re: [PATCH v5 2/4] drm/i915/gt: Refactor uabi engine class/instance list creation

[Andi Shyti]

On Tue, Mar 12, 2024 at 10:08:33AM -0700, Matt Roper wrote:
> On Fri, Mar 08, 2024 at 09:22:17PM +0100, Andi Shyti wrote:
> > For the upcoming changes we need a cleaner way to build the list
> > of uabi engines.
> > 
> > Suggested-by: Tvrtko Ursulin 
> > Signed-off-by: Andi Shyti 
> > Cc:  # v6.2+
> 
> I don't really see why we need patches 2 & 3 in this series. 

For patch number '2' We had a round of review with Tvrtko and we
wanted to avoid the change I pasted at the bottom[*], which would
decrease something that was increased earlier.

> If we want
> to restrict the platform to a single CCS engine for now (and give that
> single engine access to all of the cslices), it would be much simpler to
> only create a single intel_engine_cs which which would then cause both
> i915 and userspace to only consider a single engine, even if more than
> one is physically present.  That could be done with a simple adjustment
> to engine_mask_apply_compute_fuses() to mask off extra bits from the
> engine mask such that only a single CCS can get returned rather than the
> mask of all CCSs that are present.
> 
> Managing all of the engines in the KMD but only exposing one (some) of
> them to userspace might be something we need if you want to add extra
> functionality down to road to "hotplug" extra engines, or to allow
> userspace to explicitly request multi-CCS mode.  But none of that seems
> necessary for this series, especially for something you're backporting
> to stable kernels.

It's true, it would even be easier to mask out all the CCS
engines after the first. I thought of this.

On one hand hand, adding a for_each_available_engine() throught
the stable path its a bit of abusing, but it's functional to the
single CCS mode.

I was aiming for a longer term solution. If I add a patch to mask
off CCS engines, then I will need to revert it quite soon for
the stable release.

I'm not sure which one is better, though.

Thanks,
Andi

[*]
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 833987015b8b..7041acc77810 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -243,6 +243,15 @@  void intel_engines_driver_register(struct 
drm_i915_private *i915)
if (engine->uabi_class == I915_NO_UABI_CLASS)
continue;

+   /*
+* Do not list and do not count CCS engines other than the first
+*/
+   if (engine->uabi_class == I915_ENGINE_CLASS_COMPUTE &&
+   engine->uabi_instance > 0) {
+   i915->engine_uabi_class_count[engine->uabi_class]--;
+   continue;
+   }
+
rb_link_node(&engine->uabi_node, prev, p);
rb_insert_color(&engine->uabi_node, &i915->uabi_engines);

Re: [PATCH v2] drm/i915/hwmon: Fix locking inversion in sysfs getter

[Dixit, Ashutosh]

On Tue, 12 Mar 2024 13:34:25 -0700, Janusz Krzysztofik wrote:
>

Hi Janusz,

> On Tuesday, 12 March 2024 17:25:14 CET Dixit, Ashutosh wrote:
> > On Mon, 11 Mar 2024 13:34:58 -0700, Janusz Krzysztofik wrote:
> > >
> > > In i915 hwmon sysfs getter path we now take a hwmon_lock, then acquire an
> > > rpm wakeref.  That results in lock inversion:
> > >
> > > <4> [197.079335] ==
> > > <4> [197.085473] WARNING: possible circular locking dependency detected
> > > <4> [197.091611] 6.8.0-rc7-Patchwork_129026v7-gc4dc92fb1152+ #1 Not 
> > > tainted
> > > <4> [197.098096] --
> > > <4> [197.104231] prometheus-node/839 is trying to acquire lock:
> > > <4> [197.109680] 82764d80 (fs_reclaim){+.+.}-{0:0}, at: 
> > > __kmalloc+0x9a/0x350
> > > <4> [197.116939]
> > > but task is already holding lock:
> > > <4> [197.122730] 88811b772a40 (&hwmon->hwmon_lock){+.+.}-{3:3}, at: 
> > > hwm_energy+0x4b/0x100 [i915]
> > > <4> [197.131543]
> > > which lock already depends on the new lock.
> > > ...
> > > <4> [197.507922] Chain exists of:
> > >   fs_reclaim --> >->reset.mutex --> &hwmon->hwmon_lock
> > > <4> [197.518528]  Possible unsafe locking scenario:
> > > <4> [197.524411]CPU0CPU1
> > > <4> [197.528916]
> > > <4> [197.533418]   lock(&hwmon->hwmon_lock);
> > > <4> [197.537237]lock(>->reset.mutex);
> > > <4> [197.543376]lock(&hwmon->hwmon_lock);
> > > <4> [197.549682]   lock(fs_reclaim);
> > > ...
> > > <4> [197.632548] Call Trace:
> > > <4> [197.634990]  
> > > <4> [197.637088]  dump_stack_lvl+0x64/0xb0
> > > <4> [197.640738]  check_noncircular+0x15e/0x180
> > > <4> [197.652968]  check_prev_add+0xe9/0xce0
> > > <4> [197.656705]  __lock_acquire+0x179f/0x2300
> > > <4> [197.660694]  lock_acquire+0xd8/0x2d0
> > > <4> [197.673009]  fs_reclaim_acquire+0xa1/0xd0
> > > <4> [197.680478]  __kmalloc+0x9a/0x350
> > > <4> [197.689063]  acpi_ns_internalize_name.part.0+0x4a/0xb0
> > > <4> [197.694170]  acpi_ns_get_node_unlocked+0x60/0xf0
> > > <4> [197.720608]  acpi_ns_get_node+0x3b/0x60
> > > <4> [197.724428]  acpi_get_handle+0x57/0xb0
> > > <4> [197.728164]  acpi_has_method+0x20/0x50
> > > <4> [197.731896]  acpi_pci_set_power_state+0x43/0x120
> > > <4> [197.736485]  pci_power_up+0x24/0x1c0
> > > <4> [197.740047]  pci_pm_default_resume_early+0x9/0x30
> > > <4> [197.744725]  pci_pm_runtime_resume+0x2d/0x90
> > > <4> [197.753911]  __rpm_callback+0x3c/0x110
> > > <4> [197.762586]  rpm_callback+0x58/0x70
> > > <4> [197.766064]  rpm_resume+0x51e/0x730
> > > <4> [197.769542]  rpm_resume+0x267/0x730
> > > <4> [197.773020]  rpm_resume+0x267/0x730
> > > <4> [197.776498]  rpm_resume+0x267/0x730
> > > <4> [197.779974]  __pm_runtime_resume+0x49/0x90
> > > <4> [197.784055]  __intel_runtime_pm_get+0x19/0xa0 [i915]
> > > <4> [197.789070]  hwm_energy+0x55/0x100 [i915]
> > > <4> [197.793183]  hwm_read+0x9a/0x310 [i915]
> > > <4> [197.797124]  hwmon_attr_show+0x36/0x120
> > > <4> [197.800946]  dev_attr_show+0x15/0x60
> > > <4> [197.804509]  sysfs_kf_seq_show+0xb5/0x100
> > >
> > > Acquire the wakeref before the lock and hold it as long as the lock is
> > > also held.  Follow that pattern across the whole source file where similar
> > > lock inversion can happen.
> > >
> > > v2: Keep hardware read under the lock so the whole operation of updating
> > > energy from hardware is still atomic (Guenter),
> > >   - instead, acquire the rpm wakeref before the lock and hold it as long
> > > as the lock is held,
> > >   - use the same aproach for other similar places across the i915_hwmon.c
> > > source file (Rodrigo).
> > >
> > > Fixes: c41b8bdcc297 ("drm/i915/hwmon: Show device level energy usage")
> >
> > I would think that the lock inversion issue was introduced here:
> >
> > 1b44019a93e2 ("drm/i915/guc: Disable PL1 power limit when loading GuC 
> > firmware")
> >
> > This is the commit which introduced this sequence:
> > lock(>->reset.mutex);
> > lock(&hwmon->hwmon_lock);
> >
> > Before this, everything was fine. So perhaps the Fixes tag should reference
> > this commit?
>
> OK, thanks for pointing that out.
>
> > Otherwise the patch LGTM:
> >
> > Reviewed-by: Ashutosh Dixit 

Thanks for fixing this. Somehow I didn't see it when I did
1b44019a93e2. Maybe just didn't have lockdep enabled in the kernel.

Thanks.
--
Ashutosh

Re: [PATCH 1/5] drm/i915: Drop WA 16015675438

[Matt Roper]

On Wed, Mar 06, 2024 at 11:36:39AM -0800, Lucas De Marchi wrote:
> With dynamic load-balancing disabled on the compute side, there's no
> reason left to enable WA 16015675438. Drop it from both PVC and DG2.
> Note that this can be done because now the driver always set a fixed
> partition of EUs during initialization via the ccs_mode configuration.
> 
> The flag to GuC is still needed because of 18020744125, so update
> the comment accordingly.
> 
> Cc: Mateusz Jablonski 
> Cc: Michal Mrozek 
> Cc: Rodrigo Vivi 
> Signed-off-by: Lucas De Marchi 

Dynamic load-balancing disable hasn't landed in i915 yet (although it
probably will soon).  Assuming we wait for that to happen first before
applying this,

Reviewed-by: Matt Roper 


Matt

> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +-
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c  | 2 +-
>  2 files changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d67d44611c28..7f812409c30a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2928,14 +2928,10 @@ general_render_compute_wa_init(struct intel_engine_cs 
> *engine, struct i915_wa_li
>   wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 
> DISABLE_D8_D16_COASLESCE);
>   }
>  
> - if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) {
> + if (IS_PONTEVECCHIO(i915) || IS_DG2(i915))
>   /* Wa_14015227452:dg2,pvc */
>   wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
>  
> - /* Wa_16015675438:dg2,pvc */
> - wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, 
> GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
> - }
> -
>   if (IS_DG2(i915)) {
>   /*
>* Wa_16011620976:dg2_g11
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index d2b7425bbdcc..c6603793af89 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -315,7 +315,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>   if (IS_DG2_G11(gt->i915))
>   flags |= GUC_WA_CONTEXT_ISOLATION;
>  
> - /* Wa_16015675438 */
> + /* Wa_18020744125 */
>   if (!RCS_MASK(gt))
>   flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
>  
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv

[Matt Roper]

On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:
> PCI IDs for XEHPSDV were never added and platform always marked with
> force_probe. Drop what's not used and rename some places to either be
> xehp or dg2, depending on the platform/IP checks.
> 
> The registers not used anymore are also removed.
> 
> Signed-off-by: Lucas De Marchi 
> ---
> 
> Potential problem here that needs a deeper look, the changes in
> __gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
> I removed them, but it needs to be double checked with spec and CI
> results.
> 
...
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 76400e9c40f0..4f1e56187442 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1536,17 +1536,12 @@ static const struct intel_forcewake_range 
> __gen12_fw_ranges[] = {
>   GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /*  
> \
>   0x13200 - 0x133ff: VD2 (DG2 only)   
> \
>   0x13400 - 0x13fff: reserved */  
> \
> - GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only 
> */  \
> - GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only 
> */  \
> - GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only 
> */  \
> - GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only 
> */  \

We can't just remove ranges in the middle of the table since that breaks
the "watertight" table requirement that our selftests check for.  We
need to either roll the now-unused ranges into an adjacent range, or add
a new "reserved" range.

>   GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),   
> \
>   GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*
> \
>   0x15000 - 0x15fff: gt (DG2 only)
> \
>   0x16000 - 0x16dff: reserved */  
> \
>   GEN_FW_RANGE(0x16e00, 0x1, FORCEWAKE_RENDER),   
> \
> - GEN_FW_RANGE(0x2, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*  
> \
> - 0x2 - 0x20fff: VD0 (XEHPSDV only)   
> \
> + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*  
> \
>   0x21000 - 0x21fff: reserved */  
> \
>   GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),   
> \
>   GEN_FW_RANGE(0x24000, 0x2417f, 0), /*   
> \
> @@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range 
> __gen12_fw_ranges[] = {
>   0x1f6e00 - 0x1f7fff: reserved */
> \
>   GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
>  
> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
> - XEHP_FWRANGES(FORCEWAKE_GT)
> -};
> -
>  static const struct intel_forcewake_range __dg2_fw_ranges[] = {
>   XEHP_FWRANGES(FORCEWAKE_RENDER)

We can drop the macro here now and just make this a normal table like
everything else.


Matt

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv

[Lucas De Marchi]

On Tue, Mar 12, 2024 at 03:58:19PM -0700, Matt Roper wrote:

On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:

PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.

The registers not used anymore are also removed.

Signed-off-by: Lucas De Marchi 
---

Potential problem here that needs a deeper look, the changes in
__gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
I removed them, but it needs to be double checked with spec and CI
results.


...

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 76400e9c40f0..4f1e56187442 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1536,17 +1536,12 @@ static const struct intel_forcewake_range 
__gen12_fw_ranges[] = {
GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /*  
\
0x13200 - 0x133ff: VD2 (DG2 only)   
\
0x13400 - 0x13fff: reserved */  
\
-   GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only 
*/  \
-   GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only 
*/  \
-   GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only 
*/  \
-   GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only 
*/  \


We can't just remove ranges in the middle of the table since that breaks
the "watertight" table requirement that our selftests check for.  We
need to either roll the now-unused ranges into an adjacent range, or add
a new "reserved" range.


see 23n224gu57lfd4wbroqflav4pih6usrkf53q2ve4ntekhueylb@eqigxyktri6b





GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),   
\
GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*
\
0x15000 - 0x15fff: gt (DG2 only)
\
0x16000 - 0x16dff: reserved */  
\
GEN_FW_RANGE(0x16e00, 0x1, FORCEWAKE_RENDER),   
\
-   GEN_FW_RANGE(0x2, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*  
\
-   0x2 - 0x20fff: VD0 (XEHPSDV only)   
\
+   GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*  
\
0x21000 - 0x21fff: reserved */  
\
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),   
\
GEN_FW_RANGE(0x24000, 0x2417f, 0), /*   
\
@@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range 
__gen12_fw_ranges[] = {
0x1f6e00 - 0x1f7fff: reserved */
\
GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),

-static const struct intel_forcewake_range __xehp_fw_ranges[] = {
-   XEHP_FWRANGES(FORCEWAKE_GT)
-};
-
 static const struct intel_forcewake_range __dg2_fw_ranges[] = {
XEHP_FWRANGES(FORCEWAKE_RENDER)


We can drop the macro here now and just make this a normal table like
everything else.


will add that in v2 too, thanks

Lucas De Marchi

✗ Fi.CI.BUILD: failure for Disable automatic load CCS load balancing (rev8)

[Patchwork]

== Series Details ==

Series: Disable automatic load CCS load balancing (rev8)
URL   : https://patchwork.freedesktop.org/series/129951/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/129951/revisions/8/mbox/ not 
applied
Applying: drm/i915/gt: Disable HW load balancing for CCS
Applying: drm/i915/gt: Refactor uabi engine class/instance list creation
Applying: drm/i915/gt: Disable tests for CCS engines beyond the first
Applying: drm/i915/gt: Enable only one CCS for compute workload
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/gt/intel_engine_user.c
M   drivers/gpu/drm/i915/gt/intel_workarounds.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_workarounds.c
Auto-merging drivers/gpu/drm/i915/gt/intel_engine_user.c
CONFLICT (content): Merge conflict in 
drivers/gpu/drm/i915/gt/intel_engine_user.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0004 drm/i915/gt: Enable only one CCS for compute workload
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

[John Harrison]

On 3/12/2024 09:24, Matt Roper wrote:

On Thu, Mar 07, 2024 at 06:01:29PM -0800, john.c.harri...@intel.com wrote:

From: John Harrison 

An existing workaround has been extended in both platforms affected
and implementation complexity.

Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h |  3 ++-
  drivers/gpu/drm/i915/gt/uc/intel_guc.c|  3 ++-
  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 21 ++-
  3 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
index bebf28e3c4794..3e7060e859794 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
@@ -105,7 +105,8 @@ enum {
   * Workaround keys:
   */
  enum {
-   GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
0x9001,
+   GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE   = 
0x9001,   /* Wa_14019159160 */
+   GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE = 
0x9006,   /* Wa_14019159160 */
  };
  
  #endif /* _ABI_GUC_KLVS_ABI_H */

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 0c67d674c94de..4c3dae98656af 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -296,7 +296,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
  
  	/* Wa_16019325821 */

/* Wa_14019159160 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||

 From what I can see, this workaround is also needed on Xe_LPG+ (12.74)

Isn't that an Xe platform? Or is 12.74 just ARL?

John.


now.


Matt


+   IS_DG2(gt->i915))
flags |= GUC_WA_RCS_CCS_SWITCHOUT;
  
  	/*

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 5c9908b56616e..00fe3c21a9b1c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -815,23 +815,23 @@ guc_capture_prep_lists(struct intel_guc *guc)
return PAGE_ALIGN(total_size);
  }
  
-/* Wa_14019159160 */

-static u32 guc_waklv_ra_mode(struct intel_guc *guc, u32 offset, u32 remain)
+static void guc_waklv_enable_simple(struct intel_guc *guc, u32 *offset, u32 
*remain, u32 klv_id)
  {
u32 size;
u32 klv_entry[] = {
/* 16:16 key/length */
-   FIELD_PREP(GUC_KLV_0_KEY, 
GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE) |
+   FIELD_PREP(GUC_KLV_0_KEY, klv_id) |
FIELD_PREP(GUC_KLV_0_LEN, 0),
/* 0 dwords data */
};
  
  	size = sizeof(klv_entry);

-   GEM_BUG_ON(remain < size);
+   GEM_BUG_ON(*remain < size);
  
-	iosys_map_memcpy_to(&guc->ads_map, offset, klv_entry, size);

+   iosys_map_memcpy_to(&guc->ads_map, *offset, klv_entry, size);
  
-	return size;

+   *offset += size;
+   *remain -= size;
  }
  
  static void guc_waklv_init(struct intel_guc *guc)

@@ -850,10 +850,11 @@ static void guc_waklv_init(struct intel_guc *guc)
remain = guc_ads_waklv_size(guc);
  
  	/* Wa_14019159160 */

-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
-   size = guc_waklv_ra_mode(guc, offset, remain);
-   offset += size;
-   remain -= size;
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
IS_DG2(gt->i915)) {
+   guc_waklv_enable_simple(guc, &offset, &remain,
+   GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE);
+   guc_waklv_enable_simple(guc, &offset, &remain,
+   
GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE);
}
  
  	size = guc_ads_waklv_size(guc) - remain;

--
2.43.0

Re: [PATCH 1/5] drm/i915: Drop WA 16015675438

[Lucas De Marchi]

On Tue, Mar 12, 2024 at 03:54:09PM -0700, Matt Roper wrote:

On Wed, Mar 06, 2024 at 11:36:39AM -0800, Lucas De Marchi wrote:

With dynamic load-balancing disabled on the compute side, there's no
reason left to enable WA 16015675438. Drop it from both PVC and DG2.
Note that this can be done because now the driver always set a fixed
partition of EUs during initialization via the ccs_mode configuration.

The flag to GuC is still needed because of 18020744125, so update
the comment accordingly.

Cc: Mateusz Jablonski 
Cc: Michal Mrozek 
Cc: Rodrigo Vivi 
Signed-off-by: Lucas De Marchi 


Dynamic load-balancing disable hasn't landed in i915 yet (although it
probably will soon).  Assuming we wait for that to happen first before
applying this,

   Reviewed-by: Matt Roper 


Humn... I probably grepped the wrong tree for this one since I was
seeing ccs_mode being set. Indeed it isn't :-/, so I will have to land a
fix or revert since this patch already landed a few days ago.

Lucas De Marchi

Re: [PATCH] drm/i915/guc: Update w/a 14019159160

[Lucas De Marchi]

On Tue, Mar 12, 2024 at 04:43:06PM -0700, John Harrison wrote:

On 3/12/2024 09:24, Matt Roper wrote:

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 0c67d674c94de..4c3dae98656af 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -296,7 +296,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
/* Wa_16019325821 */
/* Wa_14019159160 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||

From what I can see, this workaround is also needed on Xe_LPG+ (12.74)

Isn't that an Xe platform? Or is 12.74 just ARL?


official xe platforms start with Xe2, with graphics version being 20

Lucas De Marchi

[PATCH v2 1/6] drm/i915: Drop dead code for xehpsdv

[Lucas De Marchi]

PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.

The registers not used anymore are also removed.

Reviewed-by: Rodrigo Vivi 
Signed-off-by: Lucas De Marchi 
---
 Documentation/gpu/rfc/i915_vm_bind.h  | 11 +--
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  | 40 
 drivers/gpu/drm/i915/gt/intel_gsc.c   | 15 ---
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 20 +---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 50 --
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   | 21 ++--
 drivers/gpu/drm/i915/gt/intel_lrc.c   | 43 -
 drivers/gpu/drm/i915/gt/intel_migrate.c   | 18 ++--
 drivers/gpu/drm/i915/gt/intel_mocs.c  | 31 --
 drivers/gpu/drm/i915/gt/intel_rps.c   |  2 -
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 95 ---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  4 +-
 drivers/gpu/drm/i915/i915_drv.h   |  4 -
 drivers/gpu/drm/i915/i915_hwmon.c |  6 --
 drivers/gpu/drm/i915/i915_pci.c   | 17 
 drivers/gpu/drm/i915/i915_perf.c  | 11 +--
 drivers/gpu/drm/i915/i915_reg.h   |  3 +-
 drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
 drivers/gpu/drm/i915/intel_device_info.c  |  1 -
 drivers/gpu/drm/i915/intel_device_info.h  |  1 -
 drivers/gpu/drm/i915/intel_step.c | 10 --
 drivers/gpu/drm/i915/intel_uncore.c   | 23 +
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  1 -
 .../gpu/drm/xe/compat-i915-headers/i915_drv.h |  2 -
 24 files changed, 55 insertions(+), 384 deletions(-)

diff --git a/Documentation/gpu/rfc/i915_vm_bind.h 
b/Documentation/gpu/rfc/i915_vm_bind.h
index 8a8fcd4fceac..bc26dc126104 100644
--- a/Documentation/gpu/rfc/i915_vm_bind.h
+++ b/Documentation/gpu/rfc/i915_vm_bind.h
@@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
  * Multiple VA mappings can be created to the same section of the object
  * (aliasing).
  *
- * The @start, @offset and @length must be 4K page aligned. However the DG2
- * and XEHPSDV has 64K page size for device local memory and has compact page
- * table. On those platforms, for binding device local-memory objects, the
- * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
- * the local memory 64K page and the system memory 4K page bindings in the same
- * 2M range.
+ * The @start, @offset and @length must be 4K page aligned. However the DG2 has
+ * 64K page size for device local memory and has compact page table. On that
+ * platform, for binding device local-memory objects, the @start, @offset and
+ * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K
+ * page and the system memory 4K page bindings in the same 2M range.
  *
  * Error code -EINVAL will be returned if @start, @offset and @length are not
  * properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index fa46d2308b0e..1bd0e041e15c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
 }
 
 static void
-xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
- struct i915_vma_resource *vma_res,
- struct sgt_dma *iter,
- unsigned int pat_index,
- u32 flags)
+xehp_ppgtt_insert_huge(struct i915_address_space *vm,
+  struct i915_vma_resource *vma_res,
+  struct sgt_dma *iter,
+  unsigned int pat_index,
+  u32 flags)
 {
const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
unsigned int rem = sg_dma_len(iter->sg);
@@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
struct sgt_dma iter = sgt_dma(vma_res);
 
if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
-   if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
-   xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, 
pat_index, flags);
+   if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
+   xehp_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, 
flags);
else
gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, 
flags);
} else  {
@@ -781,11 +781,11 @@ static void gen8_ppgtt_insert_entry(struct 
i915_address_space *vm,
drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
 }
 
-static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
-   dma_addr_t addr,
-   u64 offset,
- 

[PATCH v2 4/6] drm/i915: Update IP_VER(12, 50)

[Lucas De Marchi]

With no platform using graphics/media IP_VER(12, 50), replace the
checks throughout the code with IP_VER(12, 55) so the code makes sense
by itself with no additional explanation of previous baggage.

Reviewed-by: Rodrigo Vivi 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/gem/selftests/huge_pages.c|  4 ++--
 .../gpu/drm/i915/gem/selftests/i915_gem_client_blt.c   |  8 
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c  |  5 ++---
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c   | 10 +-
 drivers/gpu/drm/i915/gt/intel_gt.c |  4 ++--
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c |  4 ++--
 drivers/gpu/drm/i915/gt/intel_gt_mcr.h |  2 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c|  8 
 drivers/gpu/drm/i915/gt/intel_migrate.c|  4 ++--
 drivers/gpu/drm/i915/gt/intel_mocs.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c   |  4 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c|  4 ++--
 drivers/gpu/drm/i915/gt/uc/intel_guc.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |  4 ++--
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c  |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c  |  2 +-
 drivers/gpu/drm/i915/i915_getparam.c   |  4 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c  |  5 ++---
 drivers/gpu/drm/i915/i915_perf.c   |  8 
 drivers/gpu/drm/i915/i915_query.c  |  2 +-
 drivers/gpu/drm/i915/intel_uncore.c|  2 +-
 23 files changed, 46 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 3ff3d8889c6c..edb54903be0a 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -713,7 +713,7 @@ static int igt_ppgtt_huge_fill(void *arg)
 {
struct drm_i915_private *i915 = arg;
unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
-   bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+   bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
struct i915_address_space *vm;
struct i915_gem_context *ctx;
unsigned long max_pages;
@@ -857,7 +857,7 @@ static int igt_ppgtt_huge_fill(void *arg)
 static int igt_ppgtt_64K(void *arg)
 {
struct drm_i915_private *i915 = arg;
-   bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+   bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 10a7847f1b04..bac15196b4d2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -117,7 +117,7 @@ static bool fastblit_supports_x_tiling(const struct 
drm_i915_private *i915)
if (gen < 12)
return true;
 
-   if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+   if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
return false;
 
return HAS_DISPLAY(i915);
@@ -166,7 +166,7 @@ static int prepare_blit(const struct tiled_blits *t,
src_pitch = t->width; /* in dwords */
if (src->tiling == CLIENT_TILING_Y) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
-   if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= 
IP_VER(12, 50))
+   if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= 
IP_VER(12, 55))
src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
} else if (src->tiling == CLIENT_TILING_X) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
@@ -177,7 +177,7 @@ static int prepare_blit(const struct tiled_blits *t,
dst_pitch = t->width; /* in dwords */
if (dst->tiling == CLIENT_TILING_Y) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
-   if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= 
IP_VER(12, 50))
+   if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= 
IP_VER(12, 55))
dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
} else if (dst->tiling == CLIENT_TILING_X) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
@@ -365,7 +365,7 @@ static u64 tiled_offset(const struct intel_gt *gt,
v += x;
 
swizzle = gt->ggtt->bit_6_swizzle_x

[PATCH v2 2/6] drm/i915: Remove XEHP_FWRANGES()

[Lucas De Marchi]

Now that DG2 is the only user of this forcewake table, remove the macro
and use FORCEWAKE_RENDER explicitly for range 0xd800 - 0xd87f.

Suggested-by: Matt Roper 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/intel_uncore.c | 297 ++--
 1 file changed, 145 insertions(+), 152 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 7695bb946fff..b525318dbd53 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1471,159 +1471,152 @@ static const struct intel_forcewake_range 
__gen12_fw_ranges[] = {
0x1d3f00 - 0x1d3fff: VD2 */
 };
 
-/*
- * Graphics IP version 12.55 brings a slight change to the 0xd800 range,
- * switching it from the GT domain to the render domain.
- */
-#define XEHP_FWRANGES(FW_RANGE_D800)   \
-   GEN_FW_RANGE(0x0, 0x1fff, 0), /*
\
- 0x0 -  0xaff: reserved
\
-   0xb00 - 0x1fff: always on */
\
-   GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 
\
-   GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), 
\
-   GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* 
\
-   0x4b00 - 0x4fff: reserved   
\
-   0x5000 - 0x51ff: always on */   
\
-   GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 
\
-   GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 
\
-   GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 
\
-   GEN_FW_RANGE(0x8160, 0x81ff, 0), /* 
\
-   0x8160 - 0x817f: reserved   
\
-   0x8180 - 0x81ff: always on */   
\
-   GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), 
\
-   GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 
\
-   GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /*  
\
-   0x8500 - 0x87ff: gt 
\
-   0x8800 - 0x8c7f: reserved   
\
-   0x8c80 - 0x8cff: gt (DG2 only) */   
\
-   GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /*  
\
-   0x8d00 - 0x8dff: render (DG2 only)  
\
-   0x8e00 - 0x8fff: reserved */
\
-   GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /*  
\
-   0x9000 - 0x947f: gt 
\
-   0x9480 - 0x94cf: reserved */
\
-   GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 
\
-   GEN_FW_RANGE(0x9560, 0x967f, 0), /* 
\
-   0x9560 - 0x95ff: always on  
\
-   0x9600 - 0x967f: reserved */
\
-   GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*  
\
-   0x9680 - 0x96ff: render (DG2 only)  
\
-   0x9700 - 0x97ff: reserved */
\
-   GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*  
\
-   0x9800 - 0xb4ff: gt 
\
-   0xb500 - 0xbfff: reserved   
\
-   0xc000 - 0xcfff: gt */  
\
-   GEN_FW_RANGE(0xd000, 0xd7ff, 0),
\
-   GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800),\
-   GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), 
\
-   GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), 
\
-   GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*  
\
-   0xdd00 - 0xddff: gt 
\
-   0xde00 - 0xde7f: reserved */
\
-   GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*  
\
-   0xde80 - 0xdfff: render 
\
-   0xe000 - 0xe0ff: reserved   
\
-   0xe100 - 0xe8ff: render */  
\
-   GEN_FW_RANGE(0xe900, 0x, FORCEWAKE_GT), /*  
\
-   0xe900 - 0xe9ff: gt

✗ Fi.CI.IGT: failure for drm/i915/selftests: Pick correct caching mode.

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Pick correct caching mode.
URL   : https://patchwork.freedesktop.org/series/131019/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14420_full -> Patchwork_131019v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_131019v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_131019v1_full, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/index.html

Participating hosts (8 -> 9)
--

  Additional (1): shard-dg2-4 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_131019v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_eio@context-create:
- shard-dg1:  NOTRUN -> [ABORT][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg1-12/igt@gem_...@context-create.html

  * igt@gem_eio@create-ext:
- shard-dg1:  [PASS][2] -> [ABORT][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-dg1-16/igt@gem_...@create-ext.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg1-17/igt@gem_...@create-ext.html

  * igt@gem_exec_capture@capture@vcs0-lmem0:
- shard-dg2:  [PASS][4] -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-dg2-2/igt@gem_exec_capture@capt...@vcs0-lmem0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg2-10/igt@gem_exec_capture@capt...@vcs0-lmem0.html

  * igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [PASS][6] -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-tglu-3/igt@i915_module_l...@reload-with-fault-injection.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-tglu-9/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-dg2:  NOTRUN -> [ABORT][8] +1 other test abort
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg2-8/igt@kms_big...@linear-8bpp-rotate-90.html

  
 Warnings 

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-snb:  [SKIP][9] -> [FAIL][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/shard-snb2/igt@kms_frontbuffer_track...@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-snb6/igt@kms_frontbuffer_track...@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_create@create-ext-cpu-access-big:
- {shard-dg2-4}:  NOTRUN -> [INCOMPLETE][11]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg2-4/igt@gem_cre...@create-ext-cpu-access-big.html

  * igt@kms_hdr@bpc-switch-suspend:
- {shard-dg2-4}:  NOTRUN -> [SKIP][12] +1 other test skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg2-4/igt@kms_...@bpc-switch-suspend.html

  
New tests
-

  New tests have been introduced between CI_DRM_14420_full and 
Patchwork_131019v1_full:

### New IGT tests (2) ###

  * igt@gem_lmem_swapping:
- Statuses :
- Exec time: [None] s

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [4.45] s

  

Known issues


  Here are the changes found in Patchwork_131019v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg2:  NOTRUN -> [SKIP][13] ([i915#8411])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg2-8/igt@api_intel...@blit-reloc-purge-cache.html

  * igt@device_reset@cold-reset-bound:
- shard-dg1:  NOTRUN -> [SKIP][14] ([i915#7701])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg1-15/igt@device_re...@cold-reset-bound.html

  * igt@drm_fdinfo@busy-hang@bcs0:
- shard-dg2:  NOTRUN -> [SKIP][15] ([i915#8414]) +10 other tests 
skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg2-2/igt@drm_fdinfo@busy-h...@bcs0.html

  * igt@drm_fdinfo@busy-idle-check-all@vcs1:
- shard-dg1:  NOTRUN -> [SKIP][16] ([i915#8414]) +5 other tests skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131019v1/shard-dg1-13/igt@drm_fdinfo@busy-idle-check-...@vcs1.html

  * 

[PATCH v2 3/6] drm/i915: Stop inheriting IP_VER(12, 50)

[Lucas De Marchi]

All the platforms that inherit the media/graphics version
from XE_HPM_FEATURES / XE_HP_FEATURES just override it to another
version. Just set the version directly in the respective struct
and remove the versions from the _FEATURES macros. Since that was the
only use for XE_HPM_FEATURES, remove it completely.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/i915_pci.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b318b7c6bf73..8b673fdcf178 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -705,8 +705,6 @@ static const struct intel_device_info adl_p_info = {
I915_GTT_PAGE_SIZE_2M
 
 #define XE_HP_FEATURES \
-   .__runtime.graphics.ip.ver = 12, \
-   .__runtime.graphics.ip.rel = 50, \
XE_HP_PAGE_SIZES, \
TGL_CACHELEVEL, \
.dma_mask_size = 46, \
@@ -730,15 +728,12 @@ static const struct intel_device_info adl_p_info = {
.__runtime.ppgtt_size = 48, \
.__runtime.ppgtt_type = INTEL_PPGTT_FULL
 
-#define XE_HPM_FEATURES \
-   .__runtime.media.ip.ver = 12, \
-   .__runtime.media.ip.rel = 50
-
 #define DG2_FEATURES \
XE_HP_FEATURES, \
-   XE_HPM_FEATURES, \
DGFX_FEATURES, \
+   .__runtime.graphics.ip.ver = 12, \
.__runtime.graphics.ip.rel = 55, \
+   .__runtime.media.ip.ver = 12, \
.__runtime.media.ip.rel = 55, \
PLATFORM(INTEL_DG2), \
.has_64k_pages = 1, \
@@ -773,9 +768,10 @@ static const struct intel_device_info ats_m_info = {
 __maybe_unused
 static const struct intel_device_info pvc_info = {
XE_HPC_FEATURES,
-   XE_HPM_FEATURES,
DGFX_FEATURES,
+   .__runtime.graphics.ip.ver = 12,
.__runtime.graphics.ip.rel = 60,
+   .__runtime.media.ip.ver = 12,
.__runtime.media.ip.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
.has_flat_ccs = 0,
-- 
2.43.0

[PATCH v2 5/6] drm/i915: Drop dead code for pvc

[Lucas De Marchi]

PCI IDs for PVC were never added and platform always marked with
force_probe. Drop what's not used and rename some places as needed.

The registers not used anymore are also removed.

Reviewed-by: Rodrigo Vivi 
Signed-off-by: Lucas De Marchi 
---
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |   2 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |   3 -
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  33 
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c|  30 +---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |   9 --
 drivers/gpu/drm/i915/gt/intel_mocs.c  |  19 ---
 drivers/gpu/drm/i915/gt/intel_rps.c   |   4 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c  |   9 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  84 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |   4 -
 drivers/gpu/drm/i915/i915_debugfs.c   |  12 --
 drivers/gpu/drm/i915/i915_drv.h   |   9 --
 drivers/gpu/drm/i915/i915_pci.c   |  36 -
 drivers/gpu/drm/i915/i915_reg.h   |   1 -
 drivers/gpu/drm/i915/intel_clock_gating.c |  16 +-
 drivers/gpu/drm/i915/intel_device_info.c  |   1 -
 drivers/gpu/drm/i915/intel_device_info.h  |   1 -
 drivers/gpu/drm/i915/intel_step.c |  70 +
 drivers/gpu/drm/i915/intel_uncore.c   | 142 --
 drivers/gpu/drm/i915/selftests/intel_uncore.c |   2 -
 .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   4 -
 21 files changed, 10 insertions(+), 481 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0c5cdab278b6..1495b6074492 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -386,7 +386,7 @@ struct drm_i915_gem_object {
 * and kernel mode driver for caching policy control after GEN12.
 * In the meantime platform specific tables are created to translate
 * i915_cache_level into pat index, for more details check the macros
-* defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.
+* defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.
 * For backward compatibility, this field contains values exactly match
 * the entries of enum i915_cache_level for pre-GEN12 platforms (See
 * LEGACY_CACHELEVEL), so that the PTE encode functions for these
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index f59914df6b5a..e9f65f27b53f 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -189,9 +189,6 @@ static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs 
*engine)
 {
i915_reg_t reg = gen12_get_aux_inv_reg(engine);
 
-   if (IS_PONTEVECCHIO(engine->i915))
-   return false;
-
/*
 * So far platforms supported by i915 having flat ccs do not require
 * AUX invalidation. Check also whether the engine requires it.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 75bde8c1aa5d..396f5fe993c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -839,38 +839,6 @@ static void engine_mask_apply_compute_fuses(struct 
intel_gt *gt)
}
 }
 
-static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
-{
-   struct drm_i915_private *i915 = gt->i915;
-   struct intel_gt_info *info = >->info;
-   unsigned long meml3_mask;
-   unsigned long quad;
-
-   if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
- GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
-   return;
-
-   meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
-   meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
-
-   /*
-* Link Copy engines may be fused off according to meml3_mask. Each
-* bit is a quad that houses 2 Link Copy and two Sub Copy engines.
-*/
-   for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
-   unsigned int instance = quad * 2 + 1;
-   intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
-  _BCS(instance));
-
-   if (mask & info->engine_mask) {
-   gt_dbg(gt, "bcs%u fused off\n", instance);
-   gt_dbg(gt, "bcs%u fused off\n", instance + 1);
-
-   info->engine_mask &= ~mask;
-   }
-   }
-}
-
 /*
  * Determine which engines are fused off in our particular hardware.
  * Note that we have a catch-22 situation where we need to be able to access
@@ -889,7 +857,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt 
*gt)
 
engine_mask_apply_media_fuses(gt);
engine_mask_apply_compute_fuses(gt);
-   engine_mask_apply_copy_fuses(gt);
 
/*
 * The only use of the GSC CS is to

[PATCH v2 6/6] drm/i915: Remove special handling for !RCS_MASK()

[Lucas De Marchi]

With both XEHPSDV and PVC removed (as platforms, most of their code
remain used by others), there's no need to handle !RCS_MASK() as
other platforms don't ever have fused-off render. Remove those code
paths and the special WA flag when initializing GuC.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c   | 5 ++---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c  | 4 
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 -
 3 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 396f5fe993c3..476651bd0a21 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -497,9 +497,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum 
intel_engine_id id,
engine->logical_mask = BIT(logical_instance);
__sprint_engine_name(engine);
 
-   if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
-__ffs(CCS_MASK(engine->gt)) == engine->instance) ||
-engine->class == RENDER_CLASS)
+   if ((engine->class == COMPUTE_CLASS || engine->class == RENDER_CLASS) &&
+   __ffs(CCS_MASK(engine->gt) | RCS_MASK(engine->gt)) == 
engine->instance)
engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
 
/* features common between engines sharing EUs */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 217277329546..3dd7699f2ad3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -320,10 +320,6 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (IS_DG2_G11(gt->i915))
flags |= GUC_WA_CONTEXT_ISOLATION;
 
-   /* Wa_18020744125 */
-   if (!RCS_MASK(gt))
-   flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
-
/*
 * Wa_14018913170: Applicable to all platforms supported by i915 so
 * don't bother testing for all X/Y/Z platforms explicitly.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 14797e80bc92..1ad31a743197 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -101,7 +101,6 @@
 #define   GUC_WA_RCS_CCS_SWITCHOUT BIT(16)
 #define   GUC_WA_HOLD_CCS_SWITCHOUTBIT(17)
 #define   GUC_WA_POLLCSBIT(18)
-#define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
 #define   GUC_WA_ENABLE_TSC_CHECK_ON_RC6   BIT(22)
 
 #define GUC_CTL_FEATURE2
-- 
2.43.0

[PATCH v2 0/6] drm/i915: cleanup dead code

[Lucas De Marchi]

Remove platforms that never had their PCI IDs added to the driver and
are of course marked with requiring force_probe. Note that most of the
code for those platforms is actually used by subsequent ones, so it's
not a huge amount of code being removed.

drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h is also changed on the
xe side, but that should be ok: the defines are there only for compat
reasons while building the display side (and none of these platforms
have display, so it's build-issue only).

v2: handle feedback from Rodrigo, Tvrtko and Matt Roper, mainly

- Add a patch to remove XEHP_FWRANGES()
- Split out a patch touching i915_pci.c, removing the version from
  the _FEATURES macros
- Fix holes in the forcewake tables

Lucas De Marchi (6):
  drm/i915: Drop dead code for xehpsdv
  drm/i915: Remove XEHP_FWRANGES()
  drm/i915: Stop inheriting IP_VER(12, 50)
  drm/i915: Update IP_VER(12, 50)
  drm/i915: Drop dead code for pvc
  drm/i915: Remove special handling for !RCS_MASK()

 Documentation/gpu/rfc/i915_vm_bind.h  |  11 +-
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |   2 +-
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |   4 +-
 .../i915/gem/selftests/i915_gem_client_blt.c  |   8 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |   5 +-
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  |  40 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  43 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  10 +-
 drivers/gpu/drm/i915/gt/intel_gsc.c   |  15 -
 drivers/gpu/drm/i915/gt/intel_gt.c|   4 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c|  52 +--
 drivers/gpu/drm/i915/gt/intel_gt_mcr.h|   2 +-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  59 ---
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   |  21 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c   |   2 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c   |  51 +--
 drivers/gpu/drm/i915/gt/intel_migrate.c   |  22 +-
 drivers/gpu/drm/i915/gt/intel_mocs.c  |  52 +--
 drivers/gpu/drm/i915/gt/intel_rps.c   |   6 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c  |  13 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 183 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|   6 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|   4 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |   2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 -
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |   2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |   4 -
 drivers/gpu/drm/i915/i915_debugfs.c   |  12 -
 drivers/gpu/drm/i915/i915_drv.h   |  13 -
 drivers/gpu/drm/i915/i915_getparam.c  |   4 +-
 drivers/gpu/drm/i915/i915_gpu_error.c |   5 +-
 drivers/gpu/drm/i915/i915_hwmon.c |   6 -
 drivers/gpu/drm/i915/i915_pci.c   |  61 +--
 drivers/gpu/drm/i915/i915_perf.c  |  19 +-
 drivers/gpu/drm/i915/i915_query.c |   2 +-
 drivers/gpu/drm/i915/i915_reg.h   |   4 +-
 drivers/gpu/drm/i915/intel_clock_gating.c |  26 +-
 drivers/gpu/drm/i915/intel_device_info.c  |   2 -
 drivers/gpu/drm/i915/intel_device_info.h  |   2 -
 drivers/gpu/drm/i915/intel_step.c |  80 +---
 drivers/gpu/drm/i915/intel_uncore.c   | 380 +-
 drivers/gpu/drm/i915/selftests/intel_uncore.c |   3 -
 .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   6 -
 43 files changed, 215 insertions(+), 1034 deletions(-)

-- 
2.43.0

✗ Fi.CI.CHECKPATCH: warning for drm/i915: cleanup dead code

[Patchwork]

== Series Details ==

Series: drm/i915: cleanup dead code
URL   : https://patchwork.freedesktop.org/series/131049/
State : warning

== Summary ==

Error: dim checkpatch failed
0eed5859f6c8 drm/i915: Drop dead code for xehpsdv
-:918: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#918: FILE: drivers/gpu/drm/i915/intel_uncore.c:1538:
+   0x13400 - 0x147ff: reserved */  
\

-:928: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#928: FILE: drivers/gpu/drm/i915/intel_uncore.c:1544:
+   GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /*
\
+   0x16e00 - 0x1: render   
\

-:929: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#929: FILE: drivers/gpu/drm/i915/intel_uncore.c:1545:
+   0x2 - 0x21fff: reserved */  
\

total: 0 errors, 3 warnings, 0 checks, 818 lines checked
d6ab3160894a drm/i915: Remove XEHP_FWRANGES()
-:174: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#174: FILE: drivers/gpu/drm/i915/intel_uncore.c:1476:
+   GEN_FW_RANGE(0x0, 0x1fff, 0), /*
+ 0x0 -  0xaff: reserved

-:175: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#175: FILE: drivers/gpu/drm/i915/intel_uncore.c:1477:
+   0xb00 - 0x1fff: always on */

-:179: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#179: FILE: drivers/gpu/drm/i915/intel_uncore.c:1481:
+   GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*
+   0x4b00 - 0x4fff: reserved

-:180: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#180: FILE: drivers/gpu/drm/i915/intel_uncore.c:1482:
+   0x5000 - 0x51ff: always on */

-:185: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#185: FILE: drivers/gpu/drm/i915/intel_uncore.c:1487:
+   GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
+   0x8160 - 0x817f: reserved

-:186: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#186: FILE: drivers/gpu/drm/i915/intel_uncore.c:1488:
+   0x8180 - 0x81ff: always on */

-:190: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#190: FILE: drivers/gpu/drm/i915/intel_uncore.c:1492:
+   GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /*
+   0x8500 - 0x87ff: gt

-:192: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#192: FILE: drivers/gpu/drm/i915/intel_uncore.c:1494:
+   0x8c80 - 0x8cff: gt (DG2 only) */

-:194: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#194: FILE: drivers/gpu/drm/i915/intel_uncore.c:1496:
+   GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /*
+   0x8d00 - 0x8dff: render (DG2 only)

-:195: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#195: FILE: drivers/gpu/drm/i915/intel_uncore.c:1497:
+   0x8e00 - 0x8fff: reserved */

-:197: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#197: FILE: drivers/gpu/drm/i915/intel_uncore.c:1499:
+   GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /*
+   0x9000 - 0x947f: gt

-:198: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#198: FILE: drivers/gpu/drm/i915/intel_uncore.c:1500:
+   0x9480 - 0x94cf: reserved */

-:201: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#201: FILE: drivers/gpu/drm/i915/intel_uncore.c:1503:
+   GEN_FW_RANGE(0x9560, 0x967f, 0), /*
+   0x9560 - 0x95ff: always on

-:202: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#202: FILE: drivers/gpu/drm/i915/intel_uncore.c:1504:
+   0x9600 - 0x967f: reserved */

-:204: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#204: FILE: drivers/gpu/drm/i915/intel_uncore.c:1506:
+   GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
+   0x9680 - 0x96ff: render

-:205: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#205: FILE: drivers/gpu/drm/i915/intel_uncore.c:1507:
+   0x9700 - 0x97ff: reserved */

-:207: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#207: FILE: drivers/gpu/drm/i915/intel_uncore.c:1509:
+   GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
+   0x9800 - 0xb4ff: gt

-:209: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a 
separate line
#209: FILE: drivers/gpu/drm/i915/intel_uncore.c:1511:
+   0xc000 - 0xcfff: gt */

-:215: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#215: FILE: drivers/gpu/drm/i915/intel_uncore.c:1517:
+   GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
+   0xdd00 - 0xddff: gt

-:216: WARNING:B

✗ Fi.CI.SPARSE: warning for drm/i915: cleanup dead code

[Patchwork]

== Series Details ==

Series: drm/i915: cleanup dead code
URL   : https://patchwork.freedesktop.org/series/131049/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.BAT: failure for drm/i915: cleanup dead code

[Patchwork]

== Series Details ==

Series: drm/i915: cleanup dead code
URL   : https://patchwork.freedesktop.org/series/131049/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14423 -> Patchwork_131049v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_131049v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_131049v1, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/index.html

Participating hosts (33 -> 29)
--

  Missing(4): bat-dg1-7 bat-jsl-1 fi-glk-j4005 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_131049v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gtt:
- bat-arls-2: NOTRUN -> [ABORT][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@i915_selftest@l...@gtt.html

  
Known issues


  Here are the changes found in Patchwork_131049v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-cfl-8109u:   [FAIL][2] ([i915#8293]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14423/fi-cfl-8109u/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/fi-cfl-8109u/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u:   NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u:   NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html
- bat-arls-2: NOTRUN -> [SKIP][6] ([i915#10213]) +3 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-arls-2: NOTRUN -> [SKIP][7] ([i915#4083])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-arls-2: NOTRUN -> [SKIP][8] ([i915#10196] / [i915#4077]) +2 
other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-arls-2: NOTRUN -> [SKIP][9] ([i915#10197] / [i915#10211] / 
[i915#4079])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-arls-2: NOTRUN -> [SKIP][10] ([i915#10206] / [i915#4079])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-arls-2: NOTRUN -> [SKIP][11] ([i915#10209])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- bat-rpls-3: [PASS][12] -> [DMESG-WARN][13] ([i915#5591])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14423/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-rpls-3/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- bat-dg2-8:  NOTRUN -> [ABORT][14] ([i915#10366])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-dg2-8/igt@i915_selftest@l...@hugepages.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10200]) +9 other tests 
skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10202]) +1 other test skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-arls-2: NOTRUN -> [SKIP][17] ([i915#9886])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-arls-2: NOTRUN -> [SKIP][18] ([i915#10207])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131049v1/bat-arls-2/igt@kms_force_connect

✗ Fi.CI.IGT: failure for Enable LNL display (rev2)

[Patchwork]

== Series Details ==

Series: Enable LNL display (rev2)
URL   : https://patchwork.freedesktop.org/series/130689/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14421_full -> Patchwork_130689v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_130689v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_130689v2_full, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (8 -> 8)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_130689v2_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/shard-tglu-4/igt@i915_module_l...@reload-with-fault-injection.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-tglu-8/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-hdmi-a-3:
- shard-dg2:  NOTRUN -> [ABORT][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-dg2-6/igt@kms_pipe_crc_basic@hang-read-...@pipe-a-hdmi-a-3.html

  
New tests
-

  New tests have been introduced between CI_DRM_14421_full and 
Patchwork_130689v2_full:

### New IGT tests (2) ###

  * igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [2.70] s

  * igt@kms_cursor_crc@cursor-random-64x64@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [4.40] s

  

Known issues


  Here are the changes found in Patchwork_130689v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@crc32:
- shard-dg1:  NOTRUN -> [SKIP][4] ([i915#6230])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-dg1-16/igt@api_intel...@crc32.html

  * igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1:  NOTRUN -> [SKIP][5] ([i915#8414]) +11 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-dg1-15/igt@drm_fdinfo@busy-check-...@bcs0.html

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl:  [PASS][6] -> [FAIL][7] ([i915#7742])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/shard-rkl-5/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html

  * igt@drm_fdinfo@virtual-busy-all:
- shard-dg2:  NOTRUN -> [SKIP][8] ([i915#8414])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-dg2-8/igt@drm_fdi...@virtual-busy-all.html

  * igt@gem_busy@semaphore:
- shard-dg1:  NOTRUN -> [SKIP][9] ([i915#3936])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-dg1-17/igt@gem_b...@semaphore.html

  * igt@gem_ccs@block-multicopy-inplace:
- shard-dg1:  NOTRUN -> [SKIP][10] ([i915#3555] / [i915#9323]) +1 
other test skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-dg1-15/igt@gem_...@block-multicopy-inplace.html

  * igt@gem_ccs@suspend-resume:
- shard-rkl:  NOTRUN -> [SKIP][11] ([i915#9323])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-rkl-5/igt@gem_...@suspend-resume.html

  * igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb:  NOTRUN -> [SKIP][12] ([i915#1099])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-snb5/igt@gem_ctx_persiste...@engines-hostile-preempt.html

  * igt@gem_ctx_sseu@invalid-sseu:
- shard-rkl:  NOTRUN -> [SKIP][13] ([i915#280])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-rkl-5/igt@gem_ctx_s...@invalid-sseu.html

  * igt@gem_eio@kms:
- shard-dg1:  NOTRUN -> [FAIL][14] ([i915#5784])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-dg1-15/igt@gem_...@kms.html

  * igt@gem_eio@reset-stress:
- shard-dg2:  [PASS][15] -> [FAIL][16] ([i915#5784])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14421/shard-dg2-5/igt@gem_...@reset-stress.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-dg2-5/igt@gem_...@reset-stress.html

  * igt@gem_exec_balancer@bonded-sync:
- shard-dg1:  NOTRUN -> [SKIP][17] ([i915#4771])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130689v2/shard-dg1-12/igt@gem_exec_balan...@bonded-sync.html

Re: [PATCH v2 3/6] drm/i915: Stop inheriting IP_VER(12, 50)

[Gustavo Sousa]

Quoting Lucas De Marchi (2024-03-12 20:51:42-03:00)
>All the platforms that inherit the media/graphics version
>from XE_HPM_FEATURES / XE_HP_FEATURES just override it to another
>version. Just set the version directly in the respective struct
>and remove the versions from the _FEATURES macros. Since that was the
>only use for XE_HPM_FEATURES, remove it completely.
>
>Signed-off-by: Lucas De Marchi 

I took a look at the patch and also checked with the following script:

#!/bin/bash

parse_info()
{
local rev=$1
local out=$2

echo "Generating info for $(git log -n1 --format="%h %s" "$rev")"
git checkout "$rev"
make drivers/gpu/drm/i915/i915_pci.i
echo

cat drivers/gpu/drm/i915/i915_pci.i \
| grep -o \
-e 'struct\s\+intel_device_info\s\+[^=]\+' \
-e '.__runtime.\(graphics\|media\).ip.\(ver\|rel\)\s*=[^,]\+' \
| awk '
/intel_device_info/ { cur_info_var = $3 }
/__runtime/ { info[cur_info_var "::" $1] = cur_info_var "::" $0 
}
END {
for (k in info) {
print info[k]
}
}
' \
| sort \
> $out
}

parse_info c70b324e95d2a06d663111ce3498729e1f9729f9~ /tmp/a
parse_info c70b324e95d2a06d663111ce3498729e1f9729f9 /tmp/b

diff_content=$(git diff --no-index -- /tmp/a /tmp/b)
if [[ -z $diff_content ]]; then
echo "Patch looks sane :-)"
else
echo "Patch generates different IP versions!"
echo
print $diff_content
fi

And I got the following output:

Generating info for eba0fccec7de drm/i915: Remove XEHP_FWRANGES()
Previous HEAD position was c70b324e95d2 drm/i915: Stop inheriting 
IP_VER(12, 50)
HEAD is now at eba0fccec7de drm/i915: Remove XEHP_FWRANGES()
  CALLscripts/checksyscalls.sh
  DESCEND objtool
  INSTALL libsubcmd_headers
  CPP [M] drivers/gpu/drm/i915/i915_pci.i

Generating info for c70b324e95d2 drm/i915: Stop inheriting IP_VER(12, 50)
Previous HEAD position was eba0fccec7de drm/i915: Remove XEHP_FWRANGES()
HEAD is now at c70b324e95d2 drm/i915: Stop inheriting IP_VER(12, 50)
  CALLscripts/checksyscalls.sh
  DESCEND objtool
  INSTALL libsubcmd_headers
  CPP [M] drivers/gpu/drm/i915/i915_pci.i

Patch looks sane :-)

Based on that,

Reviewed-by: Gustavo Sousa 

>---
> drivers/gpu/drm/i915/i915_pci.c | 12 
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index b318b7c6bf73..8b673fdcf178 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -705,8 +705,6 @@ static const struct intel_device_info adl_p_info = {
> I915_GTT_PAGE_SIZE_2M
> 
> #define XE_HP_FEATURES \
>-.__runtime.graphics.ip.ver = 12, \
>-.__runtime.graphics.ip.rel = 50, \
> XE_HP_PAGE_SIZES, \
> TGL_CACHELEVEL, \
> .dma_mask_size = 46, \
>@@ -730,15 +728,12 @@ static const struct intel_device_info adl_p_info = {
> .__runtime.ppgtt_size = 48, \
> .__runtime.ppgtt_type = INTEL_PPGTT_FULL
> 
>-#define XE_HPM_FEATURES \
>-.__runtime.media.ip.ver = 12, \
>-.__runtime.media.ip.rel = 50
>-
> #define DG2_FEATURES \
> XE_HP_FEATURES, \
>-XE_HPM_FEATURES, \
> DGFX_FEATURES, \
>+.__runtime.graphics.ip.ver = 12, \
> .__runtime.graphics.ip.rel = 55, \
>+.__runtime.media.ip.ver = 12, \
> .__runtime.media.ip.rel = 55, \
> PLATFORM(INTEL_DG2), \
> .has_64k_pages = 1, \
>@@ -773,9 +768,10 @@ static const struct intel_device_info ats_m_info = {
> __maybe_unused
> static const struct intel_device_info pvc_info = {
> XE_HPC_FEATURES,
>-XE_HPM_FEATURES,
> DGFX_FEATURES,
>+.__runtime.graphics.ip.ver = 12,
> .__runtime.graphics.ip.rel = 60,
>+.__runtime.media.ip.ver = 12,
> .__runtime.media.ip.rel = 60,
> PLATFORM(INTEL_PONTEVECCHIO),
> .has_flat_ccs = 0,
>-- 
>2.43.0
>

RE: ✗ Fi.CI.BAT: failure for drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev4)

[Chauhan, Shekhar]

Below failures are False positive, please help to re-report.

-shekhar

From: Patchwork 
Sent: Tuesday, March 12, 2024 05:10
To: Chauhan, Shekhar 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for drm/i915/dp: Increase idle pattern wait 
timeout to 2ms (rev4)

Patch Details
Series:
drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev4)
URL:
https://patchwork.freedesktop.org/series/130643/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/index.html
CI Bug Log - changes from CI_DRM_14420 -> Patchwork_130643v4
Summary

FAILURE

Serious unknown changes coming with Patchwork_130643v4 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_130643v4, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org)
 to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/index.html

Participating hosts (34 -> 36)

Additional (3): fi-glk-j4005 bat-kbl-2 bat-mtlp-8
Missing (1): fi-snb-2520m

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_130643v4:

IGT changes
Possible regressions

· igt@kms_force_connector_basic@force-edid:
obat-dg2-8: 
PASS
 -> 
INCOMPLETE

· igt@vgem_basic@unload:
obat-arls-2: 
PASS
 -> 
INCOMPLETE
Known issues

Here are the changes found in Patchwork_130643v4 that come from known issues:

IGT changes
Issues hit

· igt@debugfs_test@basic-hwmon:
obat-mtlp-8: NOTRUN -> 
SKIP
 (i915#9318)

· igt@fbdev@info:
obat-kbl-2: NOTRUN -> 
SKIP
 (i915#1849)

· igt@gem_huc_copy@huc-copy:
ofi-glk-j4005: NOTRUN -> 
SKIP
 (i915#2190)

· igt@gem_lmem_swapping@parallel-random-engines:
obat-kbl-2: NOTRUN -> 
SKIP
 +39 other tests skip
obat-mtlp-8: NOTRUN -> 
SKIP
 (i915#4613) +3 other 
tests skip
ofi-glk-j4005: NOTRUN -> 
SKIP
 (i915#4613) +3 other 
tests skip

· igt@gem_mmap@basic:
obat-mtlp-8: NOTRUN -> 
SKIP
 (i915#4083)

· igt@gem_render_tiled_blits@basic:
obat-mtlp-8: NOTRUN -> 
SKIP
 (i915#4079) +1 other 
test skip

· igt@gem_tiled_fence_blits@basic:
obat-mtlp-8: NOTRUN -> 
SKIP
 (i915#4077) +2 other 
tests skip

· igt@i915_pm_rps@basic-api:
obat-mtlp-8: NOTRUN -> 
SKIP
 (i915#6621)

· igt@i915_selftest@live@hangcheck:
obat-dg2-14: 
PASS
 -> 
ABORT
 (i915#10366)

· igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
obat-mtlp-8: NOTRUN -> 
SKIP

[PATCH v18 8/9] drm/i915/display: Compute vrr_vsync params

[Mitul Golani]

Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.

--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START/END. (Ankit)

--v3:
- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
- Read/write vrr_vsync params only when we intend to send
adaptive_sync sdp.

--v4:
- Use VRR_SYNC_START/END macros correctly.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_display.c  |  2 ++
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c  | 30 +--
 drivers/gpu/drm/i915/i915_reg.h   |  7 +
 4 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 8f1d948408d3..fed4ed18d53b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5377,6 +5377,8 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+   PIPE_CONF_CHECK_I(vrr.vsync_start);
+   PIPE_CONF_CHECK_I(vrr.vsync_end);
}
 
 #undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8a286751dc39..c2e08f641989 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1430,6 +1430,7 @@ struct intel_crtc_state {
bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
+   u32 vsync_end, vsync_start;
} vrr;
 
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index eb5bd0743902..ed38fee196b8 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_vrr.h"
+#include "intel_dp.h"
 
 bool intel_vrr_is_capable(struct intel_connector *connector)
 {
@@ -113,6 +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state 
*crtc_state,
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+   struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
const struct drm_display_info *info = &connector->base.display_info;
int vmin, vmax;
@@ -165,6 +167,15 @@ intel_vrr_compute_config(struct intel_crtc_state 
*crtc_state,
if (crtc_state->uapi.vrr_enabled) {
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+   if (intel_dp_as_sdp_supported(intel_dp)) {
+   crtc_state->vrr.vsync_start =
+   (crtc_state->hw.adjusted_mode.crtc_vtotal -
+   
crtc_state->hw.adjusted_mode.vsync_start);
+   crtc_state->vrr.vsync_end =
+   (crtc_state->hw.adjusted_mode.crtc_vtotal -
+   crtc_state->hw.adjusted_mode.vsync_end);
+   }
}
 }
 
@@ -204,6 +215,11 @@ void intel_vrr_set_transcoder_timings(const struct 
intel_crtc_state *crtc_state)
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), 
crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 
trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), 
crtc_state->vrr.flipline - 1);
+
+   if (crtc_state->vrr.vsync_end && crtc_state->vrr.vsync_start)
+   intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+  
VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) |
+  
VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start));
 }
 
 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
@@ -264,7 +280,7 @@ void intel_vrr_get_config(struct intel_crtc_state 
*crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-   u32 trans_vrr_ctl;
+   u32 trans_vrr_ctl, trans_vrr_vsync;
 
trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
 
@@ -284,6 +300,16 @@ void intel_vrr_get_config(struct intel_crtc_state 
*crtc_state)
crtc_state->vrr.vmin = intel_de_read(dev_priv, 
TRANS_VRR_VMIN(cpu_transcoder)) + 1;
 

Re: [PATCH 2/6] drm/i915: Extract intel_ddi_post_disable_hdmi_or_sst()

[Manasi Navare]

Thanks Stan for the cleanup around post disable non MST case, one comment below

On Fri, Mar 8, 2024 at 5:11 AM Stanislav Lisovskiy
 wrote:
>
> Extract the "not-MST" stuff from intel_ddi_post_disable() so that
> the whole thing isn't so cluttered.
>
> The bigjoiner slave handling was outside of the !MST check,
> but it really should have been inside it as its the counterpart
> to the master handling inside the check. So we pull that
> in as well. There is no functional change here as we don't
> currently support bigjoiner+MST anyway.


>
> Signed-off-by: Ville Syrjälä 
> Signed-off-by: Stanislav Lisovskiy 
> Credits-to: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 37 +++-
>  1 file changed, 23 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bbce74f011d40..5628a4ab608d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3095,28 +3095,26 @@ static void intel_ddi_post_disable_hdmi(struct 
> intel_atomic_state *state,
> intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
>  }
>
> -static void intel_ddi_post_disable(struct intel_atomic_state *state,
> -  struct intel_encoder *encoder,
> -  const struct intel_crtc_state 
> *old_crtc_state,
> -  const struct drm_connector_state 
> *old_conn_state)
> +static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state 
> *state,
> +  struct intel_encoder *encoder,
> +  const struct intel_crtc_state 
> *old_master_crtc_state,
> +  const struct 
> drm_connector_state *old_conn_state)
>  {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crtc *slave_crtc;
>
> -   if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
> -   intel_crtc_vblank_off(old_crtc_state);
> +   intel_crtc_vblank_off(old_crtc_state);
>
> -   intel_disable_transcoder(old_crtc_state);
> +   intel_disable_transcoder(old_crtc_state);
>
> -   intel_ddi_disable_transcoder_func(old_crtc_state);
> +   intel_ddi_disable_transcoder_func(old_crtc_state);
>
> -   intel_dsc_disable(old_crtc_state);
> +   intel_dsc_disable(old_crtc_state);
>
> -   if (DISPLAY_VER(dev_priv) >= 9)
> -   skl_scaler_disable(old_crtc_state);
> -   else
> -   ilk_pfit_disable(old_crtc_state);
> -   }
> +   if (DISPLAY_VER(dev_priv) >= 9)
> +   skl_scaler_disable(old_crtc_state);
> +   else
> +   ilk_pfit_disable(old_crtc_state);
>
> for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
>  
> intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) {

This bigjoiner slave handling for MST path will be added later to the
intel_ddi_post_post_disable()
when we enable bigjoiner for MST?

Manasi

> @@ -3128,6 +3126,17 @@ static void intel_ddi_post_disable(struct 
> intel_atomic_state *state,
> intel_dsc_disable(old_slave_crtc_state);
> skl_scaler_disable(old_slave_crtc_state);
> }
> +}
> +
> +static void intel_ddi_post_disable(struct intel_atomic_state *state,
> +  struct intel_encoder *encoder,
> +  const struct intel_crtc_state 
> *old_crtc_state,
> +  const struct drm_connector_state 
> *old_conn_state)
> +{
> +
> +   if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
> +   intel_ddi_post_disable_hdmi_or_sst(state, encoder,
> +  old_crtc_state, 
> old_conn_state);
>
> /*
>  * When called from DP MST code:
> --
> 2.37.3
>

Re: [PATCH 3/6] drm/i915: Utilize intel_crtc_joined_pipe_mask() more

[Manasi Navare]

On Fri, Mar 8, 2024 at 5:11 AM Stanislav Lisovskiy
 wrote:
>
> Unify the master vs. slave handling in
> intel_ddi_post_disable_hdmi_or_sst() by looping over all the
> pipes in one go.

How will we handle looping through all joined pipes for MST case,
does this need to be accounted for in the last patch that enables bigjoiner
for MST now that we have separated out ddi_post_disable for hdmi/sst?

Manasi

>
> This also lets us move the intel_crtc_vblank_off() calls to
> happen in a consistent place vs. the transcoder disable.
> Previously we did the master vs. slaves on different sides
> of that.
>
> Signed-off-by: Ville Syrjälä 
> Signed-off-by: Stanislav Lisovskiy 
> Credits-to: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 34 
>  1 file changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 5628a4ab608d4..15441674c6f58 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3097,34 +3097,34 @@ static void intel_ddi_post_disable_hdmi(struct 
> intel_atomic_state *state,
>
>  static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state 
> *state,
>struct intel_encoder *encoder,
> -  const struct intel_crtc_state 
> *old_master_crtc_state,
> +  const struct intel_crtc_state 
> *old_crtc_state,
>const struct 
> drm_connector_state *old_conn_state)
>  {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -   struct intel_crtc *slave_crtc;
> +   u8 pipe_mask = intel_crtc_joined_pipe_mask(old_crtc_state);
> +   struct intel_crtc *crtc;
> +
> +   for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
> +   const struct intel_crtc_state *_old_crtc_state =
> +   intel_atomic_get_old_crtc_state(state, crtc);
>
> -   intel_crtc_vblank_off(old_crtc_state);
> +   intel_crtc_vblank_off(_old_crtc_state);
> +   }
>
> intel_disable_transcoder(old_crtc_state);
>
> intel_ddi_disable_transcoder_func(old_crtc_state);
>
> -   intel_dsc_disable(old_crtc_state);
> +   for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
> +   const struct intel_crtc_state *_old_crtc_state =
> +   intel_atomic_get_old_crtc_state(state, crtc);
>
> -   if (DISPLAY_VER(dev_priv) >= 9)
> -   skl_scaler_disable(old_crtc_state);
> -   else
> -   ilk_pfit_disable(old_crtc_state);
> +   intel_dsc_disable(_old_crtc_state);
>
> -   for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
> -
> intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) {
> -   const struct intel_crtc_state *old_slave_crtc_state =
> -   intel_atomic_get_old_crtc_state(state, slave_crtc);
> -
> -   intel_crtc_vblank_off(old_slave_crtc_state);
> -
> -   intel_dsc_disable(old_slave_crtc_state);
> -   skl_scaler_disable(old_slave_crtc_state);
> +   if (DISPLAY_VER(dev_priv) >= 9)
> +   skl_scaler_disable(_old_crtc_state);
> +   else
> +   ilk_pfit_disable(_old_crtc_state);
> }
>  }
>
> --
> 2.37.3
>

Re: [PATCH 6/6] drm/i915: Allow bigjoiner for MST

[Manasi Navare]

Now when we enable bigjoiner for MST, in MST case
intel_ddi_post_disable_hdmi_or_sst() function wont get called,
Do we need similar changes for MST case to loop over the joined pipes
in MST bigjoiner case?

Manasi

On Fri, Mar 8, 2024 at 5:12 AM Stanislav Lisovskiy
 wrote:
>
> From: Vidya Srinivas 
>
> We need bigjoiner support with MST functionality
> for MST monitor resolutions > 5K to work.
> Adding support for the same.
>
> v2: Addressed review comments from Jani.
> Revert rejection of MST bigjoiner modes and add
> functionality
>
> v3: Fixed pipe_mismatch WARN for mst_master_transcoder
> Credits-to: Manasi Navare 
>
> Signed-off-by: Vidya Srinivas 
> Reviewed-by: Manasi Navare 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c|  6 --
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +
>  2 files changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3756975bd561c..3bf8941107473 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3924,9 +3924,11 @@ static void intel_ddi_read_func_ctl(struct 
> intel_encoder *encoder,
> pipe_config->lane_count =
> ((temp & DDI_PORT_WIDTH_MASK) >> 
> DDI_PORT_WIDTH_SHIFT) + 1;
>
> -   if (DISPLAY_VER(dev_priv) >= 12)
> -   pipe_config->mst_master_transcoder =
> +   if (DISPLAY_VER(dev_priv) >= 12) {
> +   if (!intel_crtc_is_bigjoiner_slave(pipe_config))
> +   pipe_config->mst_master_transcoder =
> 
> REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
> +   }
>
> intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
>&pipe_config->dp_m_n);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 53aec023ce92f..3e6e2cd08d3ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -525,6 +525,7 @@ static int intel_dp_mst_compute_config(struct 
> intel_encoder *encoder,
>  {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_atomic_state *state = 
> to_intel_atomic_state(conn_state->state);
> +   struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> struct intel_dp *intel_dp = &intel_mst->primary->dp;
> const struct intel_connector *connector =
> @@ -542,6 +543,10 @@ static int intel_dp_mst_compute_config(struct 
> intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
>
> +   if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
> +   adjusted_mode->crtc_clock))
> +   pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, 
> crtc->pipe);
> +
> pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->has_pch_encoder = false;
> @@ -1330,12 +1335,6 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
>  *   corresponding link capabilities of the sink) in case the
>  *   stream is uncompressed for it by the last branch device.
>  */
> -   if (mode_rate > max_rate || mode->clock > max_dotclk ||
> -   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) 
> {
> -   *status = MODE_CLOCK_HIGH;
> -   return 0;
> -   }
> -
> if (mode->clock < 1) {
> *status = MODE_CLOCK_LOW;
> return 0;
> @@ -1349,8 +1348,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
> if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
> bigjoiner = true;
> max_dotclk *= 2;
> +   }
>
> -   /* TODO: add support for bigjoiner */
> +   if (mode_rate > max_rate || mode->clock > max_dotclk ||
> +   drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) 
> {
> *status = MODE_CLOCK_HIGH;
> return 0;
> }
> @@ -1397,7 +1398,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector 
> *connector,
> return 0;
> }
>
> -   *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
> +   *status = intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
> return 0;
>  }
>
> --
> 2.37.3
>

✗ Fi.CI.CHECKPATCH: warning for Enable Adaptive Sync SDP Support for DP (rev18)

[Patchwork]

== Series Details ==

Series: Enable Adaptive Sync SDP Support for DP (rev18)
URL   : https://patchwork.freedesktop.org/series/126829/
State : warning

== Summary ==

Error: dim checkpatch failed
b375ee417fe9 drm/dp: Add support to indicate if sink supports AS SDP
fe133c6b8a7d drm: Add Adaptive Sync SDP logging
1c5fca8cb6f6 drm/i915/display: Add crtc state dump for Adaptive Sync SDP
f0b8cd1cbd29 drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
2919c75a5ae8 drm/i915/dp: Add wrapper function to check AS SDP
d46c23281f6f drm/i915/display: Compute AS SDP parameters
a09302a7444c drm/i915/display: Add state checker for Adaptive Sync SDP
-:72: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#72: FILE: drivers/gpu/drm/i915/display/intel_display.c:5137:
+#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
+   if (!intel_compare_dp_as_sdp(¤t_config->infoframes.name, \
+ &pipe_config->infoframes.name)) { \
+   pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, 
__stringify(name), \
+   
¤t_config->infoframes.name, \
+   &pipe_config->infoframes.name); 
\
+   ret = false; \
+   } \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 70 lines checked
a8840a207850 drm/i915/display: Compute vrr_vsync params
fd56c33fcef9 drm/i915/display: Read/Write Adaptive Sync SDP

✗ Fi.CI.SPARSE: warning for Enable Adaptive Sync SDP Support for DP (rev18)

[Patchwork]

== Series Details ==

Series: Enable Adaptive Sync SDP Support for DP (rev18)
URL   : https://patchwork.freedesktop.org/series/126829/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.BAT: failure for Enable Adaptive Sync SDP Support for DP (rev18)

[Patchwork]

== Series Details ==

Series: Enable Adaptive Sync SDP Support for DP (rev18)
URL   : https://patchwork.freedesktop.org/series/126829/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14423 -> Patchwork_126829v18


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_126829v18 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_126829v18, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v18/index.html

Participating hosts (33 -> 32)
--

  Missing(1): fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_126829v18:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@load:
- bat-arls-2: [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14423/bat-arls-2/igt@i915_module_l...@load.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v18/bat-arls-2/igt@i915_module_l...@load.html

  
Known issues


  Here are the changes found in Patchwork_126829v18 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-cfl-8109u:   [FAIL][3] ([i915#8293]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14423/fi-cfl-8109u/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v18/fi-cfl-8109u/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u:   NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v18/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u:   NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v18/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html

  * igt@kms_pm_backlight@basic-brightness:
- fi-cfl-8109u:   NOTRUN -> [SKIP][7] +11 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v18/fi-cfl-8109u/igt@kms_pm_backli...@basic-brightness.html

  
 Possible fixes 

  * igt@i915_selftest@live@dmabuf:
- bat-dg2-8:  [ABORT][8] ([i915#10366]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14423/bat-dg2-8/igt@i915_selftest@l...@dmabuf.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v18/bat-dg2-8/igt@i915_selftest@l...@dmabuf.html

  
  [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293


Build changes
-

  * Linux: CI_DRM_14423 -> Patchwork_126829v18

  CI-20190529: 20190529
  CI_DRM_14423: 8762453258673794e13e4d59cb9df1042b97ba01 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7757: 7757
  Patchwork_126829v18: 8762453258673794e13e4d59cb9df1042b97ba01 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

bd7b8bec7b22 drm/i915/display: Read/Write Adaptive Sync SDP
a0b13ebd8f8b drm/i915/display: Compute vrr_vsync params
54086849e09c drm/i915/display: Add state checker for Adaptive Sync SDP
eeec93b9a604 drm/i915/display: Compute AS SDP parameters
10249d34bbfe drm/i915/dp: Add wrapper function to check AS SDP
85c79811ef92 drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
34285a4a67a8 drm/i915/display: Add crtc state dump for Adaptive Sync SDP
cd2e920c7a62 drm: Add Adaptive Sync SDP logging
078835ec9a9d drm/dp: Add support to indicate if sink supports AS SDP

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126829v18/index.html

Re: [PATCH v5 5/5] drm/i915/display: Increase number of fast wake precharge pulses

[Hogander, Jouni]

On Tue, 2024-03-12 at 18:44 +0200, Ville Syrjälä wrote:
> On Fri, Mar 08, 2024 at 01:00:39PM +0200, Jouni Högander wrote:
> > Increasing number of fast wake sync pulses seem to fix problems
> > with
> > certain PSR panels. This should be ok for other panels as well as
> > the eDP
> > specification allows 10...16 precharge pulses and we are still
> > within that
> > range.
> > 
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9739
> > Signed-off-by: Jouni Högander 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > index 7e69be100d90..5dff1bc85d61 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > @@ -145,7 +145,7 @@ static int intel_dp_aux_sync_len(void)
> >  
> >  int intel_dp_aux_fw_sync_len(void)
> >  {
> > -   int precharge = 10; /* 10-16 */
> > +   int precharge = 12; /* 10-16 */
> 
> This is still giving me allergies because Windows doesn't have
> anything like this. So the mystery is how does Windows work?
> This was an actual production machine I take it?

Not sure if it's already on market. To my understanding it's production
machine.

The problematic panel here is successfully used on older platform (RPL)
but now we are seeing glitches when used on MTL. More discussion about
the issue : https://gitlab.freedesktop.org/drm/intel/-/issues/9739

> 
> Did we have look at the error bits in PSR2_DEBUG to see if there
> is some difference between the working and non-working values?

There is no error bits in PSR2_DEBUG. Just bit 13 indicating "FastWake
Done"
> 
> Anyways, this at least needs a proper comment to explain why
> we're not usign the standard value.

Ok, I will add that comment and send a new version.

BR,

Jouni Högander

> 
> > int preamble = 8;
> >  
> > return precharge + preamble;
> > -- 
> > 2.34.1
> 

✓ Fi.CI.BAT: success for drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Increase idle pattern wait timeout to 2ms (rev4)
URL   : https://patchwork.freedesktop.org/series/130643/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14420 -> Patchwork_130643v4


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/index.html

Participating hosts (34 -> 36)
--

  Additional (3): fi-glk-j4005 bat-kbl-2 bat-mtlp-8 
  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_130643v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][2] ([i915#1849])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-kbl-2/igt@fb...@info.html

  * igt@gem_huc_copy@huc-copy:
- fi-glk-j4005:   NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][4] +39 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@gem_lmem_swapp...@parallel-random-engines.html
- fi-glk-j4005:   NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/fi-glk-j4005/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4083])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@gem_m...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4077]) +2 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@gem_tiled_fence_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg2-14: [PASS][11] -> [ABORT][12] ([i915#10366])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/bat-dg2-14/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-dg2-14/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#5190])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4212]) +8 other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#4213]) +1 other test skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#3840] / 
[i915#9159])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-edid:
- bat-dg2-8:  [PASS][17] -> [INCOMPLETE][18] ([i915#10419])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14420/bat-dg2-8/igt@kms_force_connector_ba...@force-edid.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-dg2-8/igt@kms_force_connector_ba...@force-edid.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-8: NOTRUN -> [SKIP][19]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130643v4/bat-mtlp-8/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-8: NOTRUN -> [SKIP][20] ([i915#5274])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/