RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks

[Kandpal, Suraj]

> -Original Message-
> From: Murthy, Arun R 
> Sent: Tuesday, April 23, 2024 10:14 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kumar, Naveen1 ;
> sebastian.w...@redhat.com
> Subject: RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> 
> 
> > -Original Message-
> > From: Kandpal, Suraj 
> > Sent: Tuesday, April 23, 2024 9:39 AM
> > To: Murthy, Arun R ;
> > intel-gfx@lists.freedesktop.org
> > Cc: Borah, Chaitanya Kumar ; Shankar,
> > Uma ; Nautiyal, Ankit K
> > ; Kumar, Naveen1
> > ; sebastian.w...@redhat.com
> > Subject: RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> >
> >
> >
> > > -Original Message-
> > > From: Murthy, Arun R 
> > > Sent: Tuesday, April 23, 2024 8:25 AM
> > > To: Kandpal, Suraj ;
> > > intel-gfx@lists.freedesktop.org
> > > Cc: Borah, Chaitanya Kumar ;
> > > Shankar, Uma ; Nautiyal, Ankit K
> > > ; Kumar, Naveen1
> > > ; sebastian.w...@redhat.com
> > > Subject: RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> > >
> > >
> > > > -Original Message-
> > > > From: Kandpal, Suraj 
> > > > Sent: Monday, April 22, 2024 9:03 AM
> > > > To: intel-gfx@lists.freedesktop.org
> > > > Cc: Borah, Chaitanya Kumar ;
> > > > Shankar, Uma ; Nautiyal, Ankit K
> > > > ; Murthy, Arun R
> > > > ; Kumar, Naveen1
> > > > ; sebastian.w...@redhat.com; Kandpal,
> > > > Suraj 
> > > > Subject: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> > > >
> > > > Add checks to see the HDR capability of TCON panel.
> > > >
> > > > Signed-off-by: Suraj Kandpal 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display_types.h|  5 +
> > > >  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 10
> > > > ++
> > > >  2 files changed, 15 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 62f7a30c37dc..1cf4caf1a0a9 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -401,6 +401,11 @@ struct intel_panel {
> > > > } vesa;
> > > > struct {
> > > > bool sdr_uses_aux;
> > > > +   bool supports_2084_decode;
> > > > +   bool supports_2020_gamut;
> > > > +   bool supports_segmented_backlight;
> > > > +   bool supports_sdp_colorimetry;
> > > > +   bool supports_tone_mapping;
> > > >
> > >   } intel;
> > > Even though not part of this patch, but the struct is growing.
> > > Can you change the name of this struct to a meaningful one, maybe
> > > tcon_capability ?
> >
> > So this was named intel because it comes under the following structure
> > and is Called like this Backlight.edp.intel Since there are two
> > standards one which is defined by intel edp hdr specs and One defined
> > by vesa hence the naming intel here plus as you see above when getting
> > Called it tells us that this pertains to intel edp backlight capability.
> > I think it makes sense to keep it as is.
> > Do you still think this needs to be renamed?
> >
> 
> Somehow just intel is not that readable, maybe intel_tcon_cap?
> 

Maybe intel_cap then since this structure is already inside edp struct

Regards,
Suraj Kandpal
> Thanks and Regards
> Arun R Murthy
> ---
> 
> > Regards,
> > Suraj Kandpal
> > >
> > > With the above change
> > > Reviewed-by: Arun R Murthy 
> > >
> > > Thanks and Regards,
> > > Arun R Murthy
> > > ---
> > >
> > > > } edp;
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > > index 4f58efdc688a..94edf982eff8 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > > @@ -158,6 +158,16 @@ intel_dp_aux_supports_hdr_backlight(struct
> > > > intel_connector *connector)
> > > >
> > > > panel->backlight.edp.intel.sdr_uses_aux =
> > > > tcon_cap[2] &
> > > INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP;
> > > > +   panel->backlight.edp.intel.supports_2084_decode =
> > > > +   tcon_cap[1] & INTEL_EDP_HDR_TCON_2084_DECODE_CAP;
> > > > +   panel->backlight.edp.intel.supports_2020_gamut =
> > > > +   tcon_cap[1] & INTEL_EDP_HDR_TCON_2020_GAMUT_CAP;
> > > > +   panel->backlight.edp.intel.supports_segmented_backlight =
> > > > +   tcon_cap[1] &
> > > > INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_CAP;
> > > > +   panel->backlight.edp.intel.supports_sdp_colorimetry =
> > > > +   tcon_cap[1] &
> > > > INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_CAP;

✓ Fi.CI.BAT: success for Uprev mesa and IGT

[Patchwork]

== Series Details ==

Series: Uprev mesa and IGT
URL   : https://patchwork.freedesktop.org/series/132746/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14630 -> Patchwork_132746v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/index.html

Participating hosts (36 -> 34)
--

  Additional (2): bat-dg2-11 fi-apl-guc 
  Missing(4): fi-kbl-8809g fi-elk-e7500 bat-mtlp-6 fi-bsw-n3050 

Known issues


  Here are the changes found in Patchwork_132746v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#4083])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@gem_m...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#4077]) +2 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#6621])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-7567u:   [PASS][6] -> [DMESG-WARN][7] ([i915#10900]) +31 other 
tests dmesg-warn
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_mocs:
- bat-arls-1: [PASS][8] -> [DMESG-WARN][9] ([i915#9522])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/bat-arls-1/igt@i915_selftest@live@gt_mocs.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-arls-1/igt@i915_selftest@live@gt_mocs.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#4212]) +7 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#5190])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#4215] / [i915#5190])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213]) +1 
other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#3840])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@kms_...@dsc-basic.html

  * igt@kms_flip@basic-flip-vs-dpms@a-dp1:
- fi-kbl-7567u:   [PASS][15] -> [DMESG-WARN][16] ([i915#10875] / 
[i915#8585]) +3 other tests dmesg-warn
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/fi-kbl-7567u/igt@kms_flip@basic-flip-vs-d...@a-dp1.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/fi-kbl-7567u/igt@kms_flip@basic-flip-vs-d...@a-dp1.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-11: NOTRUN -> [SKIP][17]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#5274])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/bat-dg2-11/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-apl-guc: NOTRUN -> [SKIP][19] +17 other tests skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132746v1/fi-apl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pm_backlight@basic-brightness:
- bat-dg2-11: NOTRUN -> [S

RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks

[Murthy, Arun R]

> -Original Message-
> From: Kandpal, Suraj 
> Sent: Tuesday, April 23, 2024 9:39 AM
> To: Murthy, Arun R ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kumar, Naveen1 ;
> sebastian.w...@redhat.com
> Subject: RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> 
> 
> 
> > -Original Message-
> > From: Murthy, Arun R 
> > Sent: Tuesday, April 23, 2024 8:25 AM
> > To: Kandpal, Suraj ;
> > intel-gfx@lists.freedesktop.org
> > Cc: Borah, Chaitanya Kumar ; Shankar,
> > Uma ; Nautiyal, Ankit K
> > ; Kumar, Naveen1
> > ; sebastian.w...@redhat.com
> > Subject: RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> >
> >
> > > -Original Message-
> > > From: Kandpal, Suraj 
> > > Sent: Monday, April 22, 2024 9:03 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Borah, Chaitanya Kumar ;
> > > Shankar, Uma ; Nautiyal, Ankit K
> > > ; Murthy, Arun R
> > > ; Kumar, Naveen1 ;
> > > sebastian.w...@redhat.com; Kandpal, Suraj 
> > > Subject: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> > >
> > > Add checks to see the HDR capability of TCON panel.
> > >
> > > Signed-off-by: Suraj Kandpal 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display_types.h|  5 +
> > >  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 10
> > > ++
> > >  2 files changed, 15 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 62f7a30c37dc..1cf4caf1a0a9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -401,6 +401,11 @@ struct intel_panel {
> > >   } vesa;
> > >   struct {
> > >   bool sdr_uses_aux;
> > > + bool supports_2084_decode;
> > > + bool supports_2020_gamut;
> > > + bool supports_segmented_backlight;
> > > + bool supports_sdp_colorimetry;
> > > + bool supports_tone_mapping;
> > >
> > } intel;
> > Even though not part of this patch, but the struct is growing.
> > Can you change the name of this struct to a meaningful one, maybe
> > tcon_capability ?
> 
> So this was named intel because it comes under the following structure and is
> Called like this Backlight.edp.intel Since there are two standards one which 
> is
> defined by intel edp hdr specs and One defined by vesa hence the naming intel
> here plus as you see above when getting Called it tells us that this pertains 
> to
> intel edp backlight capability.
> I think it makes sense to keep it as is.
> Do you still think this needs to be renamed?
> 

Somehow just intel is not that readable, maybe intel_tcon_cap?

Thanks and Regards
Arun R Murthy
---

> Regards,
> Suraj Kandpal
> >
> > With the above change
> > Reviewed-by: Arun R Murthy 
> >
> > Thanks and Regards,
> > Arun R Murthy
> > ---
> >
> > >   } edp;
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > index 4f58efdc688a..94edf982eff8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > @@ -158,6 +158,16 @@ intel_dp_aux_supports_hdr_backlight(struct
> > > intel_connector *connector)
> > >
> > >   panel->backlight.edp.intel.sdr_uses_aux =
> > >   tcon_cap[2] &
> > INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP;
> > > + panel->backlight.edp.intel.supports_2084_decode =
> > > + tcon_cap[1] & INTEL_EDP_HDR_TCON_2084_DECODE_CAP;
> > > + panel->backlight.edp.intel.supports_2020_gamut =
> > > + tcon_cap[1] & INTEL_EDP_HDR_TCON_2020_GAMUT_CAP;
> > > + panel->backlight.edp.intel.supports_segmented_backlight =
> > > + tcon_cap[1] &
> > > INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_CAP;
> > > + panel->backlight.edp.intel.supports_sdp_colorimetry =
> > > + tcon_cap[1] &
> > > INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_CAP;
> > > + panel->backlight.edp.intel.supports_tone_mapping =
> > > + tcon_cap[1] & INTEL_EDP_HDR_TCON_TONE_MAPPING_CAP;
> > >
> > >   return true;
> > >  }
> > > --
> > > 2.43.2

✗ Fi.CI.CHECKPATCH: warning for Uprev mesa and IGT

[Patchwork]

== Series Details ==

Series: Uprev mesa and IGT
URL   : https://patchwork.freedesktop.org/series/132746/
State : warning

== Summary ==

Error: dim checkpatch failed
661c85a3be29 drm/ci: uprev mesa version
867f0241d6c3 drm/ci: build virtual GPU driver as module
7d1b740578d9 drm/ci: uprev IGT and generate testlist from build
-:154: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#154: 
deleted file mode 100644

total: 0 errors, 1 warnings, 0 checks, 1694 lines checked
7368c619c5ef drm/ci: add tests on vkms
-:124: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#124: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 170 lines checked

RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks

[Kandpal, Suraj]

> -Original Message-
> From: Murthy, Arun R 
> Sent: Tuesday, April 23, 2024 8:25 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kumar, Naveen1 ;
> sebastian.w...@redhat.com
> Subject: RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> 
> 
> > -Original Message-
> > From: Kandpal, Suraj 
> > Sent: Monday, April 22, 2024 9:03 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Borah, Chaitanya Kumar ; Shankar,
> > Uma ; Nautiyal, Ankit K
> > ; Murthy, Arun R
> > ; Kumar, Naveen1 ;
> > sebastian.w...@redhat.com; Kandpal, Suraj 
> > Subject: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> >
> > Add checks to see the HDR capability of TCON panel.
> >
> > Signed-off-by: Suraj Kandpal 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_types.h|  5 +
> >  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 10 ++
> >  2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 62f7a30c37dc..1cf4caf1a0a9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -401,6 +401,11 @@ struct intel_panel {
> > } vesa;
> > struct {
> > bool sdr_uses_aux;
> > +   bool supports_2084_decode;
> > +   bool supports_2020_gamut;
> > +   bool supports_segmented_backlight;
> > +   bool supports_sdp_colorimetry;
> > +   bool supports_tone_mapping;
> >
>   } intel;
> Even though not part of this patch, but the struct is growing.
> Can you change the name of this struct to a meaningful one, maybe
> tcon_capability ?

So this was named intel because it comes under the following structure and is
Called like this
Backlight.edp.intel
Since there are two standards one which is defined by intel edp hdr specs and
One defined by vesa hence the naming intel here plus as you see above when 
getting
Called it tells us that this pertains to intel edp backlight capability.
I think it makes sense to keep it as is.
Do you still think this needs to be renamed?

Regards,
Suraj Kandpal 
> 
> With the above change
> Reviewed-by: Arun R Murthy 
> 
> Thanks and Regards,
> Arun R Murthy
> ---
> 
> > } edp;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > index 4f58efdc688a..94edf982eff8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > @@ -158,6 +158,16 @@ intel_dp_aux_supports_hdr_backlight(struct
> > intel_connector *connector)
> >
> > panel->backlight.edp.intel.sdr_uses_aux =
> > tcon_cap[2] &
> INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP;
> > +   panel->backlight.edp.intel.supports_2084_decode =
> > +   tcon_cap[1] & INTEL_EDP_HDR_TCON_2084_DECODE_CAP;
> > +   panel->backlight.edp.intel.supports_2020_gamut =
> > +   tcon_cap[1] & INTEL_EDP_HDR_TCON_2020_GAMUT_CAP;
> > +   panel->backlight.edp.intel.supports_segmented_backlight =
> > +   tcon_cap[1] &
> > INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_CAP;
> > +   panel->backlight.edp.intel.supports_sdp_colorimetry =
> > +   tcon_cap[1] &
> > INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_CAP;
> > +   panel->backlight.edp.intel.supports_tone_mapping =
> > +   tcon_cap[1] & INTEL_EDP_HDR_TCON_TONE_MAPPING_CAP;
> >
> > return true;
> >  }
> > --
> > 2.43.2

[PATCH v1 4/4] drm/ci: add tests on vkms

[Vignesh Raman]

Add job that runs igt on top of vkms.

Acked-by: Maíra Canal 
Acked-by: Helen Koike 
Signed-off-by: Vignesh Raman 
Acked-by: Jessica Zhang 
Tested-by: Jessica Zhang 
Acked-by: Maxime Ripard 
Signed-off-by: Helen Koike 
---
 MAINTAINERS   |  1 +
 drivers/gpu/drm/ci/gitlab-ci.yml  |  1 +
 drivers/gpu/drm/ci/igt_runner.sh  |  2 +-
 drivers/gpu/drm/ci/image-tags.yml |  4 +-
 drivers/gpu/drm/ci/test.yml   | 24 +-
 drivers/gpu/drm/ci/x86_64.config  |  1 +
 drivers/gpu/drm/ci/xfails/vkms-none-fails.txt | 46 +++
 .../gpu/drm/ci/xfails/vkms-none-flakes.txt| 21 +
 drivers/gpu/drm/ci/xfails/vkms-none-skips.txt | 30 
 9 files changed, 126 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/ci/xfails/vkms-none-fails.txt
 create mode 100644 drivers/gpu/drm/ci/xfails/vkms-none-flakes.txt
 create mode 100644 drivers/gpu/drm/ci/xfails/vkms-none-skips.txt

diff --git a/MAINTAINERS b/MAINTAINERS
index c97d79d0b2b4..19ad9375d7cd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7035,6 +7035,7 @@ L:dri-de...@lists.freedesktop.org
 S: Maintained
 T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
 F: Documentation/gpu/vkms.rst
+F: drivers/gpu/drm/ci/xfails/vkms*
 F: drivers/gpu/drm/vkms/
 
 DRM DRIVER FOR VIRTUALBOX VIRTUAL GPU
diff --git a/drivers/gpu/drm/ci/gitlab-ci.yml b/drivers/gpu/drm/ci/gitlab-ci.yml
index 6cc94747d8d5..6dac7ae98419 100644
--- a/drivers/gpu/drm/ci/gitlab-ci.yml
+++ b/drivers/gpu/drm/ci/gitlab-ci.yml
@@ -112,6 +112,7 @@ stages:
   - msm
   - rockchip
   - virtio-gpu
+  - software-driver
 
 # YAML anchors for rule conditions
 # 
diff --git a/drivers/gpu/drm/ci/igt_runner.sh b/drivers/gpu/drm/ci/igt_runner.sh
index 0fd7d67f91e3..2538f29fcb2c 100755
--- a/drivers/gpu/drm/ci/igt_runner.sh
+++ b/drivers/gpu/drm/ci/igt_runner.sh
@@ -30,7 +30,7 @@ case "$DRIVER_NAME" in
 export IGT_FORCE_DRIVER="panfrost"
 fi
 ;;
-amdgpu|virtio_gpu)
+amdgpu|virtio_gpu|vkms)
 # Cannot use HWCI_KERNEL_MODULES as at that point we don't have the 
module in /lib
 mv /install/modules/lib/modules/* /lib/modules/. || true
 modprobe --first-time $DRIVER_NAME
diff --git a/drivers/gpu/drm/ci/image-tags.yml 
b/drivers/gpu/drm/ci/image-tags.yml
index fd1cb6061166..43bd871c2e60 100644
--- a/drivers/gpu/drm/ci/image-tags.yml
+++ b/drivers/gpu/drm/ci/image-tags.yml
@@ -4,9 +4,9 @@ variables:
DEBIAN_BASE_TAG: "${CONTAINER_TAG}"
 
DEBIAN_X86_64_BUILD_IMAGE_PATH: "debian/x86_64_build"
-   DEBIAN_BUILD_TAG: "2024-04-22-virtio"
+   DEBIAN_BUILD_TAG: "2024-04-22-vkms"
 
-   KERNEL_ROOTFS_TAG: "2024-04-22-virtio"
+   KERNEL_ROOTFS_TAG: "2024-04-22-vkms"
PKG_REPO_REV: "3cc12a2a"
 
DEBIAN_X86_64_TEST_BASE_IMAGE: "debian/x86_64_test-base"
diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml
index 1f8cc17f2ad1..745716920ffc 100644
--- a/drivers/gpu/drm/ci/test.yml
+++ b/drivers/gpu/drm/ci/test.yml
@@ -333,7 +333,7 @@ meson:g12b:
 RUNNER_TAG: mesa-ci-x86-64-lava-meson-g12b-a311d-khadas-vim3
 
 virtio_gpu:none:
-  stage: virtio-gpu
+  stage: software-driver
   variables:
 CROSVM_GALLIUM_DRIVER: llvmpipe
 DRIVER_NAME: virtio_gpu
@@ -354,3 +354,25 @@ virtio_gpu:none:
 - debian/x86_64_test-gl
 - testing:x86_64
 - igt:x86_64
+
+vkms:none:
+  stage: software-driver
+  variables:
+DRIVER_NAME: vkms
+GPU_VERSION: none
+  extends:
+- .test-gl
+- .test-rules
+  tags:
+- kvm
+  script:
+- ln -sf $CI_PROJECT_DIR/install /install
+- mv install/bzImage /lava-files/bzImage
+- mkdir -p /lib/modules
+- mkdir -p $CI_PROJECT_DIR/results
+- ln -sf $CI_PROJECT_DIR/results /results
+- ./install/crosvm-runner.sh ./install/igt_runner.sh
+  needs:
+- debian/x86_64_test-gl
+- testing:x86_64
+- igt:x86_64
diff --git a/drivers/gpu/drm/ci/x86_64.config b/drivers/gpu/drm/ci/x86_64.config
index 78479f063e8e..66c6f67dfdd6 100644
--- a/drivers/gpu/drm/ci/x86_64.config
+++ b/drivers/gpu/drm/ci/x86_64.config
@@ -24,6 +24,7 @@ CONFIG_DRM=y
 CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_PWM_CROS_EC=y
 CONFIG_BACKLIGHT_PWM=y
+CONFIG_DRM_VKMS=m
 
 # Strip out some stuff we don't need for graphics testing, to reduce
 # the build.
diff --git a/drivers/gpu/drm/ci/xfails/vkms-none-fails.txt 
b/drivers/gpu/drm/ci/xfails/vkms-none-fails.txt
new file mode 100644
index ..c015e4a96810
--- /dev/null
+++ b/drivers/gpu/drm/ci/xfails/vkms-none-fails.txt
@@ -0,0 +1,46 @@
+core_hotunplug@hotrebind,Fail
+core_hotunplug@hotrebind-lateclose,Fail
+core_hotunplug@hotreplug,Fail
+core_hotunplug@hotreplug-lateclose,Fail
+core_hotunplug@hotunbind-rebind,Fail
+core_hotunplug@hotunplug-rescan,Fail
+core_hotunplug@unbind-rebind,Fail
+core_hotunplug@unplug-rescan,Fail
+device_reset@cold-reset-bound,Fail
+device_reset@reset-bound,Fai

[PATCH v1 2/4] drm/ci: build virtual GPU driver as module

[Vignesh Raman]

With latest IGT, the tests tries to load the module and it
fails. So build the virtual GPU driver for virtio as module.

Signed-off-by: Vignesh Raman 
---
 drivers/gpu/drm/ci/build.sh   |  1 -
 drivers/gpu/drm/ci/igt_runner.sh  |  6 +++---
 drivers/gpu/drm/ci/image-tags.yml |  4 ++--
 drivers/gpu/drm/ci/test.yml   |  1 +
 drivers/gpu/drm/ci/x86_64.config  |  2 +-
 .../gpu/drm/ci/xfails/virtio_gpu-none-fails.txt   | 15 +++
 6 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh
index 8a3baa003904..95493df9cdc2 100644
--- a/drivers/gpu/drm/ci/build.sh
+++ b/drivers/gpu/drm/ci/build.sh
@@ -156,7 +156,6 @@ fi
 
 mkdir -p artifacts/install/lib
 mv install/* artifacts/install/.
-rm -rf artifacts/install/modules
 ln -s common artifacts/install/ci-common
 cp .config artifacts/${CI_JOB_NAME}_config
 
diff --git a/drivers/gpu/drm/ci/igt_runner.sh b/drivers/gpu/drm/ci/igt_runner.sh
index f1a08b9b146f..7d2ba69294dd 100755
--- a/drivers/gpu/drm/ci/igt_runner.sh
+++ b/drivers/gpu/drm/ci/igt_runner.sh
@@ -30,10 +30,10 @@ case "$DRIVER_NAME" in
 export IGT_FORCE_DRIVER="panfrost"
 fi
 ;;
-amdgpu)
+amdgpu|virtio_gpu)
 # Cannot use HWCI_KERNEL_MODULES as at that point we don't have the 
module in /lib
-mv /install/modules/lib/modules/* /lib/modules/.
-modprobe amdgpu
+mv /install/modules/lib/modules/* /lib/modules/. || true
+modprobe --first-time $DRIVER_NAME
 ;;
 esac
 
diff --git a/drivers/gpu/drm/ci/image-tags.yml 
b/drivers/gpu/drm/ci/image-tags.yml
index d8f72b82c938..fd1cb6061166 100644
--- a/drivers/gpu/drm/ci/image-tags.yml
+++ b/drivers/gpu/drm/ci/image-tags.yml
@@ -4,9 +4,9 @@ variables:
DEBIAN_BASE_TAG: "${CONTAINER_TAG}"
 
DEBIAN_X86_64_BUILD_IMAGE_PATH: "debian/x86_64_build"
-   DEBIAN_BUILD_TAG: "2023-10-08-config"
+   DEBIAN_BUILD_TAG: "2024-04-22-virtio"
 
-   KERNEL_ROOTFS_TAG: "2023-10-06-amd"
+   KERNEL_ROOTFS_TAG: "2024-04-22-virtio"
PKG_REPO_REV: "3cc12a2a"
 
DEBIAN_X86_64_TEST_BASE_IMAGE: "debian/x86_64_test-base"
diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml
index 612c9ede3507..864ac3809d84 100644
--- a/drivers/gpu/drm/ci/test.yml
+++ b/drivers/gpu/drm/ci/test.yml
@@ -350,6 +350,7 @@ virtio_gpu:none:
   script:
 - ln -sf $CI_PROJECT_DIR/install /install
 - mv install/bzImage /lava-files/bzImage
+- mkdir -p /lib/modules
 - mkdir -p $CI_PROJECT_DIR/results
 - ln -sf $CI_PROJECT_DIR/results /results
 - install/crosvm-runner.sh install/igt_runner.sh
diff --git a/drivers/gpu/drm/ci/x86_64.config b/drivers/gpu/drm/ci/x86_64.config
index 1cbd49a5b23a..78479f063e8e 100644
--- a/drivers/gpu/drm/ci/x86_64.config
+++ b/drivers/gpu/drm/ci/x86_64.config
@@ -91,7 +91,7 @@ CONFIG_KVM=y
 CONFIG_KVM_GUEST=y
 CONFIG_VIRT_DRIVERS=y
 CONFIG_VIRTIO_FS=y
-CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_DRM_VIRTIO_GPU=m
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_VIRTIO_NET=y
 CONFIG_VIRTIO_CONSOLE=y
diff --git a/drivers/gpu/drm/ci/xfails/virtio_gpu-none-fails.txt 
b/drivers/gpu/drm/ci/xfails/virtio_gpu-none-fails.txt
index 007f21e56d89..5b8cbb28b25c 100644
--- a/drivers/gpu/drm/ci/xfails/virtio_gpu-none-fails.txt
+++ b/drivers/gpu/drm/ci/xfails/virtio_gpu-none-fails.txt
@@ -68,6 +68,7 @@ kms_plane_scaling@upscale-with-rotation-20x20,Fail
 kms_selftest@drm_format,Timeout
 kms_selftest@drm_format_helper,Timeout
 kms_setmode@basic,Fail
+kms_vblank@accuracy-idle,Fail
 kms_vblank@crtc-id,Fail
 kms_vblank@invalid,Fail
 kms_vblank@pipe-A-accuracy-idle,Fail
@@ -82,3 +83,17 @@ kms_vblank@pipe-A-wait-busy,Fail
 kms_vblank@pipe-A-wait-forked,Fail
 kms_vblank@pipe-A-wait-forked-busy,Fail
 kms_vblank@pipe-A-wait-idle,Fail
+kms_vblank@query-busy,Fail
+kms_vblank@query-forked,Fail
+kms_vblank@query-forked-busy,Fail
+kms_vblank@query-idle,Fail
+kms_vblank@ts-continuation-dpms-rpm,Fail
+kms_vblank@ts-continuation-dpms-suspend,Fail
+kms_vblank@ts-continuation-idle,Fail
+kms_vblank@ts-continuation-modeset,Fail
+kms_vblank@ts-continuation-modeset-rpm,Fail
+kms_vblank@ts-continuation-suspend,Fail
+kms_vblank@wait-busy,Fail
+kms_vblank@wait-forked,Fail
+kms_vblank@wait-forked-busy,Fail
+kms_vblank@wait-idle,Fail
-- 
2.40.1

[PATCH v1 0/4] Uprev mesa and IGT

[Vignesh Raman]

Uprev mesa and IGT to the latest version. Stop vendoring the
testlist into the kernel. Instead, use the testlist from the
IGT build to ensure we do not miss renamed or newly added tests.
Update the xfails with the latest testlist run.

Also build virtual GPU driver for virtio as module.
This series also includes patch to add vkms testing to drm-ci.

The flakes list needs to be updated upsteam. Will send it
after this series is reviewed.

https://gitlab.freedesktop.org/vigneshraman/linux/-/pipelines/1161026

Vignesh Raman (4):
  drm/ci: uprev mesa version
  drm/ci: build virtual GPU driver as module
  drm/ci: uprev IGT and generate testlist from build
  drm/ci: add tests on vkms

 MAINTAINERS   |1 +
 drivers/gpu/drm/ci/build-igt.sh   |   23 +
 drivers/gpu/drm/ci/build.sh   |2 +-
 drivers/gpu/drm/ci/container.yml  |   12 +-
 drivers/gpu/drm/ci/gitlab-ci.yml  |   14 +-
 drivers/gpu/drm/ci/igt_runner.sh  |   15 +-
 drivers/gpu/drm/ci/image-tags.yml |7 +-
 drivers/gpu/drm/ci/test.yml   |   33 +-
 drivers/gpu/drm/ci/testlist.txt   | 2761 -
 drivers/gpu/drm/ci/x86_64.config  |3 +-
 .../gpu/drm/ci/xfails/amdgpu-stoney-fails.txt |   45 +-
 .../drm/ci/xfails/amdgpu-stoney-flakes.txt|   15 +-
 .../gpu/drm/ci/xfails/amdgpu-stoney-skips.txt |   30 +-
 drivers/gpu/drm/ci/xfails/i915-amly-fails.txt |   27 +
 .../gpu/drm/ci/xfails/i915-amly-flakes.txt|9 +
 drivers/gpu/drm/ci/xfails/i915-amly-skips.txt |   22 +-
 drivers/gpu/drm/ci/xfails/i915-apl-fails.txt  |   47 +-
 drivers/gpu/drm/ci/xfails/i915-apl-skips.txt  |   24 +-
 drivers/gpu/drm/ci/xfails/i915-cml-fails.txt  |   37 +-
 drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt |6 +
 drivers/gpu/drm/ci/xfails/i915-cml-skips.txt  |   20 +
 drivers/gpu/drm/ci/xfails/i915-glk-fails.txt  |   37 +-
 drivers/gpu/drm/ci/xfails/i915-glk-skips.txt  |   21 +-
 drivers/gpu/drm/ci/xfails/i915-kbl-fails.txt  |   29 +-
 drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt |1 -
 drivers/gpu/drm/ci/xfails/i915-kbl-skips.txt  |   34 +-
 drivers/gpu/drm/ci/xfails/i915-tgl-fails.txt  |   27 +-
 drivers/gpu/drm/ci/xfails/i915-tgl-flakes.txt |6 +
 drivers/gpu/drm/ci/xfails/i915-tgl-skips.txt  |   28 +-
 drivers/gpu/drm/ci/xfails/i915-whl-fails.txt  |   57 +-
 drivers/gpu/drm/ci/xfails/i915-whl-skips.txt  |   21 +-
 .../drm/ci/xfails/mediatek-mt8173-fails.txt   |   47 +-
 .../drm/ci/xfails/mediatek-mt8173-skips.txt   |   13 +
 .../drm/ci/xfails/mediatek-mt8183-fails.txt   |   18 +-
 .../drm/ci/xfails/mediatek-mt8183-flakes.txt  |6 +
 .../drm/ci/xfails/mediatek-mt8183-skips.txt   |   15 +
 .../gpu/drm/ci/xfails/meson-g12b-fails.txt|   20 +-
 .../gpu/drm/ci/xfails/meson-g12b-flakes.txt   |7 +
 .../gpu/drm/ci/xfails/meson-g12b-skips.txt|   15 +
 .../gpu/drm/ci/xfails/msm-apq8016-fails.txt   |   25 +-
 .../gpu/drm/ci/xfails/msm-apq8016-flakes.txt  |7 +
 .../gpu/drm/ci/xfails/msm-apq8016-skips.txt   |   15 +
 .../gpu/drm/ci/xfails/msm-apq8096-fails.txt   |6 +-
 .../gpu/drm/ci/xfails/msm-apq8096-flakes.txt  |6 +
 .../gpu/drm/ci/xfails/msm-apq8096-skips.txt   |  117 +-
 .../msm-sc7180-trogdor-kingoftown-fails.txt   |   40 +-
 .../msm-sc7180-trogdor-kingoftown-flakes.txt  |6 +
 .../msm-sc7180-trogdor-kingoftown-skips.txt   |   16 +
 ...sm-sc7180-trogdor-lazor-limozeen-fails.txt |   41 +-
 ...m-sc7180-trogdor-lazor-limozeen-flakes.txt |   11 +
 ...sm-sc7180-trogdor-lazor-limozeen-skips.txt |   16 +
 .../gpu/drm/ci/xfails/msm-sdm845-fails.txt|   76 +-
 .../gpu/drm/ci/xfails/msm-sdm845-flakes.txt   |   26 +-
 .../gpu/drm/ci/xfails/msm-sdm845-skips.txt|   16 +
 .../drm/ci/xfails/rockchip-rk3288-fails.txt   |   54 -
 .../drm/ci/xfails/rockchip-rk3288-skips.txt   |   60 +-
 .../drm/ci/xfails/rockchip-rk3399-fails.txt   |   79 +-
 .../drm/ci/xfails/rockchip-rk3399-flakes.txt  |   13 +-
 .../drm/ci/xfails/rockchip-rk3399-skips.txt   |   17 +-
 .../drm/ci/xfails/virtio_gpu-none-fails.txt   |   99 +-
 .../drm/ci/xfails/virtio_gpu-none-skips.txt   |   19 +-
 drivers/gpu/drm/ci/xfails/vkms-none-fails.txt |   46 +
 .../gpu/drm/ci/xfails/vkms-none-flakes.txt|   21 +
 drivers/gpu/drm/ci/xfails/vkms-none-skips.txt |   30 +
 64 files changed, 1109 insertions(+), 3308 deletions(-)
 delete mode 100644 drivers/gpu/drm/ci/testlist.txt
 create mode 100644 drivers/gpu/drm/ci/xfails/i915-amly-flakes.txt
 create mode 100644 drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt
 delete mode 100644 drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt
 create mode 100644 drivers/gpu/drm/ci/xfails/i915-tgl-flakes.txt
 create mode 100644 drivers/gpu/drm/ci/xfails/mediatek-mt8173-skips.txt
 create mode 100644 drivers/gpu/drm/ci/xfails/mediatek-mt8183-flakes.txt
 create mode 100644 drivers/gpu/drm/ci/xfails/mediatek-mt8183-skips.txt
 create mode 100644 drivers/gpu/drm/ci/xfails/meson-g12b-flakes.txt
 create mode 1

[PATCH v1 1/4] drm/ci: uprev mesa version

[Vignesh Raman]

zlib.net is not allowing tarball download anymore and results
in below error in kernel+rootfs_arm32 container build,
urllib.error.HTTPError: HTTP Error 403: Forbidden
urllib.error.HTTPError: HTTP Error 415: Unsupported Media Type

Uprev mesa to latest version which includes a fix for this issue.
https://gitlab.freedesktop.org/mesa/mesa/-/commit/908f444e

Also copy helper scripts to install, so that the ci jobs can
use these scripts for logging.

Signed-off-by: Vignesh Raman 
---
 drivers/gpu/drm/ci/build.sh   |  1 +
 drivers/gpu/drm/ci/container.yml  | 12 
 drivers/gpu/drm/ci/gitlab-ci.yml  | 11 ---
 drivers/gpu/drm/ci/image-tags.yml |  3 ++-
 drivers/gpu/drm/ci/test.yml   |  2 ++
 5 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh
index 106f2d40d222..8a3baa003904 100644
--- a/drivers/gpu/drm/ci/build.sh
+++ b/drivers/gpu/drm/ci/build.sh
@@ -128,6 +128,7 @@ fi
 # Pass needed files to the test stage
 mkdir -p install
 cp -rfv .gitlab-ci/* install/.
+cp -rfv ci/*  install/.
 cp -rfv install/common install/ci-common
 cp -rfv drivers/gpu/drm/ci/* install/.
 
diff --git a/drivers/gpu/drm/ci/container.yml b/drivers/gpu/drm/ci/container.yml
index 9764e7921a4f..d6edf3635b23 100644
--- a/drivers/gpu/drm/ci/container.yml
+++ b/drivers/gpu/drm/ci/container.yml
@@ -36,15 +36,15 @@ debian/android_build:
   rules:
 - when: never
 
-debian/x86_64_test-android:
+.debian/x86_64_test-android:
   rules:
 - when: never
 
-windows_build_vs2019:
+windows_build_msvc:
   rules:
 - when: never
 
-windows_test_vs2019:
+windows_test_msvc:
   rules:
 - when: never
 
@@ -56,10 +56,6 @@ rustfmt:
rules:
 - when: never
 
-windows_vs2019:
-   rules:
-- when: never
-
-clang-format:
+windows_msvc:
rules:
 - when: never
\ No newline at end of file
diff --git a/drivers/gpu/drm/ci/gitlab-ci.yml b/drivers/gpu/drm/ci/gitlab-ci.yml
index 084e3ff8e3f4..9bf5190604a7 100644
--- a/drivers/gpu/drm/ci/gitlab-ci.yml
+++ b/drivers/gpu/drm/ci/gitlab-ci.yml
@@ -1,6 +1,6 @@
 variables:
   DRM_CI_PROJECT_PATH: &drm-ci-project-path mesa/mesa
-  DRM_CI_COMMIT_SHA: &drm-ci-commit-sha 
9d162de9a05155e1c4041857a5848842749164cf
+  DRM_CI_COMMIT_SHA: &drm-ci-commit-sha 
e5f133ccc426a197c48a4e88f5377f943f078180
 
   UPSTREAM_REPO: git://anongit.freedesktop.org/drm/drm
   TARGET_BRANCH: drm-next
@@ -26,10 +26,13 @@ variables:
   JOB_ARTIFACTS_BASE: ${PIPELINE_ARTIFACTS_BASE}/${CI_JOB_ID}
   # default kernel for rootfs before injecting the current kernel tree
   KERNEL_REPO: "gfx-ci/linux"
-  KERNEL_TAG: "v6.6.4-for-mesa-ci-e4f4c500f7fb"
+  KERNEL_TAG: "v6.6.21-mesa-19fc"
   KERNEL_IMAGE_BASE: https://${S3_HOST}/mesa-lava/${KERNEL_REPO}/${KERNEL_TAG}
   LAVA_TAGS: subset-1-gfx
   LAVA_JOB_PRIORITY: 30
+  ARTIFACTS_BASE_URL: 
https://${CI_PROJECT_ROOT_NAMESPACE}.${CI_PAGES_DOMAIN}/-/${CI_PROJECT_NAME}/-/jobs/${CI_JOB_ID}/artifacts
+  # Python scripts for structured logger
+  PYTHONPATH: "$PYTHONPATH:$CI_PROJECT_DIR/install"
 
 default:
   before_script:
@@ -46,6 +49,7 @@ default:
 - cd $CI_PROJECT_DIR
 - curl --output - 
$DRM_CI_PROJECT_URL/-/archive/$DRM_CI_COMMIT_SHA/mesa-$DRM_CI_COMMIT_SHA.tar.gz 
| tar -xz
 - mv mesa-$DRM_CI_COMMIT_SHA/.gitlab-ci* .
+- mv mesa-$DRM_CI_COMMIT_SHA/bin/ci .
 - rm -rf mesa-$DRM_CI_COMMIT_SHA/
 - echo -e "\e[0Ksection_end:$(date +%s):drm_ci_download_section\r\e[0K"
 
@@ -98,6 +102,7 @@ include:
 stages:
   - sanity
   - container
+  - code-validation
   - git-archive
   - build
   - amdgpu
@@ -107,7 +112,6 @@ stages:
   - msm
   - rockchip
   - virtio-gpu
-  - lint
 
 # YAML anchors for rule conditions
 # 
@@ -218,6 +222,7 @@ make git archive:
   script:
 # Remove drm-ci files we just added
 - rm -rf .gitlab-ci.*
+- rm -rf ci
 
 # Compactify the .git directory
 - git gc --aggressive
diff --git a/drivers/gpu/drm/ci/image-tags.yml 
b/drivers/gpu/drm/ci/image-tags.yml
index 7ab4f2514da8..d8f72b82c938 100644
--- a/drivers/gpu/drm/ci/image-tags.yml
+++ b/drivers/gpu/drm/ci/image-tags.yml
@@ -1,5 +1,5 @@
 variables:
-   CONTAINER_TAG: "2023-10-11-mesa-uprev"
+   CONTAINER_TAG: "2024-04-22-mesa-uprev"
DEBIAN_X86_64_BUILD_BASE_IMAGE: "debian/x86_64_build-base"
DEBIAN_BASE_TAG: "${CONTAINER_TAG}"
 
@@ -7,6 +7,7 @@ variables:
DEBIAN_BUILD_TAG: "2023-10-08-config"
 
KERNEL_ROOTFS_TAG: "2023-10-06-amd"
+   PKG_REPO_REV: "3cc12a2a"
 
DEBIAN_X86_64_TEST_BASE_IMAGE: "debian/x86_64_test-base"
DEBIAN_X86_64_TEST_IMAGE_GL_PATH: "debian/x86_64_test-gl"
diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml
index 8bc63912fddb..612c9ede3507 100644
--- a/drivers/gpu/drm/ci/test.yml
+++ b/drivers/gpu/drm/ci/test.yml
@@ -150,6 +150,8 @@ msm:sdm845:
 BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel
 GPU_VERSION: sdm845
 RUNNER_TAG: google-freedreno-cheza
+DEVICE_TYPE: sdm845-cheza-r

RE: [PATCH 4/6] drm/i915: Eliminate extra frame from skl-glk sync->async flip change

[Murthy, Arun R]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Friday, April 19, 2024 10:12 PM
> To: Murthy, Arun R 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 4/6] drm/i915: Eliminate extra frame from skl-glk sync-
> >async flip change
> 
> On Fri, Apr 19, 2024 at 06:39:48AM +, Murthy, Arun R wrote:
> >
> > > -Original Message-
> > > From: Intel-gfx  On Behalf
> > > Of Ville Syrjala
> > > Sent: Wednesday, March 20, 2024 9:34 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [PATCH 4/6] drm/i915: Eliminate extra frame from skl-glk
> > > sync->async flip change
> > >
> > > From: Ville Syrjälä 
> > >
> > > On bdw-glk the sync->async flip change takes an extra frame due to
> > > the double buffering behaviour of the async flip plane control bit.
> > >
> > > Since on skl+ we are now explicitly converting the first async flip
> > > to a sync flip (in order to allow changing the modifier and/or
> > > ddb/watermarks) we are now taking two extra frames until async flips
> > > are actually active. We can drop that back down to one frame by
> > > setting the async flip bit already during the sync flip.
> > >
> > > Note that on bdw we don't currently do the extra sync flip (see
> > > intel_plane_do_async_flip()) so technically we wouldn't have to deal
> > > with this in i9xx_plane_update_arm(). But I added the relevant
> > > snippet of code there as well, just in case we ever decide to go for
> > > the extra sync flip on pre-skl platforms as well (we might, for example, 
> > > want
> to change the fb stride).
> > >
> > > Signed-off-by: Ville Syrjälä 
> >
> > Logically changes looks good. I see failures in CI.IGT Better to have
> > this green or a Tested-by would be good.
> 
> Those are fixed by https://patchwork.freedesktop.org/series/131518/
> whereas this got tested against the previous version of the igt changes. I'll
> repost to test against the latest igt changes.
> IIRC one can't just reply to the cover letter with a new Test-with :(
> 
Will wait for the CI IGT to get green on this.

Thanks and Regards,
Arun R Murthy


> >
> > Thanks and Regards,
> > Arun R Murthy
> > ---
> > > ---
> > >  drivers/gpu/drm/i915/display/i9xx_plane.c |  5 +
> > >  drivers/gpu/drm/i915/display/intel_atomic_plane.c | 15 +++
> > >  .../gpu/drm/i915/display/skl_universal_plane.c|  5 +
> > >  3 files changed, 21 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > > b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > > index 0279c8aabdd1..76fc7626051b 100644
> > > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > > @@ -455,6 +455,11 @@ static void i9xx_plane_update_arm(struct
> > > intel_plane *plane,
> > >
> > >   dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
> > >
> > > + /* see intel_plane_atomic_calc_changes() */
> > > + if (plane->need_async_flip_disable_wa &&
> > > + crtc_state->async_flip_planes & BIT(plane->id))
> > > + dspcntr |= DISP_ASYNC_FLIP;
> > > +
> > >   linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> > >
> > >   if (DISPLAY_VER(dev_priv) >= 4)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > index 769010d0ebc4..7098a34a17c8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > @@ -437,10 +437,6 @@ static bool intel_plane_do_async_flip(struct
> > > intel_plane *plane,
> > >* only X-tile is supported with async flips, though we could
> > >* extend this so other scanout parameters (stride/etc) could
> > >* be changed as well...
> > > -  *
> > > -  * FIXME: Platforms with need_async_flip_disable_wa==true will
> > > -  * now end up doing two sync flips initially. Would be nice to
> > > -  * combine those into just the one sync flip...
> > >*/
> > >   return DISPLAY_VER(i915) < 9 || old_crtc_state->uapi.async_flip;
> > > } @@
> > > -604,6 +600,17 @@ static int intel_plane_atomic_calc_changes(const
> > > struct intel_crtc_state *old_cr
> > >   if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
> > >   new_crtc_state->do_async_flip = true;
> > >   new_crtc_state->async_flip_planes |= BIT(plane->id);
> > > + } else if (plane->need_async_flip_disable_wa &&
> > > +new_crtc_state->uapi.async_flip) {
> > > + /*
> > > +  * On platforms with double buffered async flip bit we
> > > +  * set the bit already one frame early during the sync
> > > +  * flip (see {i9xx,skl}_plane_update_arm()). The
> > > +  * hardware will therefore be ready to perform a real
> > > +  * async flip during the next commit, without having
> > > +  * to wait yet another frame for the bit to latch.
> > > +  */
> > > + 

RE: [PATCH 2/6] drm/i915: Reject async flips if we need to change DDB/watermarks

[Murthy, Arun R]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Friday, April 19, 2024 9:56 PM
> To: Murthy, Arun R 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/6] drm/i915: Reject async flips if we need to change
> DDB/watermarks
> 
> On Fri, Apr 19, 2024 at 04:27:53AM +, Murthy, Arun R wrote:
> >
> > > -Original Message-
> > > From: Intel-gfx  On Behalf
> > > Of Ville Syrjala
> > > Sent: Wednesday, March 20, 2024 9:34 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [PATCH 2/6] drm/i915: Reject async flips if we need to
> > > change DDB/watermarks
> > >
> > > From: Ville Syrjälä 
> > >
> > > DDB/watermarks are always double buffered on the vblank, so we can't
> > > safely change them during async flips. Currently this never happens,
> > > but we'll be making changing between sync and async flips a bit more
> > > flexible, in which case we can actually end up here.
> >
> > Rather on getting wm/DDB changes should we switch from async to sync flip
> to honour the wm/DDB changes else might end up in underrun or
> flicker/corruption.
> > Spec is also aligned to this approach.
> 
> I can't really parse what you're saying.
> 
> The sequence of events that can lead us here are:
> 1. start in sync flip mode
> 2. userspace asks for an async flip (potentially asking for a
>different modifier)
>- we convert it to a sync flip and proceed 3. userspace asks for another 
> async
> flip
>either:
>- the format/modifier (and thus wm/ddb) stays the same all
>  is good and we do the async flip
>- the modifier changes we will now reject the request due to
>  wm/ddb needing to change
> 
> We don't want to convert step 3 also to a sync flip because userspace could 
> just
> keep pingponging between two buffers with different modifiers and we'd never
> actually get into proper async flip mode, and would just keep doing sync 
> flips.
> That would completely defat the purpose of async flips.
> 
> And we do have to reject the request here in the wm code because otherwise
> we'll clear the do_async_flip flag and the later
> intel_async_flip_check_hw() wouldn't refuse the request even though the
> modifier is changing. The other option would be to move some/all of
> intel_async_flip_check_hw() into some earlier phase of atomic_check(), but 
> that
> would require some actual thought.
> 
Even adding some/all changes in the beginning of atomic_check will eventually 
fail the flip, so better to send the failure as is. 
Upon seeing the failure X would fallback.

Reviewed-by: Arun R Murthy 

Thanks and Regards,
Arun R Murthy
---
> 
> > Thanks and Regards,
> > Arun R Murthy
> > 
> >
> > >
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/display/skl_watermark.c | 12 
> > >  1 file changed, 12 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > index bc341abcab2f..1fa416a70d51 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > @@ -2540,6 +2540,12 @@ skl_ddb_add_affected_planes(const struct
> > > intel_crtc_state *old_crtc_state,
> > >   &new_crtc_state-
> > > >wm.skl.plane_ddb_y[plane_id]))
> > >   continue;
> > >
> > > + if (new_crtc_state->do_async_flip) {
> > > + drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Can't
> > > change DDB during async flip\n",
> > > + plane->base.base.id, plane->base.name);
> > > + return -EINVAL;
> > > + }
> > > +
> > >   plane_state = intel_atomic_get_plane_state(state, plane);
> > >   if (IS_ERR(plane_state))
> > >   return PTR_ERR(plane_state);
> > > @@ -2906,6 +2912,12 @@ static int skl_wm_add_affected_planes(struct
> > > intel_atomic_state *state,
> > >&new_crtc_state-
> > > >wm.skl.optimal))
> > >   continue;
> > >
> > > + if (new_crtc_state->do_async_flip) {
> > > + drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Can't
> > > change watermarks during async flip\n",
> > > + plane->base.base.id, plane->base.name);
> > > + return -EINVAL;
> > > + }
> > > +
> > >   plane_state = intel_atomic_get_plane_state(state, plane);
> > >   if (IS_ERR(plane_state))
> > >   return PTR_ERR(plane_state);
> > > --
> > > 2.43.2
> >
> 
> --
> Ville Syrjälä
> Intel

RE: [PATCH 1/6] drm/i915: Align PLANE_SURF to 16k on ADL for async flips

[Murthy, Arun R]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Friday, April 19, 2024 9:38 PM
> To: Murthy, Arun R 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/6] drm/i915: Align PLANE_SURF to 16k on ADL for async
> flips
> 
> On Fri, Apr 19, 2024 at 04:20:40AM +, Murthy, Arun R wrote:
> >
> > > -Original Message-
> > > From: Intel-gfx  On Behalf
> > > Of Ville Syrjala
> > > Sent: Wednesday, March 20, 2024 9:34 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [PATCH 1/6] drm/i915: Align PLANE_SURF to 16k on ADL for
> > > async flips
> > >
> > > From: Ville Syrjälä 
> > >
> > > On ADL async flips apparently generate DMAR and GGTT faults (with
> > > accompanying visual glitches) unless PLANE_SURF is aligned to at least 
> > > 16k.
> > > Bump up the alignment to 16k.
> >
> > I don’t find any such restriction in the spec. Can you please add link to 
> > the
> spec?
> 
> I don't think it's documented, hence the FIXME.
> 
Ok!

Reviewed-by: Arun R Murthy 

Thanks and Regards,
Arun R Murthy

> >
> > Thanks and Regards,
> > Arun R Murthy
> > ---
> > >
> > > TODO: analyze things better to figure out what is really
> > >   going on here
> > >
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dpt.c|  7 ---
> > >  drivers/gpu/drm/i915/display/intel_dpt.h|  3 ++-
> > >  drivers/gpu/drm/i915/display/intel_fb.c | 17 -
> > >  drivers/gpu/drm/i915/display/intel_fb_pin.c | 10 +-
> > >  4 files changed, 27 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
> > > b/drivers/gpu/drm/i915/display/intel_dpt.c
> > > index b29bceff73f2..786d3f2e94c7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpt.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
> > > @@ -121,7 +121,8 @@ static void dpt_cleanup(struct
> > > i915_address_space
> > > *vm)
> > >   i915_gem_object_put(dpt->obj);
> > >  }
> > >
> > > -struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
> > > +struct i915_vma *intel_dpt_pin(struct i915_address_space *vm,
> > > +unsigned int alignment)
> > >  {
> > >   struct drm_i915_private *i915 = vm->i915;
> > >   struct i915_dpt *dpt = i915_vm_to_dpt(vm); @@ -143,8 +144,8 @@
> > > struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
> > >   if (err)
> > >   continue;
> > >
> > > - vma = i915_gem_object_ggtt_pin_ww(dpt->obj, &ww, NULL, 0,
> > > 4096,
> > > -   pin_flags);
> > > + vma = i915_gem_object_ggtt_pin_ww(dpt->obj, &ww, NULL, 0,
> > > +   alignment, pin_flags);
> > >   if (IS_ERR(vma)) {
> > >   err = PTR_ERR(vma);
> > >   continue;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpt.h
> > > b/drivers/gpu/drm/i915/display/intel_dpt.h
> > > index e18a9f767b11..f467578a4950 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpt.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpt.h
> > > @@ -13,7 +13,8 @@ struct i915_vma;
> > >  struct intel_framebuffer;
> > >
> > >  void intel_dpt_destroy(struct i915_address_space *vm); -struct
> > > i915_vma *intel_dpt_pin(struct i915_address_space *vm);
> > > +struct i915_vma *intel_dpt_pin(struct i915_address_space *vm,
> > > +unsigned int alignment);
> > >  void intel_dpt_unpin(struct i915_address_space *vm);  void
> > > intel_dpt_suspend(struct drm_i915_private *i915);  void
> > > intel_dpt_resume(struct drm_i915_private *i915); diff --git
> > > a/drivers/gpu/drm/i915/display/intel_fb.c
> > > b/drivers/gpu/drm/i915/display/intel_fb.c
> > > index 3ea6470d6d92..58ead05fba6f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > @@ -805,8 +805,23 @@ unsigned int intel_surf_alignment(const struct
> > > drm_framebuffer *fb,  {
> > >   struct drm_i915_private *dev_priv = to_i915(fb->dev);
> > >
> > > - if (intel_fb_uses_dpt(fb))
> > > + if (intel_fb_uses_dpt(fb)) {
> > > + /* AUX_DIST needs only 4K alignment */
> > > + if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > + return 512 * 4096;
> > > +
> > > + /*
> > > +  * FIXME ADL sees GGTT/DMAR faults with async
> > > +  * flips unless we align to 16k at least.
> > > +  * Figure out what's going on here...
> > > +  */
> > > + if (IS_ALDERLAKE_P(dev_priv) &&
> > > + !intel_fb_is_ccs_modifier(fb->modifier) &&
> > > + HAS_ASYNC_FLIPS(dev_priv))
> > > + return 512 * 16 * 1024;
> > > +
> > >   return 512 * 4096;
> > > + }
> > >
> > >   /* AUX_DIST needs only 4K alignment */
> > >   if (intel_fb_is_ccs_aux_plane(fb, color_plane)) diff --git
> > > a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> > > b/drivers/gpu/drm/i91

RE: [PATCH 4/6] drm/i915/dp: Drop comments on EDP HDR DPCD registers

[Murthy, Arun R]

> -Original Message-
> From: Kandpal, Suraj 
> Sent: Monday, April 22, 2024 9:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Murthy, Arun R ;
> Kumar, Naveen1 ; sebastian.w...@redhat.com;
> Kandpal, Suraj 
> Subject: [PATCH 4/6] drm/i915/dp: Drop comments on EDP HDR DPCD registers
> 
> Drop comments for EDP HDR DPCD registers as the code and conditions will tell
> us what can be written where.
> 
> --v2
> -Drop the comments altogether instead of just renaming them [Sebastian]
> 
> Signed-off-by: Suraj Kandpal 

Reviewed-by: Arun R Murthy 

Thanks and Regards,
Arun R Murthy

> ---
>  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 3d9723714c96..b61bad218994 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -69,14 +69,14 @@
>  #define INTEL_EDP_HDR_GETSET_CTRL_PARAMS   0x344
>  # define INTEL_EDP_HDR_TCON_2084_DECODE_ENABLEBIT(0)
>  # define INTEL_EDP_HDR_TCON_2020_GAMUT_ENABLE BIT(1)
> -# define INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE   BIT(2)
> /* Pre-TGL+ */
> +# define INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE   BIT(2)
>  # define INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_ENABLE
> BIT(3)
>  # define INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE BIT(4)
>  # define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_ENABLE
> BIT(5)
>  /* Bit 6 is reserved */
>  # define INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX
> BIT(7)
> 
> -#define INTEL_EDP_HDR_CONTENT_LUMINANCE0x346 
> /*
> Pre-TGL+ */
> +#define INTEL_EDP_HDR_CONTENT_LUMINANCE0x346
>  #define INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE 0x34A
>  #define INTEL_EDP_SDR_LUMINANCE_LEVEL  0x352
>  #define INTEL_EDP_BRIGHTNESS_NITS_LSB  0x354
> --
> 2.43.2

RE: [PATCH 3/6] drm/i915/dp: Fix Register bit naming

[Murthy, Arun R]

> -Original Message-
> From: Kandpal, Suraj 
> Sent: Monday, April 22, 2024 9:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Murthy, Arun R ;
> Kumar, Naveen1 ; sebastian.w...@redhat.com;
> Kandpal, Suraj 
> Subject: [PATCH 3/6] drm/i915/dp: Fix Register bit naming
> 
> Change INTEL_EDP_HDR_TCON_SDP_COLORIMETRY enable to
> INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX as this bit is tells TCON to ignore
bit is tells -> bit tells

With the above change 
Reviewed-by: Arun R Murthy 

Thanks and Regards,
Arun R Murthy
---

> DPCD colorimetry values and take the one's sent through SDP.
> 
> Signed-off-by: Suraj Kandpal 
> ---
>  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 94edf982eff8..3d9723714c96 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -74,7 +74,7 @@
>  # define INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE BIT(4)
>  # define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_ENABLE
> BIT(5)
>  /* Bit 6 is reserved */
> -# define INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_ENABLE
> BIT(7)
> +# define INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX
> BIT(7)
> 
>  #define INTEL_EDP_HDR_CONTENT_LUMINANCE0x346 
> /*
> Pre-TGL+ */
>  #define INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE 0x34A
> --
> 2.43.2

RE: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks

[Murthy, Arun R]

> -Original Message-
> From: Kandpal, Suraj 
> Sent: Monday, April 22, 2024 9:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Murthy, Arun R ;
> Kumar, Naveen1 ; sebastian.w...@redhat.com;
> Kandpal, Suraj 
> Subject: [PATCH 2/6] drm/i915/dp: Add TCON HDR capability checks
> 
> Add checks to see the HDR capability of TCON panel.
> 
> Signed-off-by: Suraj Kandpal 
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h|  5 +
>  drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 10 ++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 62f7a30c37dc..1cf4caf1a0a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -401,6 +401,11 @@ struct intel_panel {
>   } vesa;
>   struct {
>   bool sdr_uses_aux;
> + bool supports_2084_decode;
> + bool supports_2020_gamut;
> + bool supports_segmented_backlight;
> + bool supports_sdp_colorimetry;
> + bool supports_tone_mapping;
>   
} intel;
Even though not part of this patch, but the struct is growing.
Can you change the name of this struct to a meaningful one, maybe 
tcon_capability ?

With the above change
Reviewed-by: Arun R Murthy 

Thanks and Regards,
Arun R Murthy
---

>   } edp;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 4f58efdc688a..94edf982eff8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -158,6 +158,16 @@ intel_dp_aux_supports_hdr_backlight(struct
> intel_connector *connector)
> 
>   panel->backlight.edp.intel.sdr_uses_aux =
>   tcon_cap[2] & INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP;
> + panel->backlight.edp.intel.supports_2084_decode =
> + tcon_cap[1] & INTEL_EDP_HDR_TCON_2084_DECODE_CAP;
> + panel->backlight.edp.intel.supports_2020_gamut =
> + tcon_cap[1] & INTEL_EDP_HDR_TCON_2020_GAMUT_CAP;
> + panel->backlight.edp.intel.supports_segmented_backlight =
> + tcon_cap[1] &
> INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_CAP;
> + panel->backlight.edp.intel.supports_sdp_colorimetry =
> + tcon_cap[1] &
> INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_CAP;
> + panel->backlight.edp.intel.supports_tone_mapping =
> + tcon_cap[1] & INTEL_EDP_HDR_TCON_TONE_MAPPING_CAP;
> 
>   return true;
>  }
> --
> 2.43.2

Re: [PATCH v2 2/2] drm/i915: Fix gt reset with GuC submission is disabled

[John Harrison]

On 4/22/2024 13:19, Nirmoy Das wrote:

Currently intel_gt_reset() kills the GuC and then resets requested
engines. This is problematic because there is a dedicated CSB FIFO
which only GuC can access and if that FIFO fills up, the hardware
will block on the next context switch until there is space that means
the system is effectively hung. If an engine is reset whilst actively
executing a context, a CSB entry will be sent to say that the context
has gone idle. Thus if reset happens on a very busy system then
killing GuC before killing the engines will lead to deadlock because
of filled up CSB FIFO.

To address this issue, the GuC should be killed only after resetting
the requested engines and before calling intel_gt_init_hw().

v2: Improve commit message(John)

Cc: John Harrison 
Signed-off-by: Nirmoy Das 

Reviewed-by: John Harrison 


---
  drivers/gpu/drm/i915/gt/intel_reset.c | 16 ++--
  1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index b1393863ca9b..6161f7a3ff70 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -879,8 +879,17 @@ static intel_engine_mask_t reset_prepare(struct intel_gt 
*gt)
intel_engine_mask_t awake = 0;
enum intel_engine_id id;
  
-	/* For GuC mode, ensure submission is disabled before stopping ring */

-   intel_uc_reset_prepare(>->uc);
+   /**
+* For GuC mode with submission enabled, ensure submission
+* is disabled before stopping ring.
+*
+* For GuC mode with submission disabled, ensure that GuC is not
+* sanitized, do that after engine reset. reset_prepare()
+* is followed by engine reset which in this mode requires GuC to
+* process any CSB FIFO entries generated by the resets.
+*/
+   if (intel_uc_uses_guc_submission(>->uc))
+   intel_uc_reset_prepare(>->uc);
  
  	for_each_engine(engine, gt, id) {

if (intel_engine_pm_get_if_awake(engine))
@@ -1227,6 +1236,9 @@ void intel_gt_reset(struct intel_gt *gt,
  
  	intel_overlay_reset(gt->i915);
  
+	/* sanitize uC after engine reset */

+   if (!intel_uc_uses_guc_submission(>->uc))
+   intel_uc_reset_prepare(>->uc);
/*
 * Next we need to restore the context, but we don't use those
 * yet either...

Re: [PATCH v2 1/2] drm/i915: Refactor confusing __intel_gt_reset()

[John Harrison]

On 4/22/2024 13:19, Nirmoy Das wrote:

__intel_gt_reset() is really for resetting engines though
the name might suggest something else. So add a helper function
to remove confusions with no functional changes.

v2: Move intel_gt_reset_all_engines() next to
 intel_gt_reset_engine() to make diff simple(John)

Cc: John Harrison 
Signed-off-by: Nirmoy Das 

Reviewed-by: John Harrison 


---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
  .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
  drivers/gpu/drm/i915/gt/intel_gt.c|  2 +-
  drivers/gpu/drm/i915/gt/intel_gt_pm.c |  2 +-
  drivers/gpu/drm/i915/gt/intel_reset.c | 35 +++
  drivers/gpu/drm/i915/gt/intel_reset.h |  3 +-
  drivers/gpu/drm/i915/gt/selftest_reset.c  |  2 +-
  drivers/gpu/drm/i915/i915_driver.c|  2 +-
  8 files changed, 37 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8c44af1c3451..5c8e9ee3b008 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -678,7 +678,7 @@ void intel_engines_release(struct intel_gt *gt)
 */
GEM_BUG_ON(intel_gt_pm_is_awake(gt));
if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
-   __intel_gt_reset(gt, ALL_ENGINES);
+   intel_gt_reset_all_engines(gt);
  
  	/* Decouple the backend; but keep the layout for late GPU resets */

for_each_engine(engine, gt, id) {
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 355aab5b38ba..21829439e686 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2898,7 +2898,7 @@ static void enable_error_interrupt(struct intel_engine_cs 
*engine)
drm_err(&engine->i915->drm,
"engine '%s' resumed still in error: %08x\n",
engine->name, status);
-   __intel_gt_reset(engine->gt, engine->mask);
+   intel_gt_reset_engine(engine);
}
  
  	/*

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 580b5141ce1e..626b166e67ef 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -832,7 +832,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
  
  	/* Scrub all HW state upon release */

with_intel_runtime_pm(gt->uncore->rpm, wakeref)
-   __intel_gt_reset(gt, ALL_ENGINES);
+   intel_gt_reset_all_engines(gt);
  }
  
  void intel_gt_driver_release(struct intel_gt *gt)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 220ac4f92edf..c08fdb65cc69 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -159,7 +159,7 @@ static bool reset_engines(struct intel_gt *gt)
if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
return false;
  
-	return __intel_gt_reset(gt, ALL_ENGINES) == 0;

+   return intel_gt_reset_all_engines(gt) == 0;
  }
  
  static void gt_sanitize(struct intel_gt *gt, bool force)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index c8e9aa41fdea..b1393863ca9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -764,7 +764,7 @@ wa_14015076503_end(struct intel_gt *gt, intel_engine_mask_t 
engine_mask)
 HECI_H_GS1_ER_PREP, 0);
  }
  
-int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)

+static int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t 
engine_mask)
  {
const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
reset_func reset;
@@ -978,7 +978,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
  
  	/* Even if the GPU reset fails, it should still stop the engines */

if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
-   __intel_gt_reset(gt, ALL_ENGINES);
+   intel_gt_reset_all_engines(gt);
  
  	for_each_engine(engine, gt, id)

engine->submit_request = nop_submit_request;
@@ -1089,7 +1089,7 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
/* We must reset pending GPU events before restoring our submission */
ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
-   ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
+   ok = intel_gt_reset_all_engines(gt) == 0;
if (!ok) {
/*
 * Warn CI about the unrecoverable wedged condition.
@@ -1133,10 +1133,10 @@ static int do_reset(struct intel_gt *gt, 
intel_engine_mask_t stalled_mask)
  {
int er

✓ Fi.CI.BAT: success for drm/i915/dsi: stop relying on implicit dev_priv variable (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev3)
URL   : https://patchwork.freedesktop.org/series/132285/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14630 -> Patchwork_132285v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/index.html

Participating hosts (36 -> 35)
--

  Additional (2): bat-dg2-11 fi-apl-guc 
  Missing(3): bat-kbl-2 bat-jsl-1 fi-elk-e7500 

Known issues


  Here are the changes found in Patchwork_132285v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#4083])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@gem_m...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#4077]) +2 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#6621])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#4212]) +7 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#5190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#4215] / [i915#5190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#4103] / [i915#4213]) +1 
other test skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#3840])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-11: NOTRUN -> [SKIP][11]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#5274])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-apl-guc: NOTRUN -> [SKIP][13] +17 other tests skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/fi-apl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pm_backlight@basic-brightness:
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#5354])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_pm_backli...@basic-brightness.html

  * igt@kms_psr@psr-sprite-plane-onoff:
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#1072] / [i915#9732]) +3 
other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_...@psr-sprite-plane-onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#3555])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#3708])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@prime_v...@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4077]) +1 
other test skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132285v3/bat-dg2-11/igt@prime_v...@basic-fence

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: stop relying on implicit dev_priv variable (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: stop relying on implicit dev_priv variable (rev3)
URL   : https://patchwork.freedesktop.org/series/132285/
State : warning

== Summary ==

Error: dim checkpatch failed
1c60cb4f5f7a drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition
0b6d2dbcdd06 drm/i915/dsi: add VLV_ prefix to VLV only register macros
-:62: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:92:
+#define VLV_MIPI_TEARING_CTRL(port)_MMIO_MIPI(port, 
_MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)

total: 0 errors, 1 warnings, 0 checks, 40 lines checked
2567d11c3d9f drm/i915/dsi: unify connector/encoder type and name usage
-:256: CHECK:CAMELCASE: Avoid CamelCase: 
#256: FILE: drivers/gpu/drm/i915/display/vlv_dsi.c:1991:
+   connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; 
/*XXX*/

total: 0 errors, 0 warnings, 1 checks, 264 lines checked
832d9b2447e5 drm/i915/dsi: pass display to register macros instead of implicit 
variable
-:1108: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#1108: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:22:
+#define  BXT_MIPI_TRANS_HACTIVE(tc)_MMIO_MIPI(BXT_MIPI_BASE, tc, 
_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)

-:1116: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#1116: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:26:
+#define  BXT_MIPI_TRANS_VACTIVE(tc)_MMIO_MIPI(BXT_MIPI_BASE, tc, 
_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)

-:1124: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#1124: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:30:
+#define  BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, 
_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)

-:1137: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#1137: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:40:
+#define VLV_MIPI_PORT_CTRL(port)   _MMIO_MIPI(VLV_MIPI_BASE, port, 
_MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)

-:1145: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#1145: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:45:
+#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(BXT_MIPI_BASE, tc, 
_BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)

-:1158: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#1158: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:89:
+#define VLV_MIPI_TEARING_CTRL(port)
_MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)

-:1169: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#1169: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:97:
+#define MIPI_DEVICE_READY(display, port)   
_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, 
_MIPIC_DEVICE_READY)

-:1185: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#1185: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:107:
+#define MIPI_INTR_STAT(display, port)  
_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)

-:1188: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#1188: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:110:
+#define MIPI_INTR_EN(display, port)
_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)

-:1201: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#1201: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:146:
+#define MIPI_DSI_FUNC_PRG(display, port)   
_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, 
_MIPIC_DSI_FUNC_PRG)

-:1214: WARNING:LONG_LINE: line length of 134 exceeds 100 columns
#1214: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:169:
+#define MIPI_HS_TX_TIMEOUT(display, port)  
_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, 
_MIPIC_HS_TX_TIMEOUT)

-:1222: WARNING:LONG_LINE: line length of 134 exceeds 100 columns
#1222: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:174:
+#define MIPI_LP_RX_TIMEOUT(display, port)  
_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, 
_MIPIC_LP_RX_TIMEOUT)

-:1230: WARNING:LONG_LINE: line length of 146 exceeds 100 columns
#1230: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:179:
+#define MIPI_TURN_AROUND_TIMEOUT(display, port)
_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, 
_MIPIC_TURN_AROUND_TIMEOUT)

-:1238: WARNING:LONG_LINE: line length of 144 exceeds 100 columns
#1238: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:184:
+#define MIPI_DEVICE_RESET_TIMER(display, port) 
_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, 
_MIPIC_DEVICE_RESET_TIMER)

-:1246: WARNING:LONG_LINE: line length of 136 exceeds 100 columns
#1246: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:189:
+#define MIPI_DPI_RESOLUTION(display, port) 
_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, 
_MIPIC_DPI_RESOLUTION)

-:1257: WARNING:LONG

Re: [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable

[Rodrigo Vivi]

On Mon, Apr 22, 2024 at 06:16:59PM -0300, Gustavo Sousa wrote:
> Quoting Rodrigo Vivi (2024-04-22 18:10:50-03:00)
> >On Fri, Apr 19, 2024 at 01:04:06PM +0300, Jani Nikula wrote:
> >> Stop relying on the dev_priv local variable in the DSI register
> >> macros. Pass struct intel_display pointer to the macros. Move the MIPI
> >> DSI MMIO base selection to a different level, passing it to _MMIO_MIPI()
> >> and doing the addition there.
> >> 
> >> Start using the local display variable for all intel_de_* usage, and
> >> opportunistically use it for other things than display registers as
> >> well.
> >> 
> >> Signed-off-by: Jani Nikula 
> >> 
> >> ---
> >> 
> >> Tip: Applying the patch and using 'git show --color-words' is probably
> >> the easiest way to review.
> >
> >wow! this is indeed a nice feature for this case. I had never tried it 
> >before.
> >Thanks for showing that.
> >
> >But the registers changes were easier to review the old way. ;)
> 
> What about --word-diff for those? :-)

this is overall better indeed! Thanks

although for the registers the full context was more clear... but maybe
it is just a matter of getting used to it...
nowadays with the b4 in place these small/smart diffs might help the
reviews

Thank you so much

> 
> --
> Gustavo Sousa
> 
> >
> >Reviewed-by: Rodrigo Vivi 
> >
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_display.c |   8 +-
> >>  drivers/gpu/drm/i915/display/vlv_dsi.c   | 337 ++-
> >>  drivers/gpu/drm/i915/display/vlv_dsi_pll.c   |  22 +-
> >>  drivers/gpu/drm/i915/display/vlv_dsi_regs.h  | 324 +-
> >>  4 files changed, 349 insertions(+), 342 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> >> b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 96ed1490fec7..b9434465d3a7 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -3722,8 +3722,8 @@ static bool bxt_get_dsi_transcoder_state(struct 
> >> intel_crtc *crtc,
> >>   struct intel_crtc_state 
> >> *pipe_config,
> >>   struct 
> >> intel_display_power_domain_set *power_domain_set)
> >>  {
> >> -struct drm_device *dev = crtc->base.dev;
> >> -struct drm_i915_private *dev_priv = to_i915(dev);
> >> +struct intel_display *display = to_intel_display(crtc);
> >> +struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >>  enum transcoder cpu_transcoder;
> >>  enum port port;
> >>  u32 tmp;
> >> @@ -3749,11 +3749,11 @@ static bool bxt_get_dsi_transcoder_state(struct 
> >> intel_crtc *crtc,
> >>  break;
> >>  
> >>  /* XXX: this works for video mode only */
> >> -tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
> >> +tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
> >>  if (!(tmp & DPI_ENABLE))
> >>  continue;
> >>  
> >> -tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
> >> +tmp = intel_de_read(display, MIPI_CTRL(display, port));
> >>  if ((tmp & BXT_PIPE_SELECT_MASK) != 
> >> BXT_PIPE_SELECT(crtc->pipe))
> >>  continue;
> >>  
> >> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c 
> >> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> >> index 9967ef58f1ec..ee9923c7b115 100644
> >> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> >> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> >> @@ -85,18 +85,18 @@ enum mipi_dsi_pixel_format 
> >> pixel_format_from_register_bits(u32 fmt)
> >>  
> >>  void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port 
> >> port)
> >>  {
> >> -struct drm_i915_private *dev_priv = 
> >> to_i915(intel_dsi->base.base.dev);
> >> +struct intel_display *display = 
> >> to_intel_display(&intel_dsi->base);
> >>  u32 mask;
> >>  
> >>  mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
> >>  LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
> >>  
> >> -if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
> >> +if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, 
> >> port),
> >>mask, 100))
> >> -drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
> >> +drm_err(display->drm, "DPI FIFOs are not empty\n");
> >>  }
> >>  
> >> -static void write_data(struct drm_i915_private *dev_priv,
> >> +static void write_data(struct intel_display *display,
> >> i915_reg_t reg,
> >> const u8 *data, u32 len)
> >>  {
> >> @@ -108,18 +108,18 @@ static void write_data(struct drm_i915_private 
> >> *dev_priv,
> >>  for (j = 0; j < min_t(u32, len - i, 4); j++)
> >>  val |= *data++ << 8 * j;
> >>  
> >> - 

✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915: Refactor confusing __intel_gt_reset()

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915: Refactor confusing 
__intel_gt_reset()
URL   : https://patchwork.freedesktop.org/series/132731/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14630 -> Patchwork_132731v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/index.html

Participating hosts (36 -> 36)
--

  Additional (2): fi-glk-j4005 fi-apl-guc 
  Missing(2): bat-mtlp-9 fi-kbl-8809g 

Known issues


  Here are the changes found in Patchwork_132731v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-glk-j4005:   NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
- fi-glk-j4005:   NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9:  [PASS][4] -> [FAIL][5] ([i915#10378])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][6] -> [ABORT][7] ([i915#10800])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_engines:
- bat-adls-6: [PASS][8] -> [TIMEOUT][9] ([i915#10026] / 
[i915#10134])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/bat-adls-6/igt@i915_selftest@live@gt_engines.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/bat-adls-6/igt@i915_selftest@live@gt_engines.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-j4005:   NOTRUN -> [SKIP][10] +10 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-apl-guc: NOTRUN -> [SKIP][11] +17 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/fi-apl-guc/igt@kms_hdmi_inj...@inject-audio.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- {bat-rpls-4}:   [DMESG-WARN][12] ([i915#5591]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14630/bat-rpls-4/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/bat-rpls-4/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10026]: https://gitlab.freedesktop.org/drm/intel/issues/10026
  [i915#10134]: https://gitlab.freedesktop.org/drm/intel/issues/10134
  [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
  [i915#10800]: https://gitlab.freedesktop.org/drm/intel/issues/10800
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591


Build changes
-

  * Linux: CI_DRM_14630 -> Patchwork_132731v1

  CI-20190529: 20190529
  CI_DRM_14630: d3410a305a38d42343c3beba610f2ceca377 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7815: d5d516bfdf77898e934b4c7ed947a43711cfb226 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_132731v1: d3410a305a38d42343c3beba610f2ceca377 @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132731v1/index.html

Re: [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable

[Gustavo Sousa]

Quoting Rodrigo Vivi (2024-04-22 18:10:50-03:00)
>On Fri, Apr 19, 2024 at 01:04:06PM +0300, Jani Nikula wrote:
>> Stop relying on the dev_priv local variable in the DSI register
>> macros. Pass struct intel_display pointer to the macros. Move the MIPI
>> DSI MMIO base selection to a different level, passing it to _MMIO_MIPI()
>> and doing the addition there.
>> 
>> Start using the local display variable for all intel_de_* usage, and
>> opportunistically use it for other things than display registers as
>> well.
>> 
>> Signed-off-by: Jani Nikula 
>> 
>> ---
>> 
>> Tip: Applying the patch and using 'git show --color-words' is probably
>> the easiest way to review.
>
>wow! this is indeed a nice feature for this case. I had never tried it before.
>Thanks for showing that.
>
>But the registers changes were easier to review the old way. ;)

What about --word-diff for those? :-)

--
Gustavo Sousa

>
>Reviewed-by: Rodrigo Vivi 
>
>> ---
>>  drivers/gpu/drm/i915/display/intel_display.c |   8 +-
>>  drivers/gpu/drm/i915/display/vlv_dsi.c   | 337 ++-
>>  drivers/gpu/drm/i915/display/vlv_dsi_pll.c   |  22 +-
>>  drivers/gpu/drm/i915/display/vlv_dsi_regs.h  | 324 +-
>>  4 files changed, 349 insertions(+), 342 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 96ed1490fec7..b9434465d3a7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -3722,8 +3722,8 @@ static bool bxt_get_dsi_transcoder_state(struct 
>> intel_crtc *crtc,
>>   struct intel_crtc_state 
>> *pipe_config,
>>   struct 
>> intel_display_power_domain_set *power_domain_set)
>>  {
>> -struct drm_device *dev = crtc->base.dev;
>> -struct drm_i915_private *dev_priv = to_i915(dev);
>> +struct intel_display *display = to_intel_display(crtc);
>> +struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>  enum transcoder cpu_transcoder;
>>  enum port port;
>>  u32 tmp;
>> @@ -3749,11 +3749,11 @@ static bool bxt_get_dsi_transcoder_state(struct 
>> intel_crtc *crtc,
>>  break;
>>  
>>  /* XXX: this works for video mode only */
>> -tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
>> +tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
>>  if (!(tmp & DPI_ENABLE))
>>  continue;
>>  
>> -tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
>> +tmp = intel_de_read(display, MIPI_CTRL(display, port));
>>  if ((tmp & BXT_PIPE_SELECT_MASK) != 
>> BXT_PIPE_SELECT(crtc->pipe))
>>  continue;
>>  
>> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c 
>> b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> index 9967ef58f1ec..ee9923c7b115 100644
>> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> @@ -85,18 +85,18 @@ enum mipi_dsi_pixel_format 
>> pixel_format_from_register_bits(u32 fmt)
>>  
>>  void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port 
>> port)
>>  {
>> -struct drm_i915_private *dev_priv = 
>> to_i915(intel_dsi->base.base.dev);
>> +struct intel_display *display = to_intel_display(&intel_dsi->base);
>>  u32 mask;
>>  
>>  mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
>>  LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
>>  
>> -if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
>> +if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, 
>> port),
>>mask, 100))
>> -drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
>> +drm_err(display->drm, "DPI FIFOs are not empty\n");
>>  }
>>  
>> -static void write_data(struct drm_i915_private *dev_priv,
>> +static void write_data(struct intel_display *display,
>> i915_reg_t reg,
>> const u8 *data, u32 len)
>>  {
>> @@ -108,18 +108,18 @@ static void write_data(struct drm_i915_private 
>> *dev_priv,
>>  for (j = 0; j < min_t(u32, len - i, 4); j++)
>>  val |= *data++ << 8 * j;
>>  
>> -intel_de_write(dev_priv, reg, val);
>> +intel_de_write(display, reg, val);
>>  }
>>  }
>>  
>> -static void read_data(struct drm_i915_private *dev_priv,
>> +static void read_data(struct intel_display *display,
>>i915_reg_t reg,
>>u8 *data, u32 len)
>>  {
>>  u32 i, j;
>>  
>>  for (i = 0; i < len; i += 4) {
>> -u32 val = intel_de_read(dev_priv, reg);
>> +u32 val = intel_de_read(display, reg);
>>  
>>   

✗ Fi.CI.SPARSE: warning for series starting with [v2,1/2] drm/i915: Refactor confusing __intel_gt_reset()

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915: Refactor confusing 
__intel_gt_reset()
URL   : https://patchwork.freedesktop.org/series/132731/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [PATCH v2 4/4] drm/i915/dsi: pass display to register macros instead of implicit variable

[Rodrigo Vivi]

On Fri, Apr 19, 2024 at 01:04:06PM +0300, Jani Nikula wrote:
> Stop relying on the dev_priv local variable in the DSI register
> macros. Pass struct intel_display pointer to the macros. Move the MIPI
> DSI MMIO base selection to a different level, passing it to _MMIO_MIPI()
> and doing the addition there.
> 
> Start using the local display variable for all intel_de_* usage, and
> opportunistically use it for other things than display registers as
> well.
> 
> Signed-off-by: Jani Nikula 
> 
> ---
> 
> Tip: Applying the patch and using 'git show --color-words' is probably
> the easiest way to review.

wow! this is indeed a nice feature for this case. I had never tried it before.
Thanks for showing that.

But the registers changes were easier to review the old way. ;)

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/display/intel_display.c |   8 +-
>  drivers/gpu/drm/i915/display/vlv_dsi.c   | 337 ++-
>  drivers/gpu/drm/i915/display/vlv_dsi_pll.c   |  22 +-
>  drivers/gpu/drm/i915/display/vlv_dsi_regs.h  | 324 +-
>  4 files changed, 349 insertions(+), 342 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 96ed1490fec7..b9434465d3a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3722,8 +3722,8 @@ static bool bxt_get_dsi_transcoder_state(struct 
> intel_crtc *crtc,
>struct intel_crtc_state *pipe_config,
>struct intel_display_power_domain_set 
> *power_domain_set)
>  {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   enum transcoder cpu_transcoder;
>   enum port port;
>   u32 tmp;
> @@ -3749,11 +3749,11 @@ static bool bxt_get_dsi_transcoder_state(struct 
> intel_crtc *crtc,
>   break;
>  
>   /* XXX: this works for video mode only */
> - tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
> + tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
>   if (!(tmp & DPI_ENABLE))
>   continue;
>  
> - tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
> + tmp = intel_de_read(display, MIPI_CTRL(display, port));
>   if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
>   continue;
>  
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c 
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 9967ef58f1ec..ee9923c7b115 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -85,18 +85,18 @@ enum mipi_dsi_pixel_format 
> pixel_format_from_register_bits(u32 fmt)
>  
>  void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
>  {
> - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> + struct intel_display *display = to_intel_display(&intel_dsi->base);
>   u32 mask;
>  
>   mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
>   LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
>  
> - if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
> + if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port),
> mask, 100))
> - drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
> + drm_err(display->drm, "DPI FIFOs are not empty\n");
>  }
>  
> -static void write_data(struct drm_i915_private *dev_priv,
> +static void write_data(struct intel_display *display,
>  i915_reg_t reg,
>  const u8 *data, u32 len)
>  {
> @@ -108,18 +108,18 @@ static void write_data(struct drm_i915_private 
> *dev_priv,
>   for (j = 0; j < min_t(u32, len - i, 4); j++)
>   val |= *data++ << 8 * j;
>  
> - intel_de_write(dev_priv, reg, val);
> + intel_de_write(display, reg, val);
>   }
>  }
>  
> -static void read_data(struct drm_i915_private *dev_priv,
> +static void read_data(struct intel_display *display,
> i915_reg_t reg,
> u8 *data, u32 len)
>  {
>   u32 i, j;
>  
>   for (i = 0; i < len; i += 4) {
> - u32 val = intel_de_read(dev_priv, reg);
> + u32 val = intel_de_read(display, reg);
>  
>   for (j = 0; j < min_t(u32, len - i, 4); j++)
>   *data++ = val >> 8 * j;
> @@ -131,7 +131,7 @@ static ssize_t intel_dsi_host_transfer(struct 
> mipi_dsi_host *host,
>  {
>   struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
>   struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi;
> - struct drm_i915_private *dev_pri

Re: [PATCH v2 3/4] drm/i915/dsi: unify connector/encoder type and name usage

[Rodrigo Vivi]

On Fri, Apr 19, 2024 at 01:04:05PM +0300, Jani Nikula wrote:
> Stop using struct drm_* local variables and parameters where
> possible. Drop the intel_ prefix from struct intel_encoder and
> intel_connector local variable and parameter names. Drop useless
> intermediate variables.

nice clean-up

Reviewed-by: Rodrigo Vivi 


> 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/vlv_dsi.c | 134 +++--
>  1 file changed, 60 insertions(+), 74 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c 
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 665247a2e834..9967ef58f1ec 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -85,9 +85,7 @@ enum mipi_dsi_pixel_format 
> pixel_format_from_register_bits(u32 fmt)
>  
>  void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
>  {
> - struct drm_encoder *encoder = &intel_dsi->base.base;
> - struct drm_device *dev = encoder->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
>   u32 mask;
>  
>   mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
> @@ -132,8 +130,8 @@ static ssize_t intel_dsi_host_transfer(struct 
> mipi_dsi_host *host,
>  const struct mipi_dsi_msg *msg)
>  {
>   struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
> - struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi;
> + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
>   enum port port = intel_dsi_host->port;
>   struct mipi_dsi_packet packet;
>   ssize_t ret;
> @@ -225,9 +223,7 @@ static const struct mipi_dsi_host_ops intel_dsi_host_ops 
> = {
>  static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
>   enum port port)
>  {
> - struct drm_encoder *encoder = &intel_dsi->base.base;
> - struct drm_device *dev = encoder->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
>   u32 mask;
>  
>   /* XXX: pipe, hs */
> @@ -662,8 +658,7 @@ static void intel_dsi_port_enable(struct intel_encoder 
> *encoder,
>  
>  static void intel_dsi_port_disable(struct intel_encoder *encoder)
>  {
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>   enum port port;
>  
> @@ -675,7 +670,8 @@ static void intel_dsi_port_disable(struct intel_encoder 
> *encoder)
>   intel_de_posting_read(dev_priv, port_ctrl);
>   }
>  }
> -static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> +
> +static void intel_dsi_prepare(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config);
>  static void intel_dsi_unprepare(struct intel_encoder *encoder);
>  
> @@ -1009,8 +1005,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder 
> *encoder,
>  static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
>   struct intel_crtc_state *pipe_config)
>  {
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct drm_display_mode *adjusted_mode =
>   &pipe_config->hw.adjusted_mode;
>   struct drm_display_mode *adjusted_mode_sw;
> @@ -1209,12 +1204,11 @@ static u16 txclkesc(u32 divider, unsigned int us)
>   }
>  }
>  
> -static void set_dsi_timings(struct drm_encoder *encoder,
> +static void set_dsi_timings(struct intel_encoder *encoder,
>   const struct drm_display_mode *adjusted_mode)
>  {
> - struct drm_device *dev = encoder->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_dsi *intel_dsi = 
> enc_to_intel_dsi(to_intel_encoder(encoder));
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>   enum port port;
>   unsigned int bpp = 
> mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>   unsigned int lane_count = intel_dsi->lane_count;
> @@ -1298,14 +1292,12 @@ static u32 pixel_format_to_reg(enum 
> mipi_dsi_pixel_format fmt)
>   }
>  }
>  
> -static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> +static void intel_dsi_prepare(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
>  {
> - struct drm_encoder *encoder 

Re: [PATCH v2 2/4] drm/i915/dsi: add VLV_ prefix to VLV only register macros

[Rodrigo Vivi]

On Fri, Apr 19, 2024 at 01:04:04PM +0300, Jani Nikula wrote:
> All the BXT specific macros have BXT_ prefix, do the same for VLV for
> consistency. This is helpful because the platform specific macros can
> use the static MIPI MMIO base rather than dynamic.
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/display/vlv_dsi.c  | 6 +++---
>  drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 4 ++--
>  2 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c 
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 63f4af601d15..665247a2e834 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -481,7 +481,7 @@ static void vlv_dsi_device_ready(struct intel_encoder 
> *encoder)
>* Common bit for both MIPI Port A & MIPI Port C
>* No similar bit in MIPI Port C reg
>*/
> - intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, 
> LP_OUTPUT_HOLD);
> + intel_de_rmw(dev_priv, VLV_MIPI_PORT_CTRL(PORT_A), 0, 
> LP_OUTPUT_HOLD);
>   usleep_range(1000, 1500);
>  
>   intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
> @@ -563,7 +563,7 @@ static void glk_dsi_clear_device_ready(struct 
> intel_encoder *encoder)
>  static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port 
> port)
>  {
>   return IS_GEMINILAKE(i915) || IS_BROXTON(i915) ?
> - BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> + BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port);
>  }
>  
>  static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
> @@ -576,7 +576,7 @@ static void vlv_dsi_clear_device_ready(struct 
> intel_encoder *encoder)
>   for_each_dsi_port(port, intel_dsi->ports) {
>   /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
>   i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> - BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> + BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A);
>  
>   intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
>  DEVICE_READY | ULPS_STATE_ENTER);
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h 
> b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
> index b0cdaad7db9c..12a608a73720 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
> @@ -40,7 +40,7 @@
>  
>  #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
>  #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
> -#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, 
> _MIPIC_PORT_CTRL)
> +#define VLV_MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, 
> _MIPIC_PORT_CTRL)
>  
>   /* BXT port control */
>  #define _BXT_MIPIA_PORT_CTRL 0x6B0C0
> @@ -89,7 +89,7 @@
>  
>  #define _MIPIA_TEARING_CTRL  (VLV_DISPLAY_BASE + 0x61194)
>  #define _MIPIC_TEARING_CTRL  (VLV_DISPLAY_BASE + 0x61704)
> -#define MIPI_TEARING_CTRL(port)  _MMIO_MIPI(port, 
> _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
> +#define VLV_MIPI_TEARING_CTRL(port)  _MMIO_MIPI(port, 
> _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
>  #define  TEARING_EFFECT_DELAY_SHIFT  0
>  #define  TEARING_EFFECT_DELAY_MASK   (0x << 0)
>  
> -- 
> 2.39.2
> 

Re: [PATCH v2 1/4] drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition

[Rodrigo Vivi]

On Fri, Apr 19, 2024 at 01:04:03PM +0300, Jani Nikula wrote:
> There are other unused registers, but this is also unusable and
> inadequate. Remove.
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h 
> b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
> index abbe427e462e..b0cdaad7db9c 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
> @@ -93,9 +93,6 @@
>  #define  TEARING_EFFECT_DELAY_SHIFT  0
>  #define  TEARING_EFFECT_DELAY_MASK   (0x << 0)
>  
> -/* XXX: all bits reserved */
> -#define _MIPIA_AUTOPWG   (VLV_DISPLAY_BASE + 0x611a0)
> -
>  /* MIPI DSI Controller and D-PHY registers */
>  
>  #define _MIPIA_DEVICE_READY  (_MIPI_MMIO_BASE(dev_priv) + 0xb000)
> -- 
> 2.39.2
> 

[PATCH v2 2/2] drm/i915: Fix gt reset with GuC submission is disabled

[Nirmoy Das]

Currently intel_gt_reset() kills the GuC and then resets requested
engines. This is problematic because there is a dedicated CSB FIFO
which only GuC can access and if that FIFO fills up, the hardware
will block on the next context switch until there is space that means
the system is effectively hung. If an engine is reset whilst actively
executing a context, a CSB entry will be sent to say that the context
has gone idle. Thus if reset happens on a very busy system then
killing GuC before killing the engines will lead to deadlock because
of filled up CSB FIFO.

To address this issue, the GuC should be killed only after resetting
the requested engines and before calling intel_gt_init_hw().

v2: Improve commit message(John)

Cc: John Harrison 
Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gt/intel_reset.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index b1393863ca9b..6161f7a3ff70 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -879,8 +879,17 @@ static intel_engine_mask_t reset_prepare(struct intel_gt 
*gt)
intel_engine_mask_t awake = 0;
enum intel_engine_id id;
 
-   /* For GuC mode, ensure submission is disabled before stopping ring */
-   intel_uc_reset_prepare(>->uc);
+   /**
+* For GuC mode with submission enabled, ensure submission
+* is disabled before stopping ring.
+*
+* For GuC mode with submission disabled, ensure that GuC is not
+* sanitized, do that after engine reset. reset_prepare()
+* is followed by engine reset which in this mode requires GuC to
+* process any CSB FIFO entries generated by the resets.
+*/
+   if (intel_uc_uses_guc_submission(>->uc))
+   intel_uc_reset_prepare(>->uc);
 
for_each_engine(engine, gt, id) {
if (intel_engine_pm_get_if_awake(engine))
@@ -1227,6 +1236,9 @@ void intel_gt_reset(struct intel_gt *gt,
 
intel_overlay_reset(gt->i915);
 
+   /* sanitize uC after engine reset */
+   if (!intel_uc_uses_guc_submission(>->uc))
+   intel_uc_reset_prepare(>->uc);
/*
 * Next we need to restore the context, but we don't use those
 * yet either...
-- 
2.42.0

[PATCH v2 1/2] drm/i915: Refactor confusing __intel_gt_reset()

[Nirmoy Das]

__intel_gt_reset() is really for resetting engines though
the name might suggest something else. So add a helper function
to remove confusions with no functional changes.

v2: Move intel_gt_reset_all_engines() next to
intel_gt_reset_engine() to make diff simple(John)

Cc: John Harrison 
Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_gt_pm.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_reset.c | 35 +++
 drivers/gpu/drm/i915/gt/intel_reset.h |  3 +-
 drivers/gpu/drm/i915/gt/selftest_reset.c  |  2 +-
 drivers/gpu/drm/i915/i915_driver.c|  2 +-
 8 files changed, 37 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8c44af1c3451..5c8e9ee3b008 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -678,7 +678,7 @@ void intel_engines_release(struct intel_gt *gt)
 */
GEM_BUG_ON(intel_gt_pm_is_awake(gt));
if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
-   __intel_gt_reset(gt, ALL_ENGINES);
+   intel_gt_reset_all_engines(gt);
 
/* Decouple the backend; but keep the layout for late GPU resets */
for_each_engine(engine, gt, id) {
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 355aab5b38ba..21829439e686 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2898,7 +2898,7 @@ static void enable_error_interrupt(struct intel_engine_cs 
*engine)
drm_err(&engine->i915->drm,
"engine '%s' resumed still in error: %08x\n",
engine->name, status);
-   __intel_gt_reset(engine->gt, engine->mask);
+   intel_gt_reset_engine(engine);
}
 
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 580b5141ce1e..626b166e67ef 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -832,7 +832,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
 
/* Scrub all HW state upon release */
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
-   __intel_gt_reset(gt, ALL_ENGINES);
+   intel_gt_reset_all_engines(gt);
 }
 
 void intel_gt_driver_release(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 220ac4f92edf..c08fdb65cc69 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -159,7 +159,7 @@ static bool reset_engines(struct intel_gt *gt)
if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
return false;
 
-   return __intel_gt_reset(gt, ALL_ENGINES) == 0;
+   return intel_gt_reset_all_engines(gt) == 0;
 }
 
 static void gt_sanitize(struct intel_gt *gt, bool force)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index c8e9aa41fdea..b1393863ca9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -764,7 +764,7 @@ wa_14015076503_end(struct intel_gt *gt, intel_engine_mask_t 
engine_mask)
 HECI_H_GS1_ER_PREP, 0);
 }
 
-int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
+static int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t 
engine_mask)
 {
const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
reset_func reset;
@@ -978,7 +978,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
 
/* Even if the GPU reset fails, it should still stop the engines */
if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
-   __intel_gt_reset(gt, ALL_ENGINES);
+   intel_gt_reset_all_engines(gt);
 
for_each_engine(engine, gt, id)
engine->submit_request = nop_submit_request;
@@ -1089,7 +1089,7 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
/* We must reset pending GPU events before restoring our submission */
ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
-   ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
+   ok = intel_gt_reset_all_engines(gt) == 0;
if (!ok) {
/*
 * Warn CI about the unrecoverable wedged condition.
@@ -1133,10 +1133,10 @@ static int do_reset(struct intel_gt *gt, 
intel_engine_mask_t stalled_mask)
 {
int err, i;
 
-   err = __intel_gt_reset(gt, ALL_ENGINES);
+   err = inte

[linux-next:master] BUILD REGRESSION f529a6d274b3b8c75899e949649d231298f30a32

[kernel test robot]

tree/branch: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: f529a6d274b3b8c75899e949649d231298f30a32  Add linux-next specific 
files for 20240422

Error/Warning reports:

https://lore.kernel.org/oe-kbuild-all/202404221830.cjqlhldl-...@intel.com

Error/Warning: (recently discovered and may have been fixed)

csky-linux-ld: drivers/net/pse-pd/pse_core.c:220:(.text+0x84): undefined 
reference to `rdev_get_id'
csky-linux-ld: drivers/net/pse-pd/pse_core.c:246:(.text+0x19c): undefined 
reference to `rdev_get_drvdata'
csky-linux-ld: drivers/net/pse-pd/pse_core.c:351:(.text+0x6e8): undefined 
reference to `devm_regulator_register'
drivers/net/pse-pd/pse_core.c:212:(.text+0x70): undefined reference to 
`rdev_get_drvdata'
drivers/net/pse-pd/pse_core.c:308:(.text+0x68a): undefined reference to 
`devm_regulator_register'
nios2-linux-ld: pse_core.c:(.text+0x64): undefined reference to `rdev_get_id'
powerpc-linux-ld: warning: orphan section `.bss..Lubsan_data373' from 
`kernel/ptrace.o' being placed in section `.bss..Lubsan_data373'
pse_core.c:(.text+0x4c): relocation truncated to fit: R_NIOS2_CALL26 against 
`rdev_get_drvdata'
pse_core.c:(.text+0x4c): undefined reference to `rdev_get_drvdata'
pse_core.c:(.text+0x64): relocation truncated to fit: R_NIOS2_CALL26 against 
`rdev_get_id'
pse_core.c:(.text+0xddc): relocation truncated to fit: R_NIOS2_CALL26 against 
`devm_regulator_register'
pse_core.c:(.text+0xddc): undefined reference to `devm_regulator_register'
s390-linux-ld: drivers/net/pse-pd/pse_core.c:220:(.text+0xfa): undefined 
reference to `rdev_get_id'

Unverified Error/Warning (likely false positive, please contact us if 
interested):

WARNING: modpost: "strcat" [lib/string_kunit.ko] has no CRC!
WARNING: modpost: "strncat" [lib/string_kunit.ko] has no CRC!
drivers/spmi/spmi-pmic-arb.c:1782 spmi_pmic_arb_register_buses() error: 
uninitialized symbol 'ret'.
drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c:1109 
service_callback() warn: variable dereferenced before check 'instance' (see 
line 1091)

Error/Warning ids grouped by kconfigs:

gcc_recent_errors
|-- alpha-allyesconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- alpha-randconfig-r022-20230114
|   `-- WARNING:modpost:strcat-lib-string_kunit.ko-has-no-CRC
|-- alpha-randconfig-s032-20220304
|   `-- WARNING:modpost:strncat-lib-string_kunit.ko-has-no-CRC
|-- arm-allmodconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- arm-allyesconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- csky-allmodconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- csky-allyesconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- csky-buildonly-randconfig-r001-20230308
|   |-- 
csky-linux-ld:drivers-net-pse-pd-pse_core.c:(.text):undefined-reference-to-devm_regulator_register
|   |-- 
csky-linux-ld:drivers-net-pse-pd-pse_core.c:(.text):undefined-reference-to-rdev_get_drvdata
|   |-- 
csky-linux-ld:drivers-net-pse-pd-pse_core.c:(.text):undefined-reference-to-rdev_get_id
|   |-- 
drivers-net-pse-pd-pse_core.c:(.text):undefined-reference-to-devm_regulator_register
|   `-- 
drivers-net-pse-pd-pse_core.c:(.text):undefined-reference-to-rdev_get_drvdata
|-- i386-randconfig-141-20240422
|   `-- 
drivers-gpu-drm-bridge-cadence-cdns-mhdp8546-core.c-cdns_mhdp_atomic_enable()-warn:inconsistent-returns-mhdp-link_mutex-.
|-- loongarch-allmodconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- microblaze-allmodconfig
|   |

✓ Fi.CI.BAT: success for Force CCS mode to the maximum

[Patchwork]

== Series Details ==

Series: Force CCS mode to the maximum
URL   : https://patchwork.freedesktop.org/series/132721/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14626 -> Patchwork_132721v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/index.html

Participating hosts (35 -> 34)
--

  Additional (3): fi-cfl-8109u bat-jsl-1 fi-elk-e7500 
  Missing(4): fi-kbl-7567u fi-bsw-n3050 bat-mtlp-6 bat-arls-3 

Known issues


  Here are the changes found in Patchwork_132721v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-1:  NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u:   NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html
- bat-jsl-1:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/bat-jsl-1/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u:   NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html
- bat-jsl-1:  NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@active:
- fi-cfl-guc: [PASS][6] -> [DMESG-FAIL][7] ([i915#10606])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14626/fi-cfl-guc/igt@i915_selftest@l...@active.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/fi-cfl-guc/igt@i915_selftest@l...@active.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-1:  NOTRUN -> [SKIP][8] ([i915#4103]) +1 other test skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-jsl-1:  NOTRUN -> [SKIP][9] ([i915#3555] / [i915#9886])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/bat-jsl-1/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-1:  NOTRUN -> [SKIP][10]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/bat-jsl-1/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
- fi-cfl-8109u:   NOTRUN -> [SKIP][11] +11 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/fi-cfl-8109u/igt@kms_pm_backli...@basic-brightness.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
- fi-elk-e7500:   NOTRUN -> [SKIP][12] +24 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/fi-elk-e7500/igt@kms_pm_...@basic-pci-d3-state.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-1:  NOTRUN -> [SKIP][13] ([i915#3555])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/bat-jsl-1/igt@kms_setm...@basic-clone-single-crtc.html

  
 Possible fixes 

  * igt@i915_module_load@load:
- fi-apl-guc: [DMESG-WARN][14] ([i915#10875] / [i915#180] / 
[i915#8585]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14626/fi-apl-guc/igt@i915_module_l...@load.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/fi-apl-guc/igt@i915_module_l...@load.html

  * igt@i915_module_load@reload:
- fi-apl-guc: [DMESG-WARN][16] ([i915#10636] / [i915#180] / 
[i915#1982] / [i915#8585]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14626/fi-apl-guc/igt@i915_module_l...@reload.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/fi-apl-guc/igt@i915_module_l...@reload.html

  * igt@i915_selftest@live@reset:
- fi-apl-guc: [DMESG-WARN][18] ([i915#10636]) -> [PASS][19] +36 
other tests pass
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14626/fi-apl-guc/igt@i915_selftest@l...@reset.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/fi-apl-guc/igt@i915_selftest@l...@reset.html

  * igt@kms_addfb_basic@addfb25-4-tiled:
- fi-apl-guc: [DMESG-WARN][20] -> [PASS][21] +41 other tests pass
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14626/fi-apl-guc/igt@kms_addfb_ba...@addfb25-4-tiled.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132721v1/fi-apl-guc/igt@kms_addfb_ba...@addfb25-4-tiled.html

  * i

✗ Fi.CI.SPARSE: warning for Force CCS mode to the maximum

[Patchwork]

== Series Details ==

Series: Force CCS mode to the maximum
URL   : https://patchwork.freedesktop.org/series/132721/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy 
expression type 31
+./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy 
expression type 31
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced 
symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced 
symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unrep

✗ Fi.CI.CHECKPATCH: warning for Force CCS mode to the maximum

[Patchwork]

== Series Details ==

Series: Force CCS mode to the maximum
URL   : https://patchwork.freedesktop.org/series/132721/
State : warning

== Summary ==

Error: dim checkpatch failed
1f3baf11fbf6 Revert "drm/i915/gt: Do not generate the command streamer for all 
the CCS"
-:10: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate 
one

-:36: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 23 lines checked
1a3548b4d3d2 drm/i915/gt: Force ccs_mode 4
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 37 lines checked

[CI 2/2] drm/i915/gt: Force ccs_mode 4

[Andi Shyti]

Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c 
b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
index 044219c5960a..d0f181a8e73e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
@@ -10,29 +10,33 @@
 
 void intel_gt_apply_ccs_mode(struct intel_gt *gt)
 {
+   unsigned long ccs_mask = CCS_MASK(gt);
int cslice;
u32 mode = 0;
-   int first_ccs = __ffs(CCS_MASK(gt));
+   int first_ccs = __ffs(ccs_mask);
 
if (!IS_DG2(gt->i915))
return;
 
/* Build the value for the fixed CCS load balancing */
for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
-   if (CCS_MASK(gt) & BIT(cslice))
+   if (CCS_MASK(gt) & BIT(cslice)) {
/*
 * If available, assign the cslice
 * to the first available engine...
 */
mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
-
-   else
+   first_ccs = find_next_bit(&ccs_mask,
+ I915_MAX_CCS,
+ first_ccs + 1);
+   } else {
/*
 * ... otherwise, mark the cslice as
 * unavailable if no CCS dispatches here
 */
mode |= XEHP_CCS_MODE_CSLICE(cslice,
 XEHP_CCS_MODE_CSLICE_MASK);
+   }
}
 
intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);
-- 
2.43.0

[CI 1/2] Revert "drm/i915/gt: Do not generate the command streamer for all the CCS"

[Andi Shyti]

This reverts commit ea315f98e5d6d3191b74beb0c3e5fc16081d517c.
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 -
 1 file changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8c44af1c3451..476651bd0a21 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -874,23 +874,6 @@ static intel_engine_mask_t init_engine_mask(struct 
intel_gt *gt)
info->engine_mask &= ~BIT(GSC0);
}
 
-   /*
-* Do not create the command streamer for CCS slices beyond the first.
-* All the workload submitted to the first engine will be shared among
-* all the slices.
-*
-* Once the user will be allowed to customize the CCS mode, then this
-* check needs to be removed.
-*/
-   if (IS_DG2(gt->i915)) {
-   u8 first_ccs = __ffs(CCS_MASK(gt));
-
-   /* Mask off all the CCS engine */
-   info->engine_mask &= ~GENMASK(CCS3, CCS0);
-   /* Put back in the first CCS engine */
-   info->engine_mask |= BIT(_CCS(first_ccs));
-   }
-
return info->engine_mask;
 }
 
-- 
2.43.0

[CI 0/2] Force CCS mode to the maximum

[Andi Shyti]

Hi,

There has been a regression apparently caused by the CCS mode
forced to be 1[*]. But, because I think the kernel approach is
correct and there might be something hardcoded in userspace, I
want to show that with this series we won't see the regression.

What this series does is to force CCS mode to 4 (or to the
maximum). This way we will understand whether the issue comes
because of disabling the automatic load balancing or by forcing
it to use only one CCS.

Thanks gnattu for your report, i will appreciate if you can give
this a try.

Andi

[*] https://gitlab.freedesktop.org/drm/intel/-/issues/10895

Andi Shyti (2):
  Revert "drm/i915/gt: Do not generate the command streamer for all the
CCS"
  drm/i915/gt: Force ccs_mode 4

 drivers/gpu/drm/i915/gt/intel_engine_cs.c   | 17 -
 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 12 
 2 files changed, 8 insertions(+), 21 deletions(-)

-- 
2.43.0

Re: [PATCH v2 0/5] drm/i915/dmc: firmware path handling changes

[Jani Nikula]

On Fri, 19 Apr 2024, Lucas De Marchi  wrote:
> On Fri, Apr 19, 2024 at 12:41:53PM GMT, Jani Nikula wrote:
>>v2 of https://lore.kernel.org/r/cover.1713450693.git.jani.nik...@intel.com
>>
>>Jani Nikula (5):
>>  drm/i915/dmc: handle request_firmware() errors separately
>>  drm/i915/dmc: improve firmware parse failure propagation
>>  drm/i915/dmc: split out per-platform firmware path selection
>>  drm/i915/dmc: change how to disable DMC firmware using module param
>>  drm/i915/display: move dmc_firmware_path to display params
>>
>> .../drm/i915/display/intel_display_params.c   |   4 +
>> .../drm/i915/display/intel_display_params.h   |   1 +
>> drivers/gpu/drm/i915/display/intel_dmc.c  | 175 +++---
>> drivers/gpu/drm/i915/i915_params.c|   3 -
>> drivers/gpu/drm/i915/i915_params.h|   1 -
>> drivers/gpu/drm/xe/xe_device_types.h  |   3 -
>
> Acked-by: Lucas De Marchi 

Thanks for the reviews and acks, pushed to drm-intel-next.

BR,
Jani.



>
> thanks
> Lucas De Marchi
>
>> 6 files changed, 112 insertions(+), 75 deletions(-)
>>
>>-- 
>>2.39.2
>>

-- 
Jani Nikula, Intel

✓ Fi.CI.BAT: success for drm/i915/gem: Downgrade stolen lmem setup warning (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Downgrade stolen lmem setup warning (rev2)
URL   : https://patchwork.freedesktop.org/series/132663/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14625 -> Patchwork_132663v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132663v2/index.html

Participating hosts (35 -> 32)
--

  Missing(3): bat-rplp-1 bat-kbl-2 fi-cfl-8109u 

Known issues


  Here are the changes found in Patchwork_132663v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9:  [PASS][1] -> [FAIL][2] ([i915#10378])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14625/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132663v2/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}:   [WARN][3] ([i915#10436]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14625/bat-mtlp-9/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132663v2/bat-mtlp-9/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gt_contexts:
- {bat-arls-4}:   [ABORT][5] -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14625/bat-arls-4/igt@i915_selftest@live@gt_contexts.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132663v2/bat-arls-4/igt@i915_selftest@live@gt_contexts.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
  [i915#10436]: https://gitlab.freedesktop.org/drm/intel/issues/10436


Build changes
-

  * Linux: CI_DRM_14625 -> Patchwork_132663v2

  CI-20190529: 20190529
  CI_DRM_14625: 7fb8042f224fd84650e556b13e2560d8f86a1914 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7815: d5d516bfdf77898e934b4c7ed947a43711cfb226 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_132663v2: 7fb8042f224fd84650e556b13e2560d8f86a1914 @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132663v2/index.html

✗ Fi.CI.SPARSE: warning for drm/i915/gem: Downgrade stolen lmem setup warning (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Downgrade stolen lmem setup warning (rev2)
URL   : https://patchwork.freedesktop.org/series/132663/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gem/i915_gem_stolen.c:943:32: warning: Using plain 
integer as NULL pointer

✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Downgrade stolen lmem setup warning (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Downgrade stolen lmem setup warning (rev2)
URL   : https://patchwork.freedesktop.org/series/132663/
State : warning

== Summary ==

Error: dim checkpatch failed
d08dfce4c55d drm/i915/gem: Downgrade stolen lmem setup warning
-:12: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line 
(possible unwrapped commit description?)
#12: 
<6> [144.859887] pcieport :4b:00.0: bridge window [mem 
0xb100-0xb11f]

total: 0 errors, 1 warnings, 0 checks, 14 lines checked

Re: [PATCH v8 6/6] drm/{i915,xe}: Implement fbdev emulation as in-kernel client

[Hogander, Jouni]

On Tue, 2024-04-09 at 10:04 +0200, Thomas Zimmermann wrote:
> Replace all code that initializes or releases fbdev emulation
> throughout the driver. Instead initialize the fbdev client by a
> single call to intel_fbdev_setup() after i915 has registered its
> DRM device. Just like similar code in other drivers, i915 fbdev
> emulation now acts like a regular DRM client. Do the same for xe.
> 
> The fbdev client setup consists of the initial preparation and the
> hot-plugging of the display. The latter creates the fbdev device
> and sets up the fbdev framebuffer. The setup performs display
> hot-plugging once. If no display can be detected, DRM probe helpers
> re-run the detection on each hotplug event.
> 
> A call to drm_client_dev_unregister() releases all in-kernel clients
> automatically. No further action is required within i915. If the
> fbdev
> framebuffer has been fully set up, struct fb_ops.fb_destroy
> implements
> the release. For partially initialized emulation, the fbdev client
> reverts the initial setup. Do the same for xe and remove its call to
> intel_fbdev_fini().
> 
> v8:
> - setup client in intel_display_driver_register (Jouni)
> - mention xe in commit message
> 
> v7:
> - update xe driver
> - reword commit message
> 
> v6:
> - use 'i915' for i915 device (Jouni)
> - remove unnecessary code for non-atomic mode setting (Jouni, Ville)
> - fix function name in commit message (Jouni)
> 
> v3:
> -  as before, silently ignore devices without displays
> 
> v2:
> -  let drm_client_register() handle initial hotplug
> -  fix driver name in error message (Jani)
> -  fix non-fbdev build (kernel test robot)
> 
> Signed-off-by: Thomas Zimmermann 

Reviewed-by: Jouni Högander 

> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |   1 -
>  .../drm/i915/display/intel_display_driver.c   |  20 +-
>  drivers/gpu/drm/i915/display/intel_fbdev.c    | 177 
> --
>  drivers/gpu/drm/i915/display/intel_fbdev.h    |  20 +-
>  drivers/gpu/drm/xe/display/xe_display.c   |   2 -
>  5 files changed, 80 insertions(+), 140 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 614e60420a29a..161a5aabf6746 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -85,7 +85,6 @@
>  #include "intel_dvo.h"
>  #include "intel_fb.h"
>  #include "intel_fbc.h"
> -#include "intel_fbdev.h"
>  #include "intel_fdi.h"
>  #include "intel_fifo_underrun.h"
>  #include "intel_frontbuffer.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index e5f052d4ff1cc..ed8589fa35448 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -514,10 +514,6 @@ int intel_display_driver_probe(struct
> drm_i915_private *i915)
>  
> intel_overlay_setup(i915);
>  
> -   ret = intel_fbdev_init(&i915->drm);
> -   if (ret)
> -   return ret;
> -
> /* Only enable hotplug handling once the fbdev is fully set
> up. */
> intel_hpd_init(i915);
>  
> @@ -544,16 +540,6 @@ void intel_display_driver_register(struct
> drm_i915_private *i915)
>  
> intel_display_debugfs_register(i915);
>  
> -   /*
> -    * Some ports require correctly set-up hpd registers for
> -    * detection to work properly (leading to ghost connected
> -    * connector status), e.g. VGA on gm45.  Hence we can only
> set
> -    * up the initial fbdev config after hpd irqs are fully
> -    * enabled. We do it last so that the async config cannot run
> -    * before the connectors are registered.
> -    */
> -   intel_fbdev_initial_config_async(i915);
> -
> /*
>  * We need to coordinate the hotplugs with the asynchronous
>  * fbdev configuration, for which we use the
> @@ -562,6 +548,8 @@ void intel_display_driver_register(struct
> drm_i915_private *i915)
> drm_kms_helper_poll_init(&i915->drm);
> intel_hpd_poll_disable(i915);
>  
> +   intel_fbdev_setup(i915);
> +
> intel_display_device_info_print(DISPLAY_INFO(i915),
> DISPLAY_RUNTIME_INFO(i915),
> &p);
>  }
> @@ -597,9 +585,6 @@ void intel_display_driver_remove_noirq(struct
> drm_i915_private *i915)
>  */
> intel_hpd_poll_fini(i915);
>  
> -   /* poll work can call into fbdev, hence clean that up
> afterwards */
> -   intel_fbdev_fini(i915);
> -
> intel_unregister_dsm_handler();
>  
> /* flush any delayed tasks or pending work */
> @@ -640,7 +625,6 @@ void intel_display_driver_unregister(struct
> drm_i915_private *i915)
>  
> drm_client_dev_unregister(&i915->drm);
>  
> -   intel_fbdev_unregister(i915);
> /*
>  * After flushing the fbdev (incl. a late async config which
>  * will have delayed queu

Re: [PATCH v8 4/6] drm/{i915,xe}: Unregister in-kernel clients

[Hogander, Jouni]

On Tue, 2024-04-09 at 10:04 +0200, Thomas Zimmermann wrote:
> Unregister all in-kernel clients before unloading the i915 driver.
> For
> other drivers, drm_dev_unregister() does this automatically. As i915
> and
> xe do not use this helper, they have to perform the call by
> themselves.
> 
> Note that there are currently no in-kernel clients in i915 or xe. The
> patch prepares the drivers for a related update of their fbdev
> support.
> 
> v8:
> - unregister clients in intel_display_driver_unregister() (Jani)
> - mention xe in commit message (Rodrigo, Jani)
> 
> v7:
> - update xe driver
> 
> Signed-off-by: Thomas Zimmermann 

Reviewed-by: Jouni Högander 

> ---
>  drivers/gpu/drm/i915/display/intel_display_driver.c | 3 +++
>  drivers/gpu/drm/xe/xe_device.c  | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 87dd07e0d138d..b7d636980d83a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -11,6 +11,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -638,6 +639,8 @@ void intel_display_driver_unregister(struct
> drm_i915_private *i915)
> if (!HAS_DISPLAY(i915))
> return;
>  
> +   drm_client_dev_unregister(&i915->drm);
> +
> intel_fbdev_unregister(i915);
> /*
>  * After flushing the fbdev (incl. a late async config which
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c
> index 01bd5ccf05ca6..231ab2f4cd0b9 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -9,6 +9,7 @@
>  
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 

Re: [PATCH v8 1/6] drm/client: Export drm_client_dev_unregister()

[Hogander, Jouni]

On Tue, 2024-04-09 at 10:04 +0200, Thomas Zimmermann wrote:
> Export drm_client_dev_unregister() for use by the i915 driver. The
> driver does not use drm_dev_unregister(), so it has to clean up the
> in-kernel DRM clients by itself.
> 
> Signed-off-by: Thomas Zimmermann 

Reviewed-by: Jouni Högander 

> ---
>  drivers/gpu/drm/drm_client.c | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_client.c
> b/drivers/gpu/drm/drm_client.c
> index 77fe217aeaf36..2803ac111bbd8 100644
> --- a/drivers/gpu/drm/drm_client.c
> +++ b/drivers/gpu/drm/drm_client.c
> @@ -172,6 +172,18 @@ void drm_client_release(struct drm_client_dev
> *client)
>  }
>  EXPORT_SYMBOL(drm_client_release);
>  
> +/**
> + * drm_client_dev_unregister - Unregister clients
> + * @dev: DRM device
> + *
> + * This function releases all clients by calling each client's
> + * &drm_client_funcs.unregister callback. The callback function
> + * is responsibe for releaseing all resources including the client
> + * itself.
> + *
> + * The helper drm_dev_unregister() calls this function. Drivers
> + * that use it don't need to call this function themselves.
> + */
>  void drm_client_dev_unregister(struct drm_device *dev)
>  {
> struct drm_client_dev *client, *tmp;
> @@ -191,6 +203,7 @@ void drm_client_dev_unregister(struct drm_device
> *dev)
> }
> mutex_unlock(&dev->clientlist_mutex);
>  }
> +EXPORT_SYMBOL(drm_client_dev_unregister);
>  
>  /**
>   * drm_client_dev_hotplug - Send hotplug event to clients

[PATCH v2] drm/i915/gem: Downgrade stolen lmem setup warning

[Jonathan Cavitt]

In the case where lmem_size < dsm_base, hardware is reporting that
stolen lmem is unusable.  In this case, instead of throwing a warning,
we can continue execution as normal by disabling stolen LMEM support.
For example, this change will allow the following error report from
ATS-M to no longer apply:

<6> [144.859887] pcieport :4b:00.0: bridge window [mem 
0xb100-0xb11f]
<6> [144.859900] pcieport :4b:00.0: bridge window [mem 
0x3bbc-0x3bbc17ff 64bit pref]
<6> [144.859917] pcieport :4c:01.0: PCI bridge to [bus 4d-4e]
<6> [144.859932] pcieport :4c:01.0: bridge window [mem 
0xb100-0xb11f]
<6> [144.859945] pcieport :4c:01.0: bridge window [mem 
0x3bbc-0x3bbc17ff 64bit pref]
<6> [144.859984] i915 :4d:00.0: [drm] BAR2 resized to 256M
<6> [144.860640] i915 :4d:00.0: [drm] Using a reduced BAR size of 256MiB. 
Consider enabling 'Resizable BAR' or similar, if available in the BIOS.
<4> [144.860719] ---[ cut here ]---
<4> [144.860727] WARNING: CPU: 17 PID: 1815 at 
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:939 
i915_gem_stolen_lmem_setup+0x38c/0x430 [i915]
<4> [144.861430] Modules linked in: i915 snd_intel_dspcfg snd_hda_codec 
snd_hwdep snd_hda_core snd_pcm vgem drm_shmem_helper prime_numbers i2c_algo_bit 
ttm video drm_display_helper drm_buddy fuse x86_pkg_temp_thermal coretemp 
kvm_intel kvm ixgbe mdio irqbypass ptp crct10dif_pclmul crc32_pclmul 
ghash_clmulni_intel pps_core i2c_i801 mei_me i2c_smbus mei wmi acpi_power_meter 
[last unloaded: i915]
<4> [144.861611] CPU: 17 PID: 1815 Comm: i915_module_loa Tainted: G U 
6.8.0-rc5-drmtip_1515-g78f49af27723+ #1
<4> [144.861624] Hardware name: Intel Corporation WHITLEY/WHITLEY, BIOS 
SE5C6200.86B.0020.P41.2109300305 09/30/2021
<4> [144.861632] RIP: 0010:i915_gem_stolen_lmem_setup+0x38c/0x430 [i915]
<4> [144.862287] Code: ff 41 c1 e4 05 e9 ac fe ff ff 4d 63 e4 48 89 ef 48 85 ed 
74 04 48 8b 7d 08 48 c7 c6 10 a3 7b a0 e8 e9 90 43 e1 e9 ee fd ff ff <0f> 0b 49 
c7 c4 ed ff ff ff e9 e0 fd ff ff 0f b7 d2 48 c7 c6 00 d9
<4> [144.862299] RSP: 0018:c90005607980 EFLAGS: 00010207
<4> [144.862315] RAX: fff0 RBX: 0003 RCX: 


Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10833
Suggested-by: Chris Wilson 
Signed-off-by: Jonathan Cavitt 
---

v2:
- Return 0 to allow execution to continue
- Remove white space in commit message
- s/Fixes/Closes

 drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index ad6dd7f3259bc..4d60a5b375053 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -936,8 +936,12 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, 
u16 type,
} else {
/* Use DSM base address instead for stolen memory */
dsm_base = intel_uncore_read64(uncore, GEN6_DSMBASE) & 
GEN11_BDSM_MASK;
-   if (WARN_ON(lmem_size < dsm_base))
-   return ERR_PTR(-ENODEV);
+   if (lmem_size < dsm_base) {
+   drm_dbg(&i915->drm,
+   "Disabling stolen memory support due to OOB 
placement: lmem_size = %lli vs dsm_base = %lli\n",
+   lmem_size, dsm_base);
+   return 0;
+   }
dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
}
 
-- 
2.25.1

Re: Reliably selecting non-CEA modes on Intel graphics (and maybe others)

[Jani Nikula]

On Mon, 22 Apr 2024, Michael Olbrich  wrote:
> Hi,
>
> In short: I have a HDMI monitor attached to Intel graphics. I'm trying to
> set a non-CEA mode but the driver always maps it to the corresponding CEA
> mode.

Please file a bug as described at [1], and attach dmesg with debugs
enabled, so we can see what's going on and what kernel and hardware
you're using exactly, and so on.

BR,
Jani.



[1] https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html


>
> More specifically, the monitor has two 1920x1080@60 modes in the EDID:
> 1. The CEA mode with VIC 16
> 2. A custom DTD mode with exactly the same timings (this is the preferred
>mode).
>
> From a userspace perspective, the two modes are mostly identical, except
> for the 16:9 aspect ratio flag in the CEA mode and the preferred type in
> the other.
>
> I want to select the second (preferred) mode, but that does not seem
> possible:
> intel_hdmi_compute_avi_infoframe() tries to determine which VIC should be
> added to the avi infoframe and if limited or full range is used.
> It uses various DRM helpers here but in the end drm_match_cea_mode() is
> called. And here lies the problem:
> The mode provided by the userspace has explicitly no aspect ratio. But
> here, it is interpreted as "the aspect ration is undefined". So matching
> ignored the aspect ratio and the CEA mode with VIC 16 is found and limited
> range is used.
>
> The commit that introduces this fuzzy matching
> 357768cc9e3fdacf6551da0ae1483bc87dbcb4e8 ("drm/edid: Fix cea mode aspect
> ratio handling") made sense at the time. The capability
> DRM_CLIENT_CAP_ASPECT_RATIO that exposes aspect ratios to userspace was
> introduced later in the same merge request, from what I can tell
> 7595bda2fb4378ccbb8db1d0e8de56d15ea7f7fa ("drm: Add DRM client cap for
> aspect-ratio").
>
> Am I missing something here, or is it just not possible to select the
> non-CEA mode right now? In my specific example, the selected CEA mode is
> actually supported by the monitor, but as far as I can tell, the CEA mode
> is used even if the monitor does not support it at all.
>
> I've only tested this on Intel, but I assume that other drivers that use
> the same helpers have the same problem.
>
> So how can this be fixed? I've considered matching the aspect ratio based
> on the DRM_CLIENT_CAP_ASPECT_RATIO capability, but I'm not sure if that is
> valid. The documentation is limited and I found nothing that describes what
> the userspace should do here.
> Or would a new capability make sense here? Or something entirely different?
> I'm not sure how I should proceed here. Any help would be appreciated.
>
> Regards,
> Michael

-- 
Jani Nikula, Intel

Re: [PATCH 1/2] drm/print: drop include debugfs.h and include where needed

[Dmitry Baryshkov]

On Mon, Apr 22, 2024 at 03:10:10PM +0300, Jani Nikula wrote:
> Surprisingly many places depend on debugfs.h to be included via
> drm_print.h. Fix them.
> 
> v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe
> 
> v2: Also fix ivpu and vmwgfx
> 
> Reviewed-by: Andrzej Hajda 
> Acked-by: Maxime Ripard 
> Link: 
> https://patchwork.freedesktop.org/patch/msgid/20240410141434.157908-1-jani.nik...@intel.com
> Signed-off-by: Jani Nikula 
> 
> ---
> 
> Cc: Jacek Lawrynowicz 
> Cc: Stanislaw Gruszka 
> Cc: Oded Gabbay 
> Cc: Russell King 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: Andrzej Hajda 
> Cc: Neil Armstrong 
> Cc: Robert Foss 
> Cc: Laurent Pinchart 
> Cc: Jonas Karlman 
> Cc: Jernej Skrabec 
> Cc: Maarten Lankhorst 
> Cc: Maxime Ripard 
> Cc: Thomas Zimmermann 
> Cc: Jani Nikula 
> Cc: Rodrigo Vivi 
> Cc: Joonas Lahtinen 
> Cc: Tvrtko Ursulin 
> Cc: Frank Binns 
> Cc: Matt Coster 
> Cc: Rob Clark 
> Cc: Abhinav Kumar 
> Cc: Dmitry Baryshkov 
> Cc: Sean Paul 
> Cc: Marijn Suijten 
> Cc: Karol Herbst 
> Cc: Lyude Paul 
> Cc: Danilo Krummrich 
> Cc: Alex Deucher 
> Cc: "Christian König" 
> Cc: "Pan, Xinhui" 
> Cc: Alain Volmat 
> Cc: Huang Rui 
> Cc: Zack Rusin 
> Cc: Broadcom internal kernel review list 
> 
> Cc: Lucas De Marchi 
> Cc: "Thomas Hellström" 
> Cc: dri-de...@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedr...@lists.freedesktop.org
> Cc: nouv...@lists.freedesktop.org
> Cc: amd-...@lists.freedesktop.org
> ---
>  drivers/accel/ivpu/ivpu_debugfs.c   | 2 ++
>  drivers/gpu/drm/armada/armada_debugfs.c | 1 +
>  drivers/gpu/drm/bridge/ite-it6505.c | 1 +
>  drivers/gpu/drm/bridge/panel.c  | 2 ++
>  drivers/gpu/drm/drm_print.c | 6 +++---
>  drivers/gpu/drm/i915/display/intel_dmc.c| 1 +
>  drivers/gpu/drm/imagination/pvr_fw_trace.c  | 1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 ++

Acked-by: Dmitry Baryshkov  # drm/msm

>  drivers/gpu/drm/nouveau/dispnv50/crc.c  | 2 ++
>  drivers/gpu/drm/radeon/r100.c   | 1 +
>  drivers/gpu/drm/radeon/r300.c   | 1 +
>  drivers/gpu/drm/radeon/r420.c   | 1 +
>  drivers/gpu/drm/radeon/r600.c   | 3 ++-
>  drivers/gpu/drm/radeon/radeon_fence.c   | 1 +
>  drivers/gpu/drm/radeon/radeon_gem.c | 1 +
>  drivers/gpu/drm/radeon/radeon_ib.c  | 2 ++
>  drivers/gpu/drm/radeon/radeon_pm.c  | 1 +
>  drivers/gpu/drm/radeon/radeon_ring.c| 2 ++
>  drivers/gpu/drm/radeon/radeon_ttm.c | 1 +
>  drivers/gpu/drm/radeon/rs400.c  | 1 +
>  drivers/gpu/drm/radeon/rv515.c  | 1 +
>  drivers/gpu/drm/sti/sti_drv.c   | 1 +
>  drivers/gpu/drm/ttm/ttm_device.c| 1 +
>  drivers/gpu/drm/ttm/ttm_resource.c  | 3 ++-
>  drivers/gpu/drm/ttm/ttm_tt.c| 5 +++--
>  drivers/gpu/drm/vc4/vc4_drv.h   | 1 +
>  drivers/gpu/drm/vmwgfx/vmwgfx_gem.c | 2 ++
>  drivers/gpu/drm/xe/xe_debugfs.c | 1 +
>  drivers/gpu/drm/xe/xe_gt_debugfs.c  | 2 ++
>  drivers/gpu/drm/xe/xe_uc_debugfs.c  | 2 ++
>  include/drm/drm_print.h | 2 +-
>  31 files changed, 46 insertions(+), 8 deletions(-)

-- 
With best wishes
Dmitry

Re: [PATCH 14/14] drm/i915/dpio: Extract vlv_dpio_phy_regs.h

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Pull the VLV/CHV DPIO PHY sideband registers to their own file.
>
> Signed-off-by: Ville Syrjälä 

git show --color-moved tells me this is fine.

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |   1 +
>  .../i915/display/intel_display_power_well.c   |   1 +
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c |   1 +
>  drivers/gpu/drm/i915/display/intel_dpll.c |   1 +
>  .../gpu/drm/i915/display/vlv_dpio_phy_regs.h  | 309 ++
>  drivers/gpu/drm/i915/i915_reg.h   | 298 -
>  6 files changed, 313 insertions(+), 298 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 96ed1490fec7..59f989207c74 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -120,6 +120,7 @@
>  #include "skl_scaler.h"
>  #include "skl_universal_plane.h"
>  #include "skl_watermark.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_dsi.h"
>  #include "vlv_dsi_pll.h"
>  #include "vlv_dsi_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index e4ba6efc90e6..83f616097a29 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -27,6 +27,7 @@
>  #include "intel_tc.h"
>  #include "intel_vga.h"
>  #include "skl_watermark.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_sideband.h"
>  #include "vlv_sideband_reg.h"
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 11875d18a8fc..d20e4e9cf7f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -30,6 +30,7 @@
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
>  #include "intel_dpio_phy.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_sideband.h"
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index c2ee95993a96..a981f45facb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -20,6 +20,7 @@
>  #include "intel_panel.h"
>  #include "intel_pps.h"
>  #include "intel_snps_phy.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_sideband.h"
>  
>  struct intel_dpll_funcs {
> diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h 
> b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
> new file mode 100644
> index ..477506f0b2cc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
> @@ -0,0 +1,309 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef __VLV_DPIO_PHY_REGS_H__
> +#define __VLV_DPIO_PHY_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
> +#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
> +#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
> +#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
> +#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
> +#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + 
> (dw) * 4)
> +#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
> +#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) 
> * 4)
> +#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
> +
> +/*
> + * Per pipe/PLL DPIO regs
> + */
> +#define VLV_PLL_DW3(ch)  _VLV_PLL((ch), 3)
> +#define   DPIO_S1_DIV_MASK   REG_GENMASK(30, 28)
> +#define   DPIO_S1_DIV(s1)REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
> +#define   DPIO_S1_DIV_DAC0 /* 10, DAC 25-225M rate */
> +#define   DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */
> +#define   DPIO_S1_DIV_LVDS1  2 /* 14 */
> +#define   DPIO_S1_DIV_LVDS2  3 /* 7 */
> +#define   DPIO_K_DIV_MASKREG_GENMASK(27, 24)
> +#define   DPIO_K_DIV(k)  REG_FIELD_PREP(DPIO_K_DIV_MASK, 
> (k))
> +#define   DPIO_P1_DIV_MASK   REG_GENMASK(23, 21)
> +#define   DPIO_P1_DIV(p1)REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
> +#define   DPIO_P2_DIV_MASK   REG_GENMASK(20, 16)
> +#define   DPIO_P2_DIV(p2)REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
> +#define   DPIO_N_DIV_MASKREG_GENMASK(15, 12)
> +#define   DPIO_N_DIV(n)  REG_FIELD_PREP(DPIO_N_DIV_MASK, 
> (n))
> +#define   DPIO_ENABLE_CALIBRATIONREG_BIT(11)
> +#define   DPIO_M1_DIV_MASK  

Re: [PATCH v2 1/2] drm/print: drop include debugfs.h and include where needed

[Jani Nikula]

On Thu, 18 Apr 2024, Jani Nikula  wrote:
> On Thu, 18 Apr 2024, Robert Foss  wrote:
>> I'm seeing build errors for drivers/gpu/drm/bridge/ite-it6505.c, is
>> this expected?
>
> No, but it's possible my configs didn't catch all configs. :(

Okay, enabled a bunch more arm/arm64 stuff, and hit some more issues. v3
at [1].

BR,
Jani.


[1] https://lore.kernel.org/r/20240422121011.4133236-1-jani.nik...@intel.com


-- 
Jani Nikula, Intel

Re: [PATCH 13/14] drm/i915/dpio: Clean up the vlv/chv PHY register bits

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Use REG_BIT() & co. for the vlv/chv DPIO PHY registers.
>
> Signed-off-by: Ville Syrjälä 

What a PITA patch to review!

A couple of comments inline, overall

Reviewed-by: Jani Nikula 

[snip]

>  #define VLV_PLL_DW5(ch)  _VLV_PLL((ch), 5)
> -#define   DPIO_REFSEL_OVERRIDE   27
> -#define   DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
> -#define   DPIO_BIAS_CURRENT_CTL_SHIFT21 /* 3 bits, always 0x7 */

Here the shift is 21...

> -#define   DPIO_PLL_REFCLK_SEL_SHIFT  16 /* 2 bits */
> -#define   DPIO_PLL_REFCLK_SEL_MASK   3
> -#define   DPIO_DRIVER_CTL_SHIFT  12 /* always set to 0x8 */
> -#define   DPIO_CLK_BIAS_CTL_SHIFT8 /* always set to 0x5 */
> +#define   DPIO_REFSEL_OVERRIDE   REG_BIT(27)
> +#define   DPIO_PLL_MODESEL_MASK  REG_GENMASK(26, 24)
> +#define   DPIO_BIAS_CURRENT_CTL_MASK REG_GENMASK(22, 20) /* always 0x7 */

...and here it's 20. Is this is a fix to match spec or an accident?

Code offers no help as it's unused afaict.

> +#define   DPIO_PLL_REFCLK_SEL_MASK   REG_GENMASK(17, 16)
> +#define   DPIO_DRIVER_CTL_MASK   REG_GENMASK(15, 12) /* always 
> set to 0x8 */
> +#define   DPIO_CLK_BIAS_CTL_MASK REG_GENMASK(11, 8) /* always set to 0x5 
> */
>  
>  #define VLV_PLL_DW7(ch)  _VLV_PLL((ch), 7)
>  
> @@ -253,101 +259,110 @@
>  #define VLV_PCS_DW0_GRP(ch)  _VLV_PCS_GRP((ch), 0)
>  #define VLV_PCS01_DW0(ch)_VLV_PCS((ch), 0, 0)
>  #define VLV_PCS23_DW0(ch)_VLV_PCS((ch), 1, 0)
> -#define   DPIO_PCS_TX_LANE2_RESET(1 << 16)
> -#define   DPIO_PCS_TX_LANE1_RESET(1 << 7)
> -#define   DPIO_LEFT_TXFIFO_RST_MASTER2   (1 << 4)
> -#define   DPIO_RIGHT_TXFIFO_RST_MASTER2  (1 << 3)
> +#define   DPIO_PCS_TX_LANE2_RESETREG_BIT(16)
> +#define   DPIO_PCS_TX_LANE1_RESETREG_BIT(7)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER2   REG_BIT(4)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2  REG_BIT(3)
>  
> -#define VLV_PCS_DW1_GRP(ch)  _VLV_PCS_GRP((ch), 1)
> -#define VLV_PCS01_DW1(ch)_VLV_PCS((ch), 0, 1)
> -#define VLV_PCS23_DW1(ch)_VLV_PCS((ch), 1, 1)
> -#define   CHV_PCS_REQ_SOFTRESET_EN   (1 << 23)
> -#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN  (1 << 22)
> -#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
> -#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT   (6)
> -#define   DPIO_PCS_CLK_SOFT_RESET(1 << 5)
> +#define VLV_PCS_DW1_GRP(ch)   _VLV_PCS_GRP((ch), 1)
> +#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
> +#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1)
> +#define   CHV_PCS_REQ_SOFTRESET_EN   REG_BIT(23)
> +#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN  REG_BIT(22)
> +#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_ENREG_BIT(21)
> +#define   DPIO_PCS_CLK_DATAWIDTH_MASKREG_GENMASK(7, 6)
> +#define   DPIO_PCS_CLK_DATAWIDTH_8_10
> REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)
> +#define   DPIO_PCS_CLK_DATAWIDTH_16_20   
> REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
> +#define   DPIO_PCS_CLK_DATAWIDTH_32_40   
> REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)
> +#define   DPIO_PCS_CLK_SOFT_RESETREG_BIT(5)
>  
>  #define VLV_PCS_DW8_GRP(ch)  _VLV_PCS_GRP((ch), 8)
>  #define VLV_PCS01_DW8(ch)_VLV_PCS((ch), 0, 8)
>  #define VLV_PCS23_DW8(ch)_VLV_PCS((ch), 1, 8)
> -#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
> -#define   CHV_PCS_USEDCLKCHANNEL (1 << 21)
> +#define   DPIO_PCS_USEDCLKCHANNELREG_BIT(21)
> +#define   DPIO_PCS_USEDCLKCHANNEL_OVRRIDEREG_BIT(20)
>  
> -#define VLV_PCS_DW9_GRP(ch)  _VLV_PCS_GRP((ch), 9)
> +#define  VLV_PCS_DW9_GRP(ch) _VLV_PCS_GRP((ch), 9)

Is the TAB intentional here, and in a number of similar places below?

BR,
Jani.

>  #define VLV_PCS01_DW9(ch)_VLV_PCS((ch), 0, 9)
>  #define VLV_PCS23_DW9(ch)_VLV_PCS((ch), 1, 9)
> -#define   DPIO_PCS_TX2MARGIN_MASK(0x7 << 13)
> -#define   DPIO_PCS_TX2MARGIN_000 (0 << 13)
> -#define   DPIO_PCS_TX2MARGIN_101 (1 << 13)
> -#define   DPIO_PCS_TX1MARGIN_MASK(0x7 << 10)
> -#define   DPIO_PCS_TX1MARGIN_000 (0 << 10)
> -#define   DPIO_PCS_TX1MARGIN_101 (1 << 10)
> +#define   DPIO_PCS_TX2MARGIN_MASKREG_GENMASK(15, 13)
> +#define   DPIO_PCS_TX2MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 
> 0)
> +#define   DPIO_PCS_TX2MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 
> 1)
> +#define   DPIO_PCS_TX1MARGIN_MASKREG_GENMASK(12, 10)
> +#define   DPIO_PCS_TX1MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 
> 0)
> +#define   DPIO_PCS_TX1MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 
> 1)
>  
> -#define VLV_PCS_DW10_GRP(ch) _VLV_PCS_GRP((ch), 10)
> +#define  VLV_PCS_DW10_GRP(ch)_VLV_PCS_GRP((ch), 10)
>  #define VLV_PCS

[PATCH 1/2] drm/print: drop include debugfs.h and include where needed

[Jani Nikula]

Surprisingly many places depend on debugfs.h to be included via
drm_print.h. Fix them.

v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe

v2: Also fix ivpu and vmwgfx

Reviewed-by: Andrzej Hajda 
Acked-by: Maxime Ripard 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20240410141434.157908-1-jani.nik...@intel.com
Signed-off-by: Jani Nikula 

---

Cc: Jacek Lawrynowicz 
Cc: Stanislaw Gruszka 
Cc: Oded Gabbay 
Cc: Russell King 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Andrzej Hajda 
Cc: Neil Armstrong 
Cc: Robert Foss 
Cc: Laurent Pinchart 
Cc: Jonas Karlman 
Cc: Jernej Skrabec 
Cc: Maarten Lankhorst 
Cc: Maxime Ripard 
Cc: Thomas Zimmermann 
Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
Cc: Frank Binns 
Cc: Matt Coster 
Cc: Rob Clark 
Cc: Abhinav Kumar 
Cc: Dmitry Baryshkov 
Cc: Sean Paul 
Cc: Marijn Suijten 
Cc: Karol Herbst 
Cc: Lyude Paul 
Cc: Danilo Krummrich 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: "Pan, Xinhui" 
Cc: Alain Volmat 
Cc: Huang Rui 
Cc: Zack Rusin 
Cc: Broadcom internal kernel review list 
Cc: Lucas De Marchi 
Cc: "Thomas Hellström" 
Cc: dri-de...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Cc: intel...@lists.freedesktop.org
Cc: linux-arm-...@vger.kernel.org
Cc: freedr...@lists.freedesktop.org
Cc: nouv...@lists.freedesktop.org
Cc: amd-...@lists.freedesktop.org
---
 drivers/accel/ivpu/ivpu_debugfs.c   | 2 ++
 drivers/gpu/drm/armada/armada_debugfs.c | 1 +
 drivers/gpu/drm/bridge/ite-it6505.c | 1 +
 drivers/gpu/drm/bridge/panel.c  | 2 ++
 drivers/gpu/drm/drm_print.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_dmc.c| 1 +
 drivers/gpu/drm/imagination/pvr_fw_trace.c  | 1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 ++
 drivers/gpu/drm/nouveau/dispnv50/crc.c  | 2 ++
 drivers/gpu/drm/radeon/r100.c   | 1 +
 drivers/gpu/drm/radeon/r300.c   | 1 +
 drivers/gpu/drm/radeon/r420.c   | 1 +
 drivers/gpu/drm/radeon/r600.c   | 3 ++-
 drivers/gpu/drm/radeon/radeon_fence.c   | 1 +
 drivers/gpu/drm/radeon/radeon_gem.c | 1 +
 drivers/gpu/drm/radeon/radeon_ib.c  | 2 ++
 drivers/gpu/drm/radeon/radeon_pm.c  | 1 +
 drivers/gpu/drm/radeon/radeon_ring.c| 2 ++
 drivers/gpu/drm/radeon/radeon_ttm.c | 1 +
 drivers/gpu/drm/radeon/rs400.c  | 1 +
 drivers/gpu/drm/radeon/rv515.c  | 1 +
 drivers/gpu/drm/sti/sti_drv.c   | 1 +
 drivers/gpu/drm/ttm/ttm_device.c| 1 +
 drivers/gpu/drm/ttm/ttm_resource.c  | 3 ++-
 drivers/gpu/drm/ttm/ttm_tt.c| 5 +++--
 drivers/gpu/drm/vc4/vc4_drv.h   | 1 +
 drivers/gpu/drm/vmwgfx/vmwgfx_gem.c | 2 ++
 drivers/gpu/drm/xe/xe_debugfs.c | 1 +
 drivers/gpu/drm/xe/xe_gt_debugfs.c  | 2 ++
 drivers/gpu/drm/xe/xe_uc_debugfs.c  | 2 ++
 include/drm/drm_print.h | 2 +-
 31 files changed, 46 insertions(+), 8 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_debugfs.c 
b/drivers/accel/ivpu/ivpu_debugfs.c
index d09d29775b3f..e07e447d08d1 100644
--- a/drivers/accel/ivpu/ivpu_debugfs.c
+++ b/drivers/accel/ivpu/ivpu_debugfs.c
@@ -3,6 +3,8 @@
  * Copyright (C) 2020-2023 Intel Corporation
  */
 
+#include 
+
 #include 
 #include 
 #include 
diff --git a/drivers/gpu/drm/armada/armada_debugfs.c 
b/drivers/gpu/drm/armada/armada_debugfs.c
index 29f4b52e3c8d..a763349dd89f 100644
--- a/drivers/gpu/drm/armada/armada_debugfs.c
+++ b/drivers/gpu/drm/armada/armada_debugfs.c
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/drivers/gpu/drm/bridge/ite-it6505.c 
b/drivers/gpu/drm/bridge/ite-it6505.c
index 27334173e911..3f68c82888c2 100644
--- a/drivers/gpu/drm/bridge/ite-it6505.c
+++ b/drivers/gpu/drm/bridge/ite-it6505.c
@@ -3,6 +3,7 @@
  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  */
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index 7f41525f7a6e..32506524d9a2 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -4,6 +4,8 @@
  * Copyright (C) 2017 Broadcom
  */
 
+#include 
+
 #include 
 #include 
 #include 
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index 699b7dbffd7b..cf2efb44722c 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -23,13 +23,13 @@
  * Rob Clark 
  */
 
-#include 
-
+#include 
+#include 
 #include 
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #include 
 #include 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 3697a02b51b6..09346afd1f0e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -22,6 +22,7 @@
  *
  */
 
+#include 
 #include 
 
 #include "i915_drv.h"
diff --git a/drivers/gpu/drm/imagination/

Re: [PATCH] drm/i915/display: Fixed HDMI can't show up behind a USB-C dock station

[Jani Nikula]

On Mon, 22 Apr 2024, Jani Nikula  wrote:
> On Mon, 22 Apr 2024, gareth...@intel.com wrote:
>> From: Gareth Yu 
>>
>> Re-train the main link once HPD happens without link status
>
> Please address review before sending more versions.

And, in the general case, do not send three versions of a patch in the
span of a few hours. Give review some time.

>
> Please include a patch changelog, and indicate patch version with git
> send-email/format-patch -vN option because otherwise we have no clue.
>
> BR,
> Jani.
>
>>
>> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10902
>> Cc : Tejas Upadhyay 
>> Cc : Matt Roper 
>> Cc : Ville Syrjälä 
>> Signed-off-by: Gareth Yu 
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index e05e25cd4a94..52ab549e6d08 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -5849,8 +5849,13 @@ intel_dp_detect(struct drm_connector *connector,
>>  /* Can't disconnect eDP */
>>  if (intel_dp_is_edp(intel_dp))
>>  status = edp_detect(intel_dp);
>> -else if (intel_digital_port_connected(encoder))
>> +else if (intel_digital_port_connected(encoder)) {
>>  status = intel_dp_detect_dpcd(intel_dp);
>> +if (status == connector_status_connected && intel_dp->is_mst &&
>> +!intel_dp_mst_link_status(intel_dp))
>> +if (intel_dp_retrain_link(encoder, ctx))
>> +status = connector_status_disconnected;
>> +}
>>  else
>>  status = connector_status_disconnected;

-- 
Jani Nikula, Intel

Re: [PATCH] drm/i915/display: Fixed HDMI can't show up behind a USB-C dock station

[Jani Nikula]

On Mon, 22 Apr 2024, gareth...@intel.com wrote:
> From: Gareth Yu 
>
> Re-train the main link once HPD happens without link status

Please address review before sending more versions.

Please include a patch changelog, and indicate patch version with git
send-email/format-patch -vN option because otherwise we have no clue.

BR,
Jani.

>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10902
> Cc : Tejas Upadhyay 
> Cc : Matt Roper 
> Cc : Ville Syrjälä 
> Signed-off-by: Gareth Yu 
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e05e25cd4a94..52ab549e6d08 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5849,8 +5849,13 @@ intel_dp_detect(struct drm_connector *connector,
>   /* Can't disconnect eDP */
>   if (intel_dp_is_edp(intel_dp))
>   status = edp_detect(intel_dp);
> - else if (intel_digital_port_connected(encoder))
> + else if (intel_digital_port_connected(encoder)) {
>   status = intel_dp_detect_dpcd(intel_dp);
> + if (status == connector_status_connected && intel_dp->is_mst &&
> + !intel_dp_mst_link_status(intel_dp))
> + if (intel_dp_retrain_link(encoder, ctx))
> + status = connector_status_disconnected;
> + }
>   else
>   status = connector_status_disconnected;

-- 
Jani Nikula, Intel

✓ Fi.CI.BAT: success for drm/i915/display: Fixed the main link lost in MST (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Fixed the main link lost in MST (rev3)
URL   : https://patchwork.freedesktop.org/series/132685/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14624 -> Patchwork_132685v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/index.html

Participating hosts (31 -> 32)
--

  Additional (4): bat-kbl-2 fi-cfl-8109u bat-mtlp-8 fi-kbl-8809g 
  Missing(3): fi-glk-j4005 bat-dg2-11 fi-apl-guc 

Known issues


  Here are the changes found in Patchwork_132685v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][2] ([i915#1849])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-kbl-2/igt@fb...@info.html

  * igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u:   NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-8809g:   NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-8:  [PASS][6] -> [FAIL][7] ([i915#10378])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14624/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][8] +39 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u:   NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4083])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#6621])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg2-8:  [PASS][15] -> [ABORT][16] ([i915#9840])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14624/bat-dg2-8/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-dg2-8/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#5190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#4212]) +8 other tests skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#4213]) +1 other test skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][20] ([i915#3555] / [i915#3840] / 
[i915#9159])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v3/bat-mtlp-8/igt@kms_...@dsc-ba

Re: [PATCH 11/14] drm/i915/dpio: Rename a few CHV DPIO PHY registers

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Drop the leading underscore from the CHV PHY common lane
> register definitons. We use these directly from actual

*definitions

> code so the underscore here is misleading as usually it indicates
> an intermediate define that shouldn't be used directly.

I could go either this way, or to using the parametrized definitions and
passing the channel.

*shrug*

Reviewed-by: Jani Nikula 

>
> Signed-off-by: Ville Syrjälä 
> ---
>  .../i915/display/intel_display_power_well.c   |  8 +++
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 16 ++---
>  drivers/gpu/drm/i915/i915_reg.h   | 23 +--
>  3 files changed, 23 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index e8a6e53fd551..49114afc9a61 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1442,9 +1442,9 @@ static void chv_dpio_cmn_power_well_enable(struct 
> drm_i915_private *dev_priv,
>   vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp);
>  
>   if (id == VLV_DISP_PW_DPIO_CMN_BC) {
> - tmp = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW6_CH1);
> + tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1);
>   tmp |= DPIO_DYNPWRDOWNEN_CH1;
> - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW6_CH1, tmp);
> + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp);
>   } else {
>   /*
>* Force the non-existing CL2 off. BXT does this
> @@ -1520,9 +1520,9 @@ static void assert_chv_phy_powergate(struct 
> drm_i915_private *dev_priv, enum dpi
>   return;
>  
>   if (ch == DPIO_CH0)
> - reg = _CHV_CMN_DW0_CH0;
> + reg = CHV_CMN_DW0_CH0;
>   else
> - reg = _CHV_CMN_DW6_CH1;
> + reg = CHV_CMN_DW6_CH1;
>  
>   vlv_dpio_get(dev_priv);
>   val = vlv_dpio_read(dev_priv, phy, reg);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 791902ba729c..89a51b420075 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -883,21 +883,21 @@ void chv_phy_pre_pll_enable(struct intel_encoder 
> *encoder,
>  
>   /* program left/right clock distribution */
>   if (pipe != PIPE_B) {
> - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
> + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
>   val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
>   if (ch == DPIO_CH0)
>   val |= CHV_BUFLEFTENA1_FORCE;
>   if (ch == DPIO_CH1)
>   val |= CHV_BUFRIGHTENA1_FORCE;
> - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
> + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
>   } else {
> - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
> + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
>   val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
>   if (ch == DPIO_CH0)
>   val |= CHV_BUFLEFTENA2_FORCE;
>   if (ch == DPIO_CH1)
>   val |= CHV_BUFRIGHTENA2_FORCE;
> - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
> + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
>   }
>  
>   /* program clock channel usage */
> @@ -1036,13 +1036,13 @@ void chv_phy_post_pll_disable(struct intel_encoder 
> *encoder,
>  
>   /* disable left/right clock distribution */
>   if (pipe != PIPE_B) {
> - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
> + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
>   val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
> + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
>   } else {
> - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
> + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
>   val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
> + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
>   }
>  
>   vlv_dpio_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3804ef4697d5..b24ce3cff1a0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -459,13 +459,13 @@
>  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE  1 /* 1: coarse & 0 : 
> fine  */
>  #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV

Re: [PATCH 10/14] drm/i915/dpio: Give VLV DPIO group register a clearer name

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Include _GRP in VLV DPOP PHY group access register define

*DPIO

> names. Makes it more obvious where the accesses will land.
> Also matches the naming used by BXT already.
>
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 34 +++
>  drivers/gpu/drm/i915/i915_reg.h   | 90 +--
>  2 files changed, 62 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 4fafac534967..791902ba729c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1071,18 +1071,18 @@ void vlv_set_phy_signal_level(struct intel_encoder 
> *encoder,
>  
>   vlv_dpio_get(dev_priv);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
>uniqtranscale_reg_value);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
>  
>   if (tx3_demph)
>   vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x0003);
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x0003);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);
>  
>   vlv_dpio_put(dev_priv);
>  }
> @@ -1098,19 +1098,19 @@ void vlv_phy_pre_pll_enable(struct intel_encoder 
> *encoder,
>   /* Program Tx lane resets to default */
>   vlv_dpio_get(dev_priv);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
>DPIO_PCS_TX_LANE2_RESET |
>DPIO_PCS_TX_LANE1_RESET);
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
>DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
>DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
>(1  
>   /* Fix up inter-pair skew failure */
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x1500);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x4040);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x1500);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x4040);
>  
>   vlv_dpio_put(dev_priv);
>  }
> @@ -1136,11 +1136,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
> *encoder,
>   else
>   val &= ~(1<<21);
>   val |= 0x001000c4;
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val);
>  
>   /* Program lane clock */
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);
>  
>   vlv_dpio_put(dev_priv);
>  }
> @@ -1154,7 +1154,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
>   enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  
>   vlv_dpio_get(dev_priv);
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x);
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), 0x00e00060);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);
>   vlv_dpio_put(dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 747221f8ac72..3804ef4697d5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -254,13 +254,13 @@
>   * Per DDI channel DPIO regs
>   */
>  
> -#define _VLV_PCS_DW0_CH0 0x8200
> -#define _VLV_PCS_DW0_CH1 0x8400
> +#define _VLV_PCS_DW0_CH0_GRP 0x8200
> +#define _VLV_PCS_DW0_CH1_GRP 0x8400
>  #define   DPIO_PCS_TX_LANE2_RESET(1 << 16)
>  #define   DPIO_PCS_TX_LANE1_RESET(1 << 7)

Re: [PATCH 09/14] drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooks

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> In the encoder hooks we are dealing primarily with the encoder,
> so derive the DPIO PHY from the encoder rather than the pipe.
> Technically this doesn't matter as we can't cross connect
> pipes<->port across PHY boundaries, but it does conveny the
> intention more accurately.

I'll note that for most places converting vlv_dig_port_to_* to
vlv_encoder_to_* would be more convenient in the caller side. We have
the encoder available where they're needed, and in many places we use
enc_to_dig_port(encoder) just to be able to use vlv_dig_port_to_*.

I'd just convert them to vlv_encoder_to_*.

Regardless, this does what it says on the tin,

Reviewed-by: Jani Nikula 

Oh, one comment inline near the end.

>
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 27 ---
>  drivers/gpu/drm/i915/vlv_sideband.c   |  1 -
>  2 files changed, 11 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index e4a04c9b5b19..4fafac534967 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -719,9 +719,8 @@ void chv_set_phy_signal_level(struct intel_encoder 
> *encoder,
>  {
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>   u32 val;
>   int i;
>  
> @@ -814,9 +813,9 @@ void chv_data_lane_soft_reset(struct intel_encoder 
> *encoder,
> bool reset)
>  {
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum dpio_channel ch = 
> vlv_dig_port_to_channel(enc_to_dig_port(encoder));
> - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>   u32 val;
>  
>   val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch));
> @@ -861,7 +860,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>   enum pipe pipe = crtc->pipe;
>   unsigned int lane_mask =
>   intel_dp_unused_lane_mask(crtc_state->lane_count);
> @@ -941,9 +940,8 @@ void chv_phy_pre_encoder_enable(struct intel_encoder 
> *encoder,
>   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>   int data, i, stagger;
>   u32 val;
>  
> @@ -1030,8 +1028,8 @@ void chv_phy_post_pll_disable(struct intel_encoder 
> *encoder,
> const struct intel_crtc_state *old_crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
>   enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
> - enum dpio_phy phy = vlv_pipe_to_phy(pipe);
>   u32 val;
>  
>   vlv_dpio_get(dev_priv);
> @@ -1068,9 +1066,8 @@ void vlv_set_phy_signal_level(struct intel_encoder 
> *encoder,
>  {
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  
>   vlv_dpio_get(dev_priv);
>  
> @@ -1095,9 +1092,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder 
> *encoder,
>  {
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   enum dpio_channel ch = vl

✓ Fi.CI.BAT: success for drm/i915: VLV/CHV DPIO register cleanup

[Patchwork]

== Series Details ==

Series: drm/i915: VLV/CHV DPIO register cleanup
URL   : https://patchwork.freedesktop.org/series/132691/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14624 -> Patchwork_132691v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/index.html

Participating hosts (31 -> 30)
--

  Missing(1): fi-apl-guc 

Known issues


  Here are the changes found in Patchwork_132691v1 that come from known issues:

### IGT changes ###

 Warnings 

  * igt@i915_module_load@reload:
- fi-kbl-7567u:   [DMESG-WARN][1] ([i915#10636] / [i915#180] / 
[i915#1982] / [i915#8585]) -> [DMESG-WARN][2] ([i915#10636] / [i915#180] / 
[i915#8585])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14624/fi-kbl-7567u/igt@i915_module_l...@reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/fi-kbl-7567u/igt@i915_module_l...@reload.html

  
  [i915#10636]: https://gitlab.freedesktop.org/drm/intel/issues/10636
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#8585]: https://gitlab.freedesktop.org/drm/intel/issues/8585


Build changes
-

  * Linux: CI_DRM_14624 -> Patchwork_132691v1

  CI-20190529: 20190529
  CI_DRM_14624: ff2f70f345aaee3cbcf93a3a06ff3a5ab88e1d7a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7814: 7814
  Patchwork_132691v1: ff2f70f345aaee3cbcf93a3a06ff3a5ab88e1d7a @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/index.html

Re: [PATCH 08/14] drm/i915/dpio: s/pipe/ch/

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Stop using 'pipe' directly as the DPIO PHY channel. This
> does happen to work on VLV since it just has the one PHY
> with CH0==pipe A and CH1==pipe B. But explicitly converting
> the thing to the right enum makes the whole thing less
> confusing.
>
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 49 ---
>  1 file changed, 25 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 743cc466ee39..861f4a735251 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -512,6 +512,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state 
> *crtc_state)
>  {
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>   const struct i9xx_dpll_hw_state *hw_state = 
> &crtc_state->dpll_hw_state.i9xx;
>   int refclk = 10;
> @@ -523,7 +524,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state 
> *crtc_state)
>   return;
>  
>   vlv_dpio_get(dev_priv);
> - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch));
>   vlv_dpio_put(dev_priv);
>  
>   clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
> @@ -1867,7 +1868,7 @@ void i9xx_enable_pll(const struct intel_crtc_state 
> *crtc_state)
>  }
>  
>  static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
> -  enum dpio_phy phy)
> +  enum dpio_phy phy, enum dpio_channel ch)
>  {
>   u32 tmp;
>  
> @@ -1875,19 +1876,19 @@ static void vlv_pllb_recal_opamp(struct 
> drm_i915_private *dev_priv,
>* PLLB opamp always calibrates to max value of 0x3f, force enable it
>* and set it to a reasonable value instead.
>*/
> - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
>   tmp &= 0xff00;
>   tmp |= 0x0030;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
>  
>   tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>   tmp &= 0x00ff;
>   tmp |= 0x8c00;
>   vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
>  
> - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
>   tmp &= 0xff00;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
>  
>   tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>   tmp &= 0x00ff;
> @@ -1900,6 +1901,7 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   const struct dpll *clock = &crtc_state->dpll;
> + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>   enum pipe pipe = crtc->pipe;
>   u32 tmp, coreclk;
> @@ -1910,15 +1912,15 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>  
>   /* PLL B needs special handling */
>   if (pipe == PIPE_B)
> - vlv_pllb_recal_opamp(dev_priv, phy);
> + vlv_pllb_recal_opamp(dev_priv, phy, ch);
>  
>   /* Set up Tx target for periodic Rcomp update */
>   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
>  
>   /* Disable target IRef on PLL */
> - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(ch));
>   tmp &= 0x00ff;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(ch), tmp);
>  
>   /* Disable fast lock */
>   vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
> @@ -1937,46 +1939,46 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>* Note: don't use the DAC post divider as it seems unstable.
>*/
>   tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
>  
>   tmp |= DPIO_ENABLE_CALIBRATION;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
>  
>   /* Set HBR and RBR LPF coefficients */
>   if (crtc_state->port_clock == 162000 ||
>   intel_crtc_has_type(crtc_state, INTEL_OUTPU

✗ Fi.CI.CHECKPATCH: warning for drm/i915: VLV/CHV DPIO register cleanup

[Patchwork]

== Series Details ==

Series: drm/i915: VLV/CHV DPIO register cleanup
URL   : https://patchwork.freedesktop.org/series/132691/
State : warning

== Summary ==

Error: dim checkpatch failed
184896913edd drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read
a2f8a671697e drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/
86c9cdd31e2c drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/
539c41fc43a2 drm/i915/dpio: Fix VLV DPIO PLL register dword numbering
-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1955:
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 0x009f0003);

-:77: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#77: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1958:
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 0x00df);

total: 0 errors, 0 warnings, 2 checks, 87 lines checked
23005c4598b0 drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code
e9958d5045c7 drm/i915/dpio: Rename some variables
aeed158347d0 drm/i915/dpio: s/port/ch/
-:34: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#34: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1080:
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
 uniqtranscale_reg_value);

-:64: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#64: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1106:
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
 DPIO_PCS_TX_LANE2_RESET |

-:68: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#68: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1109:
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |

total: 0 errors, 0 warnings, 3 checks, 241 lines checked
079148d63725 drm/i915/dpio: s/pipe/ch/
-:115: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#115: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1952:
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
 0x009f0003);

-:119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#119: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1955:
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
 0x00df);

-:126: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#126: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1961:
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 0x0df4);

-:130: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#130: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1964:
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 0x0df7);

-:136: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#136: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1969:
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 0x0df7);

-:140: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#140: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1972:
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 0x0df4);

total: 0 errors, 0 warnings, 6 checks, 148 lines checked
accdf36188da drm/i915/dpio: Derive the phy from the port rather than pipe in 
encoder hooks
fa7e0411e89e drm/i915/dpio: Give VLV DPIO group register a clearer name
-:29: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#29: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1077:
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
 uniqtranscale_reg_value);

-:51: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#51: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1102:
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
 DPIO_PCS_TX_LANE2_RESET |

-:55: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#55: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1105:
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |

total: 0 errors, 0 warnings, 3 checks, 262 lines checked
d14f54c49025 drm/i915/dpio: Rename a few CHV DPIO PHY registers
9376db9e9866 drm/i915/dpio: Clean up VLV/CHV DPIO PHY register defines
655636fc383b drm/i915/dpio: Clean up the vlv/chv PHY register bits
-:608: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#608: FILE: drivers/gpu/drm/i915/i915_reg.h:409:
+#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)   
REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))

Re: [PATCH 07/14] drm/i915/dpio: s/port/ch/

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Stop calling the DPIO PHY channel "port". Just say "ch", which
> is already used in a bunch of places.
>
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 44 +++
>  drivers/gpu/drm/i915/display/intel_dpll.c | 54 +--
>  2 files changed, 49 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 6cbee88e608f..e4a04c9b5b19 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1069,23 +1069,23 @@ void vlv_set_phy_signal_level(struct intel_encoder 
> *encoder,
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  
>   vlv_dpio_get(dev_priv);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port),
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
>uniqtranscale_reg_value);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
>  
>   if (tx3_demph)
> - vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph);
> + vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x0003);
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x0003);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
>  
>   vlv_dpio_put(dev_priv);
>  }
> @@ -1096,25 +1096,25 @@ void vlv_phy_pre_pll_enable(struct intel_encoder 
> *encoder,
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  
>   /* Program Tx lane resets to default */
>   vlv_dpio_get(dev_priv);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port),
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
>DPIO_PCS_TX_LANE2_RESET |
>DPIO_PCS_TX_LANE1_RESET);
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port),
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
>DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
>DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
>(1  
>   /* Fix up inter-pair skew failure */
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(port), 0x00750f00);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(port), 0x1500);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(port), 0x4040);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x1500);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x4040);
>  
>   vlv_dpio_put(dev_priv);
>  }
> @@ -1126,7 +1126,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
> *encoder,
>   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>   enum pipe pipe = crtc->pipe;
>   enum dpio_phy phy = vlv_pipe_to_phy(pipe);
>   u32 val;
> @@ -1140,11 +1140,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
> *encoder,
>   else
>   val &= ~(1<<21);
>   val |= 0x001000c4;
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
>  
>   /* Program lane clock */
> - vlv_dpio_write

Re: [PATCH 06/14] drm/i915/dpio: Rename some variables

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Use a constent 'tmp' as the variable name for the register

*consistent

> values during rmw when we don't deal with multiple registers
> in parallel.
>
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 97 +++
>  1 file changed, 48 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 01f800b6b30e..0a738b491c40 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -514,23 +514,23 @@ void vlv_crtc_clock_get(struct intel_crtc_state 
> *crtc_state)
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>   const struct i9xx_dpll_hw_state *hw_state = 
> &crtc_state->dpll_hw_state.i9xx;
> - struct dpll clock;
> - u32 mdiv;
>   int refclk = 10;
> + struct dpll clock;
> + u32 tmp;
>  
>   /* In case of DSI, DPLL will not be used */
>   if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
>   return;
>  
>   vlv_dpio_get(dev_priv);
> - mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
>   vlv_dpio_put(dev_priv);
>  
> - clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
> - clock.m2 = mdiv & DPIO_M2DIV_MASK;
> - clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
> - clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
> - clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
> + clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
> + clock.m2 = tmp & DPIO_M2DIV_MASK;
> + clock.n = (tmp >> DPIO_N_SHIFT) & 0xf;
> + clock.p1 = (tmp >> DPIO_P1_SHIFT) & 7;
> + clock.p2 = (tmp >> DPIO_P2_SHIFT) & 0x1f;
>  
>   crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
>  }
> @@ -1869,30 +1869,30 @@ void i9xx_enable_pll(const struct intel_crtc_state 
> *crtc_state)
>  static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
>enum dpio_phy phy)
>  {
> - u32 reg_val;
> + u32 tmp;
>  
>   /*
>* PLLB opamp always calibrates to max value of 0x3f, force enable it
>* and set it to a reasonable value instead.
>*/
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> - reg_val &= 0xff00;
> - reg_val |= 0x0030;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> + tmp &= 0xff00;
> + tmp |= 0x0030;
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
>  
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> - reg_val &= 0x00ff;
> - reg_val |= 0x8c00;
> - vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> + tmp &= 0x00ff;
> + tmp |= 0x8c00;
> + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
>  
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> - reg_val &= 0xff00;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> + tmp &= 0xff00;
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
>  
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> - reg_val &= 0x00ff;
> - reg_val |= 0xb000;
> - vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> + tmp &= 0x00ff;
> + tmp |= 0xb000;
> + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
>  }
>  
>  static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
> @@ -1902,7 +1902,7 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>   const struct dpll *clock = &crtc_state->dpll;
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>   enum pipe pipe = crtc->pipe;
> - u32 mdiv, coreclk, reg_val;
> + u32 tmp, coreclk;
>  
>   vlv_dpio_get(dev_priv);
>  
> @@ -1916,15 +1916,15 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
>  
>   /* Disable target IRef on PLL */
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
> - reg_val &= 0x00ff;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
> + tmp &= 0x00ff;
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
>  
>   /* Disable fast lock */
>   vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
>  
>   /* Set idtafcrecal before PLL is enabled */
> - mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
> + tmp = (clock->m1 <

Re: [PATCH 05/14] drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Drop all the local variables for the DPLL dividers for vlv/chv
> and just consult the state directly.
>
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 62 ++-
>  1 file changed, 27 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index b95032651da0..01f800b6b30e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1899,20 +1899,13 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>  {
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct dpll *clock = &crtc_state->dpll;
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>   enum pipe pipe = crtc->pipe;
> - u32 mdiv;
> - u32 bestn, bestm1, bestm2, bestp1, bestp2;
> - u32 coreclk, reg_val;
> + u32 mdiv, coreclk, reg_val;
>  
>   vlv_dpio_get(dev_priv);
>  
> - bestn = crtc_state->dpll.n;
> - bestm1 = crtc_state->dpll.m1;
> - bestm2 = crtc_state->dpll.m2;
> - bestp1 = crtc_state->dpll.p1;
> - bestp2 = crtc_state->dpll.p2;
> -
>   /* See eDP HDMI DPIO driver vbios notes doc */
>  
>   /* PLL B needs special handling */
> @@ -1931,10 +1924,12 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>   vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
>  
>   /* Set idtafcrecal before PLL is enabled */
> - mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
> - mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
> - mdiv |= ((bestn << DPIO_N_SHIFT));
> - mdiv |= (1 << DPIO_K_SHIFT);
> + mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
> + (clock->m2 & DPIO_M2DIV_MASK) |
> + (clock->p1 << DPIO_P1_SHIFT) |
> + (clock->p2 << DPIO_P2_SHIFT) |
> + (clock->n << DPIO_N_SHIFT) |
> + (1 << DPIO_K_SHIFT);
>  
>   /*
>* Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
> @@ -2030,19 +2025,14 @@ static void chv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>  {
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct dpll *clock = &crtc_state->dpll;
>   enum pipe pipe = crtc->pipe;
>   enum dpio_channel port = vlv_pipe_to_channel(pipe);
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> - u32 loopfilter, tribuf_calcntr;
> - u32 bestm2, bestp1, bestp2, bestm2_frac;
> - u32 dpio_val;
> - int vco;
> + u32 dpio_val, loopfilter, tribuf_calcntr;
> + u32 m2_frac;
>  
> - bestm2_frac = crtc_state->dpll.m2 & 0x3f;
> - bestm2 = crtc_state->dpll.m2 >> 22;
> - bestp1 = crtc_state->dpll.p1;
> - bestp2 = crtc_state->dpll.p2;
> - vco = crtc_state->dpll.vco;
> + m2_frac = clock->m2 & 0x3f;
>   dpio_val = 0;
>   loopfilter = 0;
>  
> @@ -2050,27 +2040,29 @@ static void chv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>  
>   /* p1 and p2 divider */
>   vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port),
> - 5 << DPIO_CHV_S1_DIV_SHIFT |
> - bestp1 << DPIO_CHV_P1_DIV_SHIFT |
> - bestp2 << DPIO_CHV_P2_DIV_SHIFT |
> - 1 << DPIO_CHV_K_DIV_SHIFT);
> +5 << DPIO_CHV_S1_DIV_SHIFT |
> +clock->p1 << DPIO_CHV_P1_DIV_SHIFT |
> +clock->p2 << DPIO_CHV_P2_DIV_SHIFT |
> +1 << DPIO_CHV_K_DIV_SHIFT);
>  
>   /* Feedback post-divider - m2 */
> - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), bestm2);
> + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port),
> +clock->m2 >> 22);
>  
>   /* Feedback refclk divider - n and m1 */
>   vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port),
> - DPIO_CHV_M1_DIV_BY_2 |
> - 1 << DPIO_CHV_N_DIV_SHIFT);
> +DPIO_CHV_M1_DIV_BY_2 |
> +1 << DPIO_CHV_N_DIV_SHIFT);
>  
>   /* M2 fraction division */
> - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), bestm2_frac);
> + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port),
> +m2_frac);
>  
>   /* M2 fraction division enable */
>   dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
>   dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
>   dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
> - if (bestm2_frac)
> + if (m2_frac)
>   dpio_val |= DPIO_CHV_FRAC_DIV_EN;
>   vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpi

Re: [PATCH 04/14] drm/i915/dpio: Fix VLV DPIO PLL register dword numbering

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> The spreadsheet defines the PLL register block as having
> the dwords in the following order:
>
> block   dwordsoffsets
> PLL10x0-0x7   0x00-0x1f
> PLL20x0-0x7   0x20-0x2f
> PLL1ext 0x10-0x1f 0x40-0x5f
> PLL2ext 0x10-0x1f 0x60-0x7f
>
> So dword indexes 0x8-0xf don't even exist. Renumber
> our register defines to match.
>
> Note that the spreadsheet used hex numbering whereas our
> defiens are in decimal. Perhaps we should change that?
>
> Signed-off-by: Ville Syrjälä 

I am, again, taking your word for it, instead of going on a wild goose
chase trying to find all the specs. The patch matches the commit
message,

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 18 -
>  drivers/gpu/drm/i915/i915_reg.h   | 24 +++
>  2 files changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 7e8aca3c87ec..b95032651da0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1875,19 +1875,19 @@ static void vlv_pllb_recal_opamp(struct 
> drm_i915_private *dev_priv,
>* PLLB opamp always calibrates to max value of 0x3f, force enable it
>* and set it to a reasonable value instead.
>*/
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
> + reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
>   reg_val &= 0xff00;
>   reg_val |= 0x0030;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
>  
>   reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>   reg_val &= 0x00ff;
>   reg_val |= 0x8c00;
>   vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
>  
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
> + reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
>   reg_val &= 0xff00;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
>  
>   reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>   reg_val &= 0x00ff;
> @@ -1923,9 +1923,9 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
>  
>   /* Disable target IRef on PLL */
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe));
> + reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
>   reg_val &= 0x00ff;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW8(pipe), reg_val);
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
>  
>   /* Disable fast lock */
>   vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
> @@ -1951,10 +1951,10 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>   if (crtc_state->port_clock == 162000 ||
>   intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
>   intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
>0x009f0003);
>   else
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
>0x00df);
>  
>   if (intel_crtc_has_dp_encoder(crtc_state)) {
> @@ -1981,7 +1981,7 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>   coreclk |= 0x0100;
>   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW11(pipe), 0x87871000);
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(pipe), 0x87871000);
>  
>   vlv_dpio_put(dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8f3c83d2ab8d..747221f8ac72 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -229,21 +229,21 @@
>  #define _VLV_PLL_DW7_CH1 0x803c
>  #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
>  
> -#define _VLV_PLL_DW8_CH0 0x8040
> -#define _VLV_PLL_DW8_CH1 0x8060
> -#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
> +#define _VLV_PLL_DW16_CH00x8040
> +#define _VLV_PLL_DW16_CH10x8060
> +#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1)
>  
> -#define _VLV_PLL_DW9_CH0 0x8044
> -#define _VLV_PLL_DW9_CH1 0x8064
> -#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
> +#define _VLV_PLL_DW17_CH00x8044
> +#define _VLV_PLL_DW17_CH10x8064
> +#define VLV_PLL_

✓ Fi.CI.IGT: success for Enable display support for Battlemage (rev2)

[Patchwork]

== Series Details ==

Series: Enable display support for Battlemage (rev2)
URL   : https://patchwork.freedesktop.org/series/132429/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14621_full -> Patchwork_132429v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_132429v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@object-reloc-keep-cache:
- shard-dg1:  NOTRUN -> [SKIP][1] ([i915#8411])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg1-16/igt@api_intel...@object-reloc-keep-cache.html

  * igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1:  NOTRUN -> [SKIP][2] ([i915#8414]) +9 other tests skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg1-18/igt@drm_fdinfo@busy-check-...@bcs0.html

  * igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2:  NOTRUN -> [SKIP][3] ([i915#8414]) +13 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg2-4/igt@drm_fdinfo@most-busy-check-...@bcs0.html

  * igt@drm_fdinfo@virtual-idle:
- shard-rkl:  [PASS][4] -> [FAIL][5] ([i915#7742])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14621/shard-rkl-5/igt@drm_fdi...@virtual-idle.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-rkl-3/igt@drm_fdi...@virtual-idle.html

  * igt@gem_bad_reloc@negative-reloc-lut:
- shard-rkl:  NOTRUN -> [SKIP][6] ([i915#3281]) +6 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-rkl-3/igt@gem_bad_re...@negative-reloc-lut.html

  * igt@gem_basic@multigpu-create-close:
- shard-rkl:  NOTRUN -> [SKIP][7] ([i915#7697])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-rkl-2/igt@gem_ba...@multigpu-create-close.html

  * igt@gem_ccs@block-copy-compressed:
- shard-dg1:  NOTRUN -> [SKIP][8] ([i915#3555] / [i915#9323])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg1-16/igt@gem_...@block-copy-compressed.html

  * igt@gem_ccs@suspend-resume:
- shard-rkl:  NOTRUN -> [SKIP][9] ([i915#9323])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-rkl-5/igt@gem_...@suspend-resume.html

  * igt@gem_close_race@multigpu-basic-process:
- shard-dg1:  NOTRUN -> [SKIP][10] ([i915#7697])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg1-18/igt@gem_close_r...@multigpu-basic-process.html

  * igt@gem_create@create-ext-cpu-access-big:
- shard-rkl:  NOTRUN -> [SKIP][11] ([i915#6335])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-rkl-2/igt@gem_cre...@create-ext-cpu-access-big.html

  * igt@gem_create@create-ext-set-pat:
- shard-dg2:  NOTRUN -> [SKIP][12] ([i915#8562])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg2-4/igt@gem_cre...@create-ext-set-pat.html

  * igt@gem_ctx_persistence@heartbeat-close:
- shard-dg1:  NOTRUN -> [SKIP][13] ([i915#8555])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg1-18/igt@gem_ctx_persiste...@heartbeat-close.html

  * igt@gem_ctx_sseu@engines:
- shard-rkl:  NOTRUN -> [SKIP][14] ([i915#280])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-rkl-3/igt@gem_ctx_s...@engines.html

  * igt@gem_ctx_sseu@mmap-args:
- shard-dg2:  NOTRUN -> [SKIP][15] ([i915#280])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg2-10/igt@gem_ctx_s...@mmap-args.html

  * igt@gem_eio@reset-stress:
- shard-dg1:  NOTRUN -> [FAIL][16] ([i915#5784])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg1-18/igt@gem_...@reset-stress.html

  * igt@gem_exec_balancer@bonded-pair:
- shard-dg1:  NOTRUN -> [SKIP][17] ([i915#4771])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg1-15/igt@gem_exec_balan...@bonded-pair.html

  * igt@gem_exec_balancer@bonded-sync:
- shard-dg2:  NOTRUN -> [SKIP][18] ([i915#4771])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-dg2-11/igt@gem_exec_balan...@bonded-sync.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-rkl:  NOTRUN -> [SKIP][19] ([i915#4525])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/shard-rkl-5/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_capture@many-4k-incremental:
- shard-glk:  NOTRUN -> [FAIL][20] ([i915#9606]) +1 other test fail
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_

[PATCH] drm/i915/display: Fixed HDMI can't show up behind a USB-C dock station

[gareth . yu]

From: Gareth Yu 

Re-train the main link once HPD happens without link status

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10902
Cc : Tejas Upadhyay 
Cc : Matt Roper 
Cc : Ville Syrjälä 
Signed-off-by: Gareth Yu 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index e05e25cd4a94..52ab549e6d08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5849,8 +5849,13 @@ intel_dp_detect(struct drm_connector *connector,
/* Can't disconnect eDP */
if (intel_dp_is_edp(intel_dp))
status = edp_detect(intel_dp);
-   else if (intel_digital_port_connected(encoder))
+   else if (intel_digital_port_connected(encoder)) {
status = intel_dp_detect_dpcd(intel_dp);
+   if (status == connector_status_connected && intel_dp->is_mst &&
+   !intel_dp_mst_link_status(intel_dp))
+   if (intel_dp_retrain_link(encoder, ctx))
+   status = connector_status_disconnected;
+   }
else
status = connector_status_disconnected;
 
-- 
2.25.1

Re: [PATCH 03/14] drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> VLV_PLL_DW9_BCAST is actually VLV_PCS_DW17_BCAST. The address
> does kinda look like it goes to the PLL block on a first glance,
> but broadcast is special and doesn't even exist for the PLL
> (only PCS and TX have it).
>
> The fact that we use a broadcast write here is a bit sketchy
> IMO since we're now blasting the register to all PCS splines
> across the whole PHY. So the PCS registers in the other channel
> (ie. other pipe/port) will also be written. But I guess the
> fact that we always write the same value should make this a nop
> even if the other channel is already enabled (assuming the VBIOS/GOP
> didn't screw up and use some other value...).
>
> Signed-off-by: Ville Syrjälä 

I'll take your word for it. The patch does what the commit message says,

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h   | 3 ++-
>  2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 6693beafe9c0..7e8aca3c87ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1920,7 +1920,7 @@ static void vlv_prepare_pll(const struct 
> intel_crtc_state *crtc_state)
>   vlv_pllb_recal_opamp(dev_priv, phy);
>  
>   /* Set up Tx target for periodic Rcomp update */
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9_BCAST, 0x010f);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
>  
>   /* Disable target IRef on PLL */
>   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a2fadcbe0932..8f3c83d2ab8d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -233,7 +233,6 @@
>  #define _VLV_PLL_DW8_CH1 0x8060
>  #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
>  
> -#define VLV_PLL_DW9_BCAST0xc044
>  #define _VLV_PLL_DW9_CH0 0x8044
>  #define _VLV_PLL_DW9_CH1 0x8064
>  #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
> @@ -370,6 +369,8 @@
>  #define _VLV_PCS_DW14_CH10x8438
>  #define  VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
>  
> +#define VLV_PCS_DW17_BCAST   0xc044
> +
>  #define _VLV_PCS_DW23_CH00x825c
>  #define _VLV_PCS_DW23_CH10x845c
>  #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)

-- 
Jani Nikula, Intel

Re: [PATCH 02/14] drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Our VLV_REF_DW13 is actually VLV_REF_DW11. Rename it.

I'll take your word for it. The patch does what the commit message says,

Reviewed-by: Jani Nikula 

>
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 8 
>  drivers/gpu/drm/i915/i915_reg.h   | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 49274d632716..6693beafe9c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1880,19 +1880,19 @@ static void vlv_pllb_recal_opamp(struct 
> drm_i915_private *dev_priv,
>   reg_val |= 0x0030;
>   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
>  
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
> + reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>   reg_val &= 0x00ff;
>   reg_val |= 0x8c00;
> - vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
> + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
>  
>   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
>   reg_val &= 0xff00;
>   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
>  
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
> + reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>   reg_val &= 0x00ff;
>   reg_val |= 0xb000;
> - vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
> + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
>  }
>  
>  static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8eb6c2bf4557..a2fadcbe0932 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -246,8 +246,8 @@
>  #define _VLV_PLL_DW11_CH10x806c
>  #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
>  
> -/* Spec for ref block start counts at DW10 */
> -#define VLV_REF_DW13 0x80ac
> +/* Spec for ref block start counts at DW8 */
> +#define VLV_REF_DW11 0x80ac
>  
>  #define VLV_CMN_DW0  0x8100

-- 
Jani Nikula, Intel

Re: [PATCH 01/14] drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> We don't use the result of the VLV_PCS01_DW8 read at all,
> so don't read.

Mmmh, maybe the intention was to be a rmw? Since this appears to have
worked, okay.

This part becomes a bit pointless:

else
val &= ~(1<<21);

but it was already there and you seem to clean this up in patch 13 so
*shrug*.

Reviewed-by: Jani Nikula 

>
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index c72b76b61dff..6cbee88e608f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1134,7 +1134,6 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
> *encoder,
>   vlv_dpio_get(dev_priv);
>  
>   /* Enable clock channels for this port */
> - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(port));
>   val = 0;
>   if (pipe)
>   val |= (1<<21);

-- 
Jani Nikula, Intel

✗ Fi.CI.IGT: failure for Panel replay selective update support (rev8)

[Patchwork]

== Series Details ==

Series: Panel replay selective update support (rev8)
URL   : https://patchwork.freedesktop.org/series/128193/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14621_full -> Patchwork_128193v8_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_128193v8_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_128193v8_full, please notify your bug team 
("i915-ci-in...@lists.freedesktop.org") to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/index.html

Participating hosts (9 -> 9)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_128193v8_full:

### IGT changes ###

 Possible regressions 

  * igt@drm_read@short-buffer-wakeup:
- shard-glk:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-glk2/igt@drm_r...@short-buffer-wakeup.html
- shard-dg2:  [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14621/shard-dg2-7/igt@drm_r...@short-buffer-wakeup.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-dg2-8/igt@drm_r...@short-buffer-wakeup.html

  
Known issues


  Here are the changes found in Patchwork_128193v8_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@object-reloc-keep-cache:
- shard-dg1:  NOTRUN -> [SKIP][4] ([i915#8411])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-dg1-17/igt@api_intel...@object-reloc-keep-cache.html

  * igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1:  NOTRUN -> [SKIP][5] ([i915#8414]) +9 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-dg1-17/igt@drm_fdinfo@busy-check-...@bcs0.html

  * igt@drm_fdinfo@busy-check-all@vecs1:
- shard-dg2:  NOTRUN -> [SKIP][6] ([i915#8414]) +6 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-dg2-8/igt@drm_fdinfo@busy-check-...@vecs1.html

  * igt@drm_fdinfo@virtual-idle:
- shard-rkl:  [PASS][7] -> [FAIL][8] ([i915#7742])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14621/shard-rkl-5/igt@drm_fdi...@virtual-idle.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-rkl-1/igt@drm_fdi...@virtual-idle.html

  * igt@gem_bad_reloc@negative-reloc-lut:
- shard-rkl:  NOTRUN -> [SKIP][9] ([i915#3281]) +8 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-rkl-3/igt@gem_bad_re...@negative-reloc-lut.html

  * igt@gem_basic@multigpu-create-close:
- shard-rkl:  NOTRUN -> [SKIP][10] ([i915#7697])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-rkl-5/igt@gem_ba...@multigpu-create-close.html

  * igt@gem_ccs@block-copy-compressed:
- shard-dg1:  NOTRUN -> [SKIP][11] ([i915#3555] / [i915#9323])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-dg1-17/igt@gem_...@block-copy-compressed.html

  * igt@gem_ccs@suspend-resume:
- shard-rkl:  NOTRUN -> [SKIP][12] ([i915#9323])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-rkl-6/igt@gem_...@suspend-resume.html

  * igt@gem_create@create-ext-cpu-access-big:
- shard-rkl:  NOTRUN -> [SKIP][13] ([i915#6335])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-rkl-5/igt@gem_cre...@create-ext-cpu-access-big.html

  * igt@gem_ctx_freq@sysfs@gt0:
- shard-dg2:  [PASS][14] -> [FAIL][15] ([i915#9561])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14621/shard-dg2-2/igt@gem_ctx_freq@sy...@gt0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-dg2-6/igt@gem_ctx_freq@sy...@gt0.html

  * igt@gem_ctx_sseu@engines:
- shard-rkl:  NOTRUN -> [SKIP][16] ([i915#280])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-rkl-3/igt@gem_ctx_s...@engines.html

  * igt@gem_ctx_sseu@mmap-args:
- shard-dg2:  NOTRUN -> [SKIP][17] ([i915#280])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-dg2-8/igt@gem_ctx_s...@mmap-args.html

  * igt@gem_eio@kms:
- shard-tglu: [PASS][18] -> [INCOMPLETE][19] ([i915#10513])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14621/shard-tglu-7/igt@gem_...@kms.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v8/shard-tglu-4/igt@gem_...@kms.html

  * igt@gem_eio@reset-stress:
- shard-dg1:

[PATCH 14/14] drm/i915/dpio: Extract vlv_dpio_phy_regs.h

[Ville Syrjala]

From: Ville Syrjälä 

Pull the VLV/CHV DPIO PHY sideband registers to their own file.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c  |   1 +
 .../i915/display/intel_display_power_well.c   |   1 +
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |   1 +
 drivers/gpu/drm/i915/display/intel_dpll.c |   1 +
 .../gpu/drm/i915/display/vlv_dpio_phy_regs.h  | 309 ++
 drivers/gpu/drm/i915/i915_reg.h   | 298 -
 6 files changed, 313 insertions(+), 298 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 96ed1490fec7..59f989207c74 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -120,6 +120,7 @@
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 #include "skl_watermark.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_dsi.h"
 #include "vlv_dsi_pll.h"
 #include "vlv_dsi_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e4ba6efc90e6..83f616097a29 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -27,6 +27,7 @@
 #include "intel_tc.h"
 #include "intel_vga.h"
 #include "skl_watermark.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_sideband.h"
 #include "vlv_sideband_reg.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 11875d18a8fc..d20e4e9cf7f7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -30,6 +30,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dpio_phy.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_sideband.h"
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index c2ee95993a96..a981f45facb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -20,6 +20,7 @@
 #include "intel_panel.h"
 #include "intel_pps.h"
 #include "intel_snps_phy.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_sideband.h"
 
 struct intel_dpll_funcs {
diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h 
b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
new file mode 100644
index ..477506f0b2cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __VLV_DPIO_PHY_REGS_H__
+#define __VLV_DPIO_PHY_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
+#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
+#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
+#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
+#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
+#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + 
(dw) * 4)
+#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
+#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 
4)
+#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
+
+/*
+ * Per pipe/PLL DPIO regs
+ */
+#define VLV_PLL_DW3(ch)_VLV_PLL((ch), 3)
+#define   DPIO_S1_DIV_MASK REG_GENMASK(30, 28)
+#define   DPIO_S1_DIV(s1)  REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
+#define   DPIO_S1_DIV_DAC  0 /* 10, DAC 25-225M rate */
+#define   DPIO_S1_DIV_HDMIDP   1 /* 5, DAC 225-400M rate */
+#define   DPIO_S1_DIV_LVDS12 /* 14 */
+#define   DPIO_S1_DIV_LVDS23 /* 7 */
+#define   DPIO_K_DIV_MASK  REG_GENMASK(27, 24)
+#define   DPIO_K_DIV(k)REG_FIELD_PREP(DPIO_K_DIV_MASK, 
(k))
+#define   DPIO_P1_DIV_MASK REG_GENMASK(23, 21)
+#define   DPIO_P1_DIV(p1)  REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
+#define   DPIO_P2_DIV_MASK REG_GENMASK(20, 16)
+#define   DPIO_P2_DIV(p2)  REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
+#define   DPIO_N_DIV_MASK  REG_GENMASK(15, 12)
+#define   DPIO_N_DIV(n)REG_FIELD_PREP(DPIO_N_DIV_MASK, 
(n))
+#define   DPIO_ENABLE_CALIBRATION  REG_BIT(11)
+#define   DPIO_M1_DIV_MASK REG_GENMASK(10, 8)
+#define   DPIO_M1_DIV(m1)  REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1))
+#define   DPIO_M2_DIV_MASK REG_GENMASK(7, 0)
+#define   DPIO_M2_DIV(m2)  REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2))
+
+#define VLV_PLL_DW5(ch)_VLV_PLL((ch), 5)
+#define   DPI

[PATCH 13/14] drm/i915/dpio: Clean up the vlv/chv PHY register bits

[Ville Syrjala]

From: Ville Syrjälä 

Use REG_BIT() & co. for the vlv/chv DPIO PHY registers.

Signed-off-by: Ville Syrjälä 
---
 .../i915/display/intel_display_power_well.c   |   7 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  59 ++--
 drivers/gpu/drm/i915/display/intel_dpll.c |  85 +++--
 drivers/gpu/drm/i915/i915_reg.h   | 294 ++
 4 files changed, 236 insertions(+), 209 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 49114afc9a61..e4ba6efc90e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1553,10 +1553,11 @@ static void assert_chv_phy_powergate(struct 
drm_i915_private *dev_priv, enum dpi
}
 
if (ch == DPIO_CH0)
-   actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
+   actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 |
+  DPIO_ALLDL_POWERDOWN_CH0, val);
else
-   actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
-   actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
+   actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 |
+  DPIO_ALLDL_POWERDOWN_CH1, val);
 
drm_WARN(&dev_priv->drm, actual != expected,
 "Unexpected DPIO lane power down: all %d, any %d. Expected: 
all %d, any %d. (0x%x = 0x%08x)\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index fa665d353df9..11875d18a8fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -757,7 +757,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
for (i = 0; i < crtc_state->lane_count; i++) {
val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i));
val &= ~DPIO_SWING_DEEMPH9P5_MASK;
-   val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
+   val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value);
vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val);
}
 
@@ -766,15 +766,15 @@ void chv_set_phy_signal_level(struct intel_encoder 
*encoder,
val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i));
 
val &= ~DPIO_SWING_MARGIN000_MASK;
-   val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
+   val |= DPIO_SWING_MARGIN000(margin_reg_value);
 
/*
 * Supposedly this value shouldn't matter when unique transition
 * scale is disabled, but in fact it does matter. Let's just
 * always program the same value and hope it's OK.
 */
-   val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
-   val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
+   val &= ~DPIO_UNIQ_TRANS_SCALE_MASK;
+   val |= DPIO_UNIQ_TRANS_SCALE(0x9a);
 
vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val);
}
@@ -902,20 +902,20 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 
/* program clock channel usage */
val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch));
-   val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-   if (pipe != PIPE_B)
-   val &= ~CHV_PCS_USEDCLKCHANNEL;
+   val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;
+   if (pipe == PIPE_B)
+   val |= DPIO_PCS_USEDCLKCHANNEL;
else
-   val |= CHV_PCS_USEDCLKCHANNEL;
+   val &= ~DPIO_PCS_USEDCLKCHANNEL;
vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val);
 
if (crtc_state->lane_count > 2) {
val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch));
-   val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-   if (pipe != PIPE_B)
-   val &= ~CHV_PCS_USEDCLKCHANNEL;
+   val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;
+   if (pipe == PIPE_B)
+   val |= DPIO_PCS_USEDCLKCHANNEL;
else
-   val |= CHV_PCS_USEDCLKCHANNEL;
+   val &= ~DPIO_PCS_USEDCLKCHANNEL;
vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val);
}
 
@@ -925,10 +925,10 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 * pick the CL based on the port.
 */
val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch));
-   if (pipe != PIPE_B)
-   val &= ~CHV_CMN_USEDCLKCHANNEL;
-   else
+   if (pipe == PIPE_B)
val |= CHV_CMN_USEDCLKCHANNEL;
+   else
+   val &= ~CHV_CMN_USEDCLKCHANNEL;
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val);
 
vlv_dpio_put(dev_priv);
@@ -962,11 +962,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder 
*encoder,
for (i = 0;

[PATCH 12/14] drm/i915/dpio: Clean up VLV/CHV DPIO PHY register defines

[Ville Syrjala]

From: Ville Syrjälä 

The DPIO PHY registers follow clear numbering rules. Express
those in a few macros to get rid of the hand calculated
final offsets.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |   2 +-
 drivers/gpu/drm/i915/i915_reg.h   | 271 +++---
 2 files changed, 99 insertions(+), 174 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 89a51b420075..fa665d353df9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1078,7 +1078,7 @@ void vlv_set_phy_signal_level(struct intel_encoder 
*encoder,
vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
 
if (tx3_demph)
-   vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph);
 
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x0003);
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b24ce3cff1a0..6d16f9944eff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -195,10 +195,22 @@
 #define  DPIO_SFR_BYPASS   (1 << 1)
 #define  DPIO_CMNRST   (1 << 0)
 
+#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
+#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
+#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
+#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
+#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
+#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + 
(dw) * 4)
+#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
+#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 
4)
+#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
+
 /*
  * Per pipe/PLL DPIO regs
  */
-#define _VLV_PLL_DW3_CH0   0x800c
+#define VLV_PLL_DW3(ch)_VLV_PLL((ch), 3)
 #define   DPIO_POST_DIV_SHIFT  (28) /* 3 bits */
 #define   DPIO_POST_DIV_DAC0
 #define   DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
@@ -211,10 +223,8 @@
 #define   DPIO_ENABLE_CALIBRATION  (1 << 11)
 #define   DPIO_M1DIV_SHIFT (8) /* 3 bits */
 #define   DPIO_M2DIV_MASK  0xff
-#define _VLV_PLL_DW3_CH1   0x802c
-#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
 
-#define _VLV_PLL_DW5_CH0   0x8014
+#define VLV_PLL_DW5(ch)_VLV_PLL((ch), 5)
 #define   DPIO_REFSEL_OVERRIDE 27
 #define   DPIO_PLL_MODESEL_SHIFT   24 /* 3 bits */
 #define   DPIO_BIAS_CURRENT_CTL_SHIFT  21 /* 3 bits, always 0x7 */
@@ -222,101 +232,60 @@
 #define   DPIO_PLL_REFCLK_SEL_MASK 3
 #define   DPIO_DRIVER_CTL_SHIFT12 /* always set to 0x8 */
 #define   DPIO_CLK_BIAS_CTL_SHIFT  8 /* always set to 0x5 */
-#define _VLV_PLL_DW5_CH1   0x8034
-#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
 
-#define _VLV_PLL_DW7_CH0   0x801c
-#define _VLV_PLL_DW7_CH1   0x803c
-#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
+#define VLV_PLL_DW7(ch)_VLV_PLL((ch), 7)
 
-#define _VLV_PLL_DW16_CH0  0x8040
-#define _VLV_PLL_DW16_CH1  0x8060
-#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1)
+#define VLV_PLL_DW16(ch)   _VLV_PLL((ch), 16)
 
-#define _VLV_PLL_DW17_CH0  0x8044
-#define _VLV_PLL_DW17_CH1  0x8064
-#define VLV_PLL_DW17(ch) _PIPE(ch, _VLV_PLL_DW17_CH0, _VLV_PLL_DW17_CH1)
+#define VLV_PLL_DW17(ch)   _VLV_PLL((ch), 17)
 
-#define _VLV_PLL_DW18_CH0  0x8048
-#define _VLV_PLL_DW18_CH1  0x8068
-#define VLV_PLL_DW18(ch) _PIPE(ch, _VLV_PLL_DW18_CH0, _VLV_PLL_DW18_CH1)
+#define VLV_PLL_DW18(ch)   _VLV_PLL((ch), 18)
 
-#define _VLV_PLL_DW19_CH0  0x804c
-#define _VLV_PLL_DW19_CH1  0x806c
-#define VLV_PLL_DW19(ch) _PIPE(ch, _VLV_PLL_DW19_CH0, _VLV_PLL_DW19_CH1)
+#define VLV_PLL_DW19(ch)   _VLV_PLL((ch), 19)
 
-/* Spec for ref block start counts at DW8 */
-#define VLV_REF_DW11   0x80ac
+#define VLV_REF_DW11   _VLV_REF(11)
 
-#define VLV_CMN_DW00x8100
+#define VLV_CMN_DW0_VLV_CMN(0)
 
 /*
  * Per DDI channel DPIO regs
  */
-
-#define _VLV_PCS_DW0_CH0_GRP   0x8200
-#define _VLV_PCS_DW0_CH1_GRP   0x8400
+#define VLV_PCS_DW0_GRP(ch)_VLV_PCS_GRP((ch), 0)
+#define VLV_PCS01_DW0(ch)  _VLV_PCS((ch), 0, 0)
+

[PATCH 11/14] drm/i915/dpio: Rename a few CHV DPIO PHY registers

[Ville Syrjala]

From: Ville Syrjälä 

Drop the leading underscore from the CHV PHY common lane
register definitons. We use these directly from actual
code so the underscore here is misleading as usually it indicates
an intermediate define that shouldn't be used directly.

Signed-off-by: Ville Syrjälä 
---
 .../i915/display/intel_display_power_well.c   |  8 +++
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 16 ++---
 drivers/gpu/drm/i915/i915_reg.h   | 23 +--
 3 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e8a6e53fd551..49114afc9a61 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1442,9 +1442,9 @@ static void chv_dpio_cmn_power_well_enable(struct 
drm_i915_private *dev_priv,
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp);
 
if (id == VLV_DISP_PW_DPIO_CMN_BC) {
-   tmp = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW6_CH1);
+   tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1);
tmp |= DPIO_DYNPWRDOWNEN_CH1;
-   vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW6_CH1, tmp);
+   vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp);
} else {
/*
 * Force the non-existing CL2 off. BXT does this
@@ -1520,9 +1520,9 @@ static void assert_chv_phy_powergate(struct 
drm_i915_private *dev_priv, enum dpi
return;
 
if (ch == DPIO_CH0)
-   reg = _CHV_CMN_DW0_CH0;
+   reg = CHV_CMN_DW0_CH0;
else
-   reg = _CHV_CMN_DW6_CH1;
+   reg = CHV_CMN_DW6_CH1;
 
vlv_dpio_get(dev_priv);
val = vlv_dpio_read(dev_priv, phy, reg);
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 791902ba729c..89a51b420075 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -883,21 +883,21 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 
/* program left/right clock distribution */
if (pipe != PIPE_B) {
-   val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
+   val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
if (ch == DPIO_CH0)
val |= CHV_BUFLEFTENA1_FORCE;
if (ch == DPIO_CH1)
val |= CHV_BUFRIGHTENA1_FORCE;
-   vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
+   vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
} else {
-   val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
+   val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
if (ch == DPIO_CH0)
val |= CHV_BUFLEFTENA2_FORCE;
if (ch == DPIO_CH1)
val |= CHV_BUFRIGHTENA2_FORCE;
-   vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
+   vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
}
 
/* program clock channel usage */
@@ -1036,13 +1036,13 @@ void chv_phy_post_pll_disable(struct intel_encoder 
*encoder,
 
/* disable left/right clock distribution */
if (pipe != PIPE_B) {
-   val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
+   val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-   vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
+   vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
} else {
-   val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
+   val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-   vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
+   vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
}
 
vlv_dpio_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3804ef4697d5..b24ce3cff1a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -459,13 +459,13 @@
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse & 0 : 
fine  */
 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
 
-#define _CHV_CMN_DW0_CH0   0x8100
+#define CHV_CMN_DW0_CH00x8100
 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0   19
 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0   18
 #define   DPIO_ALLDL_POWERDOWN (1 << 1)
 #d

[PATCH 09/14] drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooks

[Ville Syrjala]

From: Ville Syrjälä 

In the encoder hooks we are dealing primarily with the encoder,
so derive the DPIO PHY from the encoder rather than the pipe.
Technically this doesn't matter as we can't cross connect
pipes<->port across PHY boundaries, but it does conveny the
intention more accurately.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 27 ---
 drivers/gpu/drm/i915/vlv_sideband.c   |  1 -
 2 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index e4a04c9b5b19..4fafac534967 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -719,9 +719,8 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+   enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
u32 val;
int i;
 
@@ -814,9 +813,9 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
  bool reset)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   enum dpio_channel ch = 
vlv_dig_port_to_channel(enc_to_dig_port(encoder));
-   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
+   enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
u32 val;
 
val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch));
@@ -861,7 +860,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+   enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
enum pipe pipe = crtc->pipe;
unsigned int lane_mask =
intel_dp_unused_lane_mask(crtc_state->lane_count);
@@ -941,9 +940,8 @@ void chv_phy_pre_encoder_enable(struct intel_encoder 
*encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+   enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
int data, i, stagger;
u32 val;
 
@@ -1030,8 +1028,8 @@ void chv_phy_post_pll_disable(struct intel_encoder 
*encoder,
  const struct intel_crtc_state *old_crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
-   enum dpio_phy phy = vlv_pipe_to_phy(pipe);
u32 val;
 
vlv_dpio_get(dev_priv);
@@ -1068,9 +1066,8 @@ void vlv_set_phy_signal_level(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+   enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 
vlv_dpio_get(dev_priv);
 
@@ -1095,9 +1092,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
 {
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+   enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 
/* Program Tx lane resets to default */
vlv_dpio_get(dev_priv);
@@ -1127,8 +1123,8 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
+   enum dpio_phy phy = vlv_d

[PATCH 10/14] drm/i915/dpio: Give VLV DPIO group register a clearer name

[Ville Syrjala]

From: Ville Syrjälä 

Include _GRP in VLV DPOP PHY group access register define
names. Makes it more obvious where the accesses will land.
Also matches the naming used by BXT already.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 34 +++
 drivers/gpu/drm/i915/i915_reg.h   | 90 +--
 2 files changed, 62 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 4fafac534967..791902ba729c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1071,18 +1071,18 @@ void vlv_set_phy_signal_level(struct intel_encoder 
*encoder,
 
vlv_dpio_get(dev_priv);
 
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
 uniqtranscale_reg_value);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
 
if (tx3_demph)
vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
 
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x0003);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x0003);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);
 
vlv_dpio_put(dev_priv);
 }
@@ -1098,19 +1098,19 @@ void vlv_phy_pre_pll_enable(struct intel_encoder 
*encoder,
/* Program Tx lane resets to default */
vlv_dpio_get(dev_priv);
 
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
 DPIO_PCS_TX_LANE2_RESET |
 DPIO_PCS_TX_LANE1_RESET);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
 (1<

[PATCH 06/14] drm/i915/dpio: Rename some variables

[Ville Syrjala]

From: Ville Syrjälä 

Use a constent 'tmp' as the variable name for the register
values during rmw when we don't deal with multiple registers
in parallel.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 97 +++
 1 file changed, 48 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 01f800b6b30e..0a738b491c40 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -514,23 +514,23 @@ void vlv_crtc_clock_get(struct intel_crtc_state 
*crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
const struct i9xx_dpll_hw_state *hw_state = 
&crtc_state->dpll_hw_state.i9xx;
-   struct dpll clock;
-   u32 mdiv;
int refclk = 10;
+   struct dpll clock;
+   u32 tmp;
 
/* In case of DSI, DPLL will not be used */
if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
return;
 
vlv_dpio_get(dev_priv);
-   mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
vlv_dpio_put(dev_priv);
 
-   clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
-   clock.m2 = mdiv & DPIO_M2DIV_MASK;
-   clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
-   clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
-   clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
+   clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
+   clock.m2 = tmp & DPIO_M2DIV_MASK;
+   clock.n = (tmp >> DPIO_N_SHIFT) & 0xf;
+   clock.p1 = (tmp >> DPIO_P1_SHIFT) & 7;
+   clock.p2 = (tmp >> DPIO_P2_SHIFT) & 0x1f;
 
crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
 }
@@ -1869,30 +1869,30 @@ void i9xx_enable_pll(const struct intel_crtc_state 
*crtc_state)
 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
 enum dpio_phy phy)
 {
-   u32 reg_val;
+   u32 tmp;
 
/*
 * PLLB opamp always calibrates to max value of 0x3f, force enable it
 * and set it to a reasonable value instead.
 */
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
-   reg_val &= 0xff00;
-   reg_val |= 0x0030;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+   tmp &= 0xff00;
+   tmp |= 0x0030;
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
 
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
-   reg_val &= 0x00ff;
-   reg_val |= 0x8c00;
-   vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
+   tmp &= 0x00ff;
+   tmp |= 0x8c00;
+   vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
 
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
-   reg_val &= 0xff00;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+   tmp &= 0xff00;
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
 
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
-   reg_val &= 0x00ff;
-   reg_val |= 0xb000;
-   vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
+   tmp &= 0x00ff;
+   tmp |= 0xb000;
+   vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
 }
 
 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
@@ -1902,7 +1902,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state 
*crtc_state)
const struct dpll *clock = &crtc_state->dpll;
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
enum pipe pipe = crtc->pipe;
-   u32 mdiv, coreclk, reg_val;
+   u32 tmp, coreclk;
 
vlv_dpio_get(dev_priv);
 
@@ -1916,15 +1916,15 @@ static void vlv_prepare_pll(const struct 
intel_crtc_state *crtc_state)
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
 
/* Disable target IRef on PLL */
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
-   reg_val &= 0x00ff;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
+   tmp &= 0x00ff;
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
 
/* Disable fast lock */
vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
 
/* Set idtafcrecal before PLL is enabled */
-   mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
+   tmp = (clock->m1 << DPIO_M1DIV_SHIFT) |
(clock->m2 & DPIO_M2DIV_MASK) |
(clock->p1 << DPIO_P1_SHIFT) |
(clock->p2 << DPIO_P2_SHIFT) |
@@ -19

[PATCH 08/14] drm/i915/dpio: s/pipe/ch/

[Ville Syrjala]

From: Ville Syrjälä 

Stop using 'pipe' directly as the DPIO PHY channel. This
does happen to work on VLV since it just has the one PHY
with CH0==pipe A and CH1==pipe B. But explicitly converting
the thing to the right enum makes the whole thing less
confusing.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 49 ---
 1 file changed, 25 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 743cc466ee39..861f4a735251 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -512,6 +512,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
const struct i9xx_dpll_hw_state *hw_state = 
&crtc_state->dpll_hw_state.i9xx;
int refclk = 10;
@@ -523,7 +524,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
return;
 
vlv_dpio_get(dev_priv);
-   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch));
vlv_dpio_put(dev_priv);
 
clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
@@ -1867,7 +1868,7 @@ void i9xx_enable_pll(const struct intel_crtc_state 
*crtc_state)
 }
 
 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
-enum dpio_phy phy)
+enum dpio_phy phy, enum dpio_channel ch)
 {
u32 tmp;
 
@@ -1875,19 +1876,19 @@ static void vlv_pllb_recal_opamp(struct 
drm_i915_private *dev_priv,
 * PLLB opamp always calibrates to max value of 0x3f, force enable it
 * and set it to a reasonable value instead.
 */
-   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
tmp &= 0xff00;
tmp |= 0x0030;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
 
tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
tmp &= 0x00ff;
tmp |= 0x8c00;
vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
 
-   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
tmp &= 0xff00;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
 
tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
tmp &= 0x00ff;
@@ -1900,6 +1901,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state 
*crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct dpll *clock = &crtc_state->dpll;
+   enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
enum pipe pipe = crtc->pipe;
u32 tmp, coreclk;
@@ -1910,15 +1912,15 @@ static void vlv_prepare_pll(const struct 
intel_crtc_state *crtc_state)
 
/* PLL B needs special handling */
if (pipe == PIPE_B)
-   vlv_pllb_recal_opamp(dev_priv, phy);
+   vlv_pllb_recal_opamp(dev_priv, phy, ch);
 
/* Set up Tx target for periodic Rcomp update */
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
 
/* Disable target IRef on PLL */
-   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
+   tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(ch));
tmp &= 0x00ff;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(ch), tmp);
 
/* Disable fast lock */
vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
@@ -1937,46 +1939,46 @@ static void vlv_prepare_pll(const struct 
intel_crtc_state *crtc_state)
 * Note: don't use the DAC post divider as it seems unstable.
 */
tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
 
tmp |= DPIO_ENABLE_CALIBRATION;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
 
/* Set HBR and RBR LPF coefficients */
if (crtc_state->port_clock == 162000 ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
+   vlv_dpio_wr

[PATCH 07/14] drm/i915/dpio: s/port/ch/

[Ville Syrjala]

From: Ville Syrjälä 

Stop calling the DPIO PHY channel "port". Just say "ch", which
is already used in a bunch of places.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 44 +++
 drivers/gpu/drm/i915/display/intel_dpll.c | 54 +--
 2 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 6cbee88e608f..e4a04c9b5b19 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1069,23 +1069,23 @@ void vlv_set_phy_signal_level(struct intel_encoder 
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 
vlv_dpio_get(dev_priv);
 
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port),
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
 uniqtranscale_reg_value);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
 
if (tx3_demph)
-   vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph);
+   vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
 
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x0003);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x0003);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
 
vlv_dpio_put(dev_priv);
 }
@@ -1096,25 +1096,25 @@ void vlv_phy_pre_pll_enable(struct intel_encoder 
*encoder,
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 
/* Program Tx lane resets to default */
vlv_dpio_get(dev_priv);
 
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port),
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
 DPIO_PCS_TX_LANE2_RESET |
 DPIO_PCS_TX_LANE1_RESET);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port),
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
 (1uapi.crtc);
-   enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
enum pipe pipe = crtc->pipe;
enum dpio_phy phy = vlv_pipe_to_phy(pipe);
u32 val;
@@ -1140,11 +1140,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
*encoder,
else
val &= ~(1<<21);
val |= 0x001000c4;
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
 
/* Program lane clock */
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(port), 0x00760018);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(port), 0x00400888);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
 
vlv_dpio_put(dev_priv);
 }
@@ -1155,11 +1155,11 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-   enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 
vlv_dpio_get(dev_priv);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), 0x);
-   vlv_dpio_write(dev_

[PATCH 05/14] drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code

[Ville Syrjala]

From: Ville Syrjälä 

Drop all the local variables for the DPLL dividers for vlv/chv
and just consult the state directly.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 62 ++-
 1 file changed, 27 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index b95032651da0..01f800b6b30e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1899,20 +1899,13 @@ static void vlv_prepare_pll(const struct 
intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   const struct dpll *clock = &crtc_state->dpll;
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
enum pipe pipe = crtc->pipe;
-   u32 mdiv;
-   u32 bestn, bestm1, bestm2, bestp1, bestp2;
-   u32 coreclk, reg_val;
+   u32 mdiv, coreclk, reg_val;
 
vlv_dpio_get(dev_priv);
 
-   bestn = crtc_state->dpll.n;
-   bestm1 = crtc_state->dpll.m1;
-   bestm2 = crtc_state->dpll.m2;
-   bestp1 = crtc_state->dpll.p1;
-   bestp2 = crtc_state->dpll.p2;
-
/* See eDP HDMI DPIO driver vbios notes doc */
 
/* PLL B needs special handling */
@@ -1931,10 +1924,12 @@ static void vlv_prepare_pll(const struct 
intel_crtc_state *crtc_state)
vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
 
/* Set idtafcrecal before PLL is enabled */
-   mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
-   mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
-   mdiv |= ((bestn << DPIO_N_SHIFT));
-   mdiv |= (1 << DPIO_K_SHIFT);
+   mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
+   (clock->m2 & DPIO_M2DIV_MASK) |
+   (clock->p1 << DPIO_P1_SHIFT) |
+   (clock->p2 << DPIO_P2_SHIFT) |
+   (clock->n << DPIO_N_SHIFT) |
+   (1 << DPIO_K_SHIFT);
 
/*
 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
@@ -2030,19 +2025,14 @@ static void chv_prepare_pll(const struct 
intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   const struct dpll *clock = &crtc_state->dpll;
enum pipe pipe = crtc->pipe;
enum dpio_channel port = vlv_pipe_to_channel(pipe);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
-   u32 loopfilter, tribuf_calcntr;
-   u32 bestm2, bestp1, bestp2, bestm2_frac;
-   u32 dpio_val;
-   int vco;
+   u32 dpio_val, loopfilter, tribuf_calcntr;
+   u32 m2_frac;
 
-   bestm2_frac = crtc_state->dpll.m2 & 0x3f;
-   bestm2 = crtc_state->dpll.m2 >> 22;
-   bestp1 = crtc_state->dpll.p1;
-   bestp2 = crtc_state->dpll.p2;
-   vco = crtc_state->dpll.vco;
+   m2_frac = clock->m2 & 0x3f;
dpio_val = 0;
loopfilter = 0;
 
@@ -2050,27 +2040,29 @@ static void chv_prepare_pll(const struct 
intel_crtc_state *crtc_state)
 
/* p1 and p2 divider */
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port),
-   5 << DPIO_CHV_S1_DIV_SHIFT |
-   bestp1 << DPIO_CHV_P1_DIV_SHIFT |
-   bestp2 << DPIO_CHV_P2_DIV_SHIFT |
-   1 << DPIO_CHV_K_DIV_SHIFT);
+  5 << DPIO_CHV_S1_DIV_SHIFT |
+  clock->p1 << DPIO_CHV_P1_DIV_SHIFT |
+  clock->p2 << DPIO_CHV_P2_DIV_SHIFT |
+  1 << DPIO_CHV_K_DIV_SHIFT);
 
/* Feedback post-divider - m2 */
-   vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), bestm2);
+   vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port),
+  clock->m2 >> 22);
 
/* Feedback refclk divider - n and m1 */
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port),
-   DPIO_CHV_M1_DIV_BY_2 |
-   1 << DPIO_CHV_N_DIV_SHIFT);
+  DPIO_CHV_M1_DIV_BY_2 |
+  1 << DPIO_CHV_N_DIV_SHIFT);
 
/* M2 fraction division */
-   vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), bestm2_frac);
+   vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port),
+  m2_frac);
 
/* M2 fraction division enable */
dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
-   if (bestm2_frac)
+   if (m2_frac)
dpio_val |= DPIO_CHV_FRAC_DIV_EN;
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val);
 
@@ -2079,22 +2071,22 @@ static void chv_prepare_pll(const struct 
intel_crtc_state *crtc_state)
dpio_val &= ~(DPIO_CHV_INT_LOC

[PATCH 04/14] drm/i915/dpio: Fix VLV DPIO PLL register dword numbering

[Ville Syrjala]

From: Ville Syrjälä 

The spreadsheet defines the PLL register block as having
the dwords in the following order:

block   dwordsoffsets
PLL10x0-0x7   0x00-0x1f
PLL20x0-0x7   0x20-0x2f
PLL1ext 0x10-0x1f 0x40-0x5f
PLL2ext 0x10-0x1f 0x60-0x7f

So dword indexes 0x8-0xf don't even exist. Renumber
our register defines to match.

Note that the spreadsheet used hex numbering whereas our
defiens are in decimal. Perhaps we should change that?

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 18 -
 drivers/gpu/drm/i915/i915_reg.h   | 24 +++
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7e8aca3c87ec..b95032651da0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1875,19 +1875,19 @@ static void vlv_pllb_recal_opamp(struct 
drm_i915_private *dev_priv,
 * PLLB opamp always calibrates to max value of 0x3f, force enable it
 * and set it to a reasonable value instead.
 */
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
+   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
reg_val &= 0xff00;
reg_val |= 0x0030;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
 
reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
reg_val &= 0x00ff;
reg_val |= 0x8c00;
vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
 
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
+   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
reg_val &= 0xff00;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
 
reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
reg_val &= 0x00ff;
@@ -1923,9 +1923,9 @@ static void vlv_prepare_pll(const struct intel_crtc_state 
*crtc_state)
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
 
/* Disable target IRef on PLL */
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe));
+   reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
reg_val &= 0x00ff;
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW8(pipe), reg_val);
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
 
/* Disable fast lock */
vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
@@ -1951,10 +1951,10 @@ static void vlv_prepare_pll(const struct 
intel_crtc_state *crtc_state)
if (crtc_state->port_clock == 162000 ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 0x009f0003);
else
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 0x00df);
 
if (intel_crtc_has_dp_encoder(crtc_state)) {
@@ -1981,7 +1981,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state 
*crtc_state)
coreclk |= 0x0100;
vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk);
 
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW11(pipe), 0x87871000);
+   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(pipe), 0x87871000);
 
vlv_dpio_put(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f3c83d2ab8d..747221f8ac72 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -229,21 +229,21 @@
 #define _VLV_PLL_DW7_CH1   0x803c
 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
 
-#define _VLV_PLL_DW8_CH0   0x8040
-#define _VLV_PLL_DW8_CH1   0x8060
-#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
+#define _VLV_PLL_DW16_CH0  0x8040
+#define _VLV_PLL_DW16_CH1  0x8060
+#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1)
 
-#define _VLV_PLL_DW9_CH0   0x8044
-#define _VLV_PLL_DW9_CH1   0x8064
-#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
+#define _VLV_PLL_DW17_CH0  0x8044
+#define _VLV_PLL_DW17_CH1  0x8064
+#define VLV_PLL_DW17(ch) _PIPE(ch, _VLV_PLL_DW17_CH0, _VLV_PLL_DW17_CH1)
 
-#define _VLV_PLL_DW10_CH0  0x8048
-#define _VLV_PLL_DW10_CH1  0x8068
-#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
+#define _VLV_PLL_DW18_CH0  0x8048
+#define _VLV_PLL_DW18_CH1  0x8068
+#def

[PATCH 03/14] drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/

[Ville Syrjala]

From: Ville Syrjälä 

VLV_PLL_DW9_BCAST is actually VLV_PCS_DW17_BCAST. The address
does kinda look like it goes to the PLL block on a first glance,
but broadcast is special and doesn't even exist for the PLL
(only PCS and TX have it).

The fact that we use a broadcast write here is a bit sketchy
IMO since we're now blasting the register to all PCS splines
across the whole PHY. So the PCS registers in the other channel
(ie. other pipe/port) will also be written. But I guess the
fact that we always write the same value should make this a nop
even if the other channel is already enabled (assuming the VBIOS/GOP
didn't screw up and use some other value...).

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h   | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 6693beafe9c0..7e8aca3c87ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1920,7 +1920,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state 
*crtc_state)
vlv_pllb_recal_opamp(dev_priv, phy);
 
/* Set up Tx target for periodic Rcomp update */
-   vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9_BCAST, 0x010f);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
 
/* Disable target IRef on PLL */
reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a2fadcbe0932..8f3c83d2ab8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -233,7 +233,6 @@
 #define _VLV_PLL_DW8_CH1   0x8060
 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
 
-#define VLV_PLL_DW9_BCAST  0xc044
 #define _VLV_PLL_DW9_CH0   0x8044
 #define _VLV_PLL_DW9_CH1   0x8064
 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
@@ -370,6 +369,8 @@
 #define _VLV_PCS_DW14_CH1  0x8438
 #defineVLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
 
+#define VLV_PCS_DW17_BCAST 0xc044
+
 #define _VLV_PCS_DW23_CH0  0x825c
 #define _VLV_PCS_DW23_CH1  0x845c
 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
-- 
2.43.2

[PATCH 02/14] drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/

[Ville Syrjala]

From: Ville Syrjälä 

Our VLV_REF_DW13 is actually VLV_REF_DW11. Rename it.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 8 
 drivers/gpu/drm/i915/i915_reg.h   | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 49274d632716..6693beafe9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1880,19 +1880,19 @@ static void vlv_pllb_recal_opamp(struct 
drm_i915_private *dev_priv,
reg_val |= 0x0030;
vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
 
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
+   reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
reg_val &= 0x00ff;
reg_val |= 0x8c00;
-   vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
+   vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
 
reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
reg_val &= 0xff00;
vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
 
-   reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
+   reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
reg_val &= 0x00ff;
reg_val |= 0xb000;
-   vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
+   vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
 }
 
 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8eb6c2bf4557..a2fadcbe0932 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -246,8 +246,8 @@
 #define _VLV_PLL_DW11_CH1  0x806c
 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
 
-/* Spec for ref block start counts at DW10 */
-#define VLV_REF_DW13   0x80ac
+/* Spec for ref block start counts at DW8 */
+#define VLV_REF_DW11   0x80ac
 
 #define VLV_CMN_DW00x8100
 
-- 
2.43.2

[PATCH 01/14] drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read

[Ville Syrjala]

From: Ville Syrjälä 

We don't use the result of the VLV_PCS01_DW8 read at all,
so don't read.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index c72b76b61dff..6cbee88e608f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1134,7 +1134,6 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
*encoder,
vlv_dpio_get(dev_priv);
 
/* Enable clock channels for this port */
-   val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(port));
val = 0;
if (pipe)
val |= (1<<21);
-- 
2.43.2

[PATCH 00/14] drm/i915: VLV/CHV DPIO register cleanup

[Ville Syrjala]

From: Ville Syrjälä 

Polish the VLV/CHV DPIO stuff and extract vlv_dpio_phy_regs.h
to declutter i915_reg.h a bit.

Ville Syrjälä (14):
  drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read
  drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/
  drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/
  drm/i915/dpio: Fix VLV DPIO PLL register dword numbering
  drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code
  drm/i915/dpio: Rename some variables
  drm/i915/dpio: s/port/ch/
  drm/i915/dpio: s/pipe/ch/
  drm/i915/dpio: Derive the phy from the port rather than pipe in
encoder hooks
  drm/i915/dpio: Give VLV DPIO group register a clearer name
  drm/i915/dpio: Rename a few CHV DPIO PHY registers
  drm/i915/dpio: Clean up VLV/CHV DPIO PHY register defines
  drm/i915/dpio: Clean up the vlv/chv PHY register bits
  drm/i915/dpio: Extract vlv_dpio_phy_regs.h

 drivers/gpu/drm/i915/display/intel_display.c  |   1 +
 .../i915/display/intel_display_power_well.c   |  16 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 148 
 drivers/gpu/drm/i915/display/intel_dpll.c | 260 +++--
 .../gpu/drm/i915/display/vlv_dpio_phy_regs.h  | 309 
 drivers/gpu/drm/i915/i915_reg.h   | 343 --
 drivers/gpu/drm/i915/vlv_sideband.c   |   1 -
 7 files changed, 515 insertions(+), 563 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h

-- 
2.43.2

Re: [PATCH] drm/i915/gem: Downgrade stolen lmem setup warning

[Jani Nikula]

On Fri, 19 Apr 2024, Jonathan Cavitt  wrote:
> In the case where lmem_size < dsm_base, hardware is reporting that
> stolen lmem is unusable.  In this case, instead of throwing a warning,
> we can continue execution as normal by disabling stolen LMEM support.
> For example, this change will allow the following error report from
> ATS-M to no longer apply:
>
> <6> [144.859887] pcieport :4b:00.0: bridge window [mem 
> 0xb100-0xb11f]
> <6> [144.859900] pcieport :4b:00.0: bridge window [mem 
> 0x3bbc-0x3bbc17ff 64bit pref]
> <6> [144.859917] pcieport :4c:01.0: PCI bridge to [bus 4d-4e]
> <6> [144.859932] pcieport :4c:01.0: bridge window [mem 
> 0xb100-0xb11f]
> <6> [144.859945] pcieport :4c:01.0: bridge window [mem 
> 0x3bbc-0x3bbc17ff 64bit pref]
> <6> [144.859984] i915 :4d:00.0: [drm] BAR2 resized to 256M
> <6> [144.860640] i915 :4d:00.0: [drm] Using a reduced BAR size of 256MiB. 
> Consider enabling 'Resizable BAR' or similar, if available in the BIOS.
> <4> [144.860719] ---[ cut here ]---
> <4> [144.860727] WARNING: CPU: 17 PID: 1815 at 
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:939 
> i915_gem_stolen_lmem_setup+0x38c/0x430 [i915]
> <4> [144.861430] Modules linked in: i915 snd_intel_dspcfg snd_hda_codec 
> snd_hwdep snd_hda_core snd_pcm vgem drm_shmem_helper prime_numbers 
> i2c_algo_bit ttm video drm_display_helper drm_buddy fuse x86_pkg_temp_thermal 
> coretemp kvm_intel kvm ixgbe mdio irqbypass ptp crct10dif_pclmul crc32_pclmul 
> ghash_clmulni_intel pps_core i2c_i801 mei_me i2c_smbus mei wmi 
> acpi_power_meter [last unloaded: i915]
> <4> [144.861611] CPU: 17 PID: 1815 Comm: i915_module_loa Tainted: G U 
> 6.8.0-rc5-drmtip_1515-g78f49af27723+ #1
> <4> [144.861624] Hardware name: Intel Corporation WHITLEY/WHITLEY, BIOS 
> SE5C6200.86B.0020.P41.2109300305 09/30/2021
> <4> [144.861632] RIP: 0010:i915_gem_stolen_lmem_setup+0x38c/0x430 [i915]
> <4> [144.862287] Code: ff 41 c1 e4 05 e9 ac fe ff ff 4d 63 e4 48 89 ef 48 85 
> ed 74 04 48 8b 7d 08 48 c7 c6 10 a3 7b a0 e8 e9 90 43 e1 e9 ee fd ff ff <0f> 
> 0b 49 c7 c4 ed ff ff ff e9 e0 fd ff ff 0f b7 d2 48 c7 c6 00 d9
> <4> [144.862299] RSP: 0018:c90005607980 EFLAGS: 00010207
> <4> [144.862315] RAX: fff0 RBX: 0003 RCX: 
> 
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/10833
>

No blank lines between trailers please.

BR,
Jani.

> Suggested-by: Chris Wilson 
> Signed-off-by: Jonathan Cavitt 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index ad6dd7f3259bc..efa632a9e61c6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -936,8 +936,12 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private 
> *i915, u16 type,
>   } else {
>   /* Use DSM base address instead for stolen memory */
>   dsm_base = intel_uncore_read64(uncore, GEN6_DSMBASE) & 
> GEN11_BDSM_MASK;
> - if (WARN_ON(lmem_size < dsm_base))
> + if (lmem_size < dsm_base) {
> + drm_dbg(&i915->drm,
> + "Disabling stolen memory support due to OOB 
> placement: lmem_size = %lli vs dsm_base = %lli\n",
> + lmem_size, dsm_base);
>   return ERR_PTR(-ENODEV);
> + }
>   dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
>   }

-- 
Jani Nikula, Intel

Re: [PATCH] drm/i915/display: Fixed the main link lost in MST

[Jani Nikula]

On Mon, 22 Apr 2024, gareth...@intel.com wrote:
> From: Gareth Yu 
>
> Re-train the main link when the sink asserts a HPD for the main lnk 
> lost.

This is a completely inadequate commit message for such a fundamental
change.

Preferrably we'd additionally like a bug filed at fdo gitlab, with debug
logs that show the situation, etc.

> Cc : Tejas Upadhyay 
> Cc : Matt Roper 
> Cc : Ville Syrjälä 

Superfluous space before ":".

> Signed-off-by: Gareth Yu 
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e05e25cd4a94..db5d4fa8340b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5849,8 +5849,13 @@ intel_dp_detect(struct drm_connector *connector,
>   /* Can't disconnect eDP */
>   if (intel_dp_is_edp(intel_dp))
>   status = edp_detect(intel_dp);
> - else if (intel_digital_port_connected(encoder))
> + else if (intel_digital_port_connected(encoder)) {
>   status = intel_dp_detect_dpcd(intel_dp);
> + if (status == connector_status_connected && intel_dp->is_mst &&
> + !intel_dp_mst_link_status(intel_dp))
> + if (intel_dp_retrain_link(encoder, ctx))
> + status = connector_status_disconnected;
> + }

If we were to add this, this is definitely not the place. You can't look
at ->is_mst for clues here because it's between mst detect and
configure. We might be unconfiguring mst. This also adds unnecessary
checks for status == connected, when it's all handled below with an
early exist for disconnected, etc. And there's a path for retrain too.

All of this has to fit the existing paths nicely instead of just shoving
it here at random.


BR,
Jani.

>   else
>   status = connector_status_disconnected;

-- 
Jani Nikula, Intel

Re: [PATCH v10 6/6] drm/i915/display: force qgv check after the hw state readout

[Lisovskiy, Stanislav]

On Fri, Apr 05, 2024 at 02:35:33PM +0300, Vinod Govindapillai wrote:
> The current intel_bw_atomic_check do not check the possbility
> of a sagv configuration change after the hw state readout.
> Hence cannot update the sagv configuration until some other
> relevant changes like data rates, number of planes etc. happen.
> Introduce a flag to force qgv check in such cases.
> 
> Signed-off-by: Vinod Govindapillai 

Hmmm.. the whole point of that series is actually to put HW/SW
in sync, before we actually are able to calculate the real requirements.

When we initially for QGV/PSF GV to the highest point(thus disabling SAGV),
we exactly want to make sure that HW/SW are in sync(which wasn't the case
before that). Then later when the real plane bw requirements are calculated,
we can possibly relax the QGV point requirements, enabling more points.

I don't see why we need to force the recalculation here.

Or am I missing something?

Stan

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 8 ++--
>  drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 6fb228a1a28f..1b190be745a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -755,6 +755,7 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
>   intel_bw_crtc_data_rate(crtc_state);
>   bw_state->num_active_planes[crtc->pipe] =
>   intel_bw_crtc_num_active_planes(crtc_state);
> + bw_state->force_check_qgv = true;
>  
>   drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n",
>   pipe_name(crtc->pipe),
> @@ -1339,8 +1340,9 @@ int intel_bw_atomic_check(struct intel_atomic_state 
> *state)
>   new_bw_state = intel_atomic_get_new_bw_state(state);
>  
>   if (new_bw_state &&
> - intel_can_enable_sagv(i915, old_bw_state) !=
> - intel_can_enable_sagv(i915, new_bw_state))
> + (intel_can_enable_sagv(i915, old_bw_state) !=
> +  intel_can_enable_sagv(i915, new_bw_state) ||
> +  new_bw_state->force_check_qgv))
>   changed = true;
>  
>   /*
> @@ -1354,6 +1356,8 @@ int intel_bw_atomic_check(struct intel_atomic_state 
> *state)
>   if (ret)
>   return ret;
>  
> + new_bw_state->force_check_qgv = false;
> +
>   return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h 
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index fa1e924ec961..161813cca473 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -47,6 +47,12 @@ struct intel_bw_state {
>*/
>   u16 qgv_points_mask;
>  
> + /*
> +  * Flag to force the QGV comparison in atomic check right after the
> +  * hw state readout
> +  */
> + bool force_check_qgv;
> +
>   int min_cdclk[I915_MAX_PIPES];
>   unsigned int data_rate[I915_MAX_PIPES];
>   u8 num_active_planes[I915_MAX_PIPES];
> -- 
> 2.34.1
> 

[PATCH] drm/i915/display: Fixed the main link lost in MST

[gareth . yu]

From: Gareth Yu 

Re-train the main link when the sink asserts a HPD for the main lnk 
lost.

Cc : Tejas Upadhyay 
Cc : Matt Roper 
Cc : Ville Syrjälä 
Signed-off-by: Gareth Yu 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index e05e25cd4a94..db5d4fa8340b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5849,8 +5849,13 @@ intel_dp_detect(struct drm_connector *connector,
/* Can't disconnect eDP */
if (intel_dp_is_edp(intel_dp))
status = edp_detect(intel_dp);
-   else if (intel_digital_port_connected(encoder))
+   else if (intel_digital_port_connected(encoder)) {
status = intel_dp_detect_dpcd(intel_dp);
+   if (status == connector_status_connected && intel_dp->is_mst &&
+   !intel_dp_mst_link_status(intel_dp))
+   if (intel_dp_retrain_link(encoder, ctx))
+   status = connector_status_disconnected;
+   }
else
status = connector_status_disconnected;
 
-- 
2.25.1

✓ Fi.CI.BAT: success for Enable display support for Battlemage (rev2)

[Patchwork]

== Series Details ==

Series: Enable display support for Battlemage (rev2)
URL   : https://patchwork.freedesktop.org/series/132429/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14621 -> Patchwork_132429v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/index.html

Participating hosts (35 -> 34)
--

  Additional (2): bat-dg2-11 fi-elk-e7500 
  Missing(3): bat-kbl-2 bat-jsl-1 bat-mtlp-8 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_132429v2:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_lrc:
- {bat-rpls-4}:   [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14621/bat-rpls-4/igt@i915_selftest@live@gt_lrc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-rpls-4/igt@i915_selftest@live@gt_lrc.html

  
Known issues


  Here are the changes found in Patchwork_132429v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@gem_m...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#4077]) +2 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#6621])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#4212]) +7 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#5190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#4215] / [i915#5190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#4103] / [i915#4213]) +1 
other test skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#3555] / [i915#3840])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-11: NOTRUN -> [SKIP][12]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#5274])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_pm_backlight@basic-brightness:
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#5354])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_pm_backli...@basic-brightness.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
- fi-elk-e7500:   NOTRUN -> [SKIP][15] +24 other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/fi-elk-e7500/igt@kms_pm_...@basic-pci-d3-state.html

  * igt@kms_psr@psr-sprite-plane-onoff:
- bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#1072] / [i915#9732]) +3 
other tests skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_...@psr-sprite-plane-onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#3555])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v2/bat-dg2-11/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#3

✗ Fi.CI.SPARSE: warning for Enable display support for Battlemage (rev2)

[Patchwork]

== Series Details ==

Series: Enable display support for Battlemage (rev2)
URL   : https://patchwork.freedesktop.org/series/132429/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.CHECKPATCH: warning for Enable display support for Battlemage (rev2)

[Patchwork]

== Series Details ==

Series: Enable display support for Battlemage (rev2)
URL   : https://patchwork.freedesktop.org/series/132429/
State : warning

== Summary ==

Error: dim checkpatch failed
5adf546fb828 drm/xe/display: Lane reversal requires writes to both context lanes
47d772e57abf drm/i915/bmg: Define IS_BATTLEMAGE macro
-:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'i915' may be better as 
'(i915)' to avoid precedence issues
#35: FILE: drivers/gpu/drm/i915/i915_drv.h:545:
+#define IS_LUNARLAKE(i915) (0 && i915)

-:36: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'i915' may be better as 
'(i915)' to avoid precedence issues
#36: FILE: drivers/gpu/drm/i915/i915_drv.h:546:
+#define IS_BATTLEMAGE(i915)  (0 && i915)

total: 0 errors, 0 warnings, 2 checks, 16 lines checked
666772b8eca1 drm/i915/xe2hpd: Initial cdclk table
ded9bbbe8a4a drm/i915/bmg: Extend DG2 tc check to future
1faeea334731 drm/i915/xe2hpd: Properly disable power in port A
9807345d6a2d drm/i915/xe2hpd: Add new C20 PHY SRAM address
-:78: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#78: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2201:
+ 
PHY_C20_B_MPLLB_CNTX_CFG(i915, i));

-:84: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#84: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2205:
+ 
PHY_C20_A_MPLLB_CNTX_CFG(i915, i));

-:94: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2213:
+ 
PHY_C20_B_MPLLA_CNTX_CFG(i915, i));

-:100: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#100: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2217:
+ 
PHY_C20_A_MPLLA_CNTX_CFG(i915, i));

-:190: ERROR:SPACING: space required after that ',' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:276:
+#define _IS_XE2HPD_C20(i915)   (DISPLAY_VER_FULL(i915) == IP_VER(14,1))
^

-:193: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#193: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:279:
+   ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : 
_MTL_C20_A_TX_CNTX_CFG) - (idx))

-:195: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#195: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:281:
+   ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : 
_MTL_C20_B_TX_CNTX_CFG) - (idx))

-:203: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#203: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:285:
+   ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : 
_MTL_C20_A_CMN_CNTX_CFG) - (idx))

-:205: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:287:
+   ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_CMN_CNTX_CFG : 
_MTL_C20_B_CMN_CNTX_CFG) - (idx))

total: 1 errors, 8 warnings, 0 checks, 186 lines checked
9fe3021a7a07 drm/i915/xe2hpd: Add support for eDP PLL configuration
230e4bd54950 drm/i915/xe2hpd: update pll values in sync with Bspec
772433d8abff drm/i915/xe2hpd: Add display info
6c154275fd06 drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes
db65edc5384f drm/i915/xe2hpd: Add max memory bandwidth algorithm
0c9b7dca68c3 drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
52735a96e807 drm/i915/bmg: BMG should re-use MTL's south display logic
4eade5e6a2e5 Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
9118fe127d6e drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
4cb19a4f43dd drm/xe/gt_print: add xe_gt_err_once()
c4d54d6e76ab drm/xe/device: implement transient flush
2323e2089516 drm/i915/display: perform transient flush
-:58: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#58: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 76 lines checked
01b36e03d031 drm/xe/bmg: Enable the display support

✓ Fi.CI.BAT: success for drm/i915/display: Fixed the main link lost in MST

[Patchwork]

== Series Details ==

Series: drm/i915/display: Fixed the main link lost in MST
URL   : https://patchwork.freedesktop.org/series/132685/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14621 -> Patchwork_132685v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/index.html

Participating hosts (35 -> 34)
--

  Additional (2): bat-dg2-11 bat-mtlp-6 
  Missing(3): bat-kbl-2 bat-jsl-1 fi-kbl-8809g 

Known issues


  Here are the changes found in Patchwork_132685v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#1849] / [i915#2582])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@fb...@info.html

  * igt@fbdev@write:
- bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#2582]) +3 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@fb...@write.html

  * igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-dg2-11/igt@gem_m...@basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#4083])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@gem_m...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-dg2-11/igt@gem_tiled_pread_basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_module_load@load:
- bat-dg2-11: NOTRUN -> [DMESG-WARN][11] ([i915#10014])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-dg2-11/igt@i915_module_l...@load.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#6621])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-dg2-11/igt@i915_pm_...@basic-api.html
- bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#4212] / [i915#9792]) +8 
other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#4212]) +7 other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#5190] / [i915#9792])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#5190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#4215] / [i915#5190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213]) +1 
other test skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132685v1/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basi

✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Fixed the main link lost in MST

[Patchwork]

== Series Details ==

Series: drm/i915/display: Fixed the main link lost in MST
URL   : https://patchwork.freedesktop.org/series/132685/
State : warning

== Summary ==

Error: dim checkpatch failed
f4fd4536e8cb drm/i915/display: Fixed the main link lost in MST
-:29: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#29: FILE: drivers/gpu/drm/i915/display/intel_dp.c:5855:
+   if (status == connector_status_connected && intel_dp->is_mst &&
+   !intel_dp_mst_link_status(intel_dp))

total: 0 errors, 0 warnings, 1 checks, 14 lines checked