✓ Fi.CI.BAT: success for drm/probe-helper: Call drm_mode_validate_ycbcr420() before connector->mode_valid() (rev3)
== Series Details == Series: drm/probe-helper: Call drm_mode_validate_ycbcr420() before connector->mode_valid() (rev3) URL : https://patchwork.freedesktop.org/series/133709/ State : success == Summary == CI Bug Log - changes from CI_DRM_14777 -> Patchwork_133709v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/index.html Participating hosts (40 -> 36) -- Additional (4): bat-dg1-7 bat-dg2-11 bat-jsl-1 fi-kbl-8809g Missing(8): fi-kbl-7567u bat-mtlp-6 fi-snb-2520m fi-elk-e7500 bat-atsm-1 bat-jsl-3 bat-mtlp-8 bat-arls-3 Known issues Here are the changes found in Patchwork_133709v3 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-1: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html - bat-jsl-1: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-jsl-1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-7: NOTRUN -> [SKIP][6] ([i915#4083]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg1-7/igt@gem_m...@basic.html - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg2-11/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-7: NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html - bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#4077]) +2 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-7: NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg1-7/igt@gem_tiled_pread_basic.html - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg2-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg1-7: NOTRUN -> [SKIP][12] ([i915#6621]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg1-7/igt@i915_pm_...@basic-api.html - bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#6621]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg1-7: NOTRUN -> [SKIP][14] ([i915#4212]) +7 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg1-7/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#4212]) +7 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#5190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-7: NOTRUN -> [SKIP][17] ([i915#4215]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg1-7/igt@kms_addfb_ba...@basic-y-tiled-legacy.html - bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#4215] / [i915#5190]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v3/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html *
✗ Fi.CI.BAT: failure for drm/probe-helper: Call drm_mode_validate_ycbcr420() before connector->mode_valid() (rev2)
== Series Details ==
Series: drm/probe-helper: Call drm_mode_validate_ycbcr420() before
connector->mode_valid() (rev2)
URL : https://patchwork.freedesktop.org/series/133709/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14777 -> Patchwork_133709v2
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_133709v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133709v2, please notify your bug team
(i915-ci-in...@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/index.html
Participating hosts (40 -> 44)
--
Additional (5): bat-dg1-7 fi-glk-j4005 fi-kbl-8809g bat-dg2-11 bat-jsl-1
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_133709v2:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_heartbeat:
- bat-kbl-2: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14777/bat-kbl-2/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-kbl-2/igt@i915_selftest@live@gt_heartbeat.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_busy@basic@modeset:
- {bat-mtlp-9}: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14777/bat-mtlp-9/igt@kms_busy@ba...@modeset.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-mtlp-9/igt@kms_busy@ba...@modeset.html
* igt@kms_flip@basic-flip-vs-dpms@a-dp6:
- {bat-mtlp-9}: [PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14777/bat-mtlp-9/igt@kms_flip@basic-flip-vs-d...@a-dp6.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-mtlp-9/igt@kms_flip@basic-flip-vs-d...@a-dp6.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-dp-8:
- {bat-mtlp-9}: NOTRUN -> [DMESG-FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-d-dp-8.html
Known issues
Here are the changes found in Patchwork_133709v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-jsl-1: NOTRUN -> [SKIP][8] ([i915#9318])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][9] ([i915#2190])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
- bat-jsl-1: NOTRUN -> [SKIP][10] ([i915#2190])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-jsl-1/igt@gem_huc_c...@huc-copy.html
- fi-glk-j4005: NOTRUN -> [SKIP][11] ([i915#2190])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-jsl-1: NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-jsl-1/igt@gem_lmem_swapp...@parallel-random-engines.html
- fi-glk-j4005: NOTRUN -> [SKIP][13] ([i915#4613]) +3 other tests skip
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/fi-glk-j4005/igt@gem_lmem_swapp...@parallel-random-engines.html
- fi-kbl-8809g: NOTRUN -> [SKIP][14] ([i915#4613]) +3 other tests skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#4083])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-dg2-11/igt@gem_m...@basic.html
- bat-dg1-7: NOTRUN -> [SKIP][16] ([i915#4083])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-dg1-7/igt@gem_m...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#4079]) +1 other test skip
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-dg2-11/igt@gem_render_tiled_bl...@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-7: NOTRUN -> [SKIP][18] ([i915#4077]) +2 other tests skip
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v2/bat-dg1-7/igt@gem_tiled_bl...@basic.html
*
✓ Fi.CI.BAT: success for drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+
== Series Details ==
Series: drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+
URL : https://patchwork.freedesktop.org/series/133716/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14777 -> Patchwork_133716v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v1/index.html
Participating hosts (40 -> 37)
--
Additional (1): fi-kbl-8809g
Missing(4): bat-mtlp-6 bat-jsl-3 fi-snb-2520m bat-arls-3
Known issues
Here are the changes found in Patchwork_133716v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][1] ([i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v1/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-8: [PASS][3] -> [FAIL][4] ([i915#10378])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14777/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v1/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] +30 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html
Possible fixes
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9: [FAIL][6] ([i915#10378]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14777/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v1/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[ABORT][8] ([i915#10800]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14777/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@kms_flip@basic-plain-flip@d-dp7:
- {bat-mtlp-9}: [DMESG-WARN][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14777/bat-mtlp-9/igt@kms_flip@basic-plain-f...@d-dp7.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v1/bat-mtlp-9/igt@kms_flip@basic-plain-f...@d-dp7.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10800]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10800
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
Build changes
-
* Linux: CI_DRM_14777 -> Patchwork_133716v1
CI-20190529: 20190529
CI_DRM_14777: f5b1f5e83aca888ada6cf909735023349a73d3df @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7859: 7859
Patchwork_133716v1: f5b1f5e83aca888ada6cf909735023349a73d3df @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v1/index.html
✗ Fi.CI.BAT: failure for drm/probe-helper: Call drm_mode_validate_ycbcr420() before connector->mode_valid()
== Series Details ==
Series: drm/probe-helper: Call drm_mode_validate_ycbcr420() before
connector->mode_valid()
URL : https://patchwork.freedesktop.org/series/133709/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14776 -> Patchwork_133709v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_133709v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133709v1, please notify your bug team
(i915-ci-in...@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/index.html
Participating hosts (42 -> 42)
--
Additional (2): fi-cfl-8109u fi-elk-e7500
Missing(2): bat-dg2-11 fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_133709v1:
### IGT changes ###
Possible regressions
* igt@i915_pm_rpm@module-reload:
- bat-jsl-1: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14776/bat-jsl-1/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/bat-jsl-1/igt@i915_pm_...@module-reload.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14776/bat-mtlp-9/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/bat-mtlp-9/igt@i915_pm_...@module-reload.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-6:
- {bat-mtlp-9}: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14776/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-dp-6.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-dp-6.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-dp-6:
- {bat-mtlp-9}: [PASS][7] -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14776/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-d-dp-6.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-d-dp-6.html
Known issues
Here are the changes found in Patchwork_133709v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][9] ([i915#2190])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html
* igt@kms_dsc@dsc-basic:
- fi-cfl-8109u: NOTRUN -> [SKIP][11] +11 other tests skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/fi-cfl-8109u/igt@kms_...@dsc-basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1:
- fi-elk-e7500: NOTRUN -> [SKIP][12] +24 other tests skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-hdmi-a-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
Build changes
-
* Linux: CI_DRM_14776 -> Patchwork_133709v1
CI-20190529: 20190529
CI_DRM_14776: 01e8fd3a8450d33ddf644820ffa8de5369e6a7a8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7858: 133c90d6aabcd90871e36946317c90ee83c2f847 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133709v1: 01e8fd3a8450d33ddf644820ffa8de5369e6a7a8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133709v1/index.html
✓ Fi.CI.BAT: success for drm/i915/selftests: Set always_coherent to false when reading from CPU
== Series Details ==
Series: drm/i915/selftests: Set always_coherent to false when reading from CPU
URL : https://patchwork.freedesktop.org/series/133704/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14775 -> Patchwork_133704v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/index.html
Participating hosts (41 -> 42)
--
Additional (3): bat-jsl-3 bat-jsl-1 bat-arls-3
Missing(2): bat-dg2-11 fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_133704v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- {bat-mtlp-9}: [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-6:
- {bat-mtlp-9}: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-6.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-6.html
Known issues
Here are the changes found in Patchwork_133704v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-jsl-3: NOTRUN -> [SKIP][5] ([i915#9318])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html
- bat-jsl-1: NOTRUN -> [SKIP][6] ([i915#9318])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-3: NOTRUN -> [SKIP][7] ([i915#2190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-3/igt@gem_huc_c...@huc-copy.html
- bat-jsl-1: NOTRUN -> [SKIP][8] ([i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-1/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-jsl-3: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-3/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9: [PASS][10] -> [FAIL][11] ([i915#10378])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-jsl-1: NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-1/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_module_load@load:
- bat-arls-3: NOTRUN -> [ABORT][13] ([i915#11041])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-arls-3/igt@i915_module_l...@load.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3: NOTRUN -> [SKIP][14] ([i915#4103]) +1 other test skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-1: NOTRUN -> [SKIP][15] ([i915#4103]) +1 other test skip
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-jsl-3: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#9886])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-3/igt@kms_...@dsc-basic.html
- bat-jsl-1: NOTRUN -> [SKIP][17] ([i915#3555] / [i915#9886])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-1/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3: NOTRUN -> [SKIP][18]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-3/igt@kms_force_connector_ba...@force-load-detect.html
- bat-jsl-1: NOTRUN -> [SKIP][19]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133704v1/bat-jsl-1/igt@kms_force_connector_ba...@force-load-detect.html
*
[PATCH] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+
From: Ville Syrjälä Bspec lists the mas TMDS bitrate as 6 Gbps on ADL/DG2. Bump our limit to match. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 0faf2afa1c09..bd0ba4edcd1d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1784,7 +1784,9 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int max_tmds_clock, vbt_max_tmds_clock; - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(dev_priv) >= 13) + max_tmds_clock = 60; + else if (DISPLAY_VER(dev_priv) >= 10) max_tmds_clock = 594000; else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) max_tmds_clock = 30; -- 2.44.1
✗ Fi.CI.BUILD: failure for tracing/treewide: Remove second parameter of __assign_str() (rev3)
== Series Details == Series: tracing/treewide: Remove second parameter of __assign_str() (rev3) URL : https://patchwork.freedesktop.org/series/130320/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/130320/revisions/3/mbox/ not applied Applying: tracing/treewide: Remove second parameter of __assign_str() Using index info to reconstruct a base tree... M drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_trace.h M drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_trace.h M drivers/thermal/thermal_trace.h M fs/smb/client/trace.h M include/trace/events/btrfs.h M include/trace/events/sched.h M net/wireless/trace.h Falling back to patching base and 3-way merge... Auto-merging net/wireless/trace.h Auto-merging include/trace/events/sched.h CONFLICT (content): Merge conflict in include/trace/events/sched.h Auto-merging include/trace/events/btrfs.h Auto-merging fs/smb/client/trace.h Auto-merging drivers/thermal/thermal_trace.h Auto-merging drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_trace.h CONFLICT (content): Merge conflict in drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_trace.h Auto-merging drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_trace.h CONFLICT (content): Merge conflict in drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_trace.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 tracing/treewide: Remove second parameter of __assign_str() When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
✗ Fi.CI.BAT: failure for drm/i915: Plane register cleanups
== Series Details == Series: drm/i915: Plane register cleanups URL : https://patchwork.freedesktop.org/series/133701/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14775 -> Patchwork_133701v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_133701v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_133701v1, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/index.html Participating hosts (41 -> 41) -- Additional (2): fi-elk-e7500 bat-arls-3 Missing(2): bat-dg2-11 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_133701v1: ### IGT changes ### Possible regressions * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-dp-1: - bat-adlp-9: [PASS][1] -> [FAIL][2] +3 other tests fail [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-adlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-dp-1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-adlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-dp-1.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-dp-3: - bat-arls-3: NOTRUN -> [FAIL][3] +3 other tests fail [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-dp-3.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1: - fi-tgl-1115g4: [PASS][4] -> [DMESG-FAIL][5] +3 other tests dmesg-fail [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/fi-tgl-1115g4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-hdmi-a-1.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/fi-tgl-1115g4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-hdmi-a-1.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-1: - bat-adls-6: [PASS][6] -> [FAIL][7] +3 other tests fail [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-adls-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-dp-1.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-adls-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-dp-1.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-1: - fi-rkl-11600: [PASS][8] -> [FAIL][9] +2 other tests fail [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-hdmi-a-1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-hdmi-a-1.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-3: - bat-adlp-6: [PASS][10] -> [FAIL][11] +3 other tests fail [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-dp-3.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-dp-3.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1: - bat-adln-1: [PASS][12] -> [FAIL][13] +2 other tests fail [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-adln-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-edp-1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-adln-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-edp-1.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-hdmi-a-2: - bat-arls-1: [PASS][14] -> [FAIL][15] +3 other tests fail [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-arls-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-hdmi-a-2.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-hdmi-a-2.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1: - bat-arls-2: [PASS][16] -> [FAIL][17] +3 other tests fail [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-arls-2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-d-edp-1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-d-edp-1.html - bat-mtlp-8: [PASS][18] -> [FAIL][19] +3 other tests fail [18]:
✓ Fi.CI.BAT: success for ACPI: video: Fix name collision with architecture's video.o
== Series Details == Series: ACPI: video: Fix name collision with architecture's video.o URL : https://patchwork.freedesktop.org/series/133694/ State : success == Summary == CI Bug Log - changes from CI_DRM_14775 -> Patchwork_133694v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/index.html Participating hosts (41 -> 41) -- Additional (4): fi-elk-e7500 bat-jsl-3 bat-jsl-1 bat-arls-3 Missing(4): bat-adlp-9 bat-mtlp-9 fi-snb-2520m fi-kbl-8809g Known issues Here are the changes found in Patchwork_133694v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-jsl-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html - bat-jsl-1: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html - bat-arls-3: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - bat-jsl-1: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-jsl-1/igt@gem_huc_c...@huc-copy.html - bat-jsl-3: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-jsl-3/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - bat-jsl-3: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-jsl-3/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][7] ([i915#10213]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-jsl-1: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10197] / [i915#10211] / [i915#4079]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10196] / [i915#4077]) +2 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10206] / [i915#4079]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10209]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10200]) +9 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10202]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-jsl-3: NOTRUN -> [SKIP][16] ([i915#4103]) +1 other test skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-jsl-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-jsl-1: NOTRUN -> [SKIP][17] ([i915#4103]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#9886]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-arls-3/igt@kms_...@dsc-basic.html - bat-jsl-1: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#9886]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133694v1/bat-jsl-1/igt@kms_...@dsc-basic.html -
[PATCH] drm/probe-helper: Call drm_mode_validate_ycbcr420() before connector->mode_valid()
From: Ville Syrjälä
Make life easier for drivers by filtering out unwanted YCbCr 4:2:0
only modes prior to calling the connector->mode_valid() hook.
Currently drivers will still see YCbCr 4:2:0 only modes in said
hook, which will likely come as a suprise when the driver has
declared no support for such modes (via setting
connector->ycbcr_420_allowed to false).
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10992
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_probe_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_probe_helper.c
b/drivers/gpu/drm/drm_probe_helper.c
index 4f75a1cfd820..249c8c2cb319 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -474,6 +474,10 @@ static int __drm_helper_update_and_validate(struct
drm_connector *connector,
if (mode->status != MODE_OK)
continue;
+ mode->status = drm_mode_validate_ycbcr420(mode, connector);
+ if (mode->status != MODE_OK)
+ continue;
+
ret = drm_mode_validate_pipeline(mode, connector, ctx,
>status);
if (ret) {
@@ -486,10 +490,6 @@ static int __drm_helper_update_and_validate(struct
drm_connector *connector,
else
return -EDEADLK;
}
-
- if (mode->status != MODE_OK)
- continue;
- mode->status = drm_mode_validate_ycbcr420(mode, connector);
}
return 0;
--
2.44.1
✓ Fi.CI.BAT: success for Panel Replay eDP support
== Series Details ==
Series: Panel Replay eDP support
URL : https://patchwork.freedesktop.org/series/133684/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14775 -> Patchwork_133684v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v1/index.html
Participating hosts (41 -> 36)
--
Missing(5): fi-snb-2520m fi-glk-j4005 fi-cfl-8109u fi-kbl-8809g
bat-arls-1
Known issues
Here are the changes found in Patchwork_133684v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-bsw-nick:[PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/fi-bsw-nick/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v1/fi-bsw-nick/igt@i915_pm_...@module-reload.html
Possible fixes
* igt@core_auth@basic-auth:
- {bat-apl-1}:[DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-apl-1/igt@core_a...@basic-auth.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v1/bat-apl-1/igt@core_a...@basic-auth.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
Build changes
-
* Linux: CI_DRM_14775 -> Patchwork_133684v1
CI-20190529: 20190529
CI_DRM_14775: 3b6a503228b84c010794599203ac3e1e3d349bab @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7858: 133c90d6aabcd90871e36946317c90ee83c2f847 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133684v1: 3b6a503228b84c010794599203ac3e1e3d349bab @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133684v1/index.html
RE: [PATCH] drm/i915/selftests: Set always_coherent to false when reading from CPU
-Original Message-
From: Das, Nirmoy
Sent: Thursday, May 16, 2024 8:14 AM
To: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org; Das, Nirmoy ; Andi
Shyti ; Janusz Krzysztofik
; Cavitt, Jonathan
Subject: [PATCH] drm/i915/selftests: Set always_coherent to false when reading
from CPU
>
> The previous commit 'commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick
> correct caching mode.")' was not complete as for non LLC sharing platforms
> cpu read can happen from LLC which probably doesn't have the latest
> changes made by GPU.
>
> Cc: Andi Shyti
> Cc: Janusz Krzysztofik
> Cc: Jonathan Cavitt
> Signed-off-by: Nirmoy Das
I see no problem with this
Reviewed-by: Jonathan Cavitt
-Jonathan Cavitt
> ---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> index 65a931ea80e9..3527b8f446fe 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> @@ -196,7 +196,7 @@ static int verify_access(struct drm_i915_private *i915,
> if (err)
> goto out_file;
>
> - mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true);
> + mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false);
> vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode);
> if (IS_ERR(vaddr)) {
> err = PTR_ERR(vaddr);
> --
> 2.42.0
>
>
[PATCH] drm/i915/selftests: Set always_coherent to false when reading from CPU
The previous commit 'commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick
correct caching mode.")' was not complete as for non LLC sharing platforms
cpu read can happen from LLC which probably doesn't have the latest
changes made by GPU.
Cc: Andi Shyti
Cc: Janusz Krzysztofik
Cc: Jonathan Cavitt
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
index 65a931ea80e9..3527b8f446fe 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
@@ -196,7 +196,7 @@ static int verify_access(struct drm_i915_private *i915,
if (err)
goto out_file;
- mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true);
+ mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false);
vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode);
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
--
2.42.0
Re: [PATCH] ACPI: video: Fix name collision with architecture's video.o
Hi,
On 5/16/24 5:11 PM, Thomas Zimmermann wrote:
> Hi
>
> Am 16.05.24 um 17:03 schrieb Hans de Goede:
>> Hi,
>>
>> On 5/16/24 3:04 PM, Rafael J. Wysocki wrote:
>>> CC Hans who has been doing the majority of the ACPI video work.
>>>
>>> On Thu, May 16, 2024 at 2:43 PM Thomas Zimmermann
>>> wrote:
Commit 2fd001cd3600 ("arch: Rename fbdev header and source files")
renames the video source files under arch/ such that they does not
refer to fbdev any longer. The new files named video.o conflict with
ACPI's video.ko module.
>>> And surely nobody knew or was unable to check upfront that there was a
>>> video.ko already in the kernel.
>> Sorry, but nack for this change. I very deliberately kept the module-name
>> as video when renaming the actual .c file from video.c to acpi_video.c
>> because many people pass drivers/video/acpi_video.c module arguments
>> on the kernel commandline using video.param=val .
>>
>> Try e.g. doing a duckduckgo search for 1 off:
>>
>> "video.only_lcd"
>> "video.allow_duplicates"
>> "video.brightness_switch_enabled"
>
> Ok, that makes sense. I'll rename the other files.
Great, thank you.
Regards,
Hans
Re: [PATCH] ACPI: video: Fix name collision with architecture's video.o
Hi
Am 16.05.24 um 17:03 schrieb Hans de Goede:
Hi,
On 5/16/24 3:04 PM, Rafael J. Wysocki wrote:
CC Hans who has been doing the majority of the ACPI video work.
On Thu, May 16, 2024 at 2:43 PM Thomas Zimmermann wrote:
Commit 2fd001cd3600 ("arch: Rename fbdev header and source files")
renames the video source files under arch/ such that they does not
refer to fbdev any longer. The new files named video.o conflict with
ACPI's video.ko module.
And surely nobody knew or was unable to check upfront that there was a
video.ko already in the kernel.
Sorry, but nack for this change. I very deliberately kept the module-name
as video when renaming the actual .c file from video.c to acpi_video.c
because many people pass drivers/video/acpi_video.c module arguments
on the kernel commandline using video.param=val .
Try e.g. doing a duckduckgo search for 1 off:
"video.only_lcd"
"video.allow_duplicates"
"video.brightness_switch_enabled"
Ok, that makes sense. I'll rename the other files.
Best regards
Thomas
And you will find a lot of hits. The last one is even documented as
being "video.brightness_switch_enabled" in the main kernel-parameters.txt
as well as separately:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/admin-guide/kernel-parameters.txt#n39
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/admin-guide/kernel-parameters.txt#n7152
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/firmware-guide/acpi/video_extension.rst#n118
https://wiki.archlinux.org/title/Lenovo_ThinkPad_X1_Carbon#Brightness_control
If you rename this module then peoples config will break for
a whole lot of users.
So lets not do that and lets rename the new module which is causing
the conflict in the first place instead.
Regards,
Hans
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
Re: [PATCH] ACPI: video: Fix name collision with architecture's video.o
Hi,
On 5/16/24 3:04 PM, Rafael J. Wysocki wrote:
> CC Hans who has been doing the majority of the ACPI video work.
>
> On Thu, May 16, 2024 at 2:43 PM Thomas Zimmermann wrote:
>>
>> Commit 2fd001cd3600 ("arch: Rename fbdev header and source files")
>> renames the video source files under arch/ such that they does not
>> refer to fbdev any longer. The new files named video.o conflict with
>> ACPI's video.ko module.
>
> And surely nobody knew or was unable to check upfront that there was a
> video.ko already in the kernel.
Sorry, but nack for this change. I very deliberately kept the module-name
as video when renaming the actual .c file from video.c to acpi_video.c
because many people pass drivers/video/acpi_video.c module arguments
on the kernel commandline using video.param=val .
Try e.g. doing a duckduckgo search for 1 off:
"video.only_lcd"
"video.allow_duplicates"
"video.brightness_switch_enabled"
And you will find a lot of hits. The last one is even documented as
being "video.brightness_switch_enabled" in the main kernel-parameters.txt
as well as separately:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/admin-guide/kernel-parameters.txt#n39
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/admin-guide/kernel-parameters.txt#n7152
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/firmware-guide/acpi/video_extension.rst#n118
https://wiki.archlinux.org/title/Lenovo_ThinkPad_X1_Carbon#Brightness_control
If you rename this module then peoples config will break for
a whole lot of users.
So lets not do that and lets rename the new module which is causing
the conflict in the first place instead.
Regards,
Hans
[PULL] drm-misc-next-fixes
drm-misc-next-fixes-2024-05-16: drm-misc-next-fixes for v6.10-rc1: - VM_BIND fix for nouveau. - Lots of panthor fixes: * Fixes for panthor's heap logical block. * Reset on unrecoverable fault * Fix VM references. * Reset fix. - xlnx compile and doc fixes. The following changes since commit be3f3042391d061cfca2bd22630e0d101acea5fc: drm: zynqmp_dpsub: Always register bridge (2024-05-02 23:40:56 +0200) are available in the Git repository at: https://gitlab.freedesktop.org/drm/misc/kernel.git tags/drm-misc-next-fixes-2024-05-16 for you to fetch changes up to 959314c438caf1b62d787f02d54a193efda38880: drm/nouveau: use tile_mode and pte_kind for VM_BIND bo allocations (2024-05-13 22:27:33 +0200) drm-misc-next-fixes for v6.10-rc1: - VM_BIND fix for nouveau. - Lots of panthor fixes: * Fixes for panthor's heap logical block. * Reset on unrecoverable fault * Fix VM references. * Reset fix. - xlnx compile and doc fixes. Anatoliy Klymenko (2): drm: xlnx: zynqmp_dpsub: Fix few function comments drm: xlnx: zynqmp_dpsub: Fix compilation error Antonino Maniscalco (1): drm/panthor: Fix tiler OOM handling to allow incremental rendering Boris Brezillon (8): drm/panthor: Make sure the tiler initial/max chunks are consistent drm/panthor: Relax the constraints on the tiler chunk size drm/panthor: Fix an off-by-one in the heap context retrieval logic drm/panthor: Document drm_panthor_tiler_heap_destroy::handle validity constraints drm/panthor: Force an immediate reset on unrecoverable faults drm/panthor: Keep a ref to the VM at the panthor_kernel_bo level drm/panthor: Reset the FW VM to NULL on unplug drm/panthor: Call panthor_sched_post_reset() even if the reset failed Mohamed Ahmed (1): drm/nouveau: use tile_mode and pte_kind for VM_BIND bo allocations drivers/gpu/drm/nouveau/nouveau_abi16.c | 3 ++ drivers/gpu/drm/nouveau/nouveau_bo.c | 44 + drivers/gpu/drm/panthor/panthor_device.c | 8 ++ drivers/gpu/drm/panthor/panthor_device.h | 1 + drivers/gpu/drm/panthor/panthor_fw.c | 5 ++-- drivers/gpu/drm/panthor/panthor_gem.c| 8 -- drivers/gpu/drm/panthor/panthor_gem.h| 8 -- drivers/gpu/drm/panthor/panthor_heap.c | 36 ++-- drivers/gpu/drm/panthor/panthor_sched.c | 48 +++- drivers/gpu/drm/panthor/panthor_sched.h | 2 +- drivers/gpu/drm/xlnx/zynqmp_disp.c | 6 ++-- include/uapi/drm/nouveau_drm.h | 7 + include/uapi/drm/panthor_drm.h | 20 ++--- 13 files changed, 123 insertions(+), 73 deletions(-)
✗ Fi.CI.SPARSE: warning for drm/i915: Plane register cleanups
== Series Details == Series: drm/i915: Plane register cleanups URL : https://patchwork.freedesktop.org/series/133701/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups
== Series Details == Series: drm/i915: Plane register cleanups URL : https://patchwork.freedesktop.org/series/133701/ State : warning == Summary == Error: dim checkpatch failed 2cd1d3b16e64 drm/i915: Add skl+ plane name aliases to enum plane_id ad5e92ec05c2 drm/i915: Clean up the cursor register defines 7220bc7c82e0 drm/i915: Add separate define for SEL_FETCH_CUR_CTL() 9477d75d613a drm/i915: Simplify PIPESRC_ERLY_TPT definition -:54: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #54: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:252: +#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) total: 0 errors, 1 warnings, 0 checks, 26 lines checked bb31d70432ff drm/i915: Rename selective fetch plane registers d6e1c598110f drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES() -:90: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20: +#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20: +#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ + _PICK_EVEN_2RANGES((plane), PLANE_5, \ + _PIPE((pipe), (reg_1_a), (reg_1_b)), \ + _PIPE((pipe), (reg_2_a), (reg_2_b)), \ + _PIPE((pipe), (reg_5_a), (reg_5_b)), \ + _PIPE((pipe), (reg_6_a), (reg_6_b))) -:96: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #96: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:26: +#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ -:117: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #117: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:390: + _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \ -:118: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #118: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:391: + _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \ -:119: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #119: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:392: + _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \ -:120: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #120: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:393: + _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B) -:132: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #132: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:405: + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ -:133: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #133: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:406: + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ -:134: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #134: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:407: + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ -:135: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #135: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:408: + _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B) -:146: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #146: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:419: + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ -:147: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #147: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:420: + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ -:148: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #148: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:421: + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ -:149: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #149: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:422: + _SEL_FETCH_PLANE_POS_6_A,
[PATCH 12/13] drm/i915: Polish sprite plane register definitions
From: Ville Syrjälä Group the sprite plane register definitions such that everything to do wiht the same register is in one place. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++ 1 file changed, 134 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h index bb67705652b2..c27adbaf0f00 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h @@ -7,6 +7,8 @@ #include "intel_display_reg_defs.h" #define _DVSACNTR 0x72180 +#define _DVSBCNTR 0x73180 +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) #define DVS_ENABLE REG_BIT(31) #define DVS_PIPE_GAMMA_ENABLEREG_BIT(30) #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) @@ -28,31 +30,67 @@ #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) #define DVS_TILEDREG_BIT(10) #define DVS_DEST_KEY REG_BIT(2) + #define _DVSALINOFF0x72184 +#define _DVSBLINOFF0x73184 +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) + #define _DVSASTRIDE0x72188 +#define _DVSBSTRIDE0x73188 +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) + #define _DVSAPOS 0x7218c +#define _DVSBPOS 0x7318c +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) #define DVS_POS_Y_MASK REG_GENMASK(31, 16) #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) #define DVS_POS_X_MASK REG_GENMASK(15, 0) #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) + #define _DVSASIZE 0x72190 +#define _DVSBSIZE 0x73190 +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) #define DVS_HEIGHT(h)REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) #define DVS_WIDTH_MASK REG_GENMASK(15, 0) #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) + #define _DVSAKEYVAL0x72194 +#define _DVSBKEYVAL0x73194 +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) + #define _DVSAKEYMSK0x72198 +#define _DVSBKEYMSK0x73198 +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) + #define _DVSASURF 0x7219c +#define _DVSBSURF 0x7319c +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) #define DVS_ADDR_MASKREG_GENMASK(31, 12) + #define _DVSAKEYMAXVAL 0x721a0 +#define _DVSBKEYMAXVAL 0x731a0 +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) + #define _DVSATILEOFF 0x721a4 +#define _DVSBTILEOFF 0x731a4 +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) #define DVS_OFFSET_Y_MASKREG_GENMASK(31, 16) #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) #define DVS_OFFSET_X_MASKREG_GENMASK(15, 0) #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) + #define _DVSASURFLIVE 0x721ac +#define _DVSBSURFLIVE 0x731ac +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) + #define _DVSAGAMC_G4X 0x721e0 /* g4x */ +#define _DVSBGAMC_G4X 0x731e0 /* g4x */ +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ + #define _DVSASCALE 0x72204 +#define _DVSBSCALE 0x73204 +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) #define DVS_SCALE_ENABLE REG_BIT(31) #define DVS_FILTER_MASK REG_GENMASK(30, 29) #define DVS_FILTER_MEDIUMREG_FIELD_PREP(DVS_FILTER_MASK, 0) @@ -64,42 +102,18 @@ #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) #define DVS_SRC_HEIGHT(h)REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) + #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ -#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ - -#define _DVSBCNTR 0x73180 -#define _DVSBLINOFF0x73184 -#define _DVSBSTRIDE0x73188 -#define _DVSBPOS 0x7318c -#define _DVSBSIZE 0x73190 -#define _DVSBKEYVAL0x73194 -#define _DVSBKEYMSK0x73198 -#define _DVSBSURF 0x7319c -#define _DVSBKEYMAXVAL 0x731a0 -#define _DVSBTILEOFF 0x731a4 -#define _DVSBSURFLIVE 0x731ac -#define _DVSBGAMC_G4X 0x731e0 /* g4x */ -#define _DVSBSCALE 0x73204 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ -#define
[PATCH 13/13] drm/i915: Document which platforms use which sprite registers
From: Ville Syrjälä Note which sprite registers are valid for which platforms. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_sprite_regs.h | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h index c27adbaf0f00..73021e3ced6d 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h @@ -6,6 +6,7 @@ #include "intel_display_reg_defs.h" +/* g4x/ilk/snb video sprite */ #define _DVSACNTR 0x72180 #define _DVSBCNTR 0x73180 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) @@ -111,6 +112,7 @@ #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ +/* ivb/hsw/bdw sprite */ #define _SPRA_CTL 0x70280 #define _SPRB_CTL 0x71280 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) @@ -140,8 +142,8 @@ #define SPRITE_TILED REG_BIT(10) #define SPRITE_DEST_KEY REG_BIT(2) -#define _SPRA_LINOFF 0x70284 -#define _SPRB_LINOFF 0x71284 +#define _SPRA_LINOFF 0x70284 /* ivb */ +#define _SPRB_LINOFF 0x71284 /* ivb */ #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) #define _SPRA_STRIDE 0x70288 @@ -181,24 +183,24 @@ #define _SPRB_KEYMAX 0x712a0 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) -#define _SPRA_TILEOFF 0x702a4 -#define _SPRB_TILEOFF 0x712a4 +#define _SPRA_TILEOFF 0x702a4 /* ivb */ +#define _SPRB_TILEOFF 0x712a4 /* ivb */ #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) -#define _SPRA_OFFSET 0x702a4 -#define _SPRB_OFFSET 0x712a4 +#define _SPRA_OFFSET 0x702a4 /* hsw/bdw */ +#define _SPRB_OFFSET 0x712a4 /* hsw/bdw */ #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) #define _SPRA_SURFLIVE 0x702ac #define _SPRB_SURFLIVE 0x712ac #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) -#define _SPRA_SCALE0x70304 -#define _SPRB_SCALE0x71304 +#define _SPRA_SCALE0x70304 /* ivb */ +#define _SPRB_SCALE0x71304 /* ivb */ #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) #define SPRITE_SCALE_ENABLE REG_BIT(31) #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) @@ -224,6 +226,7 @@ #define _SPRB_GAMC17 0x7144c #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ +/* vlv/chv sprite */ #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ -- 2.44.1
[PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h
From: Ville Syrjälä Relocate all pre-skl primary plane register definitions into their own declutter i915_reg.h. Cc: Zhenyu Wang Cc: Zhi Wang Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 1 + .../gpu/drm/i915/display/i9xx_plane_regs.h| 98 +++ .../gpu/drm/i915/display/intel_atomic_plane.c | 1 + drivers/gpu/drm/i915/display/intel_color.c| 2 +- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_fbc.c | 1 + drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/display.c| 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 87 +--- drivers/gpu/drm/i915/intel_clock_gating.c | 1 + drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 13 files changed, 110 insertions(+), 87 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index ea4d8ba55ad8..1f05f9184cb2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -10,6 +10,7 @@ #include "i915_reg.h" #include "i9xx_plane.h" +#include "i9xx_plane_regs.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_de.h" diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h new file mode 100644 index ..0bf2cd42bce7 --- /dev/null +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __I9XX_PLANE_REGS_H__ +#define __I9XX_PLANE_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define _DSPAADDR_VLV 0x7017C /* vlv/chv */ +#define _DSPACNTR 0x70180 +#define DISP_ENABLE REG_BIT(31) +#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) +#define DISP_FORMAT_MASK REG_GENMASK(29, 26) +#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) +#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) +#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) +#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) +#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) +#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) +#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) +#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) +#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) +#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) +#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) +#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) +#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) +#define DISP_STEREO_ENABLE REG_BIT(25) +#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ +#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) +#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) +#define DISP_SRC_KEY_ENABLE REG_BIT(22) +#define DISP_LINE_DOUBLE REG_BIT(20) +#define DISP_STEREO_POLARITY_SECOND REG_BIT(18) +#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ +#define DISP_ROTATE_180 REG_BIT(15) +#define DISP_TRICKLE_FEED_DISABLEREG_BIT(14) /* g4x+ */ +#define DISP_TILED REG_BIT(10) +#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ +#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ +#define _DSPAADDR 0x70184 +#define _DSPASTRIDE0x70188 +#define _DSPAPOS 0x7018C /* reserved */ +#define DISP_POS_Y_MASK REG_GENMASK(31, 16) +#define DISP_POS_Y(y)REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) +#define DISP_POS_X_MASK REG_GENMASK(15, 0) +#define DISP_POS_X(x)REG_FIELD_PREP(DISP_POS_X_MASK, (x)) +#define _DSPASIZE 0x70190 +#define DISP_HEIGHT_MASK REG_GENMASK(31, 16) +#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) +#define DISP_WIDTH_MASK REG_GENMASK(15, 0) +#define DISP_WIDTH(w)REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) +#define _DSPASURF 0x7019C /* 965+ only */ +#define DISP_ADDR_MASK REG_GENMASK(31, 12) +#define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define
[PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies
From: Ville Syrjälä Add some notes indicatign which plane registers/bits are valid for which platforms. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/i9xx_plane_regs.h| 22 +-- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 929b26faf31e..d74a74d1f29a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -37,53 +37,53 @@ #define DISP_LINE_DOUBLE REG_BIT(20) #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ -#define DISP_ROTATE_180 REG_BIT(15) +#define DISP_ROTATE_180 REG_BIT(15) /* i965+ */ #define DISP_TRICKLE_FEED_DISABLEREG_BIT(14) /* g4x+ */ -#define DISP_TILED REG_BIT(10) +#define DISP_TILED REG_BIT(10) /* i965+ */ #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ -#define _DSPAADDR 0x70184 +#define _DSPAADDR 0x70184 /* pre-i965 */ #define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) -#define _DSPALINOFF0x70184 +#define _DSPALINOFF0x70184 /* i965+ */ #define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) #define _DSPASTRIDE0x70188 #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) -#define _DSPAPOS 0x7018C /* reserved */ +#define _DSPAPOS 0x7018C /* pre-g4x */ #define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) #define DISP_POS_Y_MASK REG_GENMASK(31, 16) #define DISP_POS_Y(y)REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) #define DISP_POS_X_MASK REG_GENMASK(15, 0) #define DISP_POS_X(x)REG_FIELD_PREP(DISP_POS_X_MASK, (x)) -#define _DSPASIZE 0x70190 +#define _DSPASIZE 0x70190 /* pre-g4x */ #define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) #define DISP_WIDTH_MASK REG_GENMASK(15, 0) #define DISP_WIDTH(w)REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) -#define _DSPASURF 0x7019C /* 965+ only */ +#define _DSPASURF 0x7019C /* i965+ */ #define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) #define DISP_ADDR_MASK REG_GENMASK(31, 12) -#define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define _DSPATILEOFF 0x701A4 /* i965+ */ #define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) -#define _DSPAOFFSET0x701A4 /* HSW */ +#define _DSPAOFFSET0x701A4 /* hsw+ */ #define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) -#define _DSPASURFLIVE 0x701AC +#define _DSPASURFLIVE 0x701AC /* g4x+ */ #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) -#define _DSPAGAMC 0x701E0 +#define _DSPAGAMC 0x701E0 /* pre-g4x */ #define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ -- 2.44.1
[PATCH 10/13] drm/i915: Polish pre-skl primary plane registers
From: Ville Syrjälä Group the pre-skl primary plane register definitions sensible, and toss in a few comments to indicate which platforms have what. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/i9xx_plane_regs.h| 46 --- 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 0bf2cd42bce7..929b26faf31e 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -9,7 +9,10 @@ #include "intel_display_reg_defs.h" #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ +#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) + #define _DSPACNTR 0x70180 +#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) #define DISP_ENABLE REG_BIT(31) #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) #define DISP_FORMAT_MASK REG_GENMASK(29, 26) @@ -39,60 +42,69 @@ #define DISP_TILED REG_BIT(10) #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ + #define _DSPAADDR 0x70184 +#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) + +#define _DSPALINOFF0x70184 +#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) + #define _DSPASTRIDE0x70188 +#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) + #define _DSPAPOS 0x7018C /* reserved */ +#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) #define DISP_POS_Y_MASK REG_GENMASK(31, 16) #define DISP_POS_Y(y)REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) #define DISP_POS_X_MASK REG_GENMASK(15, 0) #define DISP_POS_X(x)REG_FIELD_PREP(DISP_POS_X_MASK, (x)) + #define _DSPASIZE 0x70190 +#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) #define DISP_WIDTH_MASK REG_GENMASK(15, 0) #define DISP_WIDTH(w)REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) + #define _DSPASURF 0x7019C /* 965+ only */ +#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) #define DISP_ADDR_MASK REG_GENMASK(31, 12) + #define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) + #define _DSPAOFFSET0x701A4 /* HSW */ +#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) + #define _DSPASURFLIVE 0x701AC +#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) + #define _DSPAGAMC 0x701E0 - -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) -#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) -#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) -#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) -#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) -#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) -#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) -#define DSPLINOFF(plane) DSPADDR(plane) -#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) -#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) -#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ +#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ #define _PRIMPOS_A 0x60a08 +#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) #define PRIM_POS_Y(y)REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) #define
[PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h
From: Ville Syrjälä PIPEGCMAX was left behind when all other gamma registers moved into intel_color_regs.h. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color_regs.h | 5 + drivers/gpu/drm/i915/i915_reg.h | 4 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h index bb99ea533842..61c18b4a7fa5 100644 --- a/drivers/gpu/drm/i915/display/intel_color_regs.h +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -36,6 +36,11 @@ _CHV_PALETTE_C, _CHV_PALETTE_C) + \ (i) * 4) +/* i965/g4x/vlv/chv */ +#define _PIPEAGCMAX 0x70010 +#define _PIPEBGCMAX 0x71010 +#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ + /* ilk+ palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 52b029cd3981..f5e8833cc37e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1882,10 +1882,6 @@ #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) -#define _PIPEAGCMAX 0x70010 -#define _PIPEBGCMAX 0x71010 -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ - #define _PIPE_ARB_CTL_A0x70028 /* icl+ */ #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) -- 2.44.1
[PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits
From: Ville Syrjälä
Make a more thorough split between universal planes vs. cursors
by defining the contents of the cursor WM/DDB registers separately.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 34 +++
.../gpu/drm/i915/display/intel_cursor_regs.h | 9 +
.../drm/i915/display/skl_universal_plane.c| 4 +--
.../drm/i915/display/skl_universal_plane.h| 3 --
4 files changed, 39 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 7983cbaf83f7..cea0cfed569d 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -24,7 +24,6 @@
#include "intel_psr.h"
#include "intel_psr_regs.h"
#include "intel_vblank.h"
-#include "skl_universal_plane.h"
#include "skl_watermark.h"
#include "gem/i915_gem_object.h"
@@ -559,6 +558,29 @@ static void i9xx_cursor_update_sel_fetch_arm(struct
intel_plane *plane,
}
}
+static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+ if (!entry->end)
+ return 0;
+
+ return CUR_BUF_END(entry->end - 1) |
+ CUR_BUF_START(entry->start);
+}
+
+static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
+{
+ u32 val = 0;
+
+ if (level->enable)
+ val |= CUR_WM_EN;
+ if (level->ignore_lines)
+ val |= CUR_WM_IGNORE_LINES;
+ val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
+ val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
+
+ return val;
+}
+
static void skl_write_cursor_wm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@@ -572,22 +594,22 @@ static void skl_write_cursor_wm(struct intel_plane *plane,
for (level = 0; level < i915->display.wm.num_levels; level++)
intel_de_write_fw(i915, CUR_WM(pipe, level),
-
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+
skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
- skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
plane_id)));
+ skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm,
plane_id)));
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = _wm->planes[plane_id];
intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
- skl_plane_wm_reg_val(>sagv.wm0));
+ skl_cursor_wm_reg_val(>sagv.wm0));
intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
- skl_plane_wm_reg_val(>sagv.trans_wm));
+ skl_cursor_wm_reg_val(>sagv.trans_wm));
}
intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
- skl_plane_ddb_reg_val(ddb));
+ skl_cursor_ddb_reg_val(ddb));
}
/* TODO: split into noarm+arm pair */
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index ab02d497fba6..307a850d54b6 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -78,6 +78,10 @@
#define _CUR_WM_A_00x70140
#define _CUR_WM_B_00x71140
#define CUR_WM(pipe, level)_MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) +
(level) * 4)
+#define CUR_WM_ENREG_BIT(31)
+#define CUR_WM_IGNORE_LINES REG_BIT(30)
+#define CUR_WM_LINES_MASKREG_GENMASK(26, 14)
+#define CUR_WM_BLOCKS_MASK REG_GENMASK(11, 0)
#define _CUR_WM_SAGV_A 0x70158
#define _CUR_WM_SAGV_B 0x71158
@@ -94,6 +98,11 @@
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A,
_CUR_BUF_CFG_B)
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define CUR_BUF_END_MASK REG_GENMASK(27, 16)
+#define CUR_BUF_END(end) REG_FIELD_PREP(CUR_BUF_END_MASK, (end))
+#define CUR_BUF_START_MASK REG_GENMASK(11, 0)
+#define CUR_BUF_START(start) REG_FIELD_PREP(CUR_BUF_START_MASK,
(start))
#define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
#define _SEL_FETCH_CUR_CTL_B 0x71880
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6601baf18ae4..de51652358c9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -622,7 +622,7 @@ static u32 skl_plane_stride(const struct intel_plane_state
*plane_state,
return stride / skl_plane_stride_mult(fb,
[PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
From: Ville Syrjälä Instead of that huge _PICK() let's use PICK_EVEN_2RANGES() for the SEL_FETCH_PLANE registers. A bit more tedious to have to define 8 raw register offsets for everything, but perhaps a bit easier to understand since we use a standard mechanism now instead of hand rolling the arithmetic. Also bloat-o-meter says: add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326) Function old new delta icl_plane_update_arm 510 446 -64 icl_plane_disable_sel_fetch_arm.isra 158 54-104 icl_plane_update_noarm 18981740-158 Total: Before=2574502, After=2574176, chg -0.01% Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_psr_regs.h | 45 .../i915/display/skl_universal_plane_regs.h | 68 +++ 2 files changed, 68 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index f0bd0a726d7a..289c371c98d1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -251,51 +251,6 @@ #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 #define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) -#define _SEL_FETCH_PLANE_BASE_1_A 0x70890 -#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 -#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 -#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 -#define _SEL_FETCH_PLANE_BASE_5_A 0x70920 -#define _SEL_FETCH_PLANE_BASE_6_A 0x70940 -#define _SEL_FETCH_PLANE_BASE_7_A 0x70960 -#define _SEL_FETCH_PLANE_BASE_CUR_A0x70880 -#define _SEL_FETCH_PLANE_BASE_1_B 0x71890 - -#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ -_SEL_FETCH_PLANE_BASE_1_A, \ -_SEL_FETCH_PLANE_BASE_2_A, \ -_SEL_FETCH_PLANE_BASE_3_A, \ -_SEL_FETCH_PLANE_BASE_4_A, \ -_SEL_FETCH_PLANE_BASE_5_A, \ -_SEL_FETCH_PLANE_BASE_6_A, \ -_SEL_FETCH_PLANE_BASE_7_A, \ -_SEL_FETCH_PLANE_BASE_CUR_A) -#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) -#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ - _SEL_FETCH_PLANE_BASE_1_A + \ - _SEL_FETCH_PLANE_BASE_A(plane)) - -#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 -#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ - _SEL_FETCH_PLANE_CTL_1_A - \ - _SEL_FETCH_PLANE_BASE_1_A) -#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) - -#define _SEL_FETCH_PLANE_POS_1_A 0x70894 -#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ - _SEL_FETCH_PLANE_POS_1_A - \ - _SEL_FETCH_PLANE_BASE_1_A) - -#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 -#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ - _SEL_FETCH_PLANE_SIZE_1_A - \ - _SEL_FETCH_PLANE_BASE_1_A) - -#define _SEL_FETCH_PLANE_OFFSET_1_A0x7089C -#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ - _SEL_FETCH_PLANE_OFFSET_1_A - \ - _SEL_FETCH_PLANE_BASE_1_A) - #define _ALPM_CTL_A0x60950 #define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A) #define ALPM_CTL_ALPM_ENABLE REG_BIT(31) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index cb3bdd71b6b2..a6528e0d719e 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -17,6 +17,17 @@ #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) +#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ + _PICK_EVEN_2RANGES((plane), PLANE_5, \ + _PIPE((pipe), (reg_1_a), (reg_1_b)), \ +
[PATCH 05/13] drm/i915: Rename selective fetch plane registers
From: Ville Syrjälä Rename the selective fetch plane registers to match the spec. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +- drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 47e3a2e2977c..f0bd0a726d7a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -276,23 +276,23 @@ _SEL_FETCH_PLANE_BASE_A(plane)) #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ +#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ _SEL_FETCH_PLANE_CTL_1_A - \ _SEL_FETCH_PLANE_BASE_1_A) -#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) +#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) #define _SEL_FETCH_PLANE_POS_1_A 0x70894 -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ +#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ _SEL_FETCH_PLANE_POS_1_A - \ _SEL_FETCH_PLANE_BASE_1_A) #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 -#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ +#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ _SEL_FETCH_PLANE_SIZE_1_A - \ _SEL_FETCH_PLANE_BASE_1_A) #define _SEL_FETCH_PLANE_OFFSET_1_A0x7089C -#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ +#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ _SEL_FETCH_PLANE_OFFSET_1_A - \ _SEL_FETCH_PLANE_BASE_1_A) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index d0bfee2ca643..6601baf18ae4 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -705,7 +705,7 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane, if (!crtc_state->enable_psr2_sel_fetch) return; - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); } static void @@ -1304,7 +1304,7 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane, val = (clip->y1 + plane_state->uapi.dst.y1) << 16; val |= plane_state->uapi.dst.x1; - intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val); + intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val); x = plane_state->view.color_plane[color_plane].x; @@ -1319,13 +1319,13 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane, val = y << 16 | x; - intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), + intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val); /* Sizes are 0 based */ val = (drm_rect_height(clip) - 1) << 16; val |= (drm_rect_width(_state->uapi.src) >> 16) - 1; - intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); + intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val); } static void @@ -1414,8 +1414,8 @@ static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane, return; if (drm_rect_height(_state->psr2_sel_fetch_area) > 0) - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), - PLANE_SEL_FETCH_CTL_ENABLE); + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), + SEL_FETCH_PLANE_CTL_ENABLE); else icl_plane_disable_sel_fetch_arm(plane, crtc_state); } -- 2.44.1
[PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
From: Ville Syrjälä PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7 range. so using _MMIO_TRANS2() for it is not really correct. Also since this is a pipe register, and not present on CHV, the registers will be equally spaced out, so we can use the simpler _MMIO_PIPE() instead of _MMIO_PIPE2(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index b44809899502..7983cbaf83f7 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -525,7 +525,7 @@ static void wa_16021440873(struct intel_plane *plane, intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl); - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe), + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe), PIPESRC_HEIGHT(et_y_position)); } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index df0d14a5023f..d49e869f6be2 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2381,7 +2381,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st if (!crtc_state->enable_psr2_su_region_et) return; - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe), + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), crtc_state->pipe_srcsz_early_tpt); } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index e14cb48f2614..47e3a2e2977c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -248,8 +248,8 @@ /* PSR2 Early transport */ #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 - -#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A) +#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 +#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 -- 2.44.1
[PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
From: Ville Syrjälä
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++---
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index c780ce146131..b44809899502 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct
intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
}
static void wa_16021440873(struct intel_plane *plane,
@@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
ctl &= ~MCURSOR_MODE_MASK;
ctl |= MCURSOR_MODE_64_2B;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
PIPESRC_HEIGHT(et_y_position));
@@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct
intel_plane *plane,
val);
}
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe,
plane->id),
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
plane_state->ctl);
} else {
/* Wa_16021440873 */
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 270c26c2e6df..ab02d497fba6 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -95,4 +95,9 @@
#define _CUR_BUF_CFG_B 0x7117c
#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A,
_CUR_BUF_CFG_B)
+#define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
+#define _SEL_FETCH_CUR_CTL_B 0x71880
+#define SEL_FETCH_CUR_CTL(pipe)_MMIO_PIPE((pipe),
_SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_A)
+#define SEL_FETCH_CUR_CTL_ENABLE REG_BIT(31)
+
#endif /* __INTEL_CURSOR_REGS_H__ */
--
2.44.1
[PATCH 02/13] drm/i915: Clean up the cursor register defines
From: Ville Syrjälä Group the cursor register defines such that everything to do with one register is in one place. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_cursor_regs.h | 52 +-- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index c2190af1e9f5..270c26c2e6df 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -9,6 +9,7 @@ #include "intel_display_reg_defs.h" #define _CURACNTR 0x70080 +#define CURCNTR(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR) /* Old style CUR*CNTR flags (desktop 8xx) */ #define CURSOR_ENABLEREG_BIT(31) #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) @@ -38,61 +39,60 @@ #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) + #define _CURABASE 0x70084 +#define CURBASE(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), _CURABASE) + #define _CURAPOS 0x70088 -#define _CURAPOS_ERLY_TPT 0x7008c +#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS) #define CURSOR_POS_Y_SIGNREG_BIT(31) #define CURSOR_POS_Y_MASKREG_GENMASK(30, 16) #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) #define CURSOR_POS_X_SIGNREG_BIT(15) #define CURSOR_POS_X_MASKREG_GENMASK(14, 0) #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) + +#define _CURAPOS_ERLY_TPT 0x7008c +#define CURPOS_ERLY_TPT(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT) + #define _CURASIZE 0x700a0 /* 845/865 */ +#define CURSIZE(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE) #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) #define CURSOR_WIDTH_MASKREG_GENMASK(9, 0) #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) + #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ +#define CUR_FBC_CTL(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A) #define CUR_FBC_EN REG_BIT(31) #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) #define CUR_FBC_HEIGHT(h)REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) + #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ +#define CUR_CHICKEN(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A) + #define _CURASURFLIVE 0x700ac /* g4x+ */ -#define _CURBCNTR 0x700c0 -#define _CURBBASE 0x700c4 -#define _CURBPOS 0x700c8 - -#define _CURBCNTR_IVB 0x71080 -#define _CURBBASE_IVB 0x71084 -#define _CURBPOS_IVB 0x71088 - -#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) -#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) -#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) -#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) -#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) -#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) -#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) -#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) +#define CURSURFLIVE(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE) /* skl+ */ #define _CUR_WM_A_00x70140 #define _CUR_WM_B_00x71140 +#define CUR_WM(pipe, level)_MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4) + #define _CUR_WM_SAGV_A 0x70158 #define _CUR_WM_SAGV_B 0x71158 +#define CUR_WM_SAGV(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) + #define _CUR_WM_SAGV_TRANS_A 0x7015C #define _CUR_WM_SAGV_TRANS_B 0x7115C +#define CUR_WM_SAGV_TRANS(pipe)_MMIO_PIPE((pipe), _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) + #define _CUR_WM_TRANS_A0x70168 #define _CUR_WM_TRANS_B0x71168 -#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) -#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) -#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) -#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) -#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) +#define CUR_WM_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) -/* skl+ */ -#define _CUR_BUF_CFG_A
[PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id
From: Ville Syrjälä
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 6 ++
drivers/gpu/drm/i915/display/intel_display.c | 8 +++
.../drm/i915/display/intel_display_limits.h | 21 ---
.../gpu/drm/i915/display/intel_sprite_uapi.c | 2 +-
.../drm/i915/display/skl_universal_plane.c| 19 -
5 files changed, 30 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 339010384b86..ca6dc1dc56c8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -310,8 +310,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum
pipe pipe)
crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
if (DISPLAY_VER(dev_priv) >= 9)
- primary = skl_universal_plane_create(dev_priv, pipe,
-PLANE_PRIMARY);
+ primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1);
else
primary = intel_primary_plane_create(dev_priv, pipe);
if (IS_ERR(primary)) {
@@ -326,8 +325,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum
pipe pipe)
struct intel_plane *plane;
if (DISPLAY_VER(dev_priv) >= 9)
- plane = skl_universal_plane_create(dev_priv, pipe,
- PLANE_SPRITE0 +
sprite);
+ plane = skl_universal_plane_create(dev_priv, pipe,
PLANE_2 + sprite);
else
plane = intel_sprite_plane_create(dev_priv, pipe,
sprite);
if (IS_ERR(plane)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cce1420fb541..ee2df655b0ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4121,13 +4121,13 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
linked_state->uapi.dst = plane_state->uapi.dst;
if (icl_is_hdr_plane(dev_priv, plane->id)) {
- if (linked->id == PLANE_SPRITE5)
+ if (linked->id == PLANE_7)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
- else if (linked->id == PLANE_SPRITE4)
+ else if (linked->id == PLANE_6)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
- else if (linked->id == PLANE_SPRITE3)
+ else if (linked->id == PLANE_5)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
- else if (linked->id == PLANE_SPRITE2)
+ else if (linked->id == PLANE_4)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h
b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 5126d0b5ae5d..c4775c99dc83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -60,16 +60,23 @@ enum transcoder {
* (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
*/
enum plane_id {
- PLANE_PRIMARY,
- PLANE_SPRITE0,
- PLANE_SPRITE1,
- PLANE_SPRITE2,
- PLANE_SPRITE3,
- PLANE_SPRITE4,
- PLANE_SPRITE5,
+ /* skl+ universal plane names */
+ PLANE_1,
+ PLANE_2,
+ PLANE_3,
+ PLANE_4,
+ PLANE_5,
+ PLANE_6,
+ PLANE_7,
+
PLANE_CURSOR,
I915_MAX_PLANES,
+
+ /* pre-skl plane names */
+ PLANE_PRIMARY = PLANE_1,
+ PLANE_SPRITE0,
+ PLANE_SPRITE1,
};
enum port {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
index a76b48ebc2d3..4853c4806004 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
@@ -74,7 +74,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev,
void *data,
* pipe simultaneously.
*/
if (DISPLAY_VER(dev_priv) >= 9 &&
- to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
+ to_intel_plane(plane)->id >= PLANE_3 &&
set->flags & I915_SET_COLORKEY_DESTINATION)
return -EINVAL;
diff --git
[PATCH 00/13] drm/i915: Plane register cleanups
From: Ville Syrjälä Bunch of cleanup mostly around plane registers. Ville Syrjälä (13): drm/i915: Add skl+ plane name aliases to enum plane_id drm/i915: Clean up the cursor register defines drm/i915: Add separate define for SEL_FETCH_CUR_CTL() drm/i915: Simplify PIPESRC_ERLY_TPT definition drm/i915: Rename selective fetch plane registers drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES() drm/i915: Add separate defines for cursor WM/DDB register bits drm/i915: Move PIPEGCMAX to intel_color_regs.h drm/i915: Extract i9xx_plane_regs.h drm/i915: Polish pre-skl primary plane registers drm/i915: Document a few pre-skl primary plane platform dependencies drm/i915: Polish sprite plane register definitions drm/i915: Document which platforms use which sprite registers drivers/gpu/drm/i915/display/i9xx_plane.c | 1 + .../gpu/drm/i915/display/i9xx_plane_regs.h| 110 .../gpu/drm/i915/display/intel_atomic_plane.c | 1 + drivers/gpu/drm/i915/display/intel_color.c| 2 +- .../gpu/drm/i915/display/intel_color_regs.h | 5 + drivers/gpu/drm/i915/display/intel_crtc.c | 6 +- drivers/gpu/drm/i915/display/intel_cursor.c | 42 ++- .../gpu/drm/i915/display/intel_cursor_regs.h | 66 +++-- drivers/gpu/drm/i915/display/intel_display.c | 9 +- .../drm/i915/display/intel_display_limits.h | 21 +- drivers/gpu/drm/i915/display/intel_fbc.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 49 +--- .../gpu/drm/i915/display/intel_sprite_regs.h | 242 ++ .../gpu/drm/i915/display/intel_sprite_uapi.c | 2 +- .../drm/i915/display/skl_universal_plane.c| 35 ++- .../drm/i915/display/skl_universal_plane.h| 3 - .../i915/display/skl_universal_plane_regs.h | 68 + drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/display.c| 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 91 +-- drivers/gpu/drm/i915/intel_clock_gating.c | 1 + drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 25 files changed, 449 insertions(+), 313 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h -- 2.44.1
Re: [PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE
On Wed, May 15, 2024 at 07:56:51PM +0300, Jani Nikula wrote:
> Now that the PCI ID macros allow us to pass in the macro to use, stop
> redefining INTEL_VGA_DEVICE.
Reviewed-by: Rodrigo Vivi
>
> Cc: Lucas De Marchi
> Cc: Rodrigo Vivi
> Signed-off-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_device.c | 87 +-
> drivers/gpu/drm/i915/intel_device_info.c | 91 +--
> 2 files changed, 88 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 950e66cdba0a..cf093bc0cb28 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -795,55 +795,54 @@ static bool has_no_display(struct pci_dev *pdev)
> return pci_match_id(ids, pdev);
> }
>
> -#undef INTEL_VGA_DEVICE
> -#define INTEL_VGA_DEVICE(id, info) { id, info }
> +#define INTEL_DISPLAY_DEVICE(_id, _info) { .devid = (_id), .info = (_info) }
>
> static const struct {
> u32 devid;
> const struct intel_display_device_info *info;
> } intel_display_ids[] = {
> - INTEL_I830_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I845G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I85X_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I865G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I915G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I915GM_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I945G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I945GM_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I965G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_G33_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I965GM_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_GM45_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_G45_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_PNV_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, _d_display),
> - INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, _m_display),
> - INTEL_SNB_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_IVB_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_HSW_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_VLV_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_BDW_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_CHV_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_SKL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_BXT_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_GLK_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_KBL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_CFL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_WHL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_CML_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_ICL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_EHL_IDS(INTEL_VGA_DEVICE, _ehl_display),
> - INTEL_JSL_IDS(INTEL_VGA_DEVICE, _ehl_display),
> - INTEL_TGL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_DG1_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_RKL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_ADLS_IDS(INTEL_VGA_DEVICE, _s_display),
> - INTEL_RPLS_IDS(INTEL_VGA_DEVICE, _s_display),
> - INTEL_ADLP_IDS(INTEL_VGA_DEVICE, _lpd_display),
> - INTEL_ADLN_IDS(INTEL_VGA_DEVICE, _lpd_display),
> - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, _lpd_display),
> - INTEL_RPLP_IDS(INTEL_VGA_DEVICE, _lpd_display),
> - INTEL_DG2_IDS(INTEL_VGA_DEVICE, _hpd_display),
> + INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, _d_display),
> + INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, _m_display),
> + INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, _display),
> +
Re: [PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE
On Wed, May 15, 2024 at 07:56:51PM +0300, Jani Nikula wrote:
> Now that the PCI ID macros allow us to pass in the macro to use, stop
> redefining INTEL_VGA_DEVICE.
Reviewed-by: Rodrigo Vivi
>
> Cc: Lucas De Marchi
> Cc: Rodrigo Vivi
> Signed-off-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_device.c | 87 +-
> drivers/gpu/drm/i915/intel_device_info.c | 91 +--
> 2 files changed, 88 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 950e66cdba0a..cf093bc0cb28 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -795,55 +795,54 @@ static bool has_no_display(struct pci_dev *pdev)
> return pci_match_id(ids, pdev);
> }
>
> -#undef INTEL_VGA_DEVICE
> -#define INTEL_VGA_DEVICE(id, info) { id, info }
> +#define INTEL_DISPLAY_DEVICE(_id, _info) { .devid = (_id), .info = (_info) }
>
> static const struct {
> u32 devid;
> const struct intel_display_device_info *info;
> } intel_display_ids[] = {
> - INTEL_I830_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I845G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I85X_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I865G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I915G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I915GM_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I945G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I945GM_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I965G_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_G33_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_I965GM_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_GM45_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_G45_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_PNV_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, _d_display),
> - INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, _m_display),
> - INTEL_SNB_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_IVB_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_HSW_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_VLV_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_BDW_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_CHV_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_SKL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_BXT_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_GLK_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_KBL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_CFL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_WHL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_CML_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_ICL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_EHL_IDS(INTEL_VGA_DEVICE, _ehl_display),
> - INTEL_JSL_IDS(INTEL_VGA_DEVICE, _ehl_display),
> - INTEL_TGL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_DG1_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_RKL_IDS(INTEL_VGA_DEVICE, _display),
> - INTEL_ADLS_IDS(INTEL_VGA_DEVICE, _s_display),
> - INTEL_RPLS_IDS(INTEL_VGA_DEVICE, _s_display),
> - INTEL_ADLP_IDS(INTEL_VGA_DEVICE, _lpd_display),
> - INTEL_ADLN_IDS(INTEL_VGA_DEVICE, _lpd_display),
> - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, _lpd_display),
> - INTEL_RPLP_IDS(INTEL_VGA_DEVICE, _lpd_display),
> - INTEL_DG2_IDS(INTEL_VGA_DEVICE, _hpd_display),
> + INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, _d_display),
> + INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, _m_display),
> + INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, _display),
> + INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, _display),
> +
Re: [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
On Wed, May 15, 2024 at 07:56:50PM +0300, Jani Nikula wrote:
> The PCI ID macros in xe_pciids.h allow passing in the macro to operate
> on each PCI ID, making it more flexible. Convert i915_pciids.h to the
> same pattern.
>
> INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
> unconditionally uses INTEL_QUANTA_VGA_DEVICE().
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Cc: Lucas De Marchi
> Cc: Rodrigo Vivi
> Signed-off-by: Jani Nikula
>
> ---
>
> Tip: It's probably easiest to apply and use 'git show --color-words' for
> review.
>
> This transformation is completely scripted:
>
> | #!/bin/bash
> |
> | FILE=include/drm/i915_pciids.h
> |
> | sed -i 's/[\t ]*\\/ \\/' $FILE
> |
> | sed -i 's/^\(#define [A-Za-z0-9_]\+\)_IDS(info)/\1_IDS(MACRO__, ...)/' $FILE
> |
> | sed -i 's/^\t\([A-Za-z0-9_]\+\)(info)/\t\1(MACRO__, ## __VA_ARGS__)/' $FILE
> |
> | sed -i 's/^\tINTEL_VGA_DEVICE(\([A-Fa-f0-9x]\+\), info)/\tMACRO__(\1, ##
> __VA_ARGS__)/' $FILE
> |
> | # Special case: IVB Q transcode
> | sed -i 's/^\t\(INTEL_QUANTA_VGA_DEVICE\)(MACRO__, ## /\t\1(/' $FILE
> |
> | # Change all users
> | for file in $(git grep -l "#include "); do
> | for macro in $(git grep -ho "#define [A-Za-z0-9_]\+_IDS" $FILE | sed
> 's/#define //'); do
> | sed -i "s/$macro(/$macro(INTEL_VGA_DEVICE, /" $file
> | done
> | done
Reviewed-by: Rodrigo Vivi
> ---
> arch/x86/kernel/early-quirks.c| 80 +-
> .../drm/i915/display/intel_display_device.c | 86 +-
> drivers/gpu/drm/i915/i915_pci.c | 150 +-
> drivers/gpu/drm/i915/intel_device_info.c | 88 +-
> include/drm/i915_pciids.h | 1348 -
> 5 files changed, 876 insertions(+), 876 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index fd74d7f26f01..1c137771c5d2 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -518,46 +518,46 @@ static const struct intel_early_ops gen11_early_ops
> __initconst = {
>
> /* Intel integrated GPUs for which we need to reserve "stolen memory" */
> static const struct pci_device_id intel_early_ids[] __initconst = {
> - INTEL_I830_IDS(_early_ops),
> - INTEL_I845G_IDS(_early_ops),
> - INTEL_I85X_IDS(_early_ops),
> - INTEL_I865G_IDS(_early_ops),
> - INTEL_I915G_IDS(_early_ops),
> - INTEL_I915GM_IDS(_early_ops),
> - INTEL_I945G_IDS(_early_ops),
> - INTEL_I945GM_IDS(_early_ops),
> - INTEL_VLV_IDS(_early_ops),
> - INTEL_PNV_IDS(_early_ops),
> - INTEL_I965G_IDS(_early_ops),
> - INTEL_G33_IDS(_early_ops),
> - INTEL_I965GM_IDS(_early_ops),
> - INTEL_GM45_IDS(_early_ops),
> - INTEL_G45_IDS(_early_ops),
> - INTEL_ILK_IDS(_early_ops),
> - INTEL_SNB_IDS(_early_ops),
> - INTEL_IVB_IDS(_early_ops),
> - INTEL_HSW_IDS(_early_ops),
> - INTEL_BDW_IDS(_early_ops),
> - INTEL_CHV_IDS(_early_ops),
> - INTEL_SKL_IDS(_early_ops),
> - INTEL_BXT_IDS(_early_ops),
> - INTEL_KBL_IDS(_early_ops),
> - INTEL_CFL_IDS(_early_ops),
> - INTEL_WHL_IDS(_early_ops),
> - INTEL_CML_IDS(_early_ops),
> - INTEL_GLK_IDS(_early_ops),
> - INTEL_CNL_IDS(_early_ops),
> - INTEL_ICL_IDS(_early_ops),
> - INTEL_EHL_IDS(_early_ops),
> - INTEL_JSL_IDS(_early_ops),
> - INTEL_TGL_IDS(_early_ops),
> - INTEL_RKL_IDS(_early_ops),
> - INTEL_ADLS_IDS(_early_ops),
> - INTEL_ADLP_IDS(_early_ops),
> - INTEL_ADLN_IDS(_early_ops),
> - INTEL_RPLS_IDS(_early_ops),
> - INTEL_RPLU_IDS(_early_ops),
> - INTEL_RPLP_IDS(_early_ops),
> + INTEL_I830_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I845G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I85X_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I865G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I915G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I945G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_VLV_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_PNV_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I965G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_G33_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_GM45_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_G45_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_ILK_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_SNB_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_IVB_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_HSW_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_BDW_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_CHV_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_SKL_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_BXT_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_KBL_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_CFL_IDS(INTEL_VGA_DEVICE, _early_ops),
> +
✗ Fi.CI.CHECKPATCH: warning for ACPI: video: Fix name collision with architecture's video.o
== Series Details == Series: ACPI: video: Fix name collision with architecture's video.o URL : https://patchwork.freedesktop.org/series/133694/ State : warning == Summary == Error: dim checkpatch failed 52bfd2a8f635 ACPI: video: Fix name collision with architecture's video.o -:12: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #12: (i915_selftest:1107) igt_kmod-WARNING: i915: Unknown symbol acpi_video_unregister (err -2) -:55: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #55: rename from drivers/acpi/acpi_video.c total: 0 errors, 2 warnings, 0 checks, 24 lines checked
Re: [PATCH] ACPI: video: Fix name collision with architecture's video.o
CC Hans who has been doing the majority of the ACPI video work.
On Thu, May 16, 2024 at 2:43 PM Thomas Zimmermann wrote:
>
> Commit 2fd001cd3600 ("arch: Rename fbdev header and source files")
> renames the video source files under arch/ such that they does not
> refer to fbdev any longer. The new files named video.o conflict with
> ACPI's video.ko module.
And surely nobody knew or was unable to check upfront that there was a
video.ko already in the kernel.
> Modprobing the ACPI module can then fail with warnings about missing symbols,
> as shown below.
>
> (i915_selftest:1107) igt_kmod-WARNING: i915: Unknown symbol
> acpi_video_unregister (err -2)
> (i915_selftest:1107) igt_kmod-WARNING: i915: Unknown symbol
> acpi_video_register_backlight (err -2)
> (i915_selftest:1107) igt_kmod-WARNING: i915: Unknown symbol
> __acpi_video_get_backlight_type (err -2)
> (i915_selftest:1107) igt_kmod-WARNING: i915: Unknown symbol
> acpi_video_register (err -2)
>
> Fix this problem by renaming ACPI's video.ko to acpi_video.ko. Also
> rename a related source file and clean up the Makefile.
If you insist on renaming, rename it to backlight.c (and
backlight_detect.c for consistency), because that's what it really is
about.
> Reported-by: Chaitanya Kumar Borah
> Closes:
> https://lore.kernel.org/intel-gfx/9dcac6e9-a3bf-4ace-bbdc-f697f767f...@suse.de/T/#t
> Tested-by: Chaitanya Kumar Borah
> Signed-off-by: Thomas Zimmermann
> Fixes: 2fd001cd3600 ("arch: Rename fbdev header and source files")
> Cc: Arnd Bergmann
> Cc: linux-a...@vger.kernel.org
> Cc: linux-fb...@vger.kernel.org
> Cc: dri-de...@lists.freedesktop.org
> ---
> drivers/acpi/Makefile| 5 +++--
> drivers/acpi/{acpi_video.c => acpi_video_core.c} | 2 +-
> 2 files changed, 4 insertions(+), 3 deletions(-)
> rename drivers/acpi/{acpi_video.c => acpi_video_core.c} (99%)
>
> diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
> index 8cc8c0d9c8732..fc9e11f7afbf7 100644
> --- a/drivers/acpi/Makefile
> +++ b/drivers/acpi/Makefile
> @@ -84,7 +84,9 @@ obj-$(CONFIG_ACPI_FAN)+= fan.o
> fan-objs := fan_core.o
> fan-objs += fan_attr.o
>
> -obj-$(CONFIG_ACPI_VIDEO) += video.o
> +obj-$(CONFIG_ACPI_VIDEO) += acpi_video.o
> +acpi_video-objs+= acpi_video_core.o video_detect.o
> +
> obj-$(CONFIG_ACPI_TAD) += acpi_tad.o
> obj-$(CONFIG_ACPI_PCI_SLOT)+= pci_slot.o
> obj-$(CONFIG_ACPI_PROCESSOR) += processor.o
> @@ -124,7 +126,6 @@ obj-$(CONFIG_ACPI_CONFIGFS) += acpi_configfs.o
>
> obj-y += pmic/
>
> -video-objs += acpi_video.o video_detect.o
> obj-y += dptf/
>
> obj-$(CONFIG_ARM64)+= arm64/
> diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video_core.c
> similarity index 99%
> rename from drivers/acpi/acpi_video.c
> rename to drivers/acpi/acpi_video_core.c
> index 1fda303882973..32bf81c5773a4 100644
> --- a/drivers/acpi/acpi_video.c
> +++ b/drivers/acpi/acpi_video_core.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-or-later
> /*
> - * video.c - ACPI Video Driver
> + * acpi_video_core.c - ACPI Video Driver
> *
> * Copyright (C) 2004 Luming Yu
> * Copyright (C) 2004 Bruno Ducrot
> --
> 2.45.0
>
>
[PATCH] ACPI: video: Fix name collision with architecture's video.o
Commit 2fd001cd3600 ("arch: Rename fbdev header and source files")
renames the video source files under arch/ such that they does not
refer to fbdev any longer. The new files named video.o conflict with
ACPI's video.ko module. Modprobing the ACPI module can then fail with
warnings about missing symbols, as shown below.
(i915_selftest:1107) igt_kmod-WARNING: i915: Unknown symbol
acpi_video_unregister (err -2)
(i915_selftest:1107) igt_kmod-WARNING: i915: Unknown symbol
acpi_video_register_backlight (err -2)
(i915_selftest:1107) igt_kmod-WARNING: i915: Unknown symbol
__acpi_video_get_backlight_type (err -2)
(i915_selftest:1107) igt_kmod-WARNING: i915: Unknown symbol
acpi_video_register (err -2)
Fix this problem by renaming ACPI's video.ko to acpi_video.ko. Also
rename a related source file and clean up the Makefile.
Reported-by: Chaitanya Kumar Borah
Closes:
https://lore.kernel.org/intel-gfx/9dcac6e9-a3bf-4ace-bbdc-f697f767f...@suse.de/T/#t
Tested-by: Chaitanya Kumar Borah
Signed-off-by: Thomas Zimmermann
Fixes: 2fd001cd3600 ("arch: Rename fbdev header and source files")
Cc: Arnd Bergmann
Cc: linux-a...@vger.kernel.org
Cc: linux-fb...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
---
drivers/acpi/Makefile| 5 +++--
drivers/acpi/{acpi_video.c => acpi_video_core.c} | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
rename drivers/acpi/{acpi_video.c => acpi_video_core.c} (99%)
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index 8cc8c0d9c8732..fc9e11f7afbf7 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -84,7 +84,9 @@ obj-$(CONFIG_ACPI_FAN)+= fan.o
fan-objs := fan_core.o
fan-objs += fan_attr.o
-obj-$(CONFIG_ACPI_VIDEO) += video.o
+obj-$(CONFIG_ACPI_VIDEO) += acpi_video.o
+acpi_video-objs+= acpi_video_core.o video_detect.o
+
obj-$(CONFIG_ACPI_TAD) += acpi_tad.o
obj-$(CONFIG_ACPI_PCI_SLOT)+= pci_slot.o
obj-$(CONFIG_ACPI_PROCESSOR) += processor.o
@@ -124,7 +126,6 @@ obj-$(CONFIG_ACPI_CONFIGFS) += acpi_configfs.o
obj-y += pmic/
-video-objs += acpi_video.o video_detect.o
obj-y += dptf/
obj-$(CONFIG_ARM64)+= arm64/
diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video_core.c
similarity index 99%
rename from drivers/acpi/acpi_video.c
rename to drivers/acpi/acpi_video_core.c
index 1fda303882973..32bf81c5773a4 100644
--- a/drivers/acpi/acpi_video.c
+++ b/drivers/acpi/acpi_video_core.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * video.c - ACPI Video Driver
+ * acpi_video_core.c - ACPI Video Driver
*
* Copyright (C) 2004 Luming Yu
* Copyright (C) 2004 Bruno Ducrot
--
2.45.0
Re: Regression on linux-next (next-20240506)
Hi Am 16.05.24 um 13:04 schrieb Borah, Chaitanya Kumar: Hi Thomas, -Original Message- From: Thomas Zimmermann Sent: Wednesday, May 15, 2024 6:06 PM To: Borah, Chaitanya Kumar Cc: intel-gfx@lists.freedesktop.org; Kurmi, Suresh Kumar ; Saarinen, Jani ; Nikula, Jani Subject: Re: Regression on linux-next (next-20240506) Hi Am 15.05.24 um 13:38 schrieb Borah, Chaitanya Kumar: [...] Sorry, I didn't notice the report before. The commit is not related to ACPI. There's now asm/video.h and acpi/video.h. Maybe there's a conflict among included files. Do you have a kernel config to build with? ~Sorry my email client messed up my previous reply. So sending again~ I could not find a public link for the linux-next config we use but this should be close enough. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/kconfig.txt Builds without problems. But I think there's a name collision between the video module in drivers/acpi and the new video module in arch/*/video. The attached patch renames the ACPI module. Could you please try it and report back the results? The patch is fixing the regression for us Will you be floating it? Great! I'll send it out for review. Best regards Thomas Regards Chaitanya Best regards Thomas Regards Chaitanya Best regards Thomas Thank you. Regards Chaitanya [1] https://intel-gfx-ci.01.org/tree/linux-next/combined-alt.html? [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux- next.git/commit/?h=next-20240506 [3] https://intel-gfx-ci.01.org/tree/linux-next/next-20240506/bat-mtlp- 9/igt@i915_selftest@live@gt_contexts.html [4] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux- next.git/commit/?h=next- 20240506=2fd001cd36005846caa6456fff1008c6f5bae9d4 -- -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstrasse 146, 90461 Nuernberg, Germany GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB 36809 (AG Nuernberg) -- -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstrasse 146, 90461 Nuernberg, Germany GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB 36809 (AG Nuernberg) -- -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstrasse 146, 90461 Nuernberg, Germany GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB 36809 (AG Nuernberg)
RE: Regression on linux-next (next-20240506)
Hi Thomas, > -Original Message- > From: Thomas Zimmermann > Sent: Wednesday, May 15, 2024 6:06 PM > To: Borah, Chaitanya Kumar > Cc: intel-gfx@lists.freedesktop.org; Kurmi, Suresh Kumar > ; Saarinen, Jani ; > Nikula, Jani > Subject: Re: Regression on linux-next (next-20240506) > > Hi > > Am 15.05.24 um 13:38 schrieb Borah, Chaitanya Kumar: > [...] > >> Sorry, I didn't notice the report before. The commit is not related to > >> ACPI. > >> There's now asm/video.h and acpi/video.h. Maybe there's a conflict > >> among included files. > >> > >> Do you have a kernel config to build with? > >> > > ~Sorry my email client messed up my previous reply. So sending again~ > > > > I could not find a public link for the linux-next config we use but this > > should > be close enough. > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/kconfig.txt > > Builds without problems. > > But I think there's a name collision between the video module in drivers/acpi > and the new video module in arch/*/video. The attached patch renames the > ACPI module. Could you please try it and report back the results? > The patch is fixing the regression for us Will you be floating it? Regards Chaitanya > Best regards > Thomas > > > > > > Regards > > Chaitanya > > > > > >> Best regards > >> Thomas > >> > Thank you. > > Regards > > Chaitanya > > [1] https://intel-gfx-ci.01.org/tree/linux-next/combined-alt.html? > [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux- > next.git/commit/?h=next-20240506 > [3] > https://intel-gfx-ci.01.org/tree/linux-next/next-20240506/bat-mtlp- > 9/igt@i915_selftest@live@gt_contexts.html > [4] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux- > next.git/commit/?h=next- > 20240506=2fd001cd36005846caa6456fff1008c6f5bae9d4 > >> -- > >> -- > >> Thomas Zimmermann > >> Graphics Driver Developer > >> SUSE Software Solutions Germany GmbH > >> Frankenstrasse 146, 90461 Nuernberg, Germany > >> GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB > >> 36809 (AG Nuernberg) > > -- > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Frankenstrasse 146, 90461 Nuernberg, Germany > GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB > 36809 (AG Nuernberg)
RE: [PATCH 1/2] drm/i915/display: Move port clock calculation
> -Original Message-
> From: Sousa, Gustavo
> Sent: Wednesday, May 15, 2024 4:24 PM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre ; Kahola, Mika
> Subject: Re: [PATCH 1/2] drm/i915/display: Move port clock calculation
>
> Quoting Mika Kahola (2024-05-15 03:45:23-03:00)
> >As a preparation to remove .clock member from pll state structure,
> >let's move the port clock calculation on better location
> >
> >Signed-off-by: Mika Kahola
> >---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 176 ++-
> > 1 file changed, 91 insertions(+), 85 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >index 1b1ebafa49e8..9f860a05e623 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >@@ -1970,13 +1970,92 @@ static const struct intel_c20pll_state * const
> mtl_c20_hdmi_tables[] = {
> > NULL,
> > };
> >
> >-static int intel_c10_phy_check_hdmi_link_rate(int clock)
> >+static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> >+const struct
> >+intel_c10pll_state *pll_state) {
> >+unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> >+unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
> >+int tmpclk = 0;
> >+
> >+if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> >+frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> >+frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
> >+frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
> >+}
> >+
> >+multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state-
> >pll[3]) << 8 |
> >+ pll_state->pll[2]) / 2 + 16;
> >+
> >+tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state-
> >pll[15]);
> >+hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK,
> >+ pll_state->pll[15]);
> >+
> >+tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier <<
> >16) +
> frac_quot) +
> >+ DIV_ROUND_CLOSEST(refclk * frac_rem,
> >frac_den),
> >+ 10 << (tx_clk_div + 16));
> >+tmpclk *= (hdmi_div ? 2 : 1);
> >+
> >+return tmpclk;
> >+}
> >+
> >+static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state
> >+*state) {
> >+return state->tx[0] & C20_PHY_USE_MPLLB; }
> >+
> >+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
>
> While at it, also remove the unused "encoder" parameter?
>
> Also, note that there are legitimate checkpatch issues reported for this
> patch, with
> those addressed:
That's true. I will fix the checkpatch issues.
Thanks for the review!
-Mika-
>
> Reviewed-by: Gustavo Sousa
>
> >+const struct
> >+intel_c20pll_state *pll_state) {
> >+unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
> >+unsigned int multiplier, refclk = 38400;
> >+unsigned int tx_clk_div;
> >+unsigned int ref_clk_mpllb_div;
> >+unsigned int fb_clk_div4_en;
> >+unsigned int ref, vco;
> >+unsigned int tx_rate_mult;
> >+unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE,
> >+pll_state->tx[0]);
> >+
> >+if (intel_c20phy_use_mpllb(pll_state)) {
> >+tx_rate_mult = 1;
> >+frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN,
> >pll_state->mpllb[6]);
> >+frac_quot = pll_state->mpllb[8];
> >+frac_rem = pll_state->mpllb[9];
> >+frac_den = pll_state->mpllb[7];
> >+multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state-
> >mpllb[0]);
> >+tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK,
> >pll_state-
> >mpllb[0]);
> >+ref_clk_mpllb_div =
> >REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK,
> pll_state->mpllb[6]);
> >+fb_clk_div4_en = 0;
> >+} else {
> >+tx_rate_mult = 2;
> >+frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN,
> >pll_state->mplla[6]);
> >+frac_quot = pll_state->mplla[8];
> >+frac_rem = pll_state->mplla[9];
> >+frac_den = pll_state->mplla[7];
> >+multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state-
> >mplla[0]);
> >+tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK,
> >pll_state-
> >mplla[1]);
> >+ref_clk_mpllb_div =
> >REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK,
> pll_state->mplla[6]);
> >+fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN,
> >pll_state-
> >mplla[0]);
> >+}
> >+
> >+if (frac_en)
> >+frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
> >+else
> >+frac = 0;
> >+
>
✗ Fi.CI.SPARSE: warning for Panel Replay eDP support
== Series Details == Series: Panel Replay eDP support URL : https://patchwork.freedesktop.org/series/133684/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for Panel Replay eDP support
== Series Details == Series: Panel Replay eDP support URL : https://patchwork.freedesktop.org/series/133684/ State : warning == Summary == Error: dim checkpatch failed 74d66f8eab6a drm/i915/psr: Store pr_dpcd in intel_dp a88dca068e21 drm/panel replay: Add edp1.5 Panel Replay bits and register 911a40e9ccde drm/i915/psr: Move printing sink PSR support to own function 83bb4807fcba drm/i915/psr: Move printing PSR mode to own function eb3f74614200 drm/i915/psr: modify psr status debugfs to support eDP Panel Replay ec35f0ea9cde drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid 3f91f111d9f7 drm/i915/psr: Add Early Transport into psr debugfs interface -:23: WARNING:PREFER_SEQ_PUTS: Prefer seq_puts to seq_printf #23: FILE: drivers/gpu/drm/i915/display/intel_psr.c:3604: + seq_printf(m, " (Early Transport)"); -:29: WARNING:PREFER_SEQ_PUTS: Prefer seq_puts to seq_printf #29: FILE: drivers/gpu/drm/i915/display/intel_psr.c:3609: + seq_printf(m, " (Early Transport)"); -:30: WARNING:PREFER_SEQ_PUTS: Prefer seq_puts to seq_printf #30: FILE: drivers/gpu/drm/i915/display/intel_psr.c:3610: + seq_printf(m, "\n"); total: 0 errors, 3 warnings, 0 checks, 53 lines checked 24e1aca960e0 drm/display: Add missing aux less alpm wake related bits 711ae2456e0b drm/i915/psr: Check panel ALPM capability for eDP Panel Replay a8ce90091600 drm/i915/psr: Inform Panel Replay source support on eDP as well a7397853f8d5 drm/i915/psr: enable sink for eDP1.5 Panel Replay 98bea674499d drm/i915/psr: Check panel Early Transport capability for eDP PR e1698cf902cb drm/i915/psr: Perfrom psr2 checks related to ALPM for Panel Replay 51d464ca5155 drm/i915/psr: Check Early Transport for Panel Replay as well d73c8ce6cc42 drm/i915/psr: Modify dg2_activate_panel_replay to support eDP 6f98f7b3bfbf drm/i915/psr: Add new debug bit to disable Panel Replay dcfccabf987a Revert "drm/i915/psr: Disable early transport by default"
[PATCH 12/17] drm/i915/psr: Check panel Early Transport capability for eDP PR
Our HW doesn't support panel replay without Early Transport on eDP.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d01170ccf603..daba46aa1149 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -549,12 +549,19 @@ static void _panel_replay_init_dpcd(struct intel_dp
*intel_dp, u8 alpm_caps)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (intel_dp_is_edp(intel_dp) &&
- (!(alpm_caps & DP_ALPM_CAP) ||
-!(alpm_caps & DP_ALPM_AUX_LESS_CAP))) {
- drm_dbg_kms(>drm,
- "Panel doesn't support AUX-less ALPM, eDP Panel
Replay not possible\n");
- return;
+ if (intel_dp_is_edp(intel_dp)) {
+ if (!(alpm_caps & DP_ALPM_CAP) ||
+ !(alpm_caps & DP_ALPM_AUX_LESS_CAP)) {
+ drm_dbg_kms(>drm,
+ "Panel doesn't support AUX-less ALPM, eDP
Panel Replay not possible\n");
+ return;
+ }
+
+ if (!(intel_dp->pr_dpcd &
DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
+ drm_dbg_kms(>drm,
+ "Panel doesn't support early transport, eDP
Panel Replay not possible\n");
+ return;
+ }
}
intel_dp->psr.sink_panel_replay_support = true;
--
2.34.1
[PATCH 16/17] drm/i915/psr: Add new debug bit to disable Panel Replay
Currently there is no way to disable Panel Replay without disabling
PSR. Add new debug bit to be used with i915_edp_psr_debug debugfs
interface.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 6 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6fbfe8a18f45..f8863510e722 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1687,6 +1687,7 @@ struct intel_psr {
#define I915_PSR_DEBUG_ENABLE_SEL_FETCH0x4
#define I915_PSR_DEBUG_IRQ 0x10
#define I915_PSR_DEBUG_SU_REGION_ET_DISABLE0x20
+#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE0x40
u32 debug;
bool sink_support;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 647e5cd70cc8..6a66e738aeb3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1752,7 +1752,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- if (CAN_PANEL_REPLAY(intel_dp))
+ if (CAN_PANEL_REPLAY(intel_dp) &&
+ !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE))
crtc_state->has_panel_replay = true;
crtc_state->has_psr = crtc_state->has_panel_replay ? true :
@@ -3063,7 +3064,8 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64
val)
u32 old_mode;
int ret;
- if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
+ if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_PANEL_REPLAY_DISABLE |
+ I915_PSR_DEBUG_MODE_MASK) ||
mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
drm_dbg_kms(_priv->drm, "Invalid debug mask %llx\n", val);
return -EINVAL;
--
2.34.1
[PATCH 17/17] Revert "drm/i915/psr: Disable early transport by default"
This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d. We want to notice possible issues faced with PSR2 Region Early Transport as early as possible -> let's revert patch disabling Region Early Transport by default. Also eDP 1.5 Panel Replay requires Early Transport. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 6a66e738aeb3..e7d04ce371ab 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3372,9 +3372,6 @@ void intel_psr_init(struct intel_dp *intel_dp) if (HAS_PSR(dev_priv) && intel_dp_is_edp(intel_dp)) intel_dp->psr.source_support = true; - /* Disable early transport for now */ - intel_dp->psr.debug |= I915_PSR_DEBUG_SU_REGION_ET_DISABLE; - /* Set link_standby x link_off defaults */ if (DISPLAY_VER(dev_priv) < 12) /* For new platforms up to TGL let's respect VBT back again */ -- 2.34.1
[PATCH 14/17] drm/i915/psr: Check Early Transport for Panel Replay as well
Move Early Transport validity check to be performed for Panel Replay as well and use Early Transport for eDP Panel Replay always. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4bbb0c05054f..a84a7208e148 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1601,9 +1601,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); - if (psr2_su_region_et_valid(intel_dp, false)) - crtc_state->enable_psr2_su_region_et = true; - return true; } @@ -1668,6 +1665,9 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, goto unsupported; } + if (psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay)) + crtc_state->enable_psr2_su_region_et = true; + return true; unsupported: -- 2.34.1
[PATCH 15/17] drm/i915/psr: Modify dg2_activate_panel_replay to support eDP
There are couple of bits in PSR2_CTL which needs to be written in case of
eDP Panel Replay
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index a84a7208e148..647e5cd70cc8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -928,6 +928,18 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp)
static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_psr *psr = _dp->psr;
+ enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+
+ if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
+ u32 val = LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
+
+ if (intel_dp->psr.req_psr2_sdp_prior_scanline)
+ val |= EDP_PSR2_SU_SDP_SCANLINE;
+
+ intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder),
+ val);
+ }
intel_de_rmw(dev_priv,
PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder),
--
2.34.1
[PATCH 13/17] drm/i915/psr: Perfrom psr2 checks related to ALPM for Panel Replay
eDP1.5 support ALPM with Panel Replay as well. We need to check ALPM
related things for Panel Replay as well.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 45 +---
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index daba46aa1149..4bbb0c05054f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1590,27 +1590,6 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
- if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state))
{
- drm_dbg_kms(_priv->drm,
- "PSR2 not enabled, PSR2 SDP indication do not fit
in hblank\n");
- return false;
- }
-
- if (!_compute_alpm_params(intel_dp, crtc_state)) {
- drm_dbg_kms(_priv->drm,
- "PSR2 not enabled, Unable to use long enough wake
times\n");
- return false;
- }
-
- /* Vblank >= PSR2_CTL Block Count Number maximum line count */
- if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
- crtc_state->hw.adjusted_mode.crtc_vblank_start <
- psr2_block_count_lines(intel_dp)) {
- drm_dbg_kms(_priv->drm,
- "PSR2 not enabled, too short vblank time\n");
- return false;
- }
-
if (!crtc_state->enable_psr2_sel_fetch &&
(crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
drm_dbg_kms(_priv->drm,
@@ -1649,6 +1628,30 @@ static bool intel_sel_update_config_valid(struct
intel_dp *intel_dp,
if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp,
crtc_state))
goto unsupported;
+ if (intel_dp_is_edp(intel_dp)) {
+ if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp,
+crtc_state)) {
+ drm_dbg_kms(_priv->drm,
+ "Selective update not enabled, SDP
indication do not fit in hblank\n");
+ goto unsupported;
+ }
+
+ if (!_compute_alpm_params(intel_dp, crtc_state)) {
+ drm_dbg_kms(_priv->drm,
+ "Selective update not enabled, Unable to
use long enough wake times\n");
+ goto unsupported;
+ }
+
+ /* Vblank >= PSR2_CTL Block Count Number maximum line count */
+ if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
+ crtc_state->hw.adjusted_mode.crtc_vblank_start <
+ psr2_block_count_lines(intel_dp)) {
+ drm_dbg_kms(_priv->drm,
+ "Selective update not enabled, too short
vblank time\n");
+ goto unsupported;
+ }
+ }
+
if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 ||
!intel_dp->psr.sink_panel_replay_su_support))
goto unsupported;
--
2.34.1
[PATCH 10/17] drm/i915/psr: Inform Panel Replay source support on eDP as well
Display version >= 20 support eDP 1.5. Inform Panel Replay source support on eDP for display version >= 20. Bspec: 68920 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 3216bce7d62d..7409cdf56894 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3312,9 +3312,11 @@ void intel_psr_init(struct intel_dp *intel_dp) return; } - if (HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp)) + if ((HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp)) || + DISPLAY_VER(dev_priv) >= 20) intel_dp->psr.source_panel_replay_support = true; - else + + if (HAS_PSR(dev_priv) && intel_dp_is_edp(intel_dp)) intel_dp->psr.source_support = true; /* Disable early transport for now */ -- 2.34.1
[PATCH 11/17] drm/i915/psr: enable sink for eDP1.5 Panel Replay
eDP1.5 allows Panel Replay on eDP as well. Take this into account when
enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register
accordingly.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 63 +---
1 file changed, 46 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 7409cdf56894..d01170ccf603 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -691,6 +691,23 @@ static unsigned int
intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp)
PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;
}
+static void intel_psr_enable_sink_alpm(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state)
+{
+ u32 val;
+
+ if (!crtc_state->has_sel_update && (!crtc_state->has_panel_replay ||
+ !intel_dp_is_edp(intel_dp)))
+ return;
+
+ val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
+
+ if (crtc_state->has_panel_replay)
+ val |= DP_ALPM_MODE_AUX_LESS;
+
+ drm_dp_dpcd_writeb(_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
+}
+
/*
* Note: Most of the bits are same in PANEL_REPLAY_CONFIG and DP_PSR_EN_CFG. We
* are relying on PSR definitions on these "common" bits.
@@ -699,43 +716,55 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u8 dpcd_val = DP_PSR_ENABLE;
+ u8 enable_val = DP_PSR_ENABLE;
+ u8 panel_replay_config2 = 0;
+
+ intel_psr_enable_sink_alpm(intel_dp, crtc_state);
if (crtc_state->has_sel_update) {
- /* Enable ALPM at sink for psr2 */
- if (!crtc_state->has_panel_replay) {
- drm_dp_dpcd_writeb(_dp->aux,
- DP_RECEIVER_ALPM_CONFIG,
- DP_ALPM_ENABLE |
- DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
+ /* PSR2 and Panel Replay SU on eDP */
+ if (intel_dp_is_edp(intel_dp)) {
+ if (crtc_state->req_psr2_sdp_prior_scanline) {
+ if (crtc_state->has_panel_replay)
+ panel_replay_config2 |=
+
DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
+ else
+ enable_val |=
DP_PSR_SU_REGION_SCANLINE_CAPTURE;
+ }
if (psr2_su_region_et_valid(intel_dp,
intel_dp->psr.panel_replay_enabled))
- dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
+ enable_val |= DP_PSR_ENABLE_SU_REGION_ET;
}
- dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
+ enable_val |= DP_PSR_ENABLE_PSR2 |
DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
} else {
+ /* PSR2 and Panel Replay Full Frame Update */
if (intel_dp->psr.link_standby)
- dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+ enable_val |= DP_PSR_MAIN_LINK_ACTIVE;
if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv) >= 8)
- dpcd_val |= DP_PSR_CRC_VERIFICATION;
+ enable_val |= DP_PSR_CRC_VERIFICATION;
}
- if (crtc_state->has_panel_replay)
- dpcd_val |= DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
+ if (crtc_state->has_panel_replay) {
+ enable_val |= DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN;
- if (crtc_state->req_psr2_sdp_prior_scanline)
- dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
+ if (intel_dp_is_edp(intel_dp))
+ enable_val |= DP_PANEL_REPLAY_VSC_SDP_CRC_EN;
+ }
if (intel_dp->psr.entry_setup_frames > 0)
- dpcd_val |= DP_PSR_FRAME_CAPTURE;
+ enable_val |= DP_PSR_FRAME_CAPTURE;
drm_dp_dpcd_writeb(_dp->aux,
intel_psr_get_enable_sink_offset(intel_dp),
- dpcd_val);
+ enable_val);
+
+ if (crtc_state->has_panel_replay && intel_dp_is_edp(intel_dp))
+ drm_dp_dpcd_writeb(_dp->aux, PANEL_REPLAY_CONFIG2,
+ panel_replay_config2);
if (intel_dp_is_edp(intel_dp))
drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER,
DP_SET_POWER_D0);
--
2.34.1
[PATCH 09/17] drm/i915/psr: Check panel ALPM capability for eDP Panel Replay
Our HW doesn't support Panel Replay without AUX_LESS ALPM on eDP. Check
panel support for this and prevent eDP panel replay if it doesn't exits.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 5d2424c71d4c..3216bce7d62d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -444,16 +444,6 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32
psr_iir)
}
}
-static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
-{
- u8 alpm_caps = 0;
-
- if (drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP,
- _caps) != 1)
- return false;
- return alpm_caps & DP_ALPM_CAP;
-}
-
static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -555,10 +545,18 @@ static void intel_dp_get_su_granularity(struct intel_dp
*intel_dp)
intel_dp->psr.su_y_granularity = y;
}
-static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
+static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, u8 alpm_caps)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ if (intel_dp_is_edp(intel_dp) &&
+ (!(alpm_caps & DP_ALPM_CAP) ||
+!(alpm_caps & DP_ALPM_AUX_LESS_CAP))) {
+ drm_dbg_kms(>drm,
+ "Panel doesn't support AUX-less ALPM, eDP Panel
Replay not possible\n");
+ return;
+ }
+
intel_dp->psr.sink_panel_replay_support = true;
if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
@@ -570,7 +568,7 @@ static void _panel_replay_init_dpcd(struct intel_dp
*intel_dp)
"selective_update " : "");
}
-static void _psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp, u8 alpm_caps)
{
struct drm_i915_private *i915 =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
@@ -598,7 +596,6 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
bool y_req = intel_dp->psr_dpcd[1] &
DP_PSR2_SU_Y_COORDINATE_REQUIRED;
- bool alpm = intel_dp_get_alpm_status(intel_dp);
/*
* All panels that supports PSR version 03h (PSR2 +
@@ -611,7 +608,7 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
* Y-coordinate requirement panels we would need to enable
* GTC first.
*/
- intel_dp->psr.sink_psr2_support = y_req && alpm;
+ intel_dp->psr.sink_psr2_support = y_req && alpm_caps &
DP_ALPM_CAP;
drm_dbg_kms(>drm, "PSR2 %ssupported\n",
intel_dp->psr.sink_psr2_support ? "" : "not ");
}
@@ -619,16 +616,19 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
void intel_psr_init_dpcd(struct intel_dp *intel_dp)
{
+ u8 alpm_caps = 0;
+
drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
sizeof(intel_dp->psr_dpcd));
drm_dp_dpcd_readb(_dp->aux, DP_PANEL_REPLAY_CAP,
_dp->pr_dpcd);
+ drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP, _caps);
if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
- _panel_replay_init_dpcd(intel_dp);
+ _panel_replay_init_dpcd(intel_dp, alpm_caps);
if (intel_dp->psr_dpcd[0])
- _psr_init_dpcd(intel_dp);
+ _psr_init_dpcd(intel_dp, alpm_caps);
if (intel_dp->psr.sink_psr2_support ||
intel_dp->psr.sink_panel_replay_su_support)
--
2.34.1
[PATCH 08/17] drm/display: Add missing aux less alpm wake related bits
eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. Signed-off-by: Jouni Högander --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 79bde372b152..f3ce8c483659 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -232,6 +232,8 @@ #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ # define DP_ALPM_CAP (1 << 0) +# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_AUX_LESS_CAP (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_CAP (1 << 0) @@ -685,6 +687,7 @@ #define DP_RECEIVER_ALPM_CONFIG0x116 /* eDP 1.4 */ # define DP_ALPM_ENABLE(1 << 0) # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) +# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) -- 2.34.1
[PATCH 05/17] drm/i915/psr: modify psr status debugfs to support eDP Panel Replay
Some PSR2_CTL bits are applicable for eDP panel replay as well.
Dump this register for eDP Panel Replay as well.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 8844c9b75348..49ad83641e12 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3619,7 +3619,7 @@ static int intel_psr_status(struct seq_file *m, struct
intel_dp *intel_dp)
struct intel_psr *psr = _dp->psr;
intel_wakeref_t wakeref;
bool enabled;
- u32 val;
+ u32 val, psr2_ctl;
intel_psr_sink_capability(intel_dp, m);
@@ -3640,6 +3640,12 @@ static int intel_psr_status(struct seq_file *m, struct
intel_dp *intel_dp)
if (psr->panel_replay_enabled) {
val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));
+
+ if (intel_dp_is_edp(intel_dp))
+ psr2_ctl = intel_de_read(dev_priv,
+EDP_PSR2_CTL(dev_priv,
+ cpu_transcoder));
+
enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
} else if (psr->sel_update_enabled) {
val = intel_de_read(dev_priv,
@@ -3651,6 +3657,9 @@ static int intel_psr_status(struct seq_file *m, struct
intel_dp *intel_dp)
}
seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n",
str_enabled_disabled(enabled), val);
+ if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))
+ seq_printf(m, "PSR2_CTL: 0x%08x\n",
+ psr2_ctl);
psr_source_status(intel_dp, m);
seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
psr->busy_frontbuffer_bits);
--
2.34.1
[PATCH 07/17] drm/i915/psr: Add Early Transport into psr debugfs interface
We want to have sink Early Transport capability and usage in our psr
debugfs status interface.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 36 ++--
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index bc200fc043f0..5d2424c71d4c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3594,25 +3594,45 @@ static void intel_psr_sink_capability(struct intel_dp
*intel_dp,
if (psr->sink_support)
seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
+ if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
+ seq_printf(m, " (Early Transport)");
seq_printf(m, ", Panel Replay = %s",
str_yes_no(psr->sink_panel_replay_support));
- seq_printf(m, ", Panel Replay Selective Update = %s\n",
+ seq_printf(m, ", Panel Replay Selective Update = %s",
str_yes_no(psr->sink_panel_replay_su_support));
+ if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
+ seq_printf(m, " (Early Transport)");
+ seq_printf(m, "\n");
}
static void intel_psr_psr_mode(struct intel_dp *intel_dp,
struct seq_file *m)
{
struct intel_psr *psr = _dp->psr;
- const char *status;
+ const char *status, *mode, *region_et;
- if (psr->panel_replay_enabled)
- status = psr->sel_update_enabled ? "Panel Replay Selective
Update Enabled" :
- "Panel Replay Enabled";
+ if (psr->enabled)
+ status = " enabled";
+ else
+ status = " disabled";
+
+ if (psr->panel_replay_enabled && psr->sel_update_enabled)
+ mode = "Panel Replay Selective Update";
+ else if (psr->panel_replay_enabled)
+ mode = "Panel Replay";
+ else if (psr->sel_update_enabled)
+ mode = "PSR2";
else if (psr->enabled)
- status = psr->sel_update_enabled ? "PSR2" : "PSR1";
+ mode = "PSR1";
+ else
+ mode = "";
+
+ if (psr->sel_update_enabled &&
+ (psr2_su_region_et_valid(intel_dp, psr->panel_replay_enabled)))
+ region_et = " Early Transport";
else
- status = "disabled";
- seq_printf(m, "PSR mode: %s\n", status);
+ region_et = "";
+
+ seq_printf(m, "PSR mode: %s%s%s\n", mode, region_et, status);
}
static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
--
2.34.1
[PATCH 06/17] drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid
Early Transport is possible and in our HW mandatory on eDP Panel
Replay. Add parameter to intel_psr2_config_et_valid to differentiate
validity check for Panel Replay.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 49ad83641e12..bc200fc043f0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -672,16 +672,17 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
aux_ctl);
}
-static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
+static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool
panel_replay)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- if (DISPLAY_VER(i915) >= 20 &&
- intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
- !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
- return true;
+ if (DISPLAY_VER(i915) < 20 || !intel_dp_is_edp(intel_dp) ||
+ intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
+ return false;
- return false;
+ return panel_replay ?
+ intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
+ intel_dp->psr_dpcd[0] != DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
}
static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp)
@@ -708,7 +709,8 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
DP_ALPM_ENABLE |
DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
- if (psr2_su_region_et_valid(intel_dp))
+ if (psr2_su_region_et_valid(intel_dp,
+
intel_dp->psr.panel_replay_enabled))
dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
}
@@ -975,7 +977,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0);
}
- if (psr2_su_region_et_valid(intel_dp))
+ if (psr2_su_region_et_valid(intel_dp,
+ intel_dp->psr.panel_replay_enabled))
val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
/*
@@ -1583,7 +1586,7 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
- if (psr2_su_region_et_valid(intel_dp))
+ if (psr2_su_region_et_valid(intel_dp, false))
crtc_state->enable_psr2_su_region_et = true;
return true;
--
2.34.1
[PATCH 04/17] drm/i915/psr: Move printing PSR mode to own function
intel_psr_status has grown and is about to grow even. Let's split it a bit
and move printing PSR mode to an own function.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 26
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 626b59d3441a..8844c9b75348 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3596,13 +3596,28 @@ static void intel_psr_sink_capability(struct intel_dp
*intel_dp,
str_yes_no(psr->sink_panel_replay_su_support));
}
+static void intel_psr_psr_mode(struct intel_dp *intel_dp,
+ struct seq_file *m)
+{
+ struct intel_psr *psr = _dp->psr;
+ const char *status;
+
+ if (psr->panel_replay_enabled)
+ status = psr->sel_update_enabled ? "Panel Replay Selective
Update Enabled" :
+ "Panel Replay Enabled";
+ else if (psr->enabled)
+ status = psr->sel_update_enabled ? "PSR2" : "PSR1";
+ else
+ status = "disabled";
+ seq_printf(m, "PSR mode: %s\n", status);
+}
+
static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
struct intel_psr *psr = _dp->psr;
intel_wakeref_t wakeref;
- const char *status;
bool enabled;
u32 val;
@@ -3614,14 +3629,7 @@ static int intel_psr_status(struct seq_file *m, struct
intel_dp *intel_dp)
wakeref = intel_runtime_pm_get(_priv->runtime_pm);
mutex_lock(>lock);
- if (psr->panel_replay_enabled)
- status = psr->sel_update_enabled ? "Panel Replay Selective
Update Enabled" :
- "Panel Replay Enabled";
- else if (psr->enabled)
- status = psr->sel_update_enabled ? "PSR2" : "PSR1";
- else
- status = "disabled";
- seq_printf(m, "PSR mode: %s\n", status);
+ intel_psr_psr_mode(intel_dp, m);
if (!psr->enabled) {
seq_printf(m, "PSR sink not reliable: %s\n",
--
2.34.1
[PATCH 03/17] drm/i915/psr: Move printing sink PSR support to own function
intel_psr_status has grown and is about to grow even. Let's split it a bit
and move printing sink psr support to an own function.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 05c1069bbf60..626b59d3441a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3581,15 +3581,10 @@ psr_source_status(struct intel_dp *intel_dp, struct
seq_file *m)
seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status,
val);
}
-static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
+static void intel_psr_sink_capability(struct intel_dp *intel_dp,
+ struct seq_file *m)
{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
struct intel_psr *psr = _dp->psr;
- intel_wakeref_t wakeref;
- const char *status;
- bool enabled;
- u32 val;
seq_printf(m, "Sink support: PSR = %s",
str_yes_no(psr->sink_support));
@@ -3599,6 +3594,19 @@ static int intel_psr_status(struct seq_file *m, struct
intel_dp *intel_dp)
seq_printf(m, ", Panel Replay = %s",
str_yes_no(psr->sink_panel_replay_support));
seq_printf(m, ", Panel Replay Selective Update = %s\n",
str_yes_no(psr->sink_panel_replay_su_support));
+}
+
+static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+ struct intel_psr *psr = _dp->psr;
+ intel_wakeref_t wakeref;
+ const char *status;
+ bool enabled;
+ u32 val;
+
+ intel_psr_sink_capability(intel_dp, m);
if (!(psr->sink_support || psr->sink_panel_replay_support))
return 0;
--
2.34.1
[PATCH 02/17] drm/panel replay: Add edp1.5 Panel Replay bits and register
Add PANEL_REPLAY_CONFIGURATION_2 register and some missing Panel Replay bits. Signed-off-by: Jouni Högander --- include/drm/display/drm_dp.h | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 906949ca3cee..79bde372b152 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -544,9 +544,10 @@ /* DFP Capability Extension */ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0a3 /* 2.0 */ -#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */ -# define DP_PANEL_REPLAY_SUPPORT(1 << 0) -# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) +#define DP_PANEL_REPLAY_CAP0x0b0 /* DP 2.0 */ +# define DP_PANEL_REPLAY_SUPPORT (1 << 0) +# define DP_PANEL_REPLAY_SU_SUPPORT(1 << 1) +# define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT (1 << 2) /* eDP 1.5 */ #define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1 # define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5) @@ -734,11 +735,20 @@ #define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */ # define DP_PANEL_REPLAY_ENABLE (1 << 0) +# define DP_PANEL_REPLAY_VSC_SDP_CRC_EN (1 << 1) /* eDP 1.5 */ # define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3) # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) +#define PANEL_REPLAY_CONFIG2 0x1b1 /* eDP 1.5 */ +# define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED (1 << 0) +# define DP_PANEL_REPLAY_CRC_VERIFICATION (1 << 1) +# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_EN (1 << 2) +# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_SHIFT 3 +# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK (0xf << 3) +# define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE (1 << 7) + #define DP_PAYLOAD_ALLOCATE_SET0x1c0 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 -- 2.34.1
[PATCH 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
We need pr_dpcd contents for early transport validity check on eDP Panel
Replay and in debugfs interface to dump out panel early transport
capability.
Signed-off-by: Jouni Högander
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 19 ++-
2 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9678c2b157f6..6fbfe8a18f45 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1743,6 +1743,7 @@ struct intel_dp {
bool use_max_params;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
+ u8 pr_dpcd;
u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 2514ac48312b..05c1069bbf60 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -558,20 +558,10 @@ static void intel_dp_get_su_granularity(struct intel_dp
*intel_dp)
static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u8 pr_dpcd = 0;
-
- intel_dp->psr.sink_panel_replay_support = false;
- drm_dp_dpcd_readb(_dp->aux, DP_PANEL_REPLAY_CAP, _dpcd);
-
- if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
- drm_dbg_kms(>drm,
- "Panel replay is not supported by panel\n");
- return;
- }
intel_dp->psr.sink_panel_replay_support = true;
- if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
+ if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
intel_dp->psr.sink_panel_replay_su_support = true;
drm_dbg_kms(>drm,
@@ -629,10 +619,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
void intel_psr_init_dpcd(struct intel_dp *intel_dp)
{
- _panel_replay_init_dpcd(intel_dp);
-
drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
sizeof(intel_dp->psr_dpcd));
+ drm_dp_dpcd_readb(_dp->aux, DP_PANEL_REPLAY_CAP,
+ _dp->pr_dpcd);
+
+ if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
+ _panel_replay_init_dpcd(intel_dp);
if (intel_dp->psr_dpcd[0])
_psr_init_dpcd(intel_dp);
--
2.34.1
[PATCH 00/17] Panel Replay eDP support
This patch set is implementing eDP1.5 Panel Replay for Intel hw. Also Region Early Transport information is added into debugfs interface and patch to disable Region Early Transport by default is reverted as it is needed by eDP Panel Replay. Jouni Högander (17): drm/i915/psr: Store pr_dpcd in intel_dp drm/panel replay: Add edp1.5 Panel Replay bits and register drm/i915/psr: Move printing sink PSR support to own function drm/i915/psr: Move printing PSR mode to own function drm/i915/psr: modify psr status debugfs to support eDP Panel Replay drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid drm/i915/psr: Add Early Transport into psr debugfs interface drm/display: Add missing aux less alpm wake related bits drm/i915/psr: Check panel ALPM capability for eDP Panel Replay drm/i915/psr: Inform Panel Replay source support on eDP as well drm/i915/psr: enable sink for eDP1.5 Panel Replay drm/i915/psr: Check panel Early Transport capability for eDP PR drm/i915/psr: Perfrom psr2 checks related to ALPM for Panel Replay drm/i915/psr: Check Early Transport for Panel Replay as well drm/i915/psr: Modify dg2_activate_panel_replay to support eDP drm/i915/psr: Add new debug bit to disable Panel Replay Revert "drm/i915/psr: Disable early transport by default" .../drm/i915/display/intel_display_types.h| 2 + drivers/gpu/drm/i915/display/intel_psr.c | 287 -- include/drm/display/drm_dp.h | 19 +- 3 files changed, 208 insertions(+), 100 deletions(-) -- 2.34.1
Re: [PATCH 0/8] drm/i915: pass dev_priv explicitly to CUR* registers
On Wed, 15 May 2024, Ville Syrjälä wrote: > On Wed, May 15, 2024 at 02:56:40PM +0300, Jani Nikula wrote: >> Update all the register macros in the intel_cursor_regs.h file. >> >> Jani Nikula (8): >> drm/i915: pass dev_priv explicitly to CURCNTR >> drm/i915: pass dev_priv explicitly to CURBASE >> drm/i915: pass dev_priv explicitly to CURPOS >> drm/i915: pass dev_priv explicitly to CURPOS_ERLY_TPT >> drm/i915: pass dev_priv explicitly to CURSIZE >> drm/i915: pass dev_priv explicitly to CUR_FBC_CTL >> drm/i915: pass dev_priv explicitly to CUR_CHICKEN >> drm/i915: pass dev_priv explicitly to CURSURFLIVE > > Series is > Reviewed-by: Ville Syrjälä Thanks, pushed to din. BR, Jani. -- Jani Nikula, Intel
Re: [PATCH 0/8] drm/i915/pciids: PCI ID macro cleanups
On Wed, 15 May 2024, Dave Hansen wrote: > On 5/15/24 07:25, Jani Nikula wrote: >> No reply from Bjorn, Cc: the x86 maintainers and list, could I get an >> ack from you please? > > x86 is just a consumer of the drm/i915_pciids.h macros. The name change > is perfectly fine with me. No objections. But I really don't think you > need our acks to move forward. > > Either way: > > Acked-by: Dave Hansen # for x86 Thanks, I know the changes are benign, but it's just that I tend to err on the side of getting the acks rather than stepping on anyone's toes. :) BR, Jani. -- Jani Nikula, Intel
RE: [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure
> -Original Message-
> From: Sousa, Gustavo
> Sent: Wednesday, May 15, 2024 4:29 PM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre ; Kahola, Mika
> Subject: Re: [PATCH 2/2] drm/i915/display: Remove .clock from pll state
> structure
>
> Quoting Mika Kahola (2024-05-15 03:45:24-03:00)
> >.clock is not necessarily required to have in pll state structure as it
> >can always recalculated with the *_calc_port_clock() function. Hence,
> >let's remove this struct member complitely.
> >
> >Signed-off-by: Mika Kahola
> >---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 86 ---
> >drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 -
> > 2 files changed, 88 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >index 9f860a05e623..abb937368284 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >@@ -505,7 +505,6 @@ void intel_cx0_phy_set_signal_levels(struct
> >intel_encoder *encoder,
> > */
> >
> > static const struct intel_c10pll_state mtl_c10_dp_rbr = {
> >-.clock = 162000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xB4,
> >@@ -531,7 +530,6 @@ static const struct intel_c10pll_state
> >mtl_c10_dp_rbr = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r216 = {
> >-.clock = 216000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0x4,
> >@@ -557,7 +555,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r216 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r243 = {
> >-.clock = 243000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0x34,
> >@@ -583,7 +580,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r243 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
> >-.clock = 27,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xF4,
> >@@ -609,7 +605,6 @@ static const struct intel_c10pll_state
> >mtl_c10_dp_hbr1 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r324 = {
> >-.clock = 324000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xB4,
> >@@ -635,7 +630,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r324 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r432 = {
> >-.clock = 432000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0x4,
> >@@ -661,7 +655,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r432 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
> >-.clock = 54,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xF4,
> >@@ -687,7 +680,6 @@ static const struct intel_c10pll_state
> >mtl_c10_dp_hbr2 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r675 = {
> >-.clock = 675000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xB4,
> >@@ -713,7 +705,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r675 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_dp_hbr3 = {
> >-.clock = 81,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0x34,
> >@@ -761,7 +752,6 @@ static const struct intel_c10pll_state * const
> >mtl_c10_edp_tables[] = {
> >
> > /* C20 basic DP 1.4 tables */
> > static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> >-.clock = 162000,
> > .tx = {0xbe88, /* tx cfg0 */
> > 0x5800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> >@@ -786,7 +776,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_rbr = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> >-.clock = 27,
> > .tx = {0xbe88, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> >@@ -811,7 +800,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_hbr1 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> >-.clock = 54,
> > .tx = {0xbe88, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> >@@ -836,7 +824,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_hbr2 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> >-.clock = 81,
> > .tx = {0xbe88, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> >@@ -862,7 +849,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_hbr3 = {
> >
> > /* C20 basic DP 2.0 tables */
> > static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> >-.clock = 100, /* 10 Gbps */
> > .tx = {0xbe21, /* tx cfg0 */
> > 0xe800, /* tx
[PULL] drm-misc-fixes
Hi Dave, Sima there's only a single patch in this week's drm-misc-fixes PR. Best regards Thomas drm-misc-fixes-2024-05-16: Short summary of fixes pull: nouveau: - use tile_mode and pte_kind for VM_BIND bo allocations The following changes since commit 6897204ea3df808d342c8e4613135728bc538bcd: drm/connector: Add \n to message about demoting connector force-probes (2024-05-07 09:17:07 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/drm/misc/kernel.git tags/drm-misc-fixes-2024-05-16 for you to fetch changes up to aed9a1a4f7106ff99a882ad06318cebfa71016a2: drm/nouveau: use tile_mode and pte_kind for VM_BIND bo allocations (2024-05-13 22:17:58 +0200) Short summary of fixes pull: nouveau: - use tile_mode and pte_kind for VM_BIND bo allocations Mohamed Ahmed (1): drm/nouveau: use tile_mode and pte_kind for VM_BIND bo allocations drivers/gpu/drm/nouveau/nouveau_abi16.c | 3 +++ drivers/gpu/drm/nouveau/nouveau_bo.c| 44 ++--- include/uapi/drm/nouveau_drm.h | 7 ++ 3 files changed, 29 insertions(+), 25 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstrasse 146, 90461 Nuernberg, Germany GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB 36809 (AG Nuernberg)
