Re: [PATCH v2 2/6] drm/ci: generate testlist from build
Hi Dmitry,
On 20/05/24 16:30, Dmitry Baryshkov wrote:
On Fri, May 17, 2024 at 02:54:58PM +0530, Vignesh Raman wrote:
Stop vendoring the testlist into the kernel. Instead, use the
testlist from the IGT build to ensure we do not miss renamed
or newly added tests.
Signed-off-by: Vignesh Raman
---
v2:
- Fix testlist generation for arm and arm64 builds.
---
drivers/gpu/drm/ci/build-igt.sh | 34 +
drivers/gpu/drm/ci/igt_runner.sh |9 +-
drivers/gpu/drm/ci/testlist.txt | 2761 --
3 files changed, 39 insertions(+), 2765 deletions(-)
delete mode 100644 drivers/gpu/drm/ci/testlist.txt
diff --git a/drivers/gpu/drm/ci/build-igt.sh b/drivers/gpu/drm/ci/build-igt.sh
index 7859554756c4..e62244728613 100644
--- a/drivers/gpu/drm/ci/build-igt.sh
+++ b/drivers/gpu/drm/ci/build-igt.sh
[...]
@@ -26,6 +50,16 @@ meson build $MESON_OPTIONS $EXTRA_MESON_ARGS
ninja -C build -j${FDO_CI_CONCURRENT:-4} || ninja -C build -j 1
ninja -C build install
+if [[ "$KERNEL_ARCH" = "arm64" ]]; then
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib/aarch64-linux-gnu
+elif [[ "$KERNEL_ARCH" = "arm" ]]; then
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib
+else
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib64
Could you please clarify this part? The arm64 vs arm don't look logical
from my point of view.
The rest LGTM.
The libs are installed in the below path for different arch.
> find . -name libigt.so
./x86/igt/lib64/libigt.so
./arm64/igt/lib/aarch64-linux-gnu/libigt.so
./arm/igt/lib/libigt.so
~/igt-build
So for arm64 it is 'lib/aarch64-linux-gnu' and arm it is 'lib'.
s3.freedesktop.org/artifacts/vigneshraman/linux/1179691/arm64/igt.tar.gz
s3.freedesktop.org/artifacts/vigneshraman/linux/1179691/arm/igt.tar.gz
s3.freedesktop.org/artifacts/vigneshraman/linux/1179691/x86_64/igt.tar.gz
Regards,
Vignesh
+fi
+
+generate_testlist
+
mkdir -p artifacts/
tar -cf artifacts/igt.tar /igt
✗ Fi.CI.IGT: failure for drm/xe: Cleanup xe_mmio.h
== Series Details == Series: drm/xe: Cleanup xe_mmio.h URL : https://patchwork.freedesktop.org/series/133825/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14785_full -> Patchwork_133825v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_133825v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_133825v1_full, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/index.html Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_133825v1_full: ### IGT changes ### Possible regressions * igt@kms_vrr@seamless-rr-switch-virtual: - shard-dg2: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg2-7/igt@kms_...@seamless-rr-switch-virtual.html - shard-dg1: NOTRUN -> [SKIP][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-17/igt@kms_...@seamless-rr-switch-virtual.html New tests - New tests have been introduced between CI_DRM_14785_full and Patchwork_133825v1_full: ### New IGT tests (2) ### * igt@perf@blocking@1-vcs1: - Statuses : 1 pass(s) - Exec time: [10.02] s * igt@perf@oa-exponents@1-vcs1: - Statuses : 1 pass(s) - Exec time: [1.83] s Known issues Here are the changes found in Patchwork_133825v1_full that come from known issues: ### IGT changes ### Issues hit * igt@device_reset@unbind-reset-rebind: - shard-dg1: NOTRUN -> [INCOMPLETE][3] ([i915#9408]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-18/igt@device_re...@unbind-reset-rebind.html * igt@drm_fdinfo@virtual-busy-idle-all: - shard-dg1: NOTRUN -> [SKIP][4] ([i915#8414]) +1 other test skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-18/igt@drm_fdi...@virtual-busy-idle-all.html * igt@drm_fdinfo@virtual-idle: - shard-rkl: NOTRUN -> [FAIL][5] ([i915#7742]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-3/igt@drm_fdi...@virtual-idle.html * igt@gem_ccs@block-multicopy-compressed: - shard-rkl: NOTRUN -> [SKIP][6] ([i915#9323]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-4/igt@gem_...@block-multicopy-compressed.html * igt@gem_ccs@ctrl-surf-copy: - shard-rkl: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-4/igt@gem_...@ctrl-surf-copy.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-rkl: [PASS][8] -> [FAIL][9] ([i915#6268]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-rkl-3/igt@gem_ctx_e...@basic-nohangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-5/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-dg1: NOTRUN -> [SKIP][10] ([i915#8555]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-17/igt@gem_ctx_persiste...@heartbeat-stop.html - shard-dg2: NOTRUN -> [SKIP][11] ([i915#8555]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg2-7/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][12] ([i915#1099]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_exec_balancer@bonded-sync: - shard-dg1: NOTRUN -> [SKIP][13] ([i915#4771]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-18/igt@gem_exec_balan...@bonded-sync.html * igt@gem_exec_balancer@parallel-contexts: - shard-rkl: NOTRUN -> [SKIP][14] ([i915#4525]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-4/igt@gem_exec_balan...@parallel-contexts.html * igt@gem_exec_capture@capture-recoverable: - shard-rkl: NOTRUN -> [SKIP][15] ([i915#6344]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-rkl-4/igt@gem_exec_capt...@capture-recoverable.html * igt@gem_exec_capture@many-4k-incremental: - shard-dg1: NOTRUN -> [FAIL][16] ([i915#9606]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/shard-dg1-17/igt@gem_exec_capt...@many-4k-incremental.
Re: [PATCH 4/5] drm/i915: Compute config and mode valid changes for ultrajoiner
Hi Stanislav,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip linus/master next-20240520]
[cannot apply to drm-intel/for-linux-next-fixes v6.9]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Stanislav-Lisovskiy/drm-i915-Rename-all-bigjoiner-to-joiner/20240520-194208
base: git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:
https://lore.kernel.org/r/20240520073839.23881-5-stanislav.lisovskiy%40intel.com
patch subject: [PATCH 4/5] drm/i915: Compute config and mode valid changes for
ultrajoiner
config: x86_64-randconfig-103-20240521
(https://download.01.org/0day-ci/archive/20240521/202405211228.a5iqwc2h-...@intel.com/config)
compiler: gcc-13 (Ubuntu 13.2.0-4ubuntu3) 13.2.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202405211228.a5iqwc2h-...@intel.com/
cocci warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/display/intel_vdsc.c:813:46-47: Unneeded semicolon
vim +813 drivers/gpu/drm/i915/display/intel_vdsc.c
783
784 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
785 {
786 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
787 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
788 u32 dss_ctl1_val = 0;
789 u32 dss_ctl2_val = 0;
790 int vdsc_instances_per_pipe =
intel_dsc_get_vdsc_per_pipe(crtc_state);
791
792 if (!crtc_state->dsc.compression_enable)
793 return;
794
795 intel_dsc_pps_configure(crtc_state);
796
797 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
798 if (vdsc_instances_per_pipe > 1) {
799 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
800 dss_ctl1_val |= JOINER_ENABLE;
801 }
802
803 if (crtc_state->joiner_pipes) {
804 /*
805 * This bit doesn't seem to follow master/slave logic or
806 * any other logic, so lets just add helper function to
807 * at least hide this hassle..
808 */
809 if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
810 dss_ctl1_val |= ULTRA_JOINER_ENABLE;
811
812 if (intel_crtc_is_joiner_primary_master(crtc_state))
> 813 dss_ctl1_val |= MASTER_ULTRA_JOINER_ENABLE;;
814
815 dss_ctl1_val |= BIG_JOINER_ENABLE;
816
817 if (intel_crtc_is_bigjoiner_master(crtc_state))
818 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
819 }
820 intel_de_write(dev_priv, dss_ctl1_reg(crtc,
crtc_state->cpu_transcoder), dss_ctl1_val);
821 intel_de_write(dev_priv, dss_ctl2_reg(crtc,
crtc_state->cpu_transcoder), dss_ctl2_val);
822 }
823
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
✓ Fi.CI.BAT: success for drm/i915/dp_mst: Enable link training fallback (rev3)
== Series Details ==
Series: drm/i915/dp_mst: Enable link training fallback (rev3)
URL : https://patchwork.freedesktop.org/series/133624/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133624v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133624v3/index.html
Participating hosts (41 -> 39)
--
Missing(2): bat-dg2-11 bat-jsl-3
Known issues
Here are the changes found in Patchwork_133624v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic@lmem0:
- bat-atsm-1: [PASS][1] -> [FAIL][2] ([i915#10378])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-atsm-1/igt@gem_lmem_swapping@ba...@lmem0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133624v3/bat-atsm-1/igt@gem_lmem_swapping@ba...@lmem0.html
- bat-dg2-9: [PASS][3] -> [FAIL][4] ([i915#10378])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133624v3/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@i915_module_load@load:
- bat-arls-3: [PASS][5] -> [ABORT][6] ([i915#11041])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-arls-3/igt@i915_module_l...@load.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133624v3/bat-arls-3/igt@i915_module_l...@load.html
* igt@kms_frontbuffer_tracking@basic:
- bat-arls-2: [PASS][7] -> [DMESG-WARN][8] ([i915#7507])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-arls-2/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133624v3/bat-arls-2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_module_load@load:
- bat-dg2-8: [DMESG-WARN][9] ([i915#10014]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-8/igt@i915_module_l...@load.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133624v3/bat-dg2-8/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_timelines:
- bat-arls-2: [INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-arls-2/igt@i915_selftest@live@gt_timelines.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133624v3/bat-arls-2/igt@i915_selftest@live@gt_timelines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#11041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11041
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#7507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7507
Build changes
-
* Linux: CI_DRM_14785 -> Patchwork_133624v3
CI-20190529: 20190529
CI_DRM_14785: 1ba62f8cea9c797427d45108df1d453f4b343240 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7863: fa1dc232d5d840532521df8a6fcf1fe82c514304 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133624v3: 1ba62f8cea9c797427d45108df1d453f4b343240 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133624v3/index.html
✗ Fi.CI.SPARSE: warning for drm/i915/dp_mst: Enable link training fallback (rev3)
== Series Details == Series: drm/i915/dp_mst: Enable link training fallback (rev3) URL : https://patchwork.freedesktop.org/series/133624/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced sy
✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp_mst: Enable link training fallback (rev3)
== Series Details == Series: drm/i915/dp_mst: Enable link training fallback (rev3) URL : https://patchwork.freedesktop.org/series/133624/ State : warning == Summary == Error: dim checkpatch failed 3901134df2a3 drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs 28d65f0e37e3 drm/i915/dp: Move link train params to a substruct in intel_dp ff4e8e37d80a drm/i915/dp: Move link train fallback to intel_dp_link_training.c -:196: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #196: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:1140: + intel_dp_common_rate(intel_dp, index - 1), total: 0 errors, 1 warnings, 0 checks, 195 lines checked 9b5277bae76d drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values() 2a76291f9545 drm/i915: Factor out function to modeset commit a set of pipes 7bf5284c899d drm/i915/dp: Use a commit modeset for link retraining MST links 82047795cc89 drm/i915/dp: Recheck link state after modeset 2628e40a6de7 drm/i915/dp: Reduce link params only after retrying with unchanged params 44933405fc08 drm/i915/dp: Pass atomic state to link training function eefedc87bcc1 drm/i915/dp: Send a link training modeset-retry uevent to all MST connectors 62a79366ba9d drm/i915/dp: Use check link state work in the hotplug handler b709e61f0cc5 drm/i915/dp: Use check link state work in the detect handler b8bb9bccea89 drm/i915/dp: Use check link state work in the HPD IRQ handler 872973e3096d drm/i915/dp: Disable link retraining after the last fallback step 1f4c395aa4ea drm/i915/dp_mst: Reset intel_dp->link_trained during disabling c9e59063ea28 drm/i915/dp_mst: Enable link training fallback for MST 6572f48d2ae8 drm/i915/dp: Add debugfs entries to set a target link rate/lane count -:74: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #74: FILE: drivers/gpu/drm/i915/display/intel_dp.c:376: + return clamp(intel_dp->link.requested_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); total: 0 errors, 1 warnings, 0 checks, 419 lines checked b4d9d57db44b drm/i915/dp: Add debugfs entries to get the max link rate/lane count 66d34360dd51 drm/i915/dp: Add debugfs entry to force link training failure 52bf93fe9d04 drm/i915/dp: Add debugfs entry to force link retrain d08235d7f4ac drm/i915/dp: Add debugfs entry for link training info
✓ Fi.CI.BAT: success for drm/xe: Cleanup xe_mmio.h
== Series Details == Series: drm/xe: Cleanup xe_mmio.h URL : https://patchwork.freedesktop.org/series/133825/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133825v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/index.html Participating hosts (41 -> 39) -- Missing(2): bat-jsl-3 bat-arls-3 Known issues Here are the changes found in Patchwork_133825v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-11: [PASS][1] -> [FAIL][2] ([i915#10378]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html Possible fixes * igt@i915_module_load@load: - bat-dg2-8: [DMESG-WARN][3] ([i915#10014]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-8/igt@i915_module_l...@load.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/bat-dg2-8/igt@i915_module_l...@load.html * igt@i915_selftest@live@gt_timelines: - bat-arls-2: [INCOMPLETE][5] -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-arls-2/igt@i915_selftest@live@gt_timelines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/bat-arls-2/igt@i915_selftest@live@gt_timelines.html [i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014 [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378 Build changes - * Linux: CI_DRM_14785 -> Patchwork_133825v1 CI-20190529: 20190529 CI_DRM_14785: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7863: fa1dc232d5d840532521df8a6fcf1fe82c514304 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_133825v1: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133825v1/index.html
✗ Fi.CI.SPARSE: warning for drm/xe: Cleanup xe_mmio.h
== Series Details == Series: drm/xe: Cleanup xe_mmio.h URL : https://patchwork.freedesktop.org/series/133825/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: u
✗ Fi.CI.CHECKPATCH: warning for drm/xe: Cleanup xe_mmio.h
== Series Details ==
Series: drm/xe: Cleanup xe_mmio.h
URL : https://patchwork.freedesktop.org/series/133825/
State : warning
== Summary ==
Error: dim checkpatch failed
ff7fd69a1372 drm/i915/display: Add missing include to intel_vga.c
ce3839510f9f drm/xe: Don't rely on indirect includes from xe_mmio.h
0dd2822656ee drm/xe: Cleanup xe_mmio.h
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 54c659660d63 ("drm/xe: Make
xe_mmio_read|write() functions non-inline")'
#9:
We don't need include since commit
total: 1 errors, 0 warnings, 0 checks, 39 lines checked
[PATCH v2 16/21] drm/i915/dp_mst: Enable link training fallback for MST
Reduce the link parameters after a link training failure for MST
outputs, similarly to how this is done for SST.
For now allow the reduction only by staying in the 8b/10b vs. 128b/132b
mode. Enabling the mode switch is left for a follow-up patchset, after
taking measures ensuring that the mode switch happens properly. In
particular a rediscovery of the whole MST topology may be required for
such a switch, see the References below.
Link: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10970
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
.../gpu/drm/i915/display/intel_dp_link_training.c | 13 -
2 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 34d64fe3302ef..c8d940a2ef7af 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5844,11 +5844,7 @@ intel_dp_detect(struct drm_connector *connector,
intel_dp_mst_configure(intel_dp);
- /*
-* TODO: Reset link params when switching to MST mode, until MST
-* supports link training fallback params.
-*/
- if (intel_dp->reset_link_params || intel_dp->is_mst) {
+ if (intel_dp->reset_link_params) {
intel_dp_reset_link_params(intel_dp);
intel_dp->reset_link_params = false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 375f59afd4dec..9a59a28ca36d2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1124,6 +1124,10 @@ static int reduce_link_rate(struct intel_dp *intel_dp,
int current_rate)
new_rate = intel_dp_common_rate(intel_dp, rate_index - 1);
+ /* TODO: Make switching from UHBR to non-UHBR rates work. */
+ if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate))
+ return -1;
+
return new_rate;
}
@@ -1142,15 +1146,6 @@ static int
intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
int new_link_rate;
int new_lane_count;
- /*
-* TODO: Enable fallback on MST links once MST link compute can handle
-* the fallback params.
-*/
- if (intel_dp->is_mst) {
- drm_err(&i915->drm, "Link Training Unsuccessful\n");
- return -1;
- }
-
if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
drm_dbg_kms(&i915->drm,
"Retrying Link training for eDP with max
parameters\n");
--
2.43.3
[PATCH v2 20/21] drm/i915/dp: Add debugfs entry to force link retrain
Add a connector debugfs entry to force retrain an active link. This can
be used to test both custom link parameters (previously set via the
target link lane count/rate entries) or link train failure scenarios
(previously forced via the force-failure entry). The entry will
autoreset after the link-retrain is complete.
v2: Add the entry from intel_dp_link_training.c (Jani)
Cc: Jani Nikula
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 18 +--
.../drm/i915/display/intel_dp_link_training.c | 47 +++
3 files changed, 61 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index dbe1468fe471d..52c69c7eb52f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1771,6 +1771,7 @@ struct intel_dp {
/* Sequential link training failures after a passing LT */
int seq_train_failures;
int force_train_failure;
+ bool force_retrain;
} link;
bool reset_link_params;
int mso_link_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cf4a768fccd15..895074d548671 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5042,7 +5042,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
}
- if (!link_ok)
+ if (!link_ok || intel_dp->link.force_retrain)
intel_ddi_queue_link_check(dig_port, 0);
return !reprobe_needed;
@@ -5091,6 +5091,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
if (intel_psr_enabled(intel_dp))
return false;
+ if (intel_dp->link.force_retrain)
+ return true;
+
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
link_status) < 0)
return false;
@@ -5237,8 +5240,9 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
if (!intel_dp_needs_link_retrain(intel_dp))
return 0;
- drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
- encoder->base.base.id, encoder->base.name);
+ drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced
%s)\n",
+ encoder->base.base.id, encoder->base.name,
+ str_yes_no(intel_dp->link.force_retrain));
for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
const struct intel_crtc_state *crtc_state =
@@ -5266,7 +5270,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
encoder->base.base.id, encoder->base.name,
ERR_PTR(ret));
- return ret;
+ goto out;
}
for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
@@ -5293,7 +5297,11 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
intel_crtc_pch_transcoder(crtc), true);
}
- return 0;
+out:
+ if (ret != -EDEADLK)
+ intel_dp->link.force_retrain = false;
+
+ return ret;
}
static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index b40148a42f442..6fac8421a6918 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -26,6 +26,7 @@
#include "intel_dp.h"
#include "intel_dp_link_training.h"
#include "intel_ddi.h"
+#include "intel_hotplug.h"
#include "intel_panel.h"
#define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] "
@@ -1846,6 +1847,49 @@
DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops,
i915_dp_force_link_training_failure_show,
i915_dp_force_link_training_failure_write, "%llu\n");
+static int i915_dp_force_link_retrain_show(void *data, u64 *val)
+{
+ struct intel_connector *connector = to_intel_connector(data);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_dp *intel_dp;
+ int err;
+
+ err =
drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+ if (err)
+ return err;
+
+ intel_dp = intel_connector_to_intel_dp(connector);
+ *val = intel_dp->link.force_retrain;
+
+ drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+
+ return 0;
+}
+
+static int i915_dp_force_link_retrain_writ
[PATCH v2 21/21] drm/i915/dp: Add debugfs entry for link training info
Add counters for link training pass/failure events and a connector
debugfs entry showing these and relevant link training information. This
is meant to be used by automated testing of the driver's link retraining
and link parameter fallback functionality.
v2:
- Add the entry from intel_dp_link_training.c (Jani)
- Add separate entries for the max link rate/lane count.
Cc: Jani Nikula
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 3 ++
drivers/gpu/drm/i915/display/intel_dp.c | 7 +++-
.../drm/i915/display/intel_dp_link_training.c | 37 +++
3 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 52c69c7eb52f5..6f37f2cca2e99 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1768,6 +1768,9 @@ struct intel_dp {
int requested_lane_count;
int requested_rate;
bool retrain_disabled;
+ int train_count;
+ int retrain_count;
+ int all_train_failures;
/* Sequential link training failures after a passing LT */
int seq_train_failures;
int force_train_failure;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 895074d548671..0337be8416082 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2996,6 +2996,9 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp)
intel_dp->link.max_lane_count =
intel_dp_max_common_lane_count(intel_dp);
intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
intel_dp->link.retrain_disabled = false;
+ intel_dp->link.train_count = 0;
+ intel_dp->link.retrain_count = 0;
+ intel_dp->link.all_train_failures = 0;
intel_dp->link.seq_train_failures = 0;
}
@@ -5298,8 +5301,10 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
}
out:
- if (ret != -EDEADLK)
+ if (ret != -EDEADLK) {
+ intel_dp->link.retrain_count++;
intel_dp->link.force_retrain = false;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6fac8421a6918..969a5fc4c7b2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1490,6 +1490,8 @@ void intel_dp_start_link_train(struct intel_atomic_state
*state,
else
passed = intel_dp_link_train_all_phys(intel_dp, crtc_state,
lttpr_count);
+ intel_dp->link.train_count++;
+
if (intel_dp->link.force_train_failure) {
intel_dp->link.force_train_failure--;
lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training
failure\n");
@@ -1499,6 +1501,7 @@ void intel_dp_start_link_train(struct intel_atomic_state
*state,
return;
}
+ intel_dp->link.all_train_failures++;
intel_dp->link.seq_train_failures++;
/*
@@ -1890,6 +1893,37 @@ DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops,
i915_dp_force_link_retrain_show,
i915_dp_force_link_retrain_write, "%llu\n");
+static int i915_dp_link_training_info_show(struct seq_file *m, void *data)
+{
+ struct intel_connector *connector = to_intel_connector(m->private);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_dp *intel_dp;
+ int ret;
+
+ ret =
drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+ if (ret)
+ return ret;
+
+ intel_dp = intel_connector_to_intel_dp(connector);
+
+ seq_printf(m,
+ "retrain_disabled: %s\n"
+ "train_count: %d\n"
+ "retrain_count: %d\n"
+ "all_train_failures: %d\n"
+ "seq_train_failures: %d\n",
+ str_yes_no(intel_dp->link.retrain_disabled),
+ intel_dp->link.train_count,
+ intel_dp->link.retrain_count,
+ intel_dp->link.all_train_failures,
+ intel_dp->link.seq_train_failures);
+
+ drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(i915_dp_link_training_info);
+
void intel_dp_link_training_debugfs_add(struct intel_connector *connector)
{
struct dentry *root = connector->base.debugfs_entry;
@@ -1915,4 +1949,7 @@ void intel_dp_link_training_debugfs_add(struct
intel_connector *connector)
debugfs_create_file("i915_dp_force_link_retrain", 0644, root,
connector, &i915_dp_force_link_retrain_f
[PATCH v2 11/21] drm/i915/dp: Use check link state work in the hotplug handler
Simplify things by retraining a DP link if a bad link is detected in the
hotplug handler from the encoder's check link state work, similarly to
how this is done after a modeset link training failure.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/g4x_dp.c| 20 +---
drivers/gpu/drm/i915/display/intel_ddi.c | 11 +--
drivers/gpu/drm/i915/display/intel_dp.c | 8
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
4 files changed, 15 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index 0d7424a7581e6..1f3b6b3956a1c 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1160,9 +1160,7 @@ intel_dp_hotplug(struct intel_encoder *encoder,
struct intel_connector *connector)
{
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- struct drm_modeset_acquire_ctx ctx;
enum intel_hotplug_state state;
- int ret;
if (intel_dp->compliance.test_active &&
intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
@@ -1173,23 +1171,7 @@ intel_dp_hotplug(struct intel_encoder *encoder,
state = intel_encoder_hotplug(encoder, connector);
- drm_modeset_acquire_init(&ctx, 0);
-
- for (;;) {
- ret = intel_dp_retrain_link(encoder, &ctx);
-
- if (ret == -EDEADLK) {
- drm_modeset_backoff(&ctx);
- continue;
- }
-
- break;
- }
-
- drm_modeset_drop_locks(&ctx);
- drm_modeset_acquire_fini(&ctx);
- drm_WARN(encoder->base.dev, ret,
-"Acquiring modeset locks failed with %i\n", ret);
+ intel_dp_check_link_state(intel_dp);
/*
* Keeping it consistent with intel_ddi_hotplug() and
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 58e57a7704811..ea24404724075 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4566,14 +4566,13 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
state = intel_encoder_hotplug(encoder, connector);
if (!intel_tc_port_link_reset(dig_port)) {
- intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) {
- if (connector->base.connector_type ==
DRM_MODE_CONNECTOR_HDMIA)
+ if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
{
+ intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
ret = intel_hdmi_reset_link(encoder, &ctx);
- else
- ret = intel_dp_retrain_link(encoder, &ctx);
+ drm_WARN_ON(encoder->base.dev, ret);
+ } else {
+ intel_dp_check_link_state(intel_dp);
}
-
- drm_WARN_ON(encoder->base.dev, ret);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 87f9f12814b93..ff4ed6bb520d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5064,6 +5064,14 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
return !intel_dp_link_ok(intel_dp, link_status);
}
+void intel_dp_check_link_state(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+
+ if (intel_dp_needs_link_retrain(intel_dp))
+ intel_ddi_queue_link_check(dig_port, 0);
+}
+
static bool intel_dp_has_connector(struct intel_dp *intel_dp,
const struct drm_connector_state *conn_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 24777c035e2ad..3fa53ac601d58 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -57,6 +57,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
struct drm_modeset_acquire_ctx *ctx,
u8 *pipe_mask);
+void intel_dp_check_link_state(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
--
2.43.3
[PATCH v2 19/21] drm/i915/dp: Add debugfs entry to force link training failure
Add a connector debugfs entry to force a failure during the following
1-2 link training. The entry will auto-reset after the specified link
training events are complete.
v2: Add the entry from intel_dp_link_training.c (Jani)
Cc: Jani Nikula
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 1 +
.../drm/i915/display/intel_dp_link_training.c | 52 ++-
2 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e1c41cece249d..dbe1468fe471d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1770,6 +1770,7 @@ struct intel_dp {
bool retrain_disabled;
/* Sequential link training failures after a passing LT */
int seq_train_failures;
+ int force_train_failure;
} link;
bool reset_link_params;
int mso_link_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 764187bc42ff9..b40148a42f442 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1489,7 +1489,10 @@ void intel_dp_start_link_train(struct intel_atomic_state
*state,
else
passed = intel_dp_link_train_all_phys(intel_dp, crtc_state,
lttpr_count);
- if (passed) {
+ if (intel_dp->link.force_train_failure) {
+ intel_dp->link.force_train_failure--;
+ lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training
failure\n");
+ } else if (passed) {
intel_dp->link.seq_train_failures = 0;
intel_ddi_queue_link_check(dig_port, 2000);
return;
@@ -1799,6 +1802,50 @@ static int i915_dp_max_lane_count_show(void *data, u64
*val)
}
DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops,
i915_dp_max_lane_count_show, NULL, "%llu\n");
+static int i915_dp_force_link_training_failure_show(void *data, u64 *val)
+{
+ struct intel_connector *connector = to_intel_connector(data);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_dp *intel_dp;
+ int err;
+
+ err =
drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+ if (err)
+ return err;
+
+ intel_dp = intel_connector_to_intel_dp(connector);
+ *val = intel_dp->link.force_train_failure;
+
+ drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+
+ return 0;
+}
+
+static int i915_dp_force_link_training_failure_write(void *data, u64 val)
+{
+ struct intel_connector *connector = to_intel_connector(data);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_dp *intel_dp;
+ int err;
+
+ if (val > 2)
+ return -EINVAL;
+
+ err =
drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+ if (err)
+ return err;
+
+ intel_dp = intel_connector_to_intel_dp(connector);
+ intel_dp->link.force_train_failure = val;
+
+ drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+
+ return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops,
+i915_dp_force_link_training_failure_show,
+i915_dp_force_link_training_failure_write, "%llu\n");
+
void intel_dp_link_training_debugfs_add(struct intel_connector *connector)
{
struct dentry *root = connector->base.debugfs_entry;
@@ -1818,4 +1865,7 @@ void intel_dp_link_training_debugfs_add(struct
intel_connector *connector)
debugfs_create_file("i915_dp_max_lane_count", 0444, root,
connector, &i915_dp_max_lane_count_fops);
+
+ debugfs_create_file("i915_dp_force_link_training_failure", 0644, root,
+ connector,
&i915_dp_force_link_training_failure_fops);
}
--
2.43.3
[PATCH v2 14/21] drm/i915/dp: Disable link retraining after the last fallback step
After a link training failure if the link parameters can't be further
reduced, there is no point in trying to retrain the link in the driver.
This avoids excessive retrain attempts after detecting a bad link, for
instance while handling MST HPD IRQs, which is likely redundant as the
link training failed already twice with the same minimum link
parameters. Userspace can still try to retrain the link with these
parameters via a modeset.
While at it make the error message more accurate and emit instead a
debug message if the link training failure was only forced for testing
purposes.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 4
.../drm/i915/display/intel_dp_link_training.c | 22 +--
3 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index bde518c843468..eb0cac3e27acf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1765,6 +1765,7 @@ struct intel_dp {
int max_lane_count;
/* Max rate for the current link */
int max_rate;
+ bool retrain_disabled;
/* Sequential link training failures after a passing LT */
int seq_train_failures;
} link;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index b72dbd7becb74..34d64fe3302ef 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2950,6 +2950,7 @@ static void intel_dp_reset_link_params(struct intel_dp
*intel_dp)
{
intel_dp->link.max_lane_count =
intel_dp_max_common_lane_count(intel_dp);
intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
+ intel_dp->link.retrain_disabled = false;
intel_dp->link.seq_train_failures = 0;
}
@@ -5061,6 +5062,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
intel_dp->lane_count))
return false;
+ if (intel_dp->link.retrain_disabled)
+ return false;
+
if (intel_dp->link.seq_train_failures)
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 97d499e4b6ef7..375f59afd4dec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1165,10 +1165,8 @@ static int
intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
new_link_rate = intel_dp_max_common_rate(intel_dp);
}
- if (new_lane_count < 0) {
- drm_err(&i915->drm, "Link Training Unsuccessful\n");
+ if (new_lane_count < 0)
return -1;
- }
if (intel_dp_is_edp(intel_dp) &&
!intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate,
new_lane_count)) {
@@ -1187,7 +1185,7 @@ static int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
return 0;
}
-static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state
*state,
+static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state
*state,
struct intel_dp *intel_dp,
const struct
intel_crtc_state *crtc_state)
{
@@ -1195,7 +1193,7 @@ static void
intel_dp_schedule_fallback_link_training(struct intel_atomic_state *
if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on
disconnected sink.\n");
- return;
+ return true;
}
if (intel_dp->hobl_active) {
@@ -1203,11 +1201,13 @@ static void
intel_dp_schedule_fallback_link_training(struct intel_atomic_state *
"Link Training failed with HOBL active, not enabling it
from now on\n");
intel_dp->hobl_failed = true;
} else if (intel_dp_get_link_train_fallback_values(intel_dp,
crtc_state)) {
- return;
+ return false;
}
/* Schedule a Hotplug Uevent to userspace to start modeset */
intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
+
+ return true;
}
/* Perform the link training on all LTTPRs and the DPRX on a link. */
@@ -1518,7 +1518,15 @@ void intel_dp_start_link_train(struct intel_atomic_state
*state,
return;
}
- intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state);
+ if (intel_dp_schedule_fallback_link_training(state, intel_dp,
crtc_state))
+ return;
+
+ intel_dp->link.retrain_disa
[PATCH v2 13/21] drm/i915/dp: Use check link state work in the HPD IRQ handler
Simplify things by retraining a DP link if a bad link is detected in the
HPD IRQ handler from the encoder's check link state work, similarly to
how this is done after a modeset link training failure.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 70b00e5ae7ad7..b72dbd7becb74 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4950,6 +4950,7 @@ static bool
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
bool link_ok = true;
bool reprobe_needed = false;
@@ -4995,7 +4996,10 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
}
- return link_ok && !reprobe_needed;
+ if (!link_ok)
+ intel_ddi_queue_link_check(dig_port, 0);
+
+ return !reprobe_needed;
}
static void
@@ -5453,9 +5457,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
/* Handle CEC interrupts, if any */
drm_dp_cec_irq(&intel_dp->aux);
- /* defer to the hotplug work for link retraining if needed */
- if (intel_dp_needs_link_retrain(intel_dp))
- return false;
+ intel_dp_check_link_state(intel_dp);
intel_psr_short_pulse(intel_dp);
--
2.43.3
[PATCH v2 17/21] drm/i915/dp: Add debugfs entries to set a target link rate/lane count
Add connector debugfs entries to set a target link rate/lane count to be
used by a link training afterwards. After setting a target link
rate/lane count reset the link training parameters and for a non-auto
target disable reducing the link parameters via the fallback logic. The
former one can be used after testing link training failure scenarios
- via debugfs entries added later - to reset the reduced link parameters
after the test.
v2:
- Add the entries from intel_dp_link_training.c (Jani)
- Rename the entries to i915_dp_set_link_rate/lane_count.
Cc: Jani Nikula
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_debugfs.c | 2 +
.../drm/i915/display/intel_display_types.h| 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 63 -
drivers/gpu/drm/i915/display/intel_dp.h | 2 +
.../drm/i915/display/intel_dp_link_training.c | 230 ++
.../drm/i915/display/intel_dp_link_training.h | 4 +
6 files changed, 294 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 35f9f86ef70f4..f83ffa2534925 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -23,6 +23,7 @@
#include "intel_display_types.h"
#include "intel_dmc.h"
#include "intel_dp.h"
+#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
#include "intel_drrs.h"
#include "intel_fbc.h"
@@ -1515,6 +1516,7 @@ void intel_connector_debugfs_add(struct intel_connector
*connector)
intel_drrs_connector_debugfs_add(connector);
intel_pps_connector_debugfs_add(connector);
intel_psr_connector_debugfs_add(connector);
+ intel_dp_link_training_debugfs_add(connector);
if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector_type == DRM_MODE_CONNECTOR_HDMIA ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index eb0cac3e27acf..e1c41cece249d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1765,6 +1765,8 @@ struct intel_dp {
int max_lane_count;
/* Max rate for the current link */
int max_rate;
+ int requested_lane_count;
+ int requested_rate;
bool retrain_disabled;
/* Sequential link training failures after a passing LT */
int seq_train_failures;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c8d940a2ef7af..cf4a768fccd15 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -345,7 +345,7 @@ int intel_dp_max_common_rate(struct intel_dp *intel_dp)
return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
}
-static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
+int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
{
int vbt_max_lanes =
intel_bios_dp_max_lane_count(dig_port->base.devdata);
int max_lanes = dig_port->max_lanes;
@@ -371,19 +371,39 @@ int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp)
return min3(source_max, sink_max, lane_max);
}
+static int requested_lane_count(struct intel_dp *intel_dp)
+{
+ return clamp(intel_dp->link.requested_lane_count, 1,
intel_dp_max_common_lane_count(intel_dp));
+}
+
int intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
- switch (intel_dp->link.max_lane_count) {
+ int lane_count;
+
+ if (intel_dp->link.requested_lane_count)
+ lane_count = requested_lane_count(intel_dp);
+ else
+ lane_count = intel_dp->link.max_lane_count;
+
+ switch (lane_count) {
case 1:
case 2:
case 4:
- return intel_dp->link.max_lane_count;
+ return lane_count;
default:
- MISSING_CASE(intel_dp->link.max_lane_count);
+ MISSING_CASE(lane_count);
return 1;
}
}
+static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
+{
+ if (intel_dp->link.requested_lane_count)
+ return requested_lane_count(intel_dp);
+
+ return 1;
+}
+
/*
* The required data bandwidth for a mode with given pixel clock and bpp. This
* is the required net bandwidth independent of the data bandwidth efficiency.
@@ -1306,16 +1326,38 @@ static void intel_dp_print_rates(struct intel_dp
*intel_dp)
drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
}
+static int requested_rate(struct intel_dp *intel_dp)
+{
+ int len = intel_dp_common_len_rate_limit(intel_dp,
intel_dp->link.requested_rate);
+
+ if (len == 0)
+ return intel_dp_common_rate(intel_dp, 0);
+
+ return intel_dp_com
[PATCH v2 09/21] drm/i915/dp: Pass atomic state to link training function
From: Imre Deak
The next patch adds sending a modeset-retry uevent after a link training
failure to all MST connectors on link. This requires the atomic state,
so pass it to intel_dp_start_link_train(). In case of SST where
retraining still happens by calling this function directly instead of a
modeset commit the atomic state is not available and NULL is passed
instead. This is ok, since in this case the encoder's only DP connector
is available from intel_dp->attached_connector not requiring the atomic
state.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 4 +++-
drivers/gpu/drm/i915/display/intel_dp_link_training.h | 4 +++-
5 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index 4363e32a834df..0d7424a7581e6 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -707,7 +707,7 @@ static void intel_enable_dp(struct intel_atomic_state
*state,
intel_dp_configure_protocol_converter(intel_dp, pipe_config);
intel_dp_check_frl_training(intel_dp);
intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
- intel_dp_start_link_train(intel_dp, pipe_config);
+ intel_dp_start_link_train(state, intel_dp, pipe_config);
intel_dp_stop_link_train(intel_dp, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 86358ec27e685..58e57a7704811 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2586,7 +2586,7 @@ static void mtl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
* (timeout after 800 us)
*/
- intel_dp_start_link_train(intel_dp, crtc_state);
+ intel_dp_start_link_train(state, intel_dp, crtc_state);
/* 6.n Set DP_TP_CTL link training to Normal */
if (!is_trans_port_sync_mode(crtc_state))
@@ -2728,7 +2728,7 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
* (timeout after 800 us)
*/
- intel_dp_start_link_train(intel_dp, crtc_state);
+ intel_dp_start_link_train(state, intel_dp, crtc_state);
/* 7.k Set DP_TP_CTL link training to Normal */
if (!is_trans_port_sync_mode(crtc_state))
@@ -2795,7 +2795,7 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
to_intel_connector(conn_state->connector),
crtc_state);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
- intel_dp_start_link_train(intel_dp, crtc_state);
+ intel_dp_start_link_train(state, intel_dp, crtc_state);
if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
!is_trans_port_sync_mode(crtc_state))
intel_dp_stop_link_train(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7c824c5a13346..1f0b7cceea2dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5214,7 +5214,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
intel_dp_check_frl_training(intel_dp);
intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
- intel_dp_start_link_train(intel_dp, crtc_state);
+ intel_dp_start_link_train(NULL, intel_dp, crtc_state);
intel_dp_stop_link_train(intel_dp, crtc_state);
break;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index e804f0b801c02..4f60daa97407d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1453,6 +1453,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
/**
* intel_dp_start_link_train - start link training
+ * @state: Atomic state
* @intel_dp: DP struct
* @crtc_state: state for CRTC attached to the encoder
*
@@ -1461,7 +1462,8 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
* fails.
* After calling this function intel_dp_stop_link_train() must be called.
*/
-void intel_dp_start_link_train(struct intel_dp *intel_dp,
+void intel_dp_start_link_train(struct intel_atomic_state *state,
+ struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = dp
[PATCH v2 15/21] drm/i915/dp_mst: Reset intel_dp->link_trained during disabling
Reset the flag indicating an active link after disabling an MST link, similarly to how this is done for SST outputs. This avoids trying to retrain an MST link while its disabled. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c9c5d235744ab..66c1c59268167 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -981,6 +981,9 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, drm_dbg_kms(&i915->drm, "active links %d\n", intel_dp->active_mst_links); + if (intel_dp->active_mst_links == 1) + intel_dp->link_trained = false; + intel_hdcp_disable(intel_mst->connector); intel_dp_sink_disable_decompression(state, connector, old_crtc_state); -- 2.43.3
[PATCH v2 18/21] drm/i915/dp: Add debugfs entries to get the max link rate/lane count
Add connector debugfs entries to get the maximum link rate and lane
count.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_dp_link_training.c | 46 +++
1 file changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a6021e17cc1ef..764187bc42ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1759,6 +1759,46 @@ static ssize_t i915_dp_set_lane_count_write(struct file
*file,
}
DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_set_lane_count);
+static int i915_dp_max_link_rate_show(void *data, u64 *val)
+{
+ struct intel_connector *connector = to_intel_connector(data);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_dp *intel_dp;
+ int err;
+
+ err =
drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+ if (err)
+ return err;
+
+ intel_dp = intel_connector_to_intel_dp(connector);
+ *val = intel_dp->link.max_rate;
+
+ drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+
+ return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops,
i915_dp_max_link_rate_show, NULL, "%llu\n");
+
+static int i915_dp_max_lane_count_show(void *data, u64 *val)
+{
+ struct intel_connector *connector = to_intel_connector(data);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_dp *intel_dp;
+ int err;
+
+ err =
drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+ if (err)
+ return err;
+
+ intel_dp = intel_connector_to_intel_dp(connector);
+ *val = intel_dp->link.max_lane_count;
+
+ drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+
+ return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops,
i915_dp_max_lane_count_show, NULL, "%llu\n");
+
void intel_dp_link_training_debugfs_add(struct intel_connector *connector)
{
struct dentry *root = connector->base.debugfs_entry;
@@ -1772,4 +1812,10 @@ void intel_dp_link_training_debugfs_add(struct
intel_connector *connector)
debugfs_create_file("i915_dp_set_lane_count", 0644, root,
connector, &i915_dp_set_lane_count_fops);
+
+ debugfs_create_file("i915_dp_max_link_rate", 0444, root,
+ connector, &i915_dp_max_link_rate_fops);
+
+ debugfs_create_file("i915_dp_max_lane_count", 0444, root,
+ connector, &i915_dp_max_lane_count_fops);
}
--
2.43.3
[PATCH v2 07/21] drm/i915/dp: Recheck link state after modeset
Recheck the link state after a passing link training, with a 2 sec delay
to account for cases where the link goes bad following the link training
and the sink doesn't report this via an HPD IRQ.
The delayed work added here will be also used by a later patch after a
failed link training to try to retrain the link with unchanged link
params before reducing the link params.
v2: Don't flush an uninitialized delayed work (on HDMI-only DDI ports).
v3: Add the work to intel_digital_port instead of intel_dp.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/g4x_dp.c | 7
drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++
drivers/gpu/drm/i915/display/intel_ddi.h | 4 +++
.../drm/i915/display/intel_display_types.h| 3 ++
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
.../drm/i915/display/intel_dp_link_training.c | 12 +--
6 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index 06ec04e667e32..4363e32a834df 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -20,6 +20,7 @@
#include "intel_dp_aux.h"
#include "intel_dp_link_training.h"
#include "intel_dpio_phy.h"
+#include "intel_ddi.h"
#include "intel_fifo_underrun.h"
#include "intel_hdmi.h"
#include "intel_hotplug.h"
@@ -1241,6 +1242,10 @@ static bool ilk_digital_port_connected(struct
intel_encoder *encoder)
static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
{
+ struct intel_digital_port *dig_port =
enc_to_dig_port(to_intel_encoder(encoder));
+
+ intel_ddi_flush_link_check_work(dig_port);
+
intel_dp_encoder_flush_work(encoder);
drm_encoder_cleanup(encoder);
@@ -1309,6 +1314,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
dig_port->aux_ch = AUX_CH_NONE;
+ intel_ddi_init_link_check_work(dig_port);
+
intel_connector = intel_connector_alloc();
if (!intel_connector)
goto err_connector_alloc;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 170ba01786cf8..86358ec27e685 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4360,6 +4360,7 @@ static void intel_ddi_encoder_destroy(struct drm_encoder
*encoder)
struct drm_i915_private *i915 = to_i915(encoder->dev);
struct intel_digital_port *dig_port =
enc_to_dig_port(to_intel_encoder(encoder));
+ intel_ddi_flush_link_check_work(dig_port);
intel_dp_encoder_flush_work(encoder);
if (intel_encoder_is_tc(&dig_port->base))
intel_tc_port_cleanup(dig_port);
@@ -4441,6 +4442,37 @@ intel_ddi_init_dp_connector(struct intel_digital_port
*dig_port)
return connector;
}
+static void intel_ddi_link_check_work_fn(struct work_struct *work)
+{
+ struct intel_digital_port *dig_port =
+ container_of(work, typeof(*dig_port), check_link_work.work);
+ struct intel_encoder *encoder = &dig_port->base;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret;
+
+ intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
+ if (dig_port->dp.attached_connector)
+ ret = intel_dp_retrain_link(encoder, &ctx);
+}
+
+void intel_ddi_init_link_check_work(struct intel_digital_port *dig_port)
+{
+ INIT_DELAYED_WORK(&dig_port->check_link_work,
intel_ddi_link_check_work_fn);
+}
+
+void intel_ddi_flush_link_check_work(struct intel_digital_port *dig_port)
+{
+ cancel_delayed_work_sync(&dig_port->check_link_work);
+}
+
+void intel_ddi_queue_link_check(struct intel_digital_port *dig_port, int
delay_ms)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ mod_delayed_work(i915->unordered_wq,
+&dig_port->check_link_work,
msecs_to_jiffies(delay_ms));
+}
+
static int intel_hdmi_reset_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx)
{
@@ -4911,6 +4943,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
dig_port->aux_ch = AUX_CH_NONE;
+ intel_ddi_init_link_check_work(dig_port);
+
encoder = &dig_port->base;
encoder->devdata = devdata;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
b/drivers/gpu/drm/i915/display/intel_ddi.h
index 434de7196875a..b67714483f3cc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -15,6 +15,7 @@ struct intel_bios_encoder_data;
struct intel_connector;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_digital_port;
struct intel_dp;
struct intel_dpll_hw_state;
struct intel_encoder;
@@ -53,6 +54,9 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_wait_ddi_b
[PATCH v2 04/21] drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values()
Reduce the indentation in intel_dp_get_link_train_fallback_values() by
adding separate helpers to reduce the link rate and lane count. Also
simplify things by passing crtc_state to the function.
This also prepares for later patches in the patchset adding a limitation
on how the link params are reduced.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_dp_link_training.c | 82 ---
1 file changed, 51 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 4db293f256896..edc970036866a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1109,11 +1109,37 @@ static bool
intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
return true;
}
+static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate)
+{
+ int rate_index;
+ int new_rate;
+
+ rate_index = intel_dp_rate_index(intel_dp->common_rates,
+intel_dp->num_common_rates,
+current_rate);
+
+ if (rate_index <= 0)
+ return -1;
+
+ new_rate = intel_dp_common_rate(intel_dp, rate_index - 1);
+
+ return new_rate;
+}
+
+static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count)
+{
+ if (current_lane_count > 1)
+ return current_lane_count >> 1;
+
+ return -1;
+}
+
static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
- int link_rate, u8 lane_count)
+ const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int index;
+ int new_link_rate;
+ int new_lane_count;
/*
* TODO: Enable fallback on MST links once MST link compute can handle
@@ -1131,36 +1157,32 @@ static int
intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
return 0;
}
- index = intel_dp_rate_index(intel_dp->common_rates,
- intel_dp->num_common_rates,
- link_rate);
- if (index > 0) {
- if (intel_dp_is_edp(intel_dp) &&
- !intel_dp_can_link_train_fallback_for_edp(intel_dp,
-
intel_dp_common_rate(intel_dp, index - 1),
- lane_count)) {
- drm_dbg_kms(&i915->drm,
- "Retrying Link training for eDP with same
parameters\n");
- return 0;
- }
- intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index
- 1);
- intel_dp->link.max_lane_count = lane_count;
- } else if (lane_count > 1) {
- if (intel_dp_is_edp(intel_dp) &&
- !intel_dp_can_link_train_fallback_for_edp(intel_dp,
-
intel_dp_max_common_rate(intel_dp),
- lane_count >> 1))
{
- drm_dbg_kms(&i915->drm,
- "Retrying Link training for eDP with same
parameters\n");
- return 0;
- }
- intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
- intel_dp->link.max_lane_count = lane_count >> 1;
- } else {
+ new_lane_count = crtc_state->lane_count;
+ new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
+ if (new_link_rate < 0) {
+ new_lane_count = reduce_lane_count(intel_dp,
crtc_state->lane_count);
+ new_link_rate = intel_dp_max_common_rate(intel_dp);
+ }
+
+ if (new_lane_count < 0) {
drm_err(&i915->drm, "Link Training Unsuccessful\n");
return -1;
}
+ if (intel_dp_is_edp(intel_dp) &&
+ !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate,
new_lane_count)) {
+ drm_dbg_kms(&i915->drm,
+ "Retrying Link training for eDP with same
parameters\n");
+ return 0;
+ }
+
+ drm_dbg_kms(&i915->drm, "Reducing link parameters from %dx%d to
%dx%d\n",
+ crtc_state->lane_count, crtc_state->port_clock,
+ new_lane_count, new_link_rate);
+
+ intel_dp->link.max_rate = new_link_rate;
+ intel_dp->link.max_lane_count = new_lane_count;
+
return 0;
}
@@ -1178,9 +1200,7 @@ static void
intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
lt_dbg(intel_dp, DP_PHY_DPRX,
"Link Train
[PATCH v2 12/21] drm/i915/dp: Use check link state work in the detect handler
Simplify things by retraining a DP link if a bad link is detected in the
connector detect handler from the encoder's check link state work,
similarly to how this is done after a modeset link training failure.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ff4ed6bb520d8..70b00e5ae7ad7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5863,11 +5863,8 @@ intel_dp_detect(struct drm_connector *connector,
* Some external monitors do not signal loss of link synchronization
* with an IRQ_HPD, so force a link status check.
*/
- if (!intel_dp_is_edp(intel_dp)) {
- ret = intel_dp_retrain_link(encoder, ctx);
- if (ret)
- return ret;
- }
+ if (!intel_dp_is_edp(intel_dp))
+ intel_dp_check_link_state(intel_dp);
/*
* Clearing NACK and defer counts to get their exact values
--
2.43.3
[PATCH v2 02/21] drm/i915/dp: Move link train params to a substruct in intel_dp
For clarity move the link training parameters updated during link
training based on the pass/fail LT result under a substruct in intel_dp.
This prepares for later patches in this patchset adding similar params
here. Rename intel_dp_reset_max_link_params() to
intel_dp_reset_link_params() to better reflect what state gets reset.
v2: Add the parameters to a more generic link substruct. (Jani)
Cc: Jani Nikula
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 13
drivers/gpu/drm/i915/display/intel_dp.c | 30 +--
2 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9678c2b157f6f..1e44a23ca2125 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1739,7 +1739,6 @@ struct intel_dp {
u8 lane_count;
u8 sink_count;
bool link_trained;
- bool reset_link_params;
bool use_max_params;
u8 dpcd[DP_RECEIVER_CAP_SIZE];
u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
@@ -1760,10 +1759,14 @@ struct intel_dp {
/* intersection of source and sink rates */
int num_common_rates;
int common_rates[DP_MAX_SUPPORTED_RATES];
- /* Max lane count for the current link */
- int max_link_lane_count;
- /* Max rate for the current link */
- int max_link_rate;
+ struct {
+ /* TODO: move the rest of link specific fields to here */
+ /* Max lane count for the current link */
+ int max_lane_count;
+ /* Max rate for the current link */
+ int max_rate;
+ } link;
+ bool reset_link_params;
int mso_link_count;
int mso_pixel_overlap;
/* sink or branch descriptor */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c0a3b6d506817..ceedd3ef41946 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -372,13 +372,13 @@ int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp)
int intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
- switch (intel_dp->max_link_lane_count) {
+ switch (intel_dp->link.max_lane_count) {
case 1:
case 2:
case 4:
- return intel_dp->max_link_lane_count;
+ return intel_dp->link.max_lane_count;
default:
- MISSING_CASE(intel_dp->max_link_lane_count);
+ MISSING_CASE(intel_dp->link.max_lane_count);
return 1;
}
}
@@ -644,7 +644,7 @@ static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp, int link_rate,
* boot-up.
*/
if (link_rate == 0 ||
- link_rate > intel_dp->max_link_rate)
+ link_rate > intel_dp->link.max_rate)
return false;
if (lane_count == 0 ||
@@ -705,8 +705,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp,
"Retrying Link training for eDP with same
parameters\n");
return 0;
}
- intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index
- 1);
- intel_dp->max_link_lane_count = lane_count;
+ intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index
- 1);
+ intel_dp->link.max_lane_count = lane_count;
} else if (lane_count > 1) {
if (intel_dp_is_edp(intel_dp) &&
!intel_dp_can_link_train_fallback_for_edp(intel_dp,
@@ -716,8 +716,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp,
"Retrying Link training for eDP with same
parameters\n");
return 0;
}
- intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
- intel_dp->max_link_lane_count = lane_count >> 1;
+ intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
+ intel_dp->link.max_lane_count = lane_count >> 1;
} else {
drm_err(&i915->drm, "Link Training Unsuccessful\n");
return -1;
@@ -1382,7 +1382,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
int len;
- len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
+ len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);
return intel_dp_common_rate(intel_dp, len - 1);
}
@@ -3017,10 +3017,10 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
intel_dp->lane_count = lane_count;
}
-static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
+static void intel_dp_reset_link_params(struct intel_dp *intel_dp)
{
- intel_dp->max_link_lane_count =
intel_
[PATCH v2 08/21] drm/i915/dp: Reduce link params only after retrying with unchanged params
Try to maintain the current link parameters by retrying the link
training with unchanged link parameters before reducing these parameters
(sending an uevent to userspace to retrain the link instead).
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_types.h| 2 ++
drivers/gpu/drm/i915/display/intel_dp.c | 4
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8
3 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9317c1ae04efe..bde518c843468 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1765,6 +1765,8 @@ struct intel_dp {
int max_lane_count;
/* Max rate for the current link */
int max_rate;
+ /* Sequential link training failures after a passing LT */
+ int seq_train_failures;
} link;
bool reset_link_params;
int mso_link_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8da277f0c2735..7c824c5a13346 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2950,6 +2950,7 @@ static void intel_dp_reset_link_params(struct intel_dp
*intel_dp)
{
intel_dp->link.max_lane_count =
intel_dp_max_common_lane_count(intel_dp);
intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
+ intel_dp->link.seq_train_failures = 0;
}
/* Enable backlight PWM and backlight PP control. */
@@ -5056,6 +5057,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
intel_dp->lane_count))
return false;
+ if (intel_dp->link.seq_train_failures)
+ return true;
+
/* Retrain if link not ok */
return !intel_dp_link_ok(intel_dp, link_status);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index ad1fbb150ff90..e804f0b801c02 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1486,10 +1486,13 @@ void intel_dp_start_link_train(struct intel_dp
*intel_dp,
passed = intel_dp_link_train_all_phys(intel_dp, crtc_state,
lttpr_count);
if (passed) {
+ intel_dp->link.seq_train_failures = 0;
intel_ddi_queue_link_check(dig_port, 2000);
return;
}
+ intel_dp->link.seq_train_failures++;
+
/*
* Ignore the link failure in CI
*
@@ -1507,6 +1510,11 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
return;
}
+ if (intel_dp->link.seq_train_failures < 2) {
+ intel_ddi_queue_link_check(dig_port, 0);
+ return;
+ }
+
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
}
--
2.43.3
[PATCH v2 06/21] drm/i915/dp: Use a commit modeset for link retraining MST links
Instead of direct calls to the link train functions, retrain the link
via a commit modeset. The direct call means that the output port will be
disabled/re-enabled while the rest of the pipeline (transcoder) is
active, which doesn't seem to work on MST at least. It leads to
underruns and black screen, presumedly because the transcoder is not
disabled/re-enabled along the port.
Leave switching to a commit modeset on SST for a later patchset, as that
seems to work ok currently (though better to using a commit there too,
due to the suppressed underruns).
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 81e620dd33bb7..120f7b420807b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5147,6 +5147,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_crtc *crtc;
u8 pipe_mask;
+ bool mst_output = false;
int ret;
if (!intel_dp_is_connected(intel_dp))
@@ -5177,6 +5178,11 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
+ mst_output = true;
+ break;
+ }
+
/* Suppress underruns caused by re-training */
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe,
false);
if (crtc_state->has_pch_encoder)
@@ -5184,16 +5190,23 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
intel_crtc_pch_transcoder(crtc), false);
}
+ /* TODO: use a modeset for SST as well. */
+ if (mst_output) {
+ ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx);
+
+ if (ret && ret != -EDEADLK)
+ drm_dbg_kms(&dev_priv->drm,
+ "[ENCODER:%d:%s] link retraining failed:
%pe\n",
+ encoder->base.base.id, encoder->base.name,
+ ERR_PTR(ret));
+
+ return ret;
+ }
+
for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
- /* retrain on the MST master transcoder */
- if (DISPLAY_VER(dev_priv) >= 12 &&
- intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
- !intel_dp_mst_is_master_trans(crtc_state))
- continue;
-
intel_dp_check_frl_training(intel_dp);
intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp, crtc_state);
--
2.43.3
[PATCH v2 10/21] drm/i915/dp: Send a link training modeset-retry uevent to all MST connectors
Send a modeset-retry uevent to all connectors in the same MST topology
after a link training failure and reduction of the link parameters. This
matches the way the same uevent is sent after a DP tunnel BW allocation
failure.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 1 -
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 9 +
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 1f0b7cceea2dc..87f9f12814b93 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2791,7 +2791,7 @@ intel_dp_audio_compute_config(struct intel_encoder
*encoder,
intel_dp_is_uhbr(pipe_config);
}
-void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)
+static void intel_dp_queue_modeset_retry_work(struct intel_connector
*connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index e7b47e7bcd98b..24777c035e2ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -44,7 +44,6 @@ bool intel_dp_limited_color_range(const struct
intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
int intel_dp_min_bpp(enum intel_output_format output_format);
void intel_dp_init_modeset_retry_work(struct intel_connector *connector);
-void intel_dp_queue_modeset_retry_work(struct intel_connector *connector);
void
intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 4f60daa97407d..97d499e4b6ef7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1187,10 +1187,11 @@ static int
intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
return 0;
}
-static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
+static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state
*state,
+struct intel_dp *intel_dp,
const struct
intel_crtc_state *crtc_state)
{
- struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on
disconnected sink.\n");
@@ -1206,7 +1207,7 @@ static void
intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
}
/* Schedule a Hotplug Uevent to userspace to start modeset */
- intel_dp_queue_modeset_retry_work(intel_connector);
+ intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
}
/* Perform the link training on all LTTPRs and the DPRX on a link. */
@@ -1517,7 +1518,7 @@ void intel_dp_start_link_train(struct intel_atomic_state
*state,
return;
}
- intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+ intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state);
}
void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
--
2.43.3
[PATCH v2 05/21] drm/i915: Factor out function to modeset commit a set of pipes
Factor out a function to modeset commit a set of pipes, which a later
patch will reuse for DP link retraining.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 31 +-
drivers/gpu/drm/i915/display/intel_display.c | 34
drivers/gpu/drm/i915/display/intel_display.h | 3 ++
3 files changed, 38 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3c3fc53376ce3..170ba01786cf8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4441,35 +4441,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port
*dig_port)
return connector;
}
-static int modeset_pipe(struct drm_crtc *crtc,
- struct drm_modeset_acquire_ctx *ctx)
-{
- struct drm_atomic_state *state;
- struct drm_crtc_state *crtc_state;
- int ret;
-
- state = drm_atomic_state_alloc(crtc->dev);
- if (!state)
- return -ENOMEM;
-
- state->acquire_ctx = ctx;
- to_intel_atomic_state(state)->internal = true;
-
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
- if (IS_ERR(crtc_state)) {
- ret = PTR_ERR(crtc_state);
- goto out;
- }
-
- crtc_state->connectors_changed = true;
-
- ret = drm_atomic_commit(state);
-out:
- drm_atomic_state_put(state);
-
- return ret;
-}
-
static int intel_hdmi_reset_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx)
{
@@ -4539,7 +4510,7 @@ static int intel_hdmi_reset_link(struct intel_encoder
*encoder,
* would be perfectly happy if were to just reconfigure
* the SCDC settings on the fly.
*/
- return modeset_pipe(&crtc->base, ctx);
+ return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx);
}
static enum intel_hotplug_state
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cce1420fb5417..4edb1ede4a1b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5569,6 +5569,40 @@ int intel_modeset_all_pipes_late(struct
intel_atomic_state *state,
return 0;
}
+int intel_modeset_commit_pipes(struct drm_i915_private *i915,
+ u8 pipe_mask,
+ struct drm_modeset_acquire_ctx *ctx)
+{
+ struct drm_atomic_state *state;
+ struct intel_crtc *crtc;
+ int ret;
+
+ state = drm_atomic_state_alloc(&i915->drm);
+ if (!state)
+ return -ENOMEM;
+
+ state->acquire_ctx = ctx;
+ to_intel_atomic_state(state)->internal = true;
+
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_crtc_state(state, crtc);
+
+ if (IS_ERR(crtc_state)) {
+ ret = PTR_ERR(crtc_state);
+ goto out;
+ }
+
+ crtc_state->uapi.connectors_changed = true;
+ }
+
+ ret = drm_atomic_commit(state);
+out:
+ drm_atomic_state_put(state);
+
+ return ret;
+}
+
/*
* This implements the workaround described in the "notes" section of the mode
* set sequence documentation. When going from no pipes or single pipe to
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 56d1c0e3e62cd..dfdc42cef8723 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -537,6 +537,9 @@ int intel_modeset_pipes_in_mask_early(struct
intel_atomic_state *state,
const char *reason, u8 pipe_mask);
int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
const char *reason);
+int intel_modeset_commit_pipes(struct drm_i915_private *i915,
+ u8 pipe_mask,
+ struct drm_modeset_acquire_ctx *ctx);
void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
struct intel_power_domain_mask
*old_domains);
void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
--
2.43.3
[PATCH v2 03/21] drm/i915/dp: Move link train fallback to intel_dp_link_training.c
Move the functions used to reduce the link parameters during link
training to intel_dp_link_training.c .
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 76 +--
drivers/gpu/drm/i915/display/intel_dp.h | 4 +-
.../drm/i915/display/intel_dp_link_training.c | 73 ++
3 files changed, 77 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ceedd3ef41946..81e620dd33bb7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -329,7 +329,7 @@ static int intel_dp_common_len_rate_limit(const struct
intel_dp *intel_dp,
intel_dp->num_common_rates, max_rate);
}
-static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
+int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
{
if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
index < 0 || index >= intel_dp->num_common_rates))
@@ -604,7 +604,7 @@ static int intersect_rates(const int *source_rates, int
source_len,
}
/* return index of rate in rates array, or -1 if not found */
-static int intel_dp_rate_index(const int *rates, int len, int rate)
+int intel_dp_rate_index(const int *rates, int len, int rate)
{
int i;
@@ -654,78 +654,6 @@ static bool intel_dp_link_params_valid(struct intel_dp
*intel_dp, int link_rate,
return true;
}
-static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
-int link_rate,
-u8 lane_count)
-{
- /* FIXME figure out what we actually want here */
- const struct drm_display_mode *fixed_mode =
- intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
- int mode_rate, max_rate;
-
- mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
- max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
- if (mode_rate > max_rate)
- return false;
-
- return true;
-}
-
-int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
- int link_rate, u8 lane_count)
-{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int index;
-
- /*
-* TODO: Enable fallback on MST links once MST link compute can handle
-* the fallback params.
-*/
- if (intel_dp->is_mst) {
- drm_err(&i915->drm, "Link Training Unsuccessful\n");
- return -1;
- }
-
- if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
- drm_dbg_kms(&i915->drm,
- "Retrying Link training for eDP with max
parameters\n");
- intel_dp->use_max_params = true;
- return 0;
- }
-
- index = intel_dp_rate_index(intel_dp->common_rates,
- intel_dp->num_common_rates,
- link_rate);
- if (index > 0) {
- if (intel_dp_is_edp(intel_dp) &&
- !intel_dp_can_link_train_fallback_for_edp(intel_dp,
-
intel_dp_common_rate(intel_dp, index - 1),
- lane_count)) {
- drm_dbg_kms(&i915->drm,
- "Retrying Link training for eDP with same
parameters\n");
- return 0;
- }
- intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index
- 1);
- intel_dp->link.max_lane_count = lane_count;
- } else if (lane_count > 1) {
- if (intel_dp_is_edp(intel_dp) &&
- !intel_dp_can_link_train_fallback_for_edp(intel_dp,
-
intel_dp_max_common_rate(intel_dp),
- lane_count >> 1))
{
- drm_dbg_kms(&i915->drm,
- "Retrying Link training for eDP with same
parameters\n");
- return 0;
- }
- intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
- intel_dp->link.max_lane_count = lane_count >> 1;
- } else {
- drm_err(&i915->drm, "Link Training Unsuccessful\n");
- return -1;
- }
-
- return 0;
-}
-
u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
{
return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index aad2223df2a35..e7b47e7bcd98b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@
[PATCH v2 00/21] drm/i915/dp_mst: Enable link training fallback
This is v2 of [1], addressing the feedback comments from Jani and Ville: - Use a more generic 'link' substruct instead of 'link_train'. (Patch 2) - Add the debugfs entries from intel_dp_link_training.c . (Patch 17-21) - Add the link state check work to intel_digital_port instead of intel_dp, to allow using it later for HDMI. (Patch 7) - Keep using the atomic state to look up MST connectors, avoiding the access to any object's current state. (Patch 9) - Add a separate debugfs entry to get the max link rate/lane count. (Patch 18) [1] https://lore.kernel.org/all/20240514191418.2863344-1-imre.d...@intel.com Cc: Jani Nikula Cc: Ville Syrjälä Imre Deak (21): drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs drm/i915/dp: Move link train params to a substruct in intel_dp drm/i915/dp: Move link train fallback to intel_dp_link_training.c drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values() drm/i915: Factor out function to modeset commit a set of pipes drm/i915/dp: Use a commit modeset for link retraining MST links drm/i915/dp: Recheck link state after modeset drm/i915/dp: Reduce link params only after retrying with unchanged params drm/i915/dp: Pass atomic state to link training function drm/i915/dp: Send a link training modeset-retry uevent to all MST connectors drm/i915/dp: Use check link state work in the hotplug handler drm/i915/dp: Use check link state work in the detect handler drm/i915/dp: Use check link state work in the HPD IRQ handler drm/i915/dp: Disable link retraining after the last fallback step drm/i915/dp_mst: Reset intel_dp->link_trained during disabling drm/i915/dp_mst: Enable link training fallback for MST drm/i915/dp: Add debugfs entries to set a target link rate/lane count drm/i915/dp: Add debugfs entries to get the max link rate/lane count drm/i915/dp: Add debugfs entry to force link training failure drm/i915/dp: Add debugfs entry to force link retrain drm/i915/dp: Add debugfs entry for link training info drivers/gpu/drm/i915/display/g4x_dp.c | 29 +- drivers/gpu/drm/i915/display/intel_ddi.c | 64 +- drivers/gpu/drm/i915/display/intel_ddi.h | 4 + drivers/gpu/drm/i915/display/intel_display.c | 34 ++ drivers/gpu/drm/i915/display/intel_display.h | 3 + .../drm/i915/display/intel_display_debugfs.c | 2 + .../drm/i915/display/intel_display_types.h| 26 +- drivers/gpu/drm/i915/display/intel_dp.c | 241 drivers/gpu/drm/i915/display/intel_dp.h | 8 +- .../drm/i915/display/intel_dp_link_training.c | 545 +- .../drm/i915/display/intel_dp_link_training.h | 8 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 30 +- 12 files changed, 805 insertions(+), 189 deletions(-) -- 2.43.3
[PATCH v2 01/21] drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs
Symbols consisting of multiple (4) TU timeslots may get split across MTPs when using 2 or 1 link lanes. Avoid this, as required by Bspec by aligning the allocated TUs to 2 when using 2 lanes and 4 when using 1 lane. Atm, we also have to align the PBNs used to allocate BW along the MST path, since DRM core keeps track of its own TU value, derived from the PBN and that TU value must match what the driver calculates. On some platforms the alignment is only required on 8b/10b links, a follow-up patch will remove the limitation for those. Bspec: 49266, 68922 Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 27 ++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c772ba19c5477..c9c5d235744ab 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -207,6 +207,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, int remote_bw_overhead; int link_bpp_x16; int remote_tu; + fixed20_12 pbn; drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -237,11 +238,29 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, * crtc_state->dp_m_n.tu), provided that the driver doesn't * enable SSC on the corresponding link. */ - crtc_state->pbn = intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, - link_bpp_x16, - remote_bw_overhead); + pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, + link_bpp_x16, + remote_bw_overhead)); + remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full); - remote_tu = DIV_ROUND_UP(dfixed_const(crtc_state->pbn), mst_state->pbn_div.full); + /* +* Aligning the TUs ensures that symbols consisting of multiple +* (4) symbol cycles don't get split between two consecutive +* MTPs, as required by Bspec. +* TODO: remove the alignment restriction for 128b/132b links +* on some platforms, where Bspec allows this. +*/ + remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count); + + /* +* Also align PBNs accordingly, since MST core will derive its +* own copy of TU from the PBN in drm_dp_atomic_find_time_slots(). +* The above comment about the difference between the PBN +* allocated for the whole path and the TUs allocated for the +* first branch device's link also applies here. +*/ + pbn.full = remote_tu * mst_state->pbn_div.full; + crtc_state->pbn = dfixed_trunc(pbn); drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu); crtc_state->dp_m_n.tu = remote_tu; -- 2.43.3
✓ Fi.CI.BAT: success for drm/i915/dpt: Make DPT object unshrinkable (rev2)
== Series Details == Series: drm/i915/dpt: Make DPT object unshrinkable (rev2) URL : https://patchwork.freedesktop.org/series/133818/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133818v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/index.html Participating hosts (41 -> 42) -- Additional (2): fi-kbl-8809g fi-bsw-n3050 Missing(1): bat-arls-3 Known issues Here are the changes found in Patchwork_133818v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][1] ([i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-8: [PASS][2] -> [FAIL][3] ([i915#10378]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_pm_rpm@module-reload: - fi-kbl-7567u: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/fi-kbl-7567u/igt@i915_pm_...@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/fi-kbl-7567u/igt@i915_pm_...@module-reload.html * igt@kms_dsc@dsc-basic: - fi-kbl-8809g: NOTRUN -> [SKIP][7] +30 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/fi-kbl-8809g/igt@kms_...@dsc-basic.html * igt@kms_psr@psr-primary-mmap-gtt: - fi-bsw-n3050: NOTRUN -> [SKIP][8] +19 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/fi-bsw-n3050/igt@kms_...@psr-primary-mmap-gtt.html Possible fixes * igt@i915_module_load@load: - bat-dg2-8: [DMESG-WARN][9] ([i915#10014]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-8/igt@i915_module_l...@load.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/bat-dg2-8/igt@i915_module_l...@load.html * igt@i915_selftest@live@gt_timelines: - bat-arls-2: [INCOMPLETE][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-arls-2/igt@i915_selftest@live@gt_timelines.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/bat-arls-2/igt@i915_selftest@live@gt_timelines.html [i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014 [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378 [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 Build changes - * Linux: CI_DRM_14785 -> Patchwork_133818v2 CI-20190529: 20190529 CI_DRM_14785: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7863: fa1dc232d5d840532521df8a6fcf1fe82c514304 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_133818v2: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v2/index.html
✗ Fi.CI.SPARSE: warning for drm/i915/dpt: Make DPT object unshrinkable (rev2)
== Series Details == Series: drm/i915/dpt: Make DPT object unshrinkable (rev2) URL : https://patchwork.freedesktop.org/series/133818/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [PATCH 2/5] drm/i915: Implement basic functions for ultrajoiner support
On Mon, May 20, 2024 at 10:38:36AM +0300, Stanislav Lisovskiy wrote:
> Lets implement or change basic functions required for ultrajoiner
> support from atomic commit/modesetting point of view.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 66 +---
> 1 file changed, 56 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c74721188e59..c390b79a43d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -242,33 +242,65 @@ is_trans_port_sync_mode(const struct intel_crtc_state
> *crtc_state)
> is_trans_port_sync_slave(crtc_state);
> }
>
> -static enum pipe joiner_master_pipe(const struct intel_crtc_state
> *crtc_state)
> +static u8 joiner_master_pipes(const struct intel_crtc_state *crtc_state)
> {
> - return ffs(crtc_state->joiner_pipes) - 1;
> + return BIT(PIPE_A) | BIT(PIPE_C);
Not a fan of the hardcoded pipes.
We could just do something like
joiner_pipes & ((BIT(2) | BIT(0)) << joiner_master_pipe())
or some variant of that.
> +}
> +
> +static u8 joiner_primary_master_pipes(const struct intel_crtc_state
> *crtc_state)
> +{
> + return BIT(PIPE_A);
This is just the joiner_master_pipe() we already have.
> }
>
> u8 intel_crtc_joiner_slave_pipes(const struct intel_crtc_state *crtc_state)
> {
> - if (crtc_state->joiner_pipes)
> - return crtc_state->joiner_pipes &
> ~BIT(joiner_master_pipe(crtc_state));
> + if (intel_is_ultrajoiner(crtc_state))
> + return crtc_state->joiner_pipes &
> ~joiner_primary_master_pipes(crtc_state);
> + else if (intel_is_bigjoiner(crtc_state))
> + return crtc_state->joiner_pipes &
> ~joiner_master_pipes(crtc_state);
> else
> return 0;
I don't see why this should make any distinction between bigjoiner
and ultrajoiner.
Either it returns everything that isn't the overall master, or it
returns just all the bigjoiner slave pipes. Which one we want
depends on the use case I guess. So we might need both variants.
> }
>
> -bool intel_crtc_is_joiner_slave(const struct intel_crtc_state *crtc_state)
> +bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> return crtc_state->joiner_pipes &&
> - crtc->pipe != joiner_master_pipe(crtc_state);
> + !(BIT(crtc->pipe) & joiner_master_pipes(crtc_state));
I'd probably add a joiner_slave_pipes() so that the logic is less
convoluted.
But I think first we need a solid agreement on the terminology,
and stick to it consistently.
Perhaps we need names for?
- the single master within the overall set of joined pipes
(be it ultrajoiner master or the bigjoiner/uncompressed
joiner master when ultrajoiner isn't used).
Just call this joiner_master perhaps? Or perhaps just call it
ultrajoiner_master but document that it is valid to use it
also for the non-ultrajoiner cases.
- every other pipe in the set, ie. the inverse of above
Should be just {ultra,}joiner_slaves to match the
above I guess? Do we actually even need this? Not sure.
And the for the modeset sequencing we would perhaps need:
- all bigjoiner masters within the entire set of joined pipes
- all bigjoiner slaves within the entire set of joined pipes
(inverse of the above)
The one slight snag here is that the "bigjoiner" name is
a bit incorrect for uncompressed joiner, but unless we want to
come up with some other name for these then I guess we'll just
have to live with it.
The other option is we try to come up with some generic names
for the two levels of pipe roles.
--
Ville Syrjälä
Intel
✓ Fi.CI.BAT: success for drm/i915: Plane register cleanups (rev3)
== Series Details ==
Series: drm/i915: Plane register cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/133701/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133701v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/index.html
Participating hosts (41 -> 41)
--
Additional (1): fi-bsw-n3050
Missing(1): bat-arls-1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_133701v3:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1:
- {bat-twl-1}:[PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-twl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-edp-1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-twl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-edp-1.html
Known issues
Here are the changes found in Patchwork_133701v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9: [PASS][3] -> [FAIL][4] ([i915#10378])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][5] +19 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1:
- bat-mtlp-8: [PASS][6] -> [DMESG-WARN][7] ([i915#9157]) +1 other
test dmesg-warn
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-edp-1.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-edp-1.html
Possible fixes
* igt@i915_module_load@load:
- bat-dg2-8: [DMESG-WARN][8] ([i915#10014]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-8/igt@i915_module_l...@load.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-dg2-8/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_timelines:
- bat-arls-2: [INCOMPLETE][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-arls-2/igt@i915_selftest@live@gt_timelines.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-arls-2/igt@i915_selftest@live@gt_timelines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157
Build changes
-
* Linux: CI_DRM_14785 -> Patchwork_133701v3
CI-20190529: 20190529
CI_DRM_14785: 1ba62f8cea9c797427d45108df1d453f4b343240 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7863: fa1dc232d5d840532521df8a6fcf1fe82c514304 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133701v3: 1ba62f8cea9c797427d45108df1d453f4b343240 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/index.html
[PATCH 3/3] drm/xe: Cleanup xe_mmio.h
We don't need include since commit 5c09bd6ccd41
("drm/xe/mmio: Move xe_mmio_wait32() to xe_mmio.c").
We don't need include since commit
54c659660d63 ("drm/xe: Make xe_mmio_read|write() functions non-
inline").
And since commit 924e6a9789a0 ("drm/xe/uapi: Remove MMIO ioctl")
we don't need forward declarations of drm_device and drm_file.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/xe/xe_mmio.c | 7 +--
drivers/gpu/drm/xe/xe_mmio.h | 9 +
2 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 05edab0e085d..548dc37e5893 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -3,10 +3,12 @@
* Copyright © 2021-2023 Intel Corporation
*/
-#include
-
#include "xe_mmio.h"
+#include
+#include
+#include
+
#include
#include
@@ -19,6 +21,7 @@
#include "xe_ggtt.h"
#include "xe_gt.h"
#include "xe_gt_mcr.h"
+#include "xe_gt_printk.h"
#include "xe_macros.h"
#include "xe_module.h"
#include "xe_sriov.h"
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 445ec6a0753e..9ef7deecf38f 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -6,17 +6,10 @@
#ifndef _XE_MMIO_H_
#define _XE_MMIO_H_
-#include
-#include
-
-#include "regs/xe_reg_defs.h"
-#include "xe_device_types.h"
-#include "xe_gt_printk.h"
#include "xe_gt_types.h"
-struct drm_device;
-struct drm_file;
struct xe_device;
+struct xe_reg;
#define LMEM_BAR 2
--
2.43.0
[PATCH 2/3] drm/xe: Don't rely on indirect includes from xe_mmio.h
These compilation units use udelay() or some GT oriented printk functions without explicitly including proper header files, and relying on #includes from the xe_mmio.h instead. Fix that. Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/xe/xe_device.c | 2 ++ drivers/gpu/drm/xe/xe_gsc.c| 2 ++ drivers/gpu/drm/xe/xe_gt_ccs_mode.c| 1 + drivers/gpu/drm/xe/xe_guc_ads.c| 1 + drivers/gpu/drm/xe/xe_huc.c| 2 ++ drivers/gpu/drm/xe/xe_mocs.c | 1 + drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 1 + drivers/gpu/drm/xe/xe_uc_fw.c | 1 + 8 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 8da90934c900..28a4e0c3b1fe 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -5,6 +5,7 @@ #include "xe_device.h" +#include #include #include @@ -33,6 +34,7 @@ #include "xe_gsc_proxy.h" #include "xe_gt.h" #include "xe_gt_mcr.h" +#include "xe_gt_printk.h" #include "xe_hwmon.h" #include "xe_irq.h" #include "xe_memirq.h" diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c index 8cc6420a9e7f..80a61934decc 100644 --- a/drivers/gpu/drm/xe/xe_gsc.c +++ b/drivers/gpu/drm/xe/xe_gsc.c @@ -5,6 +5,8 @@ #include "xe_gsc.h" +#include + #include #include diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c index a34c9a24dafc..f90cf679c5d7 100644 --- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c +++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c @@ -9,6 +9,7 @@ #include "xe_assert.h" #include "xe_gt.h" #include "xe_gt_ccs_mode.h" +#include "xe_gt_printk.h" #include "xe_gt_sysfs.h" #include "xe_mmio.h" diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index 9c33cca4e370..1c60b685dbc6 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -16,6 +16,7 @@ #include "xe_bo.h" #include "xe_gt.h" #include "xe_gt_ccs_mode.h" +#include "xe_gt_printk.h" #include "xe_guc.h" #include "xe_guc_ct.h" #include "xe_hw_engine.h" diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c index 39a484a57585..b039ff49341b 100644 --- a/drivers/gpu/drm/xe/xe_huc.c +++ b/drivers/gpu/drm/xe/xe_huc.c @@ -5,6 +5,8 @@ #include "xe_huc.h" +#include + #include #include "abi/gsc_pxp_commands_abi.h" diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c index f04754ad911b..de3f2d3f1b04 100644 --- a/drivers/gpu/drm/xe/xe_mocs.c +++ b/drivers/gpu/drm/xe/xe_mocs.c @@ -12,6 +12,7 @@ #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_mcr.h" +#include "xe_gt_printk.h" #include "xe_mmio.h" #include "xe_platform_types.h" #include "xe_pm.h" diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c index f77367329760..64592a8e527b 100644 --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c @@ -18,6 +18,7 @@ #include "xe_bo.h" #include "xe_device.h" #include "xe_gt.h" +#include "xe_gt_printk.h" #include "xe_mmio.h" #include "xe_res_cursor.h" #include "xe_sriov.h" diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c index ed819f1df888..12346645a8e5 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.c +++ b/drivers/gpu/drm/xe/xe_uc_fw.c @@ -14,6 +14,7 @@ #include "xe_force_wake.h" #include "xe_gsc.h" #include "xe_gt.h" +#include "xe_gt_printk.h" #include "xe_map.h" #include "xe_mmio.h" #include "xe_module.h" -- 2.43.0
[PATCH 0/3] drm/xe: Cleanup xe_mmio.h
Unfortunately, this is cross i915/Xe series. Cc: Jani Nikula Cc: Lucas De Marchi Michal Wajdeczko (3): drm/i915/display: Add missing include to intel_vga.c drm/xe: Don't rely on indirect includes from xe_mmio.h drm/xe: Cleanup xe_mmio.h drivers/gpu/drm/i915/display/intel_vga.c | 1 + drivers/gpu/drm/xe/xe_device.c | 2 ++ drivers/gpu/drm/xe/xe_gsc.c | 2 ++ drivers/gpu/drm/xe/xe_gt_ccs_mode.c | 1 + drivers/gpu/drm/xe/xe_guc_ads.c | 1 + drivers/gpu/drm/xe/xe_huc.c | 2 ++ drivers/gpu/drm/xe/xe_mmio.c | 7 +-- drivers/gpu/drm/xe/xe_mmio.h | 9 + drivers/gpu/drm/xe/xe_mocs.c | 1 + drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 1 + drivers/gpu/drm/xe/xe_uc_fw.c| 1 + 11 files changed, 18 insertions(+), 10 deletions(-) -- 2.43.0
[PATCH 1/3] drm/i915/display: Add missing include to intel_vga.c
This compilation unit uses udelay() function without including it's header file. Fix that to break dependency on other code. Signed-off-by: Michal Wajdeczko Cc: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vga.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 4b98833bfa8c..0b5916c15307 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -3,6 +3,7 @@ * Copyright © 2019 Intel Corporation */ +#include #include #include -- 2.43.0
✗ Fi.CI.SPARSE: warning for drm/i915: Plane register cleanups (rev3)
== Series Details == Series: drm/i915: Plane register cleanups (rev3) URL : https://patchwork.freedesktop.org/series/133701/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev3)
== Series Details == Series: drm/i915: Plane register cleanups (rev3) URL : https://patchwork.freedesktop.org/series/133701/ State : warning == Summary == Error: dim checkpatch failed 9638afbf50ae drm/i915: Add skl+ plane name aliases to enum plane_id 4d3ce0118a4b drm/i915: Clean up the cursor register defines 49ffeb900e72 drm/i915: Add separate define for SEL_FETCH_CUR_CTL() e5eefbbe6b08 drm/i915: Simplify PIPESRC_ERLY_TPT definition -:55: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #55: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:256: +#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) total: 0 errors, 1 warnings, 0 checks, 26 lines checked 49bf1f81d37a drm/i915: Rename selective fetch plane registers 26034ecefc36 drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES() -:90: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20: +#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20: +#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ + _PICK_EVEN_2RANGES((plane), PLANE_5, \ + _PIPE((pipe), (reg_1_a), (reg_1_b)), \ + _PIPE((pipe), (reg_2_a), (reg_2_b)), \ + _PIPE((pipe), (reg_5_a), (reg_5_b)), \ + _PIPE((pipe), (reg_6_a), (reg_6_b))) -:96: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #96: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:26: +#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ -:117: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #117: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:390: + _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \ -:118: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #118: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:391: + _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \ -:119: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #119: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:392: + _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \ -:120: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #120: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:393: + _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B) -:132: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #132: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:405: + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ -:133: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #133: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:406: + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ -:134: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #134: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:407: + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ -:135: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #135: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:408: + _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B) -:146: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #146: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:419: + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ -:147: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #147: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:420: + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ -:148: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #148: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:421: + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ -:149: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #149: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:422: + _SEL_FETCH_PLANE_POS
✓ Fi.CI.IGT: success for Link off between frames for edp (rev5)
== Series Details == Series: Link off between frames for edp (rev5) URL : https://patchwork.freedesktop.org/series/130650/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785_full -> Patchwork_130650v5_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts New tests - New tests have been introduced between CI_DRM_14785_full and Patchwork_130650v5_full: ### New IGT tests (3) ### * igt@perf@blocking@1-vcs1: - Statuses : 1 pass(s) - Exec time: [10.02] s * igt@perf@enable-disable@1-vcs0: - Statuses : 1 pass(s) - Exec time: [4.23] s * igt@perf@oa-exponents@1-vcs0: - Statuses : 1 pass(s) - Exec time: [1.85] s Known issues Here are the changes found in Patchwork_130650v5_full that come from known issues: ### IGT changes ### Issues hit * igt@device_reset@cold-reset-bound: - shard-rkl: NOTRUN -> [SKIP][1] ([i915#11078]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-rkl-4/igt@device_re...@cold-reset-bound.html * igt@device_reset@unbind-cold-reset-rebind: - shard-dg1: NOTRUN -> [SKIP][2] ([i915#11078]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg1-16/igt@device_re...@unbind-cold-reset-rebind.html * igt@device_reset@unbind-reset-rebind: - shard-dg1: NOTRUN -> [INCOMPLETE][3] ([i915#9408]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg1-18/igt@device_re...@unbind-reset-rebind.html * igt@drm_fdinfo@virtual-busy-all: - shard-dg1: NOTRUN -> [SKIP][4] ([i915#8414]) +2 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg1-16/igt@drm_fdi...@virtual-busy-all.html * igt@drm_fdinfo@virtual-idle: - shard-rkl: NOTRUN -> [FAIL][5] ([i915#7742]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-rkl-4/igt@drm_fdi...@virtual-idle.html * igt@gem_ccs@block-multicopy-compressed: - shard-rkl: NOTRUN -> [SKIP][6] ([i915#9323]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-rkl-5/igt@gem_...@block-multicopy-compressed.html * igt@gem_create@create-ext-cpu-access-big: - shard-rkl: NOTRUN -> [SKIP][7] ([i915#6335]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-rkl-4/igt@gem_cre...@create-ext-cpu-access-big.html * igt@gem_ctx_freq@sysfs@gt0: - shard-dg2: [PASS][8] -> [FAIL][9] ([i915#9561]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-1/igt@gem_ctx_freq@sy...@gt0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg2-11/igt@gem_ctx_freq@sy...@gt0.html * igt@gem_ctx_persistence@heartbeat-hostile: - shard-dg1: NOTRUN -> [SKIP][10] ([i915#8555]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg1-15/igt@gem_ctx_persiste...@heartbeat-hostile.html * igt@gem_ctx_sseu@invalid-args: - shard-dg1: NOTRUN -> [SKIP][11] ([i915#280]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg1-16/igt@gem_ctx_s...@invalid-args.html * igt@gem_eio@kms: - shard-tglu: [PASS][12] -> [INCOMPLETE][13] ([i915#10513]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-tglu-6/igt@gem_...@kms.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-tglu-5/igt@gem_...@kms.html - shard-dg1: NOTRUN -> [INCOMPLETE][14] ([i915#10513]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg1-15/igt@gem_...@kms.html * igt@gem_exec_balancer@bonded-sync: - shard-dg1: NOTRUN -> [SKIP][15] ([i915#4771]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg1-18/igt@gem_exec_balan...@bonded-sync.html * igt@gem_exec_balancer@parallel-contexts: - shard-rkl: NOTRUN -> [SKIP][16] ([i915#4525]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-rkl-5/igt@gem_exec_balan...@parallel-contexts.html * igt@gem_exec_capture@capture-recoverable: - shard-rkl: NOTRUN -> [SKIP][17] ([i915#6344]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-rkl-5/igt@gem_exec_capt...@capture-recoverable.html * igt@gem_exec_capture@capture@vecs0-lmem0: - shard-dg1: NOTRUN -> [FAIL][18] ([i915#10386]) +1 other test fail [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg1-16/igt@gem_exec_capture@capt...@vecs0-lmem0.html * igt@gem_exec_capture@many-4k-incremental: - shard-dg1: NOTRUN -> [FAIL][19] ([i915#9606]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/shard-dg1-13/igt@gem_exec_cap
✗ Fi.CI.BAT: failure for drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+ (rev2)
== Series Details == Series: drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+ (rev2) URL : https://patchwork.freedesktop.org/series/133716/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133716v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_133716v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_133716v2, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/index.html Participating hosts (41 -> 41) -- Additional (2): fi-kbl-8809g fi-bsw-n3050 Missing(2): bat-kbl-2 bat-mtlp-6 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_133716v2: ### IGT changes ### Possible regressions * igt@i915_selftest@live@active: - fi-rkl-11600: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/fi-rkl-11600/igt@i915_selftest@l...@active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/fi-rkl-11600/igt@i915_selftest@l...@active.html Known issues Here are the changes found in Patchwork_133716v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-11: [PASS][5] -> [FAIL][6] ([i915#10378]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@random-engines: - fi-bsw-n3050: NOTRUN -> [SKIP][7] +19 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html * igt@i915_selftest@live@hangcheck: - bat-dg2-9: [PASS][8] -> [ABORT][9] ([i915#9840]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html * igt@kms_force_connector_basic@force-load-detect: - fi-kbl-8809g: NOTRUN -> [SKIP][10] +30 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html Possible fixes * igt@i915_module_load@load: - bat-dg2-8: [DMESG-WARN][11] ([i915#10014]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-8/igt@i915_module_l...@load.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/bat-dg2-8/igt@i915_module_l...@load.html * igt@i915_selftest@live@gt_timelines: - bat-arls-2: [INCOMPLETE][13] -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-arls-2/igt@i915_selftest@live@gt_timelines.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/bat-arls-2/igt@i915_selftest@live@gt_timelines.html [i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014 [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378 [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 [i915#9840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9840 Build changes - * Linux: CI_DRM_14785 -> Patchwork_133716v2 CI-20190529: 20190529 CI_DRM_14785: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7863: fa1dc232d5d840532521df8a6fcf1fe82c514304 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_133716v2: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133716v2/index.html
[PATCH] drm/i915/dpt: Make DPT object unshrinkable
In some scenarios, the DPT object gets shrunk but
the actual framebuffer did not and thus its still
there on the DPT's vm->bound_list. Then it tries to
rewrite the PTEs via a stale CPU mapping. This causes panic.
Credits-to: Ville Syrjala
Shawn Lee
Cc: sta...@vger.kernel.org
Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation for dpt")
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3560a062d287..e6b485fc54d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -284,7 +284,8 @@ bool i915_gem_object_has_iomem(const struct
drm_i915_gem_object *obj);
static inline bool
i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
{
- return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE);
+ return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) &&
+ !obj->is_dpt;
}
static inline bool
--
2.34.1
[PATCH v2 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
From: Ville Syrjälä
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
v2: Pass the correct register offset fpr pipe B (Jani)
s/mtl+/tgl+/ as that's where this was introduced
Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents
actually match the normal CUR_CTL register
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++---
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index c780ce146131..b44809899502 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct
intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
}
static void wa_16021440873(struct intel_plane *plane,
@@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
ctl &= ~MCURSOR_MODE_MASK;
ctl |= MCURSOR_MODE_64_2B;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
PIPESRC_HEIGHT(et_y_position));
@@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct
intel_plane *plane,
val);
}
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe,
plane->id),
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
plane_state->ctl);
} else {
/* Wa_16021440873 */
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 270c26c2e6df..e58930ff32ea 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -95,4 +95,9 @@
#define _CUR_BUF_CFG_B 0x7117c
#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A,
_CUR_BUF_CFG_B)
+/* tgl+ */
+#define _SEL_FETCH_CUR_CTL_A 0x70880
+#define _SEL_FETCH_CUR_CTL_B 0x71880
+#define SEL_FETCH_CUR_CTL(pipe)_MMIO_PIPE((pipe),
_SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_B)
+
#endif /* __INTEL_CURSOR_REGS_H__ */
--
2.44.1
RE: [PATCH] drm/i915/dpt: Make DPT object unshrinkable
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, May 20, 2024 10:10 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville
> ; Lee,
> Shawn C ; srini...@freedesktop.org
> Subject: Re: [PATCH] drm/i915/dpt: Make DPT object unshrinkable
>
> On Mon, May 20, 2024 at 08:54:10PM +0530, Srinivas, Vidya wrote:
> > In some scenarios, the DPT object gets shrunk but the actual
> > framebuffer did not and thus its still there on the DPT's
> > vm->bound_list. Then it tries to rewrite the PTEs via a stale CPU
> > mapping. This causes panic.
> >
> > Credits-to: Ville Syrjala
> > Shawn Lee
> >
> > Signed-off-by: Srinivas, Vidya
>
> The format should be "first_name last_name "
Apologies for the mistake. My gitconfig got messed up.
>
> We also probably want
> Cc: sta...@vger.kernel.org
> Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation for
> dpt")
>
Thank you so much. Will float new patch with this added.
> Although the patch won't actually build unless we also have commit
> 779cb5ba64ec ("drm/i915/dpt: Treat the DPT BO as a framebuffer") but that
> hast the same fixes tag, so should be fine even if someone backports things
> that far back.
>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > index 3560a062d287..e6b485fc54d4 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > @@ -284,7 +284,8 @@ bool i915_gem_object_has_iomem(const struct
> > drm_i915_gem_object *obj); static inline bool
> > i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
> > {
>
> Maybe toss something like this here:
> /* TODO: make DPT shrinkable when it has no bound vmas */
>
> DPTs aren't necessarily so small that shrinking them wouldn't have any
> benefits. But actually implementing that would require some actual work, so
> not suitable for a quick fix.
>
> I can add all that stuff when applying the patch, no need to resend for this.
>
> > - return i915_gem_object_type_has(obj,
> I915_GEM_OBJECT_IS_SHRINKABLE);
> > + return i915_gem_object_type_has(obj,
> I915_GEM_OBJECT_IS_SHRINKABLE) &&
> > + !obj->is_dpt;
> > }
> >
> > static inline bool
> > --
> > 2.34.1
>
> --
> Ville Syrjälä
> Intel
Re: [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
On Mon, May 20, 2024 at 12:27:20PM +0300, Jani Nikula wrote:
> On Thu, 16 May 2024, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Split the cursor stuff from the rest of the selective fetch
> > plane registers so that we can collect all cursor registers
> > in intel_cursor_regs.h. Also take the opportunity to rename
> > the registers to match the spec.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++---
> > drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +
> > 2 files changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> > b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index c780ce146131..b44809899502 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct
> > intel_plane *plane,
> > if (!crtc_state->enable_psr2_sel_fetch)
> > return;
> >
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
> > + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
> > }
> >
> > static void wa_16021440873(struct intel_plane *plane,
> > @@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
> > ctl &= ~MCURSOR_MODE_MASK;
> > ctl |= MCURSOR_MODE_64_2B;
> >
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
> > + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
> >
> > intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
> >PIPESRC_HEIGHT(et_y_position));
> > @@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct
> > intel_plane *plane,
> > val);
> > }
> >
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe,
> > plane->id),
> > + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
> > plane_state->ctl);
> > } else {
> > /* Wa_16021440873 */
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > index 270c26c2e6df..ab02d497fba6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > @@ -95,4 +95,9 @@
> > #define _CUR_BUF_CFG_B 0x7117c
> > #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A,
> > _CUR_BUF_CFG_B)
> >
> > +#define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
> > +#define _SEL_FETCH_CUR_CTL_B 0x71880
> > +#define SEL_FETCH_CUR_CTL(pipe)_MMIO_PIPE((pipe),
> > _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_A)
>
> _SEL_FETCH_CUR_CTL_A is doubled, the latter should be _B.
Derp. I also don't know where I got that mtl+ note. I must have been
thinking about early transport or something, but selective fetch
in general should be a thing for tgl+.
>
> With that,
>
> Reviewed-by: Jani Nikula
>
> I must admit I was trying to follow how PLANE_SEL_FETCH_CTL(pipe,
> CURSOR_A) ends up being identical to this new SEL_FETCH_CUR_CTL(pipe),
> but holy crap it trips my brain completely. How did we come up with so
> many levels of abstractions for this stuff, in such complicated ways?!
> :o
>
>
> > +#define SEL_FETCH_CUR_CTL_ENABLE REG_BIT(31)
> > +
> > #endif /* __INTEL_CURSOR_REGS_H__ */
>
> --
> Jani Nikula, Intel
--
Ville Syrjälä
Intel
[PATCH v2] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL-S/ADL-P/DG2+
From: Ville Syrjälä Bspec lists the mas TMDS bitrate as 6 Gbps on ADL-S/ADL-P/DG2. Bump our limit to match. v2: Bump for ADL-S as well (Jani) Cc: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 0faf2afa1c09..9ac670a40bc1 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1784,7 +1784,9 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int max_tmds_clock, vbt_max_tmds_clock; - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_S(dev_priv)) + max_tmds_clock = 60; + else if (DISPLAY_VER(dev_priv) >= 10) max_tmds_clock = 594000; else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) max_tmds_clock = 30; -- 2.44.1
Re: [PATCH] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+
On Mon, May 20, 2024 at 01:37:26PM +0300, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Bspec lists the mas TMDS bitrate as 6 Gbps on ADL/DG2. > > *max > > There's also ADL-S with display 12 and 6 Gbps support? Looks like it. Too many weird platform variants... > > BR, > Jani. > > > Bump our limit to match. > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c > > b/drivers/gpu/drm/i915/display/intel_hdmi.c > > index 0faf2afa1c09..bd0ba4edcd1d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > > @@ -1784,7 +1784,9 @@ static int intel_hdmi_source_max_tmds_clock(struct > > intel_encoder *encoder) > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > int max_tmds_clock, vbt_max_tmds_clock; > > > > - if (DISPLAY_VER(dev_priv) >= 10) > > + if (DISPLAY_VER(dev_priv) >= 13) > > + max_tmds_clock = 60; > > + else if (DISPLAY_VER(dev_priv) >= 10) > > max_tmds_clock = 594000; > > else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) > > max_tmds_clock = 30; > > -- > Jani Nikula, Intel -- Ville Syrjälä Intel
Re: [PATCH] drm/i915/dpt: Make DPT object unshrinkable
On Mon, May 20, 2024 at 08:54:10PM +0530, Srinivas, Vidya wrote:
> In some scenarios, the DPT object gets shrunk but
> the actual framebuffer did not and thus its still
> there on the DPT's vm->bound_list. Then it tries to
> rewrite the PTEs via a stale CPU mapping. This causes panic.
>
> Credits-to: Ville Syrjala
> Shawn Lee
>
> Signed-off-by: Srinivas, Vidya
The format should be "first_name last_name "
We also probably want
Cc: sta...@vger.kernel.org
Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation for dpt")
Although the patch won't actually build unless we also have
commit 779cb5ba64ec ("drm/i915/dpt: Treat the DPT BO as a framebuffer")
but that hast the same fixes tag, so should be fine even if
someone backports things that far back.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index 3560a062d287..e6b485fc54d4 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> @@ -284,7 +284,8 @@ bool i915_gem_object_has_iomem(const struct
> drm_i915_gem_object *obj);
> static inline bool
> i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
> {
Maybe toss something like this here:
/* TODO: make DPT shrinkable when it has no bound vmas */
DPTs aren't necessarily so small that shrinking them wouldn't
have any benefits. But actually implementing that would require
some actual work, so not suitable for a quick fix.
I can add all that stuff when applying the patch, no need to
resend for this.
> - return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE);
> + return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) &&
> + !obj->is_dpt;
> }
>
> static inline bool
> --
> 2.34.1
--
Ville Syrjälä
Intel
Re: [PATCH 02/13] drm/i915: Clean up the cursor register defines
On Mon, 20 May 2024, Ville Syrjälä wrote: > On Mon, May 20, 2024 at 12:10:30PM +0300, Jani Nikula wrote: >> On Thu, 16 May 2024, Ville Syrjala wrote: >> I also think it's kind of unnecessary when they're only >> passed on as parameters. Or is there some corner case where it matters? > > I think cargo-culting is probably the best argument for protecting > each and every macro argument. If used universally then I think > it'll be a bit more likely that newly added macros, where it > might matter more, will inherit it as well. That's a good point. BR, Jani. -- Jani Nikula, Intel
✓ Fi.CI.BAT: success for drm/i915/dpt: Make DPT object unshrinkable
== Series Details == Series: drm/i915/dpt: Make DPT object unshrinkable URL : https://patchwork.freedesktop.org/series/133818/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133818v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v1/index.html Participating hosts (41 -> 38) -- Missing(3): fi-kbl-7567u bat-jsl-1 bat-arls-2 Known issues Here are the changes found in Patchwork_133818v1 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_module_load@load: - bat-dg2-8: [DMESG-WARN][1] ([i915#10014]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-8/igt@i915_module_l...@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v1/bat-dg2-8/igt@i915_module_l...@load.html [i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014 Build changes - * Linux: CI_DRM_14785 -> Patchwork_133818v1 CI-20190529: 20190529 CI_DRM_14785: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7863: fa1dc232d5d840532521df8a6fcf1fe82c514304 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_133818v1: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133818v1/index.html
[linux-next:master] BUILD REGRESSION 632483ea8004edfadd035de36e1ab2c7c4f53158
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 632483ea8004edfadd035de36e1ab2c7c4f53158 Add linux-next specific files for 20240520 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202405202243.shvs2otq-...@intel.com https://lore.kernel.org/oe-kbuild-all/202405210004.5m02x213-...@intel.com Error/Warning: (recently discovered and may have been fixed) drivers/thermal/thermal_trip.o: warning: objtool: unexpected relocation symbol type in .rela.discard.reachable Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arc-allmodconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arc-allyesconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arc-randconfig-002-20240520 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm-randconfig-003-20240520 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-randconfig-001-20240520 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-allmodconfig | |-- ERROR:__udivdi3-drivers-vdpa-octeon_ep-octep_vdpa.ko-undefined | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-allyesconfig | |-- ERROR:__udivdi3-drivers-vdpa-octeon_ep-octep_vdpa.ko-undefined | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-012-20240520 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-014-20240520 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-016-20240520 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- loongarch-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- loongarch-defconfig | `-- drivers-thermal-thermal_trip.o:warning:objtool:unexpected-relocation-symbol-type-in-.rela.discard.reachable |-- loongarch-randconfig-002-20240520 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- m68k-allmodconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- m68k-allyesconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not
Re: [PATCH 02/13] drm/i915: Clean up the cursor register defines
On Mon, May 20, 2024 at 12:10:30PM +0300, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Group the cursor register defines such that everything to > > do with one register is in one place. > > > > Signed-off-by: Ville Syrjälä > > Reviewed-by: Jani Nikula > > but a couple of nitpicks inline... > > > --- > > .../gpu/drm/i915/display/intel_cursor_regs.h | 52 +-- > > 1 file changed, 26 insertions(+), 26 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h > > b/drivers/gpu/drm/i915/display/intel_cursor_regs.h > > index c2190af1e9f5..270c26c2e6df 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h > > +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h > > @@ -9,6 +9,7 @@ > > #include "intel_display_reg_defs.h" > > > > #define _CURACNTR 0x70080 > > +#define CURCNTR(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), > > _CURACNTR) > > In addition to code movement, these add braces around (dev_priv) and > (pipe). While it makes review harder by breaking 'git show > --color-moved', Sorry. Forgot I snuck it in there. > I also think it's kind of unnecessary when they're only > passed on as parameters. Or is there some corner case where it matters? I think cargo-culting is probably the best argument for protecting each and every macro argument. If used universally then I think it'll be a bit more likely that newly added macros, where it might matter more, will inherit it as well. And we've certainly had incidents with misplaced commas (the i915_reg_t addition was a reaction to one such event), so I wouldn't dare claim that there is zero chance of screwups with these. > Comma has the lowest precedence, and I don't think you could easily pass > in a value with a comma operator. > > No need to change for this, it's not wrong either. > > > /* Old style CUR*CNTR flags (desktop 8xx) */ > > #define CURSOR_ENABLEREG_BIT(31) > > #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) > > @@ -38,61 +39,60 @@ > > #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) > > #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) > > #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) > > + > > #define _CURABASE 0x70084 > > +#define CURBASE(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), > > _CURABASE) > > + > > #define _CURAPOS 0x70088 > > -#define _CURAPOS_ERLY_TPT 0x7008c > > +#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), > > _CURAPOS) > > #define CURSOR_POS_Y_SIGNREG_BIT(31) > > #define CURSOR_POS_Y_MASKREG_GENMASK(30, 16) > > #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) > > #define CURSOR_POS_X_SIGNREG_BIT(15) > > #define CURSOR_POS_X_MASKREG_GENMASK(14, 0) > > #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) > > + > > +#define _CURAPOS_ERLY_TPT 0x7008c > > +#define CURPOS_ERLY_TPT(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), > > (pipe), _CURAPOS_ERLY_TPT) > > + > > #define _CURASIZE 0x700a0 /* 845/865 */ > > +#define CURSIZE(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), (pipe), > > _CURASIZE) > > #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) > > #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) > > #define CURSOR_WIDTH_MASKREG_GENMASK(9, 0) > > #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) > > + > > #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ > > +#define CUR_FBC_CTL(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), > > (pipe), _CUR_FBC_CTL_A) > > #define CUR_FBC_EN REG_BIT(31) > > #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) > > #define CUR_FBC_HEIGHT(h) > > REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) > > + > > #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ > > +#define CUR_CHICKEN(dev_priv, pipe)_MMIO_CURSOR2((dev_priv), > > (pipe), _CUR_CHICKEN_A) > > + > > #define _CURASURFLIVE 0x700ac /* g4x+ */ > > -#define _CURBCNTR 0x700c0 > > -#define _CURBBASE 0x700c4 > > -#define _CURBPOS 0x700c8 > > - > > -#define _CURBCNTR_IVB 0x71080 > > -#define _CURBBASE_IVB 0x71084 > > -#define _CURBPOS_IVB 0x71088 > > - > > -#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) > > -#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) > > -#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) > > -#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, > > _CURAPOS_ERLY_TPT) > > -#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) > > -#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, >
✗ Fi.CI.SPARSE: warning for drm/i915/dpt: Make DPT object unshrinkable
== Series Details == Series: drm/i915/dpt: Make DPT object unshrinkable URL : https://patchwork.freedesktop.org/series/133818/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [PATCH 2/7] drm/i915: Extract intel_dp_has_dsc()
On Mon, May 20, 2024 at 01:47:34PM +0300, Jani Nikula wrote:
> On Fri, 17 May 2024, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Extract a helper to check whether the source+sink combo
> > supports DSC. That basic check is needed both during mode
> > validation and compute config. We'll also need to add extra
> > checks to both places, so having a single place for it is nicer.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
> > 1 file changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 1e88449fe5f2..7bf283b4df7f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1220,6 +1220,19 @@ bool intel_dp_need_bigjoiner(struct intel_dp
> > *intel_dp,
> >connector->force_bigjoiner_enable;
> > }
> >
> > +static bool intel_dp_has_dsc(struct intel_connector *connector)
>
> Why not const?
We've generally not consted these things. And then whenver add
one const somewhere it usually ends up getting in the way later,
not because we need mutability but simply because we want to
call something that doesn't have the const.
I suppose if we do want to start consting things more we should
just do some kind of bigger pass over the whole codebase so that
that there's less chance of pain later.
We're also not using container_of_const() for these right now,
so the const can vanish semi-accidentally when casting things.
I suppose this thing might be low level enough that the const
could be kept. I'll have another think about it.
>
> > +{
> > + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > +
> > + if (!HAS_DSC(i915))
> > + return false;
> > +
> > + if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
> > + return false;
> > +
> > + return true;
> > +}
> > +
> > static enum drm_mode_status
> > intel_dp_mode_valid(struct drm_connector *_connector,
> > struct drm_display_mode *mode)
> > @@ -1274,8 +1287,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> > mode_rate = intel_dp_link_required(target_clock,
> >
> > intel_dp_mode_min_output_bpp(connector, mode));
> >
> > - if (HAS_DSC(dev_priv) &&
> > - drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
> > + if (intel_dp_has_dsc(connector)) {
> > enum intel_output_format sink_format, output_format;
> > int pipe_bpp;
>
> --
> Jani Nikula, Intel
--
Ville Syrjälä
Intel
[PATCH] drm/i915/dpt: Make DPT object unshrinkable
In some scenarios, the DPT object gets shrunk but
the actual framebuffer did not and thus its still
there on the DPT's vm->bound_list. Then it tries to
rewrite the PTEs via a stale CPU mapping. This causes panic.
Credits-to: Ville Syrjala
Shawn Lee
Signed-off-by: Srinivas, Vidya
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3560a062d287..e6b485fc54d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -284,7 +284,8 @@ bool i915_gem_object_has_iomem(const struct
drm_i915_gem_object *obj);
static inline bool
i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
{
- return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE);
+ return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) &&
+ !obj->is_dpt;
}
static inline bool
--
2.34.1
Re: Is it possible to distinguish between HDMI and DVI in i915?
On Mon, 20 May 2024, Arkadiusz Drabczyk wrote: > My Asus Z97-A motherboard has DVI and HDMI connectors but i915 shows > 2x HDMI ports (and the 3rd one for DP but a separate DP1 is also > shown). Would it be possible to distinguish between DVI and HDMI in > the driver code for example by reading some undocumented VBT registers > or testing port characteristics or something? Please file a bug as described at [1], attach dmesg with drm.debug=14 and VBT as described in the link, and we'll be able to tell you more. Thanks, Jani. [1] https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html -- Jani Nikula, Intel
Is it possible to distinguish between HDMI and DVI in i915?
My Asus Z97-A motherboard has DVI and HDMI connectors but i915 shows 2x HDMI ports (and the 3rd one for DP but a separate DP1 is also shown). Would it be possible to distinguish between DVI and HDMI in the driver code for example by reading some undocumented VBT registers or testing port characteristics or something? -- Arkadiusz Drabczyk
✓ Fi.CI.BAT: success for Link off between frames for edp (rev5)
== Series Details == Series: Link off between frames for edp (rev5) URL : https://patchwork.freedesktop.org/series/130650/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_130650v5 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/index.html Participating hosts (41 -> 41) -- Additional (1): fi-kbl-8809g Missing(1): fi-glk-j4005 Known issues Here are the changes found in Patchwork_130650v5 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][1] ([i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][3] -> [ABORT][4] ([i915#10594]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@kms_force_connector_basic@force-load-detect: - fi-kbl-8809g: NOTRUN -> [SKIP][5] +30 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html Possible fixes * igt@i915_module_load@load: - bat-dg2-8: [DMESG-WARN][6] ([i915#10014]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-8/igt@i915_module_l...@load.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/bat-dg2-8/igt@i915_module_l...@load.html * igt@i915_selftest@live@gt_timelines: - bat-arls-2: [INCOMPLETE][8] -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-arls-2/igt@i915_selftest@live@gt_timelines.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/bat-arls-2/igt@i915_selftest@live@gt_timelines.html [i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014 [i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594 [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 Build changes - * Linux: CI_DRM_14785 -> Patchwork_130650v5 CI-20190529: 20190529 CI_DRM_14785: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7863: fa1dc232d5d840532521df8a6fcf1fe82c514304 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_130650v5: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130650v5/index.html
Re: [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits
On Thu, 16 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make a more thorough split between universal planes vs. cursors
> by defining the contents of the cursor WM/DDB registers separately.
>
> Signed-off-by: Ville Syrjälä
I like this better than exposing the reg val functions.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 34 +++
> .../gpu/drm/i915/display/intel_cursor_regs.h | 9 +
> .../drm/i915/display/skl_universal_plane.c| 4 +--
> .../drm/i915/display/skl_universal_plane.h| 3 --
> 4 files changed, 39 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 7983cbaf83f7..cea0cfed569d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -24,7 +24,6 @@
> #include "intel_psr.h"
> #include "intel_psr_regs.h"
> #include "intel_vblank.h"
> -#include "skl_universal_plane.h"
> #include "skl_watermark.h"
>
> #include "gem/i915_gem_object.h"
> @@ -559,6 +558,29 @@ static void i9xx_cursor_update_sel_fetch_arm(struct
> intel_plane *plane,
> }
> }
>
> +static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
> +{
> + if (!entry->end)
> + return 0;
> +
> + return CUR_BUF_END(entry->end - 1) |
> + CUR_BUF_START(entry->start);
> +}
> +
> +static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
> +{
> + u32 val = 0;
> +
> + if (level->enable)
> + val |= CUR_WM_EN;
> + if (level->ignore_lines)
> + val |= CUR_WM_IGNORE_LINES;
> + val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
> + val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
> +
> + return val;
> +}
> +
> static void skl_write_cursor_wm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -572,22 +594,22 @@ static void skl_write_cursor_wm(struct intel_plane
> *plane,
>
> for (level = 0; level < i915->display.wm.num_levels; level++)
> intel_de_write_fw(i915, CUR_WM(pipe, level),
> -
> skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
> +
> skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
>
> intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
> - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
> plane_id)));
> + skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm,
> plane_id)));
>
> if (HAS_HW_SAGV_WM(i915)) {
> const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
>
> intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
> - skl_plane_wm_reg_val(&wm->sagv.wm0));
> + skl_cursor_wm_reg_val(&wm->sagv.wm0));
> intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
> - skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> + skl_cursor_wm_reg_val(&wm->sagv.trans_wm));
> }
>
> intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
> - skl_plane_ddb_reg_val(ddb));
> + skl_cursor_ddb_reg_val(ddb));
> }
>
> /* TODO: split into noarm+arm pair */
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> index ab02d497fba6..307a850d54b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> @@ -78,6 +78,10 @@
> #define _CUR_WM_A_0 0x70140
> #define _CUR_WM_B_0 0x71140
> #define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) +
> (level) * 4)
> +#define CUR_WM_EN REG_BIT(31)
> +#define CUR_WM_IGNORE_LINESREG_BIT(30)
> +#define CUR_WM_LINES_MASK REG_GENMASK(26, 14)
> +#define CUR_WM_BLOCKS_MASK REG_GENMASK(11, 0)
>
> #define _CUR_WM_SAGV_A 0x70158
> #define _CUR_WM_SAGV_B 0x71158
> @@ -94,6 +98,11 @@
> #define _CUR_BUF_CFG_A 0x7017c
> #define _CUR_BUF_CFG_B 0x7117c
> #define CUR_BUF_CFG(pipe)_MMIO_PIPE((pipe), _CUR_BUF_CFG_A,
> _CUR_BUF_CFG_B)
> +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> +#define CUR_BUF_END_MASK REG_GENMASK(27, 16)
> +#define CUR_BUF_END(end) REG_FIELD_PREP(CUR_BUF_END_MASK, (end))
> +#define CUR_BUF_START_MASK REG_GENMASK(11, 0)
> +#define CUR_BUF_START(start)
> REG_FIELD_PREP(CUR_BUF_START_MASK, (start))
>
> #define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
> #define _SEL_FETCH_CUR_CTL_B 0x71880
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm
Re: [PATCH 13/13] drm/i915: Document which platforms use which sprite registers
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Note which sprite registers are valid for which platforms. > > Signed-off-by: Ville Syrjälä Acked-by: Jani Nikula > --- > .../gpu/drm/i915/display/intel_sprite_regs.h | 19 +++ > 1 file changed, 11 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h > b/drivers/gpu/drm/i915/display/intel_sprite_regs.h > index c27adbaf0f00..73021e3ced6d 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h > @@ -6,6 +6,7 @@ > > #include "intel_display_reg_defs.h" > > +/* g4x/ilk/snb video sprite */ > #define _DVSACNTR0x72180 > #define _DVSBCNTR0x73180 > #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) > @@ -111,6 +112,7 @@ > #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ > #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, > _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ > > +/* ivb/hsw/bdw sprite */ > #define _SPRA_CTL0x70280 > #define _SPRB_CTL0x71280 > #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) > @@ -140,8 +142,8 @@ > #define SPRITE_TILED REG_BIT(10) > #define SPRITE_DEST_KEYREG_BIT(2) > > -#define _SPRA_LINOFF 0x70284 > -#define _SPRB_LINOFF 0x71284 > +#define _SPRA_LINOFF 0x70284 /* ivb */ > +#define _SPRB_LINOFF 0x71284 /* ivb */ > #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) > > #define _SPRA_STRIDE 0x70288 > @@ -181,24 +183,24 @@ > #define _SPRB_KEYMAX 0x712a0 > #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) > > -#define _SPRA_TILEOFF0x702a4 > -#define _SPRB_TILEOFF0x712a4 > +#define _SPRA_TILEOFF0x702a4 /* ivb */ > +#define _SPRB_TILEOFF0x712a4 /* ivb */ > #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) > #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) > #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) > #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) > #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) > > -#define _SPRA_OFFSET 0x702a4 > -#define _SPRB_OFFSET 0x712a4 > +#define _SPRA_OFFSET 0x702a4 /* hsw/bdw */ > +#define _SPRB_OFFSET 0x712a4 /* hsw/bdw */ > #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) > > #define _SPRA_SURFLIVE 0x702ac > #define _SPRB_SURFLIVE 0x712ac > #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) > > -#define _SPRA_SCALE 0x70304 > -#define _SPRB_SCALE 0x71304 > +#define _SPRA_SCALE 0x70304 /* ivb */ > +#define _SPRB_SCALE 0x71304 /* ivb */ > #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) > #define SPRITE_SCALE_ENABLEREG_BIT(31) > #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) > @@ -224,6 +226,7 @@ > #define _SPRB_GAMC17 0x7144c > #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + > (i) * 4) /* 3 x u2.10 */ > > +/* vlv/chv sprite */ > #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ > _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) > #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ -- Jani Nikula, Intel
Re: [PATCH 12/13] drm/i915: Polish sprite plane register definitions
On Mon, 20 May 2024, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: >> From: Ville Syrjälä >> >> Group the sprite plane register definitions such that everything >> to do wiht the same register is in one place. *with >> >> Signed-off-by: Ville Syrjälä > > Reviewed-by: Jani Nikula > >> --- >> .../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++ >> 1 file changed, 134 insertions(+), 97 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h >> b/drivers/gpu/drm/i915/display/intel_sprite_regs.h >> index bb67705652b2..c27adbaf0f00 100644 >> --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h >> +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h >> @@ -7,6 +7,8 @@ >> #include "intel_display_reg_defs.h" >> >> #define _DVSACNTR 0x72180 >> +#define _DVSBCNTR 0x73180 >> +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) >> #define DVS_ENABLEREG_BIT(31) >> #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) >> #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) >> @@ -28,31 +30,67 @@ >> #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) >> #define DVS_TILED REG_BIT(10) >> #define DVS_DEST_KEY REG_BIT(2) >> + >> #define _DVSALINOFF 0x72184 >> +#define _DVSBLINOFF 0x73184 >> +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) >> + >> #define _DVSASTRIDE 0x72188 >> +#define _DVSBSTRIDE 0x73188 >> +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) >> + >> #define _DVSAPOS0x7218c >> +#define _DVSBPOS0x7318c >> +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) >> #define DVS_POS_Y_MASKREG_GENMASK(31, 16) >> #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, >> (y)) >> #define DVS_POS_X_MASKREG_GENMASK(15, 0) >> #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, >> (x)) >> + >> #define _DVSASIZE 0x72190 >> +#define _DVSBSIZE 0x73190 >> +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) >> #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) >> #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, >> (h)) >> #define DVS_WIDTH_MASKREG_GENMASK(15, 0) >> #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, >> (w)) >> + >> #define _DVSAKEYVAL 0x72194 >> +#define _DVSBKEYVAL 0x73194 >> +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) >> + >> #define _DVSAKEYMSK 0x72198 >> +#define _DVSBKEYMSK 0x73198 >> +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) >> + >> #define _DVSASURF 0x7219c >> +#define _DVSBSURF 0x7319c >> +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) >> #define DVS_ADDR_MASK REG_GENMASK(31, 12) >> + >> #define _DVSAKEYMAXVAL 0x721a0 >> +#define _DVSBKEYMAXVAL 0x731a0 >> +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) >> + >> #define _DVSATILEOFF0x721a4 >> +#define _DVSBTILEOFF0x731a4 >> +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) >> #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) >> #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) >> #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) >> #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) >> + >> #define _DVSASURFLIVE 0x721ac >> +#define _DVSBSURFLIVE 0x731ac >> +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) >> + >> #define _DVSAGAMC_G4X 0x721e0 /* g4x */ >> +#define _DVSBGAMC_G4X 0x731e0 /* g4x */ >> +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, >> _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ >> + >> #define _DVSASCALE 0x72204 >> +#define _DVSBSCALE 0x73204 >> +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) >> #define DVS_SCALE_ENABLE REG_BIT(31) >> #define DVS_FILTER_MASK REG_GENMASK(30, 29) >> #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) >> @@ -64,42 +102,18 @@ >> #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) >> #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) >> #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) >> + >> #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ >> -#define _DVSAGAMCMAX_ILK0x72340 /* ilk/snb */ >> - >> -#define _DVSBCNTR 0x73180 >> -#define _DVSBLINOFF 0x73184 >> -#define _DVSBSTRIDE 0x73188 >> -#define _DVSBPOS0x7318c >> -#define _DVSBSIZE 0x73190 >> -#
Re: [PATCH 12/13] drm/i915: Polish sprite plane register definitions
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Group the sprite plane register definitions such that everything > to do wiht the same register is in one place. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > .../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++ > 1 file changed, 134 insertions(+), 97 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h > b/drivers/gpu/drm/i915/display/intel_sprite_regs.h > index bb67705652b2..c27adbaf0f00 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h > @@ -7,6 +7,8 @@ > #include "intel_display_reg_defs.h" > > #define _DVSACNTR0x72180 > +#define _DVSBCNTR0x73180 > +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) > #define DVS_ENABLE REG_BIT(31) > #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) > #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) > @@ -28,31 +30,67 @@ > #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) > #define DVS_TILED REG_BIT(10) > #define DVS_DEST_KEY REG_BIT(2) > + > #define _DVSALINOFF 0x72184 > +#define _DVSBLINOFF 0x73184 > +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) > + > #define _DVSASTRIDE 0x72188 > +#define _DVSBSTRIDE 0x73188 > +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) > + > #define _DVSAPOS 0x7218c > +#define _DVSBPOS 0x7318c > +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) > #define DVS_POS_Y_MASK REG_GENMASK(31, 16) > #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, > (y)) > #define DVS_POS_X_MASK REG_GENMASK(15, 0) > #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, > (x)) > + > #define _DVSASIZE0x72190 > +#define _DVSBSIZE0x73190 > +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) > #define DVS_HEIGHT_MASKREG_GENMASK(31, 16) > #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, > (h)) > #define DVS_WIDTH_MASK REG_GENMASK(15, 0) > #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, > (w)) > + > #define _DVSAKEYVAL 0x72194 > +#define _DVSBKEYVAL 0x73194 > +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) > + > #define _DVSAKEYMSK 0x72198 > +#define _DVSBKEYMSK 0x73198 > +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) > + > #define _DVSASURF0x7219c > +#define _DVSBSURF0x7319c > +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) > #define DVS_ADDR_MASK REG_GENMASK(31, 12) > + > #define _DVSAKEYMAXVAL 0x721a0 > +#define _DVSBKEYMAXVAL 0x731a0 > +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) > + > #define _DVSATILEOFF 0x721a4 > +#define _DVSBTILEOFF 0x731a4 > +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) > #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) > #define DVS_OFFSET_Y(y)REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) > #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) > #define DVS_OFFSET_X(x)REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) > + > #define _DVSASURFLIVE0x721ac > +#define _DVSBSURFLIVE0x731ac > +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) > + > #define _DVSAGAMC_G4X0x721e0 /* g4x */ > +#define _DVSBGAMC_G4X0x731e0 /* g4x */ > +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) > + (5 - (i)) * 4) /* 6 x u0.8 */ > + > #define _DVSASCALE 0x72204 > +#define _DVSBSCALE 0x73204 > +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) > #define DVS_SCALE_ENABLE REG_BIT(31) > #define DVS_FILTER_MASKREG_GENMASK(30, 29) > #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) > @@ -64,42 +102,18 @@ > #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) > #define DVS_SRC_HEIGHT_MASKREG_GENMASK(10, 0) > #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) > + > #define _DVSAGAMC_ILK0x72300 /* ilk/snb */ > -#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ > - > -#define _DVSBCNTR0x73180 > -#define _DVSBLINOFF 0x73184 > -#define _DVSBSTRIDE 0x73188 > -#define _DVSBPOS 0x7318c > -#define _DVSBSIZE0x73190 > -#define _DVSBKEYVAL 0x73194 > -#define _DVSBKEYMSK 0x73198 > -#define _DVSBSURF0x7319c > -#define _DVSB
Re: [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Add some notes indicatign which plane registers/bits are *indicating > valid for which platforms. > > Signed-off-by: Ville Syrjälä Acked-by: Jani Nikula because I'm not going to chase through all the specs for these. ;) > --- > .../gpu/drm/i915/display/i9xx_plane_regs.h| 22 +-- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > index 929b26faf31e..d74a74d1f29a 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > @@ -37,53 +37,53 @@ > #define DISP_LINE_DOUBLE REG_BIT(20) > #define DISP_STEREO_POLARITY_SECONDREG_BIT(18) > #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ > -#define DISP_ROTATE_180REG_BIT(15) > +#define DISP_ROTATE_180REG_BIT(15) /* i965+ */ > #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ > -#define DISP_TILED REG_BIT(10) > +#define DISP_TILED REG_BIT(10) /* i965+ */ > #define DISP_ASYNC_FLIPREG_BIT(9) /* g4x+ */ > #define DISP_MIRRORREG_BIT(8) /* CHV pipe B */ > > -#define _DSPAADDR0x70184 > +#define _DSPAADDR0x70184 /* pre-i965 */ > #define DSPADDR(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPAADDR) > > -#define _DSPALINOFF 0x70184 > +#define _DSPALINOFF 0x70184 /* i965+ */ > #define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPALINOFF) > > #define _DSPASTRIDE 0x70188 > #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPASTRIDE) > > -#define _DSPAPOS 0x7018C /* reserved */ > +#define _DSPAPOS 0x7018C /* pre-g4x */ > #define DSPPOS(plane)_MMIO_PIPE2(dev_priv, > plane, _DSPAPOS) > #define DISP_POS_Y_MASKREG_GENMASK(31, 16) > #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, > (y)) > #define DISP_POS_X_MASKREG_GENMASK(15, 0) > #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, > (x)) > > -#define _DSPASIZE0x70190 > +#define _DSPASIZE0x70190 /* pre-g4x */ > #define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPASIZE) > #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) > #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) > #define DISP_WIDTH_MASKREG_GENMASK(15, 0) > #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, > (w)) > > -#define _DSPASURF0x7019C /* 965+ only */ > +#define _DSPASURF0x7019C /* i965+ */ > #define DSPSURF(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPASURF) > #define DISP_ADDR_MASK REG_GENMASK(31, 12) > > -#define _DSPATILEOFF 0x701A4 /* 965+ only */ > +#define _DSPATILEOFF 0x701A4 /* i965+ */ > #define DSPTILEOFF(plane)_MMIO_PIPE2(dev_priv, plane, > _DSPATILEOFF) > #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) > #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) > #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) > #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) > > -#define _DSPAOFFSET 0x701A4 /* HSW */ > +#define _DSPAOFFSET 0x701A4 /* hsw+ */ > #define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPAOFFSET) > > -#define _DSPASURFLIVE0x701AC > +#define _DSPASURFLIVE0x701AC /* g4x+ */ > #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPASURFLIVE) > > -#define _DSPAGAMC0x701E0 > +#define _DSPAGAMC0x701E0 /* pre-g4x */ > #define DSPGAMC(plane, i)_MMIO_PIPE2(dev_priv, plane, > _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ > > /* CHV pipe B primary plane */ -- Jani Nikula, Intel
Re: [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Group the pre-skl primary plane register definitions > sensible, and toss in a few comments to indicate which > platforms have what. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > .../gpu/drm/i915/display/i9xx_plane_regs.h| 46 --- > 1 file changed, 29 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > index 0bf2cd42bce7..929b26faf31e 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > @@ -9,7 +9,10 @@ > #include "intel_display_reg_defs.h" > > #define _DSPAADDR_VLV0x7017C /* vlv/chv */ > +#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPAADDR_VLV) > + > #define _DSPACNTR0x70180 > +#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPACNTR) > #define DISP_ENABLEREG_BIT(31) > #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) > #define DISP_FORMAT_MASK REG_GENMASK(29, 26) > @@ -39,60 +42,69 @@ > #define DISP_TILED REG_BIT(10) > #define DISP_ASYNC_FLIPREG_BIT(9) /* g4x+ */ > #define DISP_MIRRORREG_BIT(8) /* CHV pipe B */ > + > #define _DSPAADDR0x70184 > +#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPAADDR) > + > +#define _DSPALINOFF 0x70184 > +#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPALINOFF) > + > #define _DSPASTRIDE 0x70188 > +#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPASTRIDE) > + > #define _DSPAPOS 0x7018C /* reserved */ > +#define DSPPOS(plane)_MMIO_PIPE2(dev_priv, > plane, _DSPAPOS) > #define DISP_POS_Y_MASKREG_GENMASK(31, 16) > #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, > (y)) > #define DISP_POS_X_MASKREG_GENMASK(15, 0) > #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, > (x)) > + > #define _DSPASIZE0x70190 > +#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPASIZE) > #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) > #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) > #define DISP_WIDTH_MASKREG_GENMASK(15, 0) > #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, > (w)) > + > #define _DSPASURF0x7019C /* 965+ only */ > +#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPASURF) > #define DISP_ADDR_MASK REG_GENMASK(31, 12) > + > #define _DSPATILEOFF 0x701A4 /* 965+ only */ > +#define DSPTILEOFF(plane)_MMIO_PIPE2(dev_priv, plane, > _DSPATILEOFF) > #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) > #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) > #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) > #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) > + > #define _DSPAOFFSET 0x701A4 /* HSW */ > +#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPAOFFSET) > + > #define _DSPASURFLIVE0x701AC > +#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPASURFLIVE) > + > #define _DSPAGAMC0x701E0 > - > -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) > -#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) > -#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) > -#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) > -#define DSPPOS(plane)_MMIO_PIPE2(dev_priv, plane, _DSPAPOS) > -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) > -#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) > -#define DSPTILEOFF(plane)_MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) > -#define DSPLINOFF(plane) DSPADDR(plane) > -#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) > -#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) > -#define DSPGAMC(plane, i)_MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - > (i)) * 4) /* plane C only, 6 x u0.8 */ > +#define DSPGAMC(plane, i)_MMIO_PIPE2(dev_priv, plane, > _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ > > /* CHV pipe B primar
Re: [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > PIPEGCMAX was left behind when all other gamma registers moved > into intel_color_regs.h. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_color_regs.h | 5 + > drivers/gpu/drm/i915/i915_reg.h | 4 > 2 files changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h > b/drivers/gpu/drm/i915/display/intel_color_regs.h > index bb99ea533842..61c18b4a7fa5 100644 > --- a/drivers/gpu/drm/i915/display/intel_color_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h > @@ -36,6 +36,11 @@ > _CHV_PALETTE_C, > _CHV_PALETTE_C) + \ > (i) * 4) > > +/* i965/g4x/vlv/chv */ > +#define _PIPEAGCMAX 0x70010 > +#define _PIPEBGCMAX 0x71010 > +#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) > * 4) /* u1.16 */ > + > /* ilk+ palette */ > #define _LGC_PALETTE_A 0x4a000 > #define _LGC_PALETTE_B 0x4a800 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 52b029cd3981..f5e8833cc37e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1882,10 +1882,6 @@ > #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) > #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) > > -#define _PIPEAGCMAX 0x70010 > -#define _PIPEBGCMAX 0x71010 > -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) > * 4) /* u1.16 */ > - > #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ > #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, > _PIPE_ARB_CTL_A) > #define PIPE_ARB_USE_PROG_SLOTSREG_BIT(13) -- Jani Nikula, Intel
✗ Fi.CI.SPARSE: warning for Link off between frames for edp (rev5)
== Series Details == Series: Link off between frames for edp (rev5) URL : https://patchwork.freedesktop.org/series/130650/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for Link off between frames for edp (rev5)
== Series Details ==
Series: Link off between frames for edp (rev5)
URL : https://patchwork.freedesktop.org/series/130650/
State : warning
== Summary ==
Error: dim checkpatch failed
70ca27e269fd drm/i915/alpm: Move alpm parameters from intel_psr
-:83: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#83: FILE: drivers/gpu/drm/i915/display/intel_psr.c:958:
+ tmp = map[intel_dp->alpm_parameters.fast_wake_lines -
TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
total: 0 errors, 1 warnings, 0 checks, 143 lines checked
282883ab4b76 drm/i915/alpm: Move alpm related code to a new file
-:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#27:
new file mode 100644
-:233: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#233: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:202:
+bool intel_alpm_compute_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
-:255: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#255: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:224:
+ io_wake_lines = intel_usecs_to_scanlines(
-:257: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#257: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:226:
+ fast_wake_lines = intel_usecs_to_scanlines(
-:268: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#268: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:237:
+ io_wake_lines = fast_wake_lines = max_wake_lines;
-:301: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#301: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:270:
+ PORT_ALPM_CTL_SILENCE_PERIOD(
-:307: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#307: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:276:
+ PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
-:309: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#309: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:278:
+
PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
-:311: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#311: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:280:
+ PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
total: 0 errors, 1 warnings, 8 checks, 640 lines checked
5267bfc09f04 drm/display: Add missing aux less alpm wake related bits
dcf0642f3fdf drm/i915/alpm: Add compute config for lobf
60be9b73a915 drm/i915/alpm: Enable lobf from source in ALPM_CTL
c98622a7d6de drm/i915/alpm: Add debugfs for LOBF
Re: [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Relocate all pre-skl primary plane register definitions > into their own declutter i915_reg.h. > > Cc: Zhenyu Wang > Cc: Zhi Wang > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/i9xx_plane.c | 1 + > .../gpu/drm/i915/display/i9xx_plane_regs.h| 98 +++ > .../gpu/drm/i915/display/intel_atomic_plane.c | 1 + > drivers/gpu/drm/i915/display/intel_color.c| 2 +- > drivers/gpu/drm/i915/display/intel_display.c | 1 + > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + > drivers/gpu/drm/i915/gvt/display.c| 1 + > drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + > drivers/gpu/drm/i915/gvt/handlers.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 87 +--- > drivers/gpu/drm/i915/intel_clock_gating.c | 1 + > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + > 13 files changed, 110 insertions(+), 87 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c > b/drivers/gpu/drm/i915/display/i9xx_plane.c > index ea4d8ba55ad8..1f05f9184cb2 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > @@ -10,6 +10,7 @@ > > #include "i915_reg.h" > #include "i9xx_plane.h" > +#include "i9xx_plane_regs.h" > #include "intel_atomic.h" > #include "intel_atomic_plane.h" > #include "intel_de.h" > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > new file mode 100644 > index ..0bf2cd42bce7 > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > @@ -0,0 +1,98 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2024 Intel Corporation > + */ > + > +#ifndef __I9XX_PLANE_REGS_H__ > +#define __I9XX_PLANE_REGS_H__ > + > +#include "intel_display_reg_defs.h" > + > +#define _DSPAADDR_VLV0x7017C /* vlv/chv */ > +#define _DSPACNTR0x70180 > +#define DISP_ENABLEREG_BIT(31) > +#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) > +#define DISP_FORMAT_MASK REG_GENMASK(29, 26) > +#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) > +#define DISP_FORMAT_BGRA555 > REG_FIELD_PREP(DISP_FORMAT_MASK, 3) > +#define DISP_FORMAT_BGRX555 > REG_FIELD_PREP(DISP_FORMAT_MASK, 4) > +#define DISP_FORMAT_BGRX565 > REG_FIELD_PREP(DISP_FORMAT_MASK, 5) > +#define DISP_FORMAT_BGRX888 > REG_FIELD_PREP(DISP_FORMAT_MASK, 6) > +#define DISP_FORMAT_BGRA888 > REG_FIELD_PREP(DISP_FORMAT_MASK, 7) > +#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) > +#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) > +#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) > +#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) > +#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) > +#define DISP_FORMAT_RGBX888 > REG_FIELD_PREP(DISP_FORMAT_MASK, 14) > +#define DISP_FORMAT_RGBA888 > REG_FIELD_PREP(DISP_FORMAT_MASK, 15) > +#define DISP_STEREO_ENABLE REG_BIT(25) > +#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ > +#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) > +#define DISP_PIPE_SEL(pipe) > REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) > +#define DISP_SRC_KEY_ENABLEREG_BIT(22) > +#define DISP_LINE_DOUBLE REG_BIT(20) > +#define DISP_STEREO_POLARITY_SECONDREG_BIT(18) > +#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ > +#define DISP_ROTATE_180REG_BIT(15) > +#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ > +#define DISP_TILED REG_BIT(10) > +#define DISP_ASYNC_FLIPREG_BIT(9) /* g4x+ */ > +#define DISP_MIRRORREG_BIT(8) /* CHV pipe B */ > +#define _DSPAADDR0x70184 > +#define _DSPASTRIDE 0x70188 > +#define _DSPAPOS 0x7018C /* reserved */ > +#define DISP_POS_Y_MASKREG_GENMASK(31, 16) > +#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, > (y)) > +#define DISP_POS_X_MASKREG_GENMASK(15, 0) > +#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, > (x)) > +#define _DSPASIZE0x70190 > +#define DISP_HEIGHT_MASK REG_GENMASK(31, 16) > +#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) > +#define DISP_WIDTH_MASKREG_GENMASK(15, 0
Re: [linux-next:master] [mm/slab] 7bd230a266: WARNING:at_mm/util.c:#kvmalloc_node_noprof
this looks like an i915 bug
On Wed, May 15, 2024 at 10:41:19AM +0800, kernel test robot wrote:
>
>
> Hello,
>
> as we understand, this commit is not the root-cause of this WARNING. the
> WARNING
> just shows in another way by commit changes.
>
> 53ed0af496422959 7bd230a26648ac68ab3731ebbc4
> ---
>fail:runs %reproductionfail:runs
>| | |
> 6:6 -83%:6 dmesg.RIP:kvmalloc_node
>:6 33% 6:6 dmesg.RIP:kvmalloc_node_noprof
> 6:6 -83%:6
> dmesg.WARNING:at_mm/util.c:#kvmalloc_node
>:6 33% 6:6
> dmesg.WARNING:at_mm/util.c:#kvmalloc_node_noprof
>
>
> but we failed to bisect "dmesg.WARNING:at_mm/util.c:#kvmalloc_node".
>
> we still made this report FYI what we observed in our tests, not sure if it
> could give somebody some hints to find the real problem then judge if a fix
> is needed.
>
> below is full report.
>
>
>
> kernel test robot noticed "WARNING:at_mm/util.c:#kvmalloc_node_noprof" on:
>
> commit: 7bd230a26648ac68ab3731ebbc449090f0ac6a37 ("mm/slab: enable slab
> allocation tagging for kmalloc and friends")
> https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git master
>
> [test failed on linux-next/master 6ba6c795dc73c22ce2c86006f17c4aa802db2a60]
>
> in testcase: igt
> version: igt-x86_64-86712f2ef-1_20240511
> with following parameters:
>
> group: gem_exec_reloc
>
>
>
> compiler: gcc-13
> test machine: 20 threads 1 sockets (Commet Lake) with 16G memory
>
> (please refer to attached dmesg/kmsg for entire log/backtrace)
>
>
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version
> of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot
> | Closes:
> https://lore.kernel.org/oe-lkp/202405151008.6ddd1aaf-oliver.s...@intel.com
>
>
> [ 940.101700][ T5353] [ cut here ]
> [ 940.107107][ T5353] WARNING: CPU: 1 PID: 5353 at mm/util.c:649
> kvmalloc_node_noprof (mm/util.c:649 (discriminator 1))
> [ 940.116178][ T5353] Modules linked in: netconsole btrfs blake2b_generic
> xor zstd_compress intel_rapl_msr intel_rapl_common intel_uncore_frequency
> intel_uncore_frequency_common raid6_pq libcrc32c x86_pkg_temp_thermal
> intel_powerclamp coretemp kvm_intel sd_mod t10_pi crc64_rocksoft_generic
> crc64_rocksoft ipmi_devintf crc64 sg ipmi_msghandler kvm crct10dif_pclmul
> crc32_pclmul crc32c_intel ghash_clmulni_intel i915 sha512_ssse3 sdhci_pci
> drm_buddy cqhci ahci rapl intel_gtt drm_display_helper sdhci libahci mei_me
> ttm intel_cstate i2c_designware_platform ppdev intel_uncore
> intel_wmi_thunderbolt wmi_bmof libata mei i2c_designware_core idma64
> drm_kms_helper mmc_core i2c_i801 i2c_smbus intel_pch_thermal parport_pc video
> parport pinctrl_cannonlake wmi acpi_pad acpi_tad serio_raw binfmt_misc drm
> fuse loop dm_mod ip_tables
> [ 940.188041][ T5353] CPU: 1 PID: 5353 Comm: gem_exec_reloc Not tainted
> 6.9.0-rc4-00085-g7bd230a26648 #1
> [ 940.197459][ T5353] RIP: 0010:kvmalloc_node_noprof (mm/util.c:649
> (discriminator 1))
> [ 940.203412][ T5353] Code: 04 a3 0d 00 48 83 c4 18 48 83 c4 08 5b 5d 41 5c
> 41 5d 41 5e c3 cc cc cc cc 49 be 00 00 00 00 00 20 00 00 eb 9f 80 e7 20 75 de
> <0f> 0b eb da 48 c7 c7 10 ec af 84 e8 0e a6 18 00 e9 3f ff ff ff 48
> All code
>
>0: 04 a3 add$0xa3,%al
>2: 0d 00 48 83 c4 or $0xc4834800,%eax
>7: 18 48 83sbb%cl,-0x7d(%rax)
>a: c4 (bad)
>b: 08 5b 5dor %bl,0x5d(%rbx)
>e: 41 5c pop%r12
> 10: 41 5d pop%r13
> 12: 41 5e pop%r14
> 14: c3 retq
> 15: cc int3
> 16: cc int3
> 17: cc int3
> 18: cc int3
> 19: 49 be 00 00 00 00 00movabs $0x2000,%r14
> 20: 20 00 00
> 23: eb 9f jmp0xffc4
> 25: 80 e7 20and$0x20,%bh
> 28: 75 de jne0x8
> 2a:*0f 0b ud2 <-- trapping instruction
> 2c: eb da jmp0x8
> 2e: 48 c7 c7 10 ec af 84mov$0x84afec10,%rdi
> 35: e8 0e a6 18 00 callq 0x18a648
> 3a: e9 3f ff ff ff jmpq 0xff7e
> 3f: 48 rex.W
>
> Code starting with the faulting instruction
> ===
>0: 0f 0b ud2
>2: eb da jmp0xffde
>4: 48 c7 c7 10 ec af 84mov$0x84afec10,%rdi
>b: e8 0e a6 18 00 callq 0x18a61e
> 10: e9 3f ff ff ff jmpq 0xff5
Re: [PATCH] drm/i915/gt: Fix CCS id's calculation for CCS mode setting
> On May 17, 2024, at 17:06, Andi Shyti wrote:
>
> The whole point of the previous fixes has been to change the CCS
> hardware configuration to generate only one stream available to
> the compute users. We did this by changing the info.engine_mask
> that is set during device probe, reset during the detection of
> the fused engines, and finally reset again when choosing the CCS
> mode.
>
> We can't use the engine_mask variable anymore, as with the
> current configuration, it imposes only one CCS no matter what the
> hardware configuration is.
>
> Before changing the engine_mask for the third time, save it and
> use it for calculating the CCS mode.
>
> After the previous changes, the user reported a performance drop
> to around 1/4. We have tested that the compute operations, with
> the current patch, have improved by the same factor.
>
> Fixes: 6db31251bb26 ("drm/i915/gt: Enable only one CCS for compute workload")
> Cc: Chris Wilson
> Cc: Gnattu OC
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Tested-by: Jian Ye
> ---
> Hi,
>
> This ensures that all four CCS engines work properly. However,
> during the tests, Jian detected that the performance during
> memory copy assigned to the CCS engines is negatively impacted.
>
> I believe this might be expected, considering that based on the
> engines' availability, the media user might decide to reduce the
> copy in multitasking.
>
> With the upcoming work that will give the user the chance to
> configure the CCS mode, this might improve.
>
> Gnattu, can I use your kindness to ask for a test on this patch
> and check whether the performance improve on your side as well?
>
> Thanks,
> Andi
>
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++
> drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h| 8
> 3 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 5c8e9ee3b008..3b740ca25000 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -885,6 +885,12 @@ static intel_engine_mask_t init_engine_mask(struct
> intel_gt *gt)
> if (IS_DG2(gt->i915)) {
> u8 first_ccs = __ffs(CCS_MASK(gt));
>
> + /*
> + * Store the number of active cslices before
> + * changing the CCS engine configuration
> + */
> + gt->ccs.cslices = CCS_MASK(gt);
> +
> /* Mask off all the CCS engine */
> info->engine_mask &= ~GENMASK(CCS3, CCS0);
> /* Put back in the first CCS engine */
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
> b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
> index 99b71bb7da0a..3c62a44e9106 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
> @@ -19,7 +19,7 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
>
> /* Build the value for the fixed CCS load balancing */
> for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
> - if (CCS_MASK(gt) & BIT(cslice))
> + if (gt->ccs.cslices & BIT(cslice))
> /*
>* If available, assign the cslice
>* to the first available engine...
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index def7dd0eb6f1..cfdd2ad5e954 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -207,6 +207,14 @@ struct intel_gt {
> [MAX_ENGINE_INSTANCE + 1];
> enum intel_submission_method submission_method;
>
> + struct {
> + /*
> + * Mask of the non fused CCS slices
> + * to be used for the load balancing
> + */
> + intel_engine_mask_t cslices;
> + } ccs;
> +
> /*
>* Default address space (either GGTT or ppGTT depending on arch).
>*
> --
> 2.43.0
Hi Andi,
I can confirm that this patch restores most of the performance we had before
the CCS change.
I do notice a reduction in memcpy performance, but it is good enough for our
use case since our video processing pipeline is zero-copy once the video is
loaded to the VRAM.
Tested-by: Gnattu OC mailto:gnatt...@me.com>>
Re: [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
On Wed, 15 May 2024, Jani Nikula wrote:
> The PCI ID macros in xe_pciids.h allow passing in the macro to operate
> on each PCI ID, making it more flexible. Convert i915_pciids.h to the
> same pattern.
>
> INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
> unconditionally uses INTEL_QUANTA_VGA_DEVICE().
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
Bjorn, since I asked for acks on the last ones, I probably should here
too. :)
I'm hoping to stop mucking with the macros after this.
BR,
Jani.
> Cc: Lucas De Marchi
> Cc: Rodrigo Vivi
> Signed-off-by: Jani Nikula
>
> ---
>
> Tip: It's probably easiest to apply and use 'git show --color-words' for
> review.
>
> This transformation is completely scripted:
>
> | #!/bin/bash
> |
> | FILE=include/drm/i915_pciids.h
> |
> | sed -i 's/[\t ]*\\/ \\/' $FILE
> |
> | sed -i 's/^\(#define [A-Za-z0-9_]\+\)_IDS(info)/\1_IDS(MACRO__, ...)/' $FILE
> |
> | sed -i 's/^\t\([A-Za-z0-9_]\+\)(info)/\t\1(MACRO__, ## __VA_ARGS__)/' $FILE
> |
> | sed -i 's/^\tINTEL_VGA_DEVICE(\([A-Fa-f0-9x]\+\), info)/\tMACRO__(\1, ##
> __VA_ARGS__)/' $FILE
> |
> | # Special case: IVB Q transcode
> | sed -i 's/^\t\(INTEL_QUANTA_VGA_DEVICE\)(MACRO__, ## /\t\1(/' $FILE
> |
> | # Change all users
> | for file in $(git grep -l "#include "); do
> | for macro in $(git grep -ho "#define [A-Za-z0-9_]\+_IDS" $FILE | sed
> 's/#define //'); do
> | sed -i "s/$macro(/$macro(INTEL_VGA_DEVICE, /" $file
> | done
> | done
> ---
> arch/x86/kernel/early-quirks.c| 80 +-
> .../drm/i915/display/intel_display_device.c | 86 +-
> drivers/gpu/drm/i915/i915_pci.c | 150 +-
> drivers/gpu/drm/i915/intel_device_info.c | 88 +-
> include/drm/i915_pciids.h | 1348 -
> 5 files changed, 876 insertions(+), 876 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index fd74d7f26f01..1c137771c5d2 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -518,46 +518,46 @@ static const struct intel_early_ops gen11_early_ops
> __initconst = {
>
> /* Intel integrated GPUs for which we need to reserve "stolen memory" */
> static const struct pci_device_id intel_early_ids[] __initconst = {
> - INTEL_I830_IDS(&i830_early_ops),
> - INTEL_I845G_IDS(&i845_early_ops),
> - INTEL_I85X_IDS(&i85x_early_ops),
> - INTEL_I865G_IDS(&i865_early_ops),
> - INTEL_I915G_IDS(&gen3_early_ops),
> - INTEL_I915GM_IDS(&gen3_early_ops),
> - INTEL_I945G_IDS(&gen3_early_ops),
> - INTEL_I945GM_IDS(&gen3_early_ops),
> - INTEL_VLV_IDS(&gen6_early_ops),
> - INTEL_PNV_IDS(&gen3_early_ops),
> - INTEL_I965G_IDS(&gen3_early_ops),
> - INTEL_G33_IDS(&gen3_early_ops),
> - INTEL_I965GM_IDS(&gen3_early_ops),
> - INTEL_GM45_IDS(&gen3_early_ops),
> - INTEL_G45_IDS(&gen3_early_ops),
> - INTEL_ILK_IDS(&gen3_early_ops),
> - INTEL_SNB_IDS(&gen6_early_ops),
> - INTEL_IVB_IDS(&gen6_early_ops),
> - INTEL_HSW_IDS(&gen6_early_ops),
> - INTEL_BDW_IDS(&gen8_early_ops),
> - INTEL_CHV_IDS(&chv_early_ops),
> - INTEL_SKL_IDS(&gen9_early_ops),
> - INTEL_BXT_IDS(&gen9_early_ops),
> - INTEL_KBL_IDS(&gen9_early_ops),
> - INTEL_CFL_IDS(&gen9_early_ops),
> - INTEL_WHL_IDS(&gen9_early_ops),
> - INTEL_CML_IDS(&gen9_early_ops),
> - INTEL_GLK_IDS(&gen9_early_ops),
> - INTEL_CNL_IDS(&gen9_early_ops),
> - INTEL_ICL_IDS(&gen11_early_ops),
> - INTEL_EHL_IDS(&gen11_early_ops),
> - INTEL_JSL_IDS(&gen11_early_ops),
> - INTEL_TGL_IDS(&gen11_early_ops),
> - INTEL_RKL_IDS(&gen11_early_ops),
> - INTEL_ADLS_IDS(&gen11_early_ops),
> - INTEL_ADLP_IDS(&gen11_early_ops),
> - INTEL_ADLN_IDS(&gen11_early_ops),
> - INTEL_RPLS_IDS(&gen11_early_ops),
> - INTEL_RPLU_IDS(&gen11_early_ops),
> - INTEL_RPLP_IDS(&gen11_early_ops),
> + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_early_ops),
> + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_early_ops),
> + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_early_ops),
> + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865_early_ops),
> + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_PNV_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_G33_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_G45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_ILK_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_SNB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_IVB_IDS(INTEL_VGA_DEVICE, &gen6
Re: [PATCH v5 6/6] drm/i915/alpm: Add debugfs for LOBF
On Mon, 20 May 2024, Animesh Manna wrote:
> For validation purpose add debugfs for LOBF.
>
> v1: Initial version.
> v2: Add aux-wake/less info along with lobf status. [Jouni]
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 49 +++
> drivers/gpu/drm/i915/display/intel_alpm.h | 2 +
> .../drm/i915/display/intel_display_debugfs.c | 2 +
> 3 files changed, 53 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 8f4da817ef55..843ffb5fcb7a 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -360,3 +360,52 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
> {
> lnl_alpm_configure(intel_dp, crtc_state);
> }
> +
> +static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
> +{
> + struct intel_connector *connector = m->private;
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct drm_crtc *crtc;
> + struct intel_crtc_state *crtc_state;
> + enum transcoder cpu_transcoder;
> + u32 alpm_ctl;
> + int ret;
> +
> + ret =
> drm_modeset_lock_single_interruptible(&dev_priv->drm.mode_config.connection_mutex);
> + if (ret)
> + return ret;
> +
> + crtc = connector->base.state->crtc;
> + if (connector->base.status != connector_status_connected || !crtc) {
> + ret = -ENODEV;
> + goto out;
> + }
> +
> + crtc_state = to_intel_crtc_state(crtc->state);
> + cpu_transcoder = crtc_state->cpu_transcoder;
> + alpm_ctl = intel_de_read(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder));
> + seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl &
> ALPM_CTL_LOBF_ENABLE));
> + seq_printf(m, "Aux-wake alpm status: %s\n",
> +str_enabled_disabled(!(alpm_ctl &
> ALPM_CTL_ALPM_AUX_LESS_ENABLE)));
> + seq_printf(m, "Aux-less alpm status: %s\n",
> +str_enabled_disabled(alpm_ctl &
> ALPM_CTL_ALPM_AUX_LESS_ENABLE));
> +out:
> + drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex);
> +
> + return ret;
> +}
> +
> +DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
> +
> +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
This file is about alpm, and might add more alpm related debugfs files
later. There's no need to encode lobf in the name here.
> +{
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct dentry *root = connector->base.debugfs_entry;
> +
> + if (DISPLAY_VER(i915) < 20 ||
> + connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
> + return;
> +
> + debugfs_create_file("i915_edp_lobf_info", 0444, root,
Why does the filename need to include edp? The connector debugfs files
for psr don't include that either.
> + connector, &i915_edp_lobf_info_fops);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index fd9be8aa876c..0dab2068164a 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -11,6 +11,7 @@
> struct intel_dp;
> struct intel_crtc_state;
> struct drm_connector_state;
> +struct intel_connector;
>
> void intel_alpm_get_capability(struct intel_dp *intel_dp);
> bool intel_alpm_compute_params(struct intel_dp *intel_dp,
> @@ -20,4 +21,5 @@ void intel_alpm_compute_lobf_config(struct intel_dp
> *intel_dp,
> struct drm_connector_state *conn_state);
> void intel_alpm_configure(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 35f9f86ef70f..86d9900c40af 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -13,6 +13,7 @@
> #include "i915_debugfs.h"
> #include "i915_irq.h"
> #include "i915_reg.h"
> +#include "intel_alpm.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_crtc_state_dump.h"
> @@ -1515,6 +1516,7 @@ void intel_connector_debugfs_add(struct intel_connector
> *connector)
> intel_drrs_connector_debugfs_add(connector);
> intel_pps_connector_debugfs_add(connector);
> intel_psr_connector_debugfs_add(connector);
> + intel_alpm_lobf_debugfs_add(connector);
All the others are intel_foo_connector_debugfs_add(). So should this.
>
> if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> connector_type == DRM_MODE_CONNECTOR_HDMIA ||
--
Jani Nikula, Intel
Re: [PATCH v5 4/6] drm/i915/alpm: Add compute config for lobf
On Mon, 20 May 2024, Animesh Manna wrote:
> Link Off Between Active Frames, is a new feature for eDP
> that allows the panel to go to lower power state after
> transmission of data. This is a feature on top of ALPM, AS SDP.
> Add compute config during atomic-check phase.
>
> v1: RFC version.
> v2: Add separate flag for auxless-alpm. [Jani]
> v3:
> - intel_dp->lobf_supported replaced with crtc_state->has_lobf. [Jouni]
> - Add DISPLAY_VER() check. [Jouni]
> - Modify function name of get_aux_less_status. [Jani]
> v4: Add enum alpm_mode to hold the aux-wake/less capability.
> v5: Add alpm_dpcd to intel_dp and use aux_wake_supported()/
> aux_less_wake_supported() instead of enum alpm_mode. [Jouni]
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 61 +++
> drivers/gpu/drm/i915/display/intel_alpm.h | 5 ++
> .../drm/i915/display/intel_display_types.h| 5 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++
> 4 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 7307e02277d6..c2334197e723 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -11,6 +11,26 @@
> #include "intel_dp_aux.h"
> #include "intel_psr_regs.h"
>
> +static bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
> +{
> + return intel_dp->alpm_dpcd & DP_ALPM_CAP;
> +}
> +
> +static bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
> +{
> + return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
> +}
> +
> +void intel_alpm_get_capability(struct intel_dp *intel_dp)
> +{
> + u8 dpcd;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
> + return;
> +
> + intel_dp->alpm_dpcd = dpcd;
> +}
> +
> /*
> * See Bspec: 71632 for the table
> *
> @@ -243,6 +263,47 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
> return true;
> }
>
> +void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
Please prefer something_something_compute_config() naming instead of
something_compute_something_config().
BR,
Jani.
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> + int waketime_in_lines, first_sdp_position;
> + int context_latency, guardband;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + if (DISPLAY_VER(i915) < 20)
> + return;
> +
> + if (!intel_dp_as_sdp_supported(intel_dp))
> + return;
> +
> + if (crtc_state->has_psr)
> + return;
> +
> + if (!(intel_alpm_aux_wake_supported(intel_dp) ||
> + intel_alpm_aux_less_wake_supported(intel_dp)))
> + return;
> +
> + if (!intel_alpm_compute_params(intel_dp, crtc_state))
> + return;
> +
> + context_latency = adjusted_mode->crtc_vblank_start -
> adjusted_mode->crtc_vdisplay;
> + guardband = adjusted_mode->crtc_vtotal -
> + adjusted_mode->crtc_vdisplay - context_latency;
> + first_sdp_position = adjusted_mode->crtc_vtotal -
> adjusted_mode->crtc_vsync_start;
> + if (intel_alpm_aux_less_wake_supported(intel_dp))
> + waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines;
> + else
> + waketime_in_lines = intel_dp->alpm_parameters.fast_wake_lines;
> +
> + crtc_state->has_lobf = (context_latency + guardband) >
> + (first_sdp_position + waketime_in_lines);
> +}
> +
> static void lnl_alpm_configure(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index c45d078e5a6b..45c07f023a63 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -10,9 +10,14 @@
>
> struct intel_dp;
> struct intel_crtc_state;
> +struct drm_connector_state;
>
> +void intel_alpm_get_capability(struct intel_dp *intel_dp);
> bool intel_alpm_compute_params(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state);
> +void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state);
> void intel_alpm_configure(struct intel_dp *intel_dp);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0ad6134ba94e..d77a9f22b5c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/g
Re: [PATCH v2 6/6] drm/ci: update xfails for the new testlist
On Fri, May 17, 2024 at 02:55:02PM +0530, Vignesh Raman wrote: > Now the testlist is used from IGT build, so update > xfails with the new testlist. > > Set the timeout of all i915 jobs to 1h30m since some jobs > takes more than 1 hour to complete. > > Signed-off-by: Vignesh Raman > --- > > v2: > - Set the timeout of all i915 jobs to 1h30m and updated expectations file. > > --- > drivers/gpu/drm/ci/test.yml | 6 +- > .../gpu/drm/ci/xfails/amdgpu-stoney-fails.txt | 41 ++-- > .../drm/ci/xfails/amdgpu-stoney-flakes.txt| 6 + > .../gpu/drm/ci/xfails/amdgpu-stoney-skips.txt | 18 ++ > drivers/gpu/drm/ci/xfails/i915-amly-fails.txt | 31 > .../gpu/drm/ci/xfails/i915-amly-flakes.txt| 8 + > drivers/gpu/drm/ci/xfails/i915-amly-skips.txt | 11 ++ > drivers/gpu/drm/ci/xfails/i915-apl-fails.txt | 46 +++-- > drivers/gpu/drm/ci/xfails/i915-apl-flakes.txt | 5 + > drivers/gpu/drm/ci/xfails/i915-apl-skips.txt | 15 ++ > drivers/gpu/drm/ci/xfails/i915-cml-fails.txt | 38 > drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt | 5 + > drivers/gpu/drm/ci/xfails/i915-cml-skips.txt | 14 ++ > drivers/gpu/drm/ci/xfails/i915-glk-fails.txt | 41 +++- > drivers/gpu/drm/ci/xfails/i915-glk-flakes.txt | 6 + > drivers/gpu/drm/ci/xfails/i915-glk-skips.txt | 15 ++ > drivers/gpu/drm/ci/xfails/i915-kbl-fails.txt | 42 ++--- > drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt | 6 +- > drivers/gpu/drm/ci/xfails/i915-kbl-skips.txt | 25 +++ > drivers/gpu/drm/ci/xfails/i915-tgl-fails.txt | 77 > drivers/gpu/drm/ci/xfails/i915-tgl-skips.txt | 16 ++ > drivers/gpu/drm/ci/xfails/i915-whl-fails.txt | 63 --- > drivers/gpu/drm/ci/xfails/i915-whl-flakes.txt | 5 + > drivers/gpu/drm/ci/xfails/i915-whl-skips.txt | 11 ++ > .../drm/ci/xfails/mediatek-mt8173-fails.txt | 30 ++- > .../drm/ci/xfails/mediatek-mt8173-flakes.txt | 10 + > .../drm/ci/xfails/mediatek-mt8173-skips.txt | 4 + > .../drm/ci/xfails/mediatek-mt8183-fails.txt | 21 +-- > .../drm/ci/xfails/mediatek-mt8183-skips.txt | 4 + > .../gpu/drm/ci/xfails/meson-g12b-fails.txt| 24 +-- > .../gpu/drm/ci/xfails/meson-g12b-skips.txt| 4 + > .../gpu/drm/ci/xfails/msm-apq8016-fails.txt | 12 +- > .../gpu/drm/ci/xfails/msm-apq8016-skips.txt | 4 + > .../gpu/drm/ci/xfails/msm-apq8096-fails.txt | 7 + > .../gpu/drm/ci/xfails/msm-apq8096-flakes.txt | 5 + > .../gpu/drm/ci/xfails/msm-apq8096-skips.txt | 12 ++ > .../msm-sc7180-trogdor-kingoftown-fails.txt | 175 +- > .../msm-sc7180-trogdor-kingoftown-flakes.txt | 7 + > .../msm-sc7180-trogdor-kingoftown-skips.txt | 7 + > ...sm-sc7180-trogdor-lazor-limozeen-fails.txt | 175 +- > ...m-sc7180-trogdor-lazor-limozeen-flakes.txt | 5 + > ...sm-sc7180-trogdor-lazor-limozeen-skips.txt | 4 + > .../gpu/drm/ci/xfails/msm-sdm845-fails.txt| 38 +--- > .../gpu/drm/ci/xfails/msm-sdm845-flakes.txt | 26 ++- > .../gpu/drm/ci/xfails/msm-sdm845-skips.txt| 7 + Reviewed-by: Dmitry Baryshkov # msm testlists We'd need to triage why the tests are failing, but at least it looks logical from my POV, no more full-test skips, etc. > .../drm/ci/xfails/rockchip-rk3288-fails.txt | 62 +-- > .../drm/ci/xfails/rockchip-rk3288-skips.txt | 4 + > .../drm/ci/xfails/rockchip-rk3399-fails.txt | 83 + > .../drm/ci/xfails/rockchip-rk3399-flakes.txt | 12 +- > .../drm/ci/xfails/rockchip-rk3399-skips.txt | 4 + > drivers/gpu/drm/ci/xfails/update-xfails.py| 4 +- > .../drm/ci/xfails/virtio_gpu-none-fails.txt | 94 +++--- > .../drm/ci/xfails/virtio_gpu-none-skips.txt | 4 + > 53 files changed, 1010 insertions(+), 389 deletions(-) > create mode 100644 drivers/gpu/drm/ci/xfails/i915-amly-flakes.txt > create mode 100644 drivers/gpu/drm/ci/xfails/i915-apl-flakes.txt > create mode 100644 drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt > create mode 100644 drivers/gpu/drm/ci/xfails/i915-glk-flakes.txt > create mode 100644 drivers/gpu/drm/ci/xfails/i915-whl-flakes.txt > create mode 100644 drivers/gpu/drm/ci/xfails/mediatek-mt8173-flakes.txt > create mode 100644 drivers/gpu/drm/ci/xfails/msm-apq8096-flakes.txt > create mode 100644 > drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-flakes.txt > create mode 100644 > drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-flakes.txt -- With best wishes Dmitry
[PATCH v5 3/6] drm/display: Add missing aux less alpm wake related bits
From: Jouni Högander eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. Signed-off-by: Jouni Högander --- include/drm/display/drm_dp.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 906949ca3cee..3317ff88ed59 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -232,6 +232,8 @@ #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ # define DP_ALPM_CAP (1 << 0) +# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_AUX_LESS_CAP (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_CAP (1 << 0) @@ -683,7 +685,8 @@ #define DP_RECEIVER_ALPM_CONFIG0x116 /* eDP 1.4 */ # define DP_ALPM_ENABLE(1 << 0) -# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) -- 2.29.0
[PATCH v5 6/6] drm/i915/alpm: Add debugfs for LOBF
For validation purpose add debugfs for LOBF.
v1: Initial version.
v2: Add aux-wake/less info along with lobf status. [Jouni]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 49 +++
drivers/gpu/drm/i915/display/intel_alpm.h | 2 +
.../drm/i915/display/intel_display_debugfs.c | 2 +
3 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
b/drivers/gpu/drm/i915/display/intel_alpm.c
index 8f4da817ef55..843ffb5fcb7a 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -360,3 +360,52 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
{
lnl_alpm_configure(intel_dp, crtc_state);
}
+
+static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
+{
+ struct intel_connector *connector = m->private;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct drm_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ enum transcoder cpu_transcoder;
+ u32 alpm_ctl;
+ int ret;
+
+ ret =
drm_modeset_lock_single_interruptible(&dev_priv->drm.mode_config.connection_mutex);
+ if (ret)
+ return ret;
+
+ crtc = connector->base.state->crtc;
+ if (connector->base.status != connector_status_connected || !crtc) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ crtc_state = to_intel_crtc_state(crtc->state);
+ cpu_transcoder = crtc_state->cpu_transcoder;
+ alpm_ctl = intel_de_read(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder));
+ seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl &
ALPM_CTL_LOBF_ENABLE));
+ seq_printf(m, "Aux-wake alpm status: %s\n",
+ str_enabled_disabled(!(alpm_ctl &
ALPM_CTL_ALPM_AUX_LESS_ENABLE)));
+ seq_printf(m, "Aux-less alpm status: %s\n",
+ str_enabled_disabled(alpm_ctl &
ALPM_CTL_ALPM_AUX_LESS_ENABLE));
+out:
+ drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex);
+
+ return ret;
+}
+
+DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
+
+void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct dentry *root = connector->base.debugfs_entry;
+
+ if (DISPLAY_VER(i915) < 20 ||
+ connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
+ return;
+
+ debugfs_create_file("i915_edp_lobf_info", 0444, root,
+ connector, &i915_edp_lobf_info_fops);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
b/drivers/gpu/drm/i915/display/intel_alpm.h
index fd9be8aa876c..0dab2068164a 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -11,6 +11,7 @@
struct intel_dp;
struct intel_crtc_state;
struct drm_connector_state;
+struct intel_connector;
void intel_alpm_get_capability(struct intel_dp *intel_dp);
bool intel_alpm_compute_params(struct intel_dp *intel_dp,
@@ -20,4 +21,5 @@ void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
struct drm_connector_state *conn_state);
void intel_alpm_configure(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 35f9f86ef70f..86d9900c40af 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -13,6 +13,7 @@
#include "i915_debugfs.h"
#include "i915_irq.h"
#include "i915_reg.h"
+#include "intel_alpm.h"
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_crtc_state_dump.h"
@@ -1515,6 +1516,7 @@ void intel_connector_debugfs_add(struct intel_connector
*connector)
intel_drrs_connector_debugfs_add(connector);
intel_pps_connector_debugfs_add(connector);
intel_psr_connector_debugfs_add(connector);
+ intel_alpm_lobf_debugfs_add(connector);
if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector_type == DRM_MODE_CONNECTOR_HDMIA ||
--
2.29.0
[PATCH v5 5/6] drm/i915/alpm: Enable lobf from source in ALPM_CTL
Set the Link Off Between Frames Enable bit in ALPM_CTL register.
Note: Lobf need to be enabled adaptive sync fixed refresh mode
where vmin = vmax = flipline, which will arise after cmmr feature
enablement. Will add enabling sequence in a separate patch.
v1: Initial version.
v2: Condition check modified in alpm_configure(). [Jouni]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++-
drivers/gpu/drm/i915/display/intel_alpm.h | 4 ++--
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
b/drivers/gpu/drm/i915/display/intel_alpm.c
index c2334197e723..8f4da817ef55 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -304,10 +304,11 @@ void intel_alpm_compute_lobf_config(struct intel_dp
*intel_dp,
(first_sdp_position + waketime_in_lines);
}
-static void lnl_alpm_configure(struct intel_dp *intel_dp)
+static void lnl_alpm_configure(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 alpm_ctl;
if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled &&
@@ -318,7 +319,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
* Panel Replay on eDP is always using ALPM aux less. I.e. no need to
* check panel support at this point.
*/
- if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {
+ if ((intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) ||
+ (crtc_state->has_lobf &&
intel_alpm_aux_less_wake_supported(intel_dp))) {
alpm_ctl = ALPM_CTL_ALPM_ENABLE |
ALPM_CTL_ALPM_AUX_LESS_ENABLE |
ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
@@ -345,12 +347,16 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);
}
+ if (crtc_state->has_lobf)
+ alpm_ctl |= ALPM_CTL_LOBF_ENABLE;
+
alpm_ctl |=
ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);
intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl);
}
-void intel_alpm_configure(struct intel_dp *intel_dp)
+void intel_alpm_configure(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
- lnl_alpm_configure(intel_dp);
+ lnl_alpm_configure(intel_dp, crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
b/drivers/gpu/drm/i915/display/intel_alpm.h
index 45c07f023a63..fd9be8aa876c 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -18,6 +18,6 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
-void intel_alpm_configure(struct intel_dp *intel_dp);
-
+void intel_alpm_configure(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index e2d3be0bf99c..10c71e79a1c8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1692,7 +1692,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
IGNORE_PSR2_HW_TRACKING : 0);
if (intel_dp_is_edp(intel_dp))
- intel_alpm_configure(intel_dp);
+ intel_alpm_configure(intel_dp, crtc_state);
/*
* Wa_16013835468
--
2.29.0
[PATCH v5 4/6] drm/i915/alpm: Add compute config for lobf
Link Off Between Active Frames, is a new feature for eDP
that allows the panel to go to lower power state after
transmission of data. This is a feature on top of ALPM, AS SDP.
Add compute config during atomic-check phase.
v1: RFC version.
v2: Add separate flag for auxless-alpm. [Jani]
v3:
- intel_dp->lobf_supported replaced with crtc_state->has_lobf. [Jouni]
- Add DISPLAY_VER() check. [Jouni]
- Modify function name of get_aux_less_status. [Jani]
v4: Add enum alpm_mode to hold the aux-wake/less capability.
v5: Add alpm_dpcd to intel_dp and use aux_wake_supported()/
aux_less_wake_supported() instead of enum alpm_mode. [Jouni]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_alpm.c | 61 +++
drivers/gpu/drm/i915/display/intel_alpm.h | 5 ++
.../drm/i915/display/intel_display_types.h| 5 ++
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++
4 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
b/drivers/gpu/drm/i915/display/intel_alpm.c
index 7307e02277d6..c2334197e723 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -11,6 +11,26 @@
#include "intel_dp_aux.h"
#include "intel_psr_regs.h"
+static bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
+{
+ return intel_dp->alpm_dpcd & DP_ALPM_CAP;
+}
+
+static bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
+{
+ return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
+}
+
+void intel_alpm_get_capability(struct intel_dp *intel_dp)
+{
+ u8 dpcd;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
+ return;
+
+ intel_dp->alpm_dpcd = dpcd;
+}
+
/*
* See Bspec: 71632 for the table
*
@@ -243,6 +263,47 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
return true;
}
+void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ int waketime_in_lines, first_sdp_position;
+ int context_latency, guardband;
+
+ if (!intel_dp_is_edp(intel_dp))
+ return;
+
+ if (DISPLAY_VER(i915) < 20)
+ return;
+
+ if (!intel_dp_as_sdp_supported(intel_dp))
+ return;
+
+ if (crtc_state->has_psr)
+ return;
+
+ if (!(intel_alpm_aux_wake_supported(intel_dp) ||
+ intel_alpm_aux_less_wake_supported(intel_dp)))
+ return;
+
+ if (!intel_alpm_compute_params(intel_dp, crtc_state))
+ return;
+
+ context_latency = adjusted_mode->crtc_vblank_start -
adjusted_mode->crtc_vdisplay;
+ guardband = adjusted_mode->crtc_vtotal -
+ adjusted_mode->crtc_vdisplay - context_latency;
+ first_sdp_position = adjusted_mode->crtc_vtotal -
adjusted_mode->crtc_vsync_start;
+ if (intel_alpm_aux_less_wake_supported(intel_dp))
+ waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines;
+ else
+ waketime_in_lines = intel_dp->alpm_parameters.fast_wake_lines;
+
+ crtc_state->has_lobf = (context_latency + guardband) >
+ (first_sdp_position + waketime_in_lines);
+}
+
static void lnl_alpm_configure(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
b/drivers/gpu/drm/i915/display/intel_alpm.h
index c45d078e5a6b..45c07f023a63 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -10,9 +10,14 @@
struct intel_dp;
struct intel_crtc_state;
+struct drm_connector_state;
+void intel_alpm_get_capability(struct intel_dp *intel_dp);
bool intel_alpm_compute_params(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
+void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state);
void intel_alpm_configure(struct intel_dp *intel_dp);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0ad6134ba94e..d77a9f22b5c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1410,6 +1410,9 @@ struct intel_crtc_state {
/* for loading single buffered registers during vblank */
struct drm_vblank_work vblank_work;
+
+ /* LOBF flag */
+ bool has_lobf;
};
enum intel_pipe_crc_source {
@@ -1845,6 +1848,8 @@ struct intel_dp {
[PATCH v5 2/6] drm/i915/alpm: Move alpm related code to a new file
Move ALPM feature related code as it will be used for
non-psr panel also thorugh LOBF feature.
v1: Initial version.
v2: Correct ordering in makefile. [Jani]
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_alpm.c | 295 ++
drivers/gpu/drm/i915/display/intel_alpm.h | 18 ++
drivers/gpu/drm/i915/display/intel_psr.c | 283 +
drivers/gpu/drm/xe/Makefile | 1 +
5 files changed, 318 insertions(+), 280 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_alpm.c
create mode 100644 drivers/gpu/drm/i915/display/intel_alpm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7cad944b825c..9a3f910ce4fd 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -243,6 +243,7 @@ i915-y += \
display/hsw_ips.o \
display/i9xx_plane.o \
display/i9xx_wm.o \
+ display/intel_alpm.o \
display/intel_atomic.o \
display/intel_atomic_plane.o \
display/intel_audio.o \
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
b/drivers/gpu/drm/i915/display/intel_alpm.c
new file mode 100644
index ..7307e02277d6
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2024, Intel Corporation.
+ */
+
+#include "intel_alpm.h"
+#include "intel_crtc.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_dp.h"
+#include "intel_dp_aux.h"
+#include "intel_psr_regs.h"
+
+/*
+ * See Bspec: 71632 for the table
+ *
+ * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2)
+ *
+ * Half cycle duration:
+ *
+ * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns
+ * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) )
+ *
+ * Link rates 5.4 - 8.1
+ * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10
+ * LFPS Period chosen is the mid-point of the min:max values from the table
+ * FLOOR( LFPS Period in Symbol clocks /
+ * (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) )
+ */
+static bool _lnl_get_silence_period_and_lfps_half_cycle(int link_rate,
+ int *silence_period,
+ int *lfps_half_cycle)
+{
+ switch (link_rate) {
+ case 162000:
+ *silence_period = 20;
+ *lfps_half_cycle = 5;
+ break;
+ case 216000:
+ *silence_period = 27;
+ *lfps_half_cycle = 7;
+ break;
+ case 243000:
+ *silence_period = 31;
+ *lfps_half_cycle = 8;
+ break;
+ case 27:
+ *silence_period = 34;
+ *lfps_half_cycle = 9;
+ break;
+ case 324000:
+ *silence_period = 41;
+ *lfps_half_cycle = 11;
+ break;
+ case 432000:
+ *silence_period = 56;
+ *lfps_half_cycle = 15;
+ break;
+ case 54:
+ *silence_period = 69;
+ *lfps_half_cycle = 12;
+ break;
+ case 648000:
+ *silence_period = 84;
+ *lfps_half_cycle = 15;
+ break;
+ case 675000:
+ *silence_period = 87;
+ *lfps_half_cycle = 15;
+ break;
+ case 81:
+ *silence_period = 104;
+ *lfps_half_cycle = 19;
+ break;
+ default:
+ *silence_period = *lfps_half_cycle = -1;
+ return false;
+ }
+ return true;
+}
+
+/*
+ * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
+ * tSilence, Max+ tPHY Establishment + tCDS) / tline)
+ * For the "PHY P2 to P0" latency see the PHY Power Control page
+ * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965
+ * : 12 us
+ * The tLFPS_Period, Max term is 800ns
+ * The tSilence, Max term is 180ns
+ * The tPHY Establishment (a.k.a. t1) term is 50us
+ * The tCDS term is 1 or 2 times t2
+ * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK
+ * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1)
+ * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and
+ * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start
+ * within the CDS period complete within the CDS period regardless of
+ * entry into the period
+ * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
+ * TPS4 Length = 252 Symbols
+ */
+static int _lnl_compute_aux_less_wake_time(int port_clock)
+{
+ int tphy2_p2_to_p0 = 12 * 1000;
+ int tlfps_period_max = 800;
+ int tsilence_max = 180;
+ int t1 = 50 * 1000;
+ int tps4 = 252;
+ int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock;
+ int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
+ int t2 = num_ml_
[PATCH v5 1/6] drm/i915/alpm: Move alpm parameters from intel_psr
ALPM can be enabled for non psr panel and currenly aplm-params are
encapsulated under intel_psr struct, so moving out to intel_dp struct.
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 21 +
drivers/gpu/drm/i915/display/intel_psr.c | 44 +--
2 files changed, 31 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9678c2b157f6..0ad6134ba94e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1705,17 +1705,6 @@ struct intel_psr {
bool psr2_sel_fetch_cff_enabled;
bool req_psr2_sdp_prior_scanline;
u8 sink_sync_latency;
-
- struct {
- u8 io_wake_lines;
- u8 fast_wake_lines;
-
- /* LNL and beyond */
- u8 check_entry_lines;
- u8 silence_period_sym_clocks;
- u8 lfps_half_cycle_num_of_syms;
- } alpm_parameters;
-
ktime_t last_entry_attempt;
ktime_t last_exit;
bool sink_not_reliable;
@@ -1846,6 +1835,16 @@ struct intel_dp {
unsigned long last_oui_write;
bool colorimetry_support;
+
+ struct {
+ u8 io_wake_lines;
+ u8 fast_wake_lines;
+
+ /* LNL and beyond */
+ u8 check_entry_lines;
+ u8 silence_period_sym_clocks;
+ u8 lfps_half_cycle_num_of_syms;
+ } alpm_parameters;
};
enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d18baeb971bb..a9019fde907f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -871,8 +871,8 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
static int psr2_block_count_lines(struct intel_dp *intel_dp)
{
- return intel_dp->psr.alpm_parameters.io_wake_lines < 9 &&
- intel_dp->psr.alpm_parameters.fast_wake_lines < 9 ? 8 : 12;
+ return intel_dp->alpm_parameters.io_wake_lines < 9 &&
+ intel_dp->alpm_parameters.fast_wake_lines < 9 ? 8 : 12;
}
static int psr2_block_count(struct intel_dp *intel_dp)
@@ -910,7 +910,6 @@ static void dg2_activate_panel_replay(struct intel_dp
*intel_dp)
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct intel_psr *psr = &intel_dp->psr;
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
@@ -952,20 +951,20 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
*/
int tmp;
- tmp = map[psr->alpm_parameters.io_wake_lines -
+ tmp = map[intel_dp->alpm_parameters.io_wake_lines -
TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp +
TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES);
- tmp = map[psr->alpm_parameters.fast_wake_lines -
TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
+ tmp = map[intel_dp->alpm_parameters.fast_wake_lines -
TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
val |= TGL_EDP_PSR2_FAST_WAKE(tmp +
TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);
} else if (DISPLAY_VER(dev_priv) >= 20) {
- val |=
LNL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
+ val |=
LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);
} else if (DISPLAY_VER(dev_priv) >= 12) {
- val |=
TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
- val |=
TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);
+ val |=
TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);
+ val |=
TGL_EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines);
} else if (DISPLAY_VER(dev_priv) >= 9) {
- val |=
EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
- val |= EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);
+ val |=
EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines);
+ val |=
EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines);
}
if (intel_dp->psr.req_psr2_sdp_prior_scanline)
@@ -1348,9 +1347,9 @@ static int _lnl_compute_aux_less_alpm_params(struct
intel_dp *intel_dp,
if (i915->display.params.psr_safest_params)
aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;
- intel_dp->psr.alpm_parameters.fast_wake_lines = aux_less_wake_lines;
- intel_dp->psr.alpm_parameters.silence_period_sym_clocks =
silence_period;
- intel_dp->psr.alpm_parameters.lfps_half_cycle_num_of_syms =
lfps_half_cycle;
+
[PATCH v5 0/6] Link off between frames for edp
Link Off Between Active Frames (LOBF) allows an eDP link to be turned Off and On durning long VBLANK durations without enabling any of the PSR/PSR2/PR modes of operation. Bspec: 71477 Note: Lobf need to be enabled adaptive sync fixed refresh mode where vmin = vmax = flipline, which will arise after cmmr feature enablement. Currently existing code refactored and make compute-config() and enabling function ready. Will add enabling sequence in a separate patch. Signed-off-by: Animesh Manna Animesh Manna (5): drm/i915/alpm: Move alpm parameters from intel_psr drm/i915/alpm: Move alpm related code to a new file drm/i915/alpm: Add compute config for lobf drm/i915/alpm: Enable lobf from source in ALPM_CTL drm/i915/alpm: Add debugfs for LOBF Jouni Högander (1): drm/display: Add missing aux less alpm wake related bits drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_alpm.c | 411 ++ drivers/gpu/drm/i915/display/intel_alpm.h | 25 ++ .../drm/i915/display/intel_display_debugfs.c | 2 + .../drm/i915/display/intel_display_types.h| 26 +- drivers/gpu/drm/i915/display/intel_dp.c | 4 + drivers/gpu/drm/i915/display/intel_psr.c | 303 + drivers/gpu/drm/xe/Makefile | 1 + include/drm/display/drm_dp.h | 5 +- 9 files changed, 475 insertions(+), 303 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_alpm.c create mode 100644 drivers/gpu/drm/i915/display/intel_alpm.h -- 2.29.0
Re: [PATCH v2 5/6] drm/ci: skip driver specific tests
On Fri, May 17, 2024 at 02:55:01PM +0530, Vignesh Raman wrote: > Skip driver specific tests and skip kms tests for > panfrost driver since it is not a kms driver. > > Signed-off-by: Vignesh Raman > --- I didn't perform a through check, but generally looks good. Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH 0/7] drm/i915: DSC stuff
On Fri, 17 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Respect the VBT's edp_disable_dsc bit, and do a bunch > of refactoring around checking for DSC support. > > Also threw in a bonus cleanup to intel_dp_has_audio() > that caught my eye. The dropping of const here and there sticks out a bit, but with that explained or fixed, the series is Reviewed-by: Jani Nikula > > Ville Syrjälä (7): > drm/i915: Drop redundant dsc_decompression_aux check > drm/i915: Extract intel_dp_has_dsc() > drm/i915: Handle MST in intel_dp_has_dsc() > drm/i915: Use intel_dp_has_dsc() during .compute_config() > drm/i915: Reuse intel_dp_supports_dsc() for MST > drm/i915: Utilize edp_disable_dsc from VBT > drm/i915: Remove bogus MST check in intel_dp_has_audio() > > drivers/gpu/drm/i915/display/intel_bios.c | 4 ++ > .../drm/i915/display/intel_display_types.h| 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 42 +-- > drivers/gpu/drm/i915/display/intel_dp.h | 4 ++ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++--- > 5 files changed, 44 insertions(+), 30 deletions(-) -- Jani Nikula, Intel
Re: [PATCH v2 4/6] drm/ci: uprev IGT
On Fri, May 17, 2024 at 02:55:00PM +0530, Vignesh Raman wrote: > test-list.txt and test-list-full.txt are not generated for > cross-builds and they are required by drm-ci for testing > arm32 targets. > > This is fixed in igt-gpu-tools. So uprev IGT to include the > commit which fixes this issue. Disable building xe driver > tests for non-intel platforms. > > Signed-off-by: Vignesh Raman > --- > > v2: > - Split IGT uprev to seperate patch. > Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH v2 3/6] drm/ci: build virtual GPU driver as module
On Fri, May 17, 2024 at 02:54:59PM +0530, Vignesh Raman wrote:
> With latest IGT, the tests tries to load the module and it
> fails. So build the virtual GPU driver for virtio as module.
Why? If the test fails on module loading (if the driver is built-in)
then it's the test that needs to be fixed, not the kerenel config.
It's fine as a temporal workaround, but please include a link to the
patch posted to fix the issue.
>
> Signed-off-by: Vignesh Raman
> ---
>
> v2:
> - No changes.
>
> ---
> drivers/gpu/drm/ci/build.sh | 1 -
> drivers/gpu/drm/ci/igt_runner.sh | 6 +++---
> drivers/gpu/drm/ci/image-tags.yml | 4 ++--
> drivers/gpu/drm/ci/test.yml | 1 +
> drivers/gpu/drm/ci/x86_64.config | 2 +-
> 5 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh
> index a67871fdcd3f..e938074ac8e7 100644
> --- a/drivers/gpu/drm/ci/build.sh
> +++ b/drivers/gpu/drm/ci/build.sh
> @@ -157,7 +157,6 @@ fi
>
> mkdir -p artifacts/install/lib
> mv install/* artifacts/install/.
> -rm -rf artifacts/install/modules
> ln -s common artifacts/install/ci-common
> cp .config artifacts/${CI_JOB_NAME}_config
>
> diff --git a/drivers/gpu/drm/ci/igt_runner.sh
> b/drivers/gpu/drm/ci/igt_runner.sh
> index 20026612a9bd..55532f79fbdc 100755
> --- a/drivers/gpu/drm/ci/igt_runner.sh
> +++ b/drivers/gpu/drm/ci/igt_runner.sh
> @@ -30,10 +30,10 @@ case "$DRIVER_NAME" in
> export IGT_FORCE_DRIVER="panfrost"
> fi
> ;;
> -amdgpu)
> +amdgpu|virtio_gpu)
> # Cannot use HWCI_KERNEL_MODULES as at that point we don't have the
> module in /lib
> -mv /install/modules/lib/modules/* /lib/modules/.
> -modprobe amdgpu
> +mv /install/modules/lib/modules/* /lib/modules/. || true
> +modprobe --first-time $DRIVER_NAME
> ;;
> esac
>
> diff --git a/drivers/gpu/drm/ci/image-tags.yml
> b/drivers/gpu/drm/ci/image-tags.yml
> index 60323ebc7304..328f5c560742 100644
> --- a/drivers/gpu/drm/ci/image-tags.yml
> +++ b/drivers/gpu/drm/ci/image-tags.yml
> @@ -4,9 +4,9 @@ variables:
> DEBIAN_BASE_TAG: "${CONTAINER_TAG}"
>
> DEBIAN_X86_64_BUILD_IMAGE_PATH: "debian/x86_64_build"
> - DEBIAN_BUILD_TAG: "2023-10-08-config"
> + DEBIAN_BUILD_TAG: "2024-05-09-virtio"
>
> - KERNEL_ROOTFS_TAG: "2023-10-06-amd"
> + KERNEL_ROOTFS_TAG: "2024-05-09-virtio"
>
> DEBIAN_X86_64_TEST_BASE_IMAGE: "debian/x86_64_test-base"
> DEBIAN_X86_64_TEST_IMAGE_GL_PATH: "debian/x86_64_test-gl"
> diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml
> index 612c9ede3507..864ac3809d84 100644
> --- a/drivers/gpu/drm/ci/test.yml
> +++ b/drivers/gpu/drm/ci/test.yml
> @@ -350,6 +350,7 @@ virtio_gpu:none:
>script:
> - ln -sf $CI_PROJECT_DIR/install /install
> - mv install/bzImage /lava-files/bzImage
> +- mkdir -p /lib/modules
Is it necessary to create it manually here?
> - mkdir -p $CI_PROJECT_DIR/results
> - ln -sf $CI_PROJECT_DIR/results /results
> - install/crosvm-runner.sh install/igt_runner.sh
> diff --git a/drivers/gpu/drm/ci/x86_64.config
> b/drivers/gpu/drm/ci/x86_64.config
> index 1cbd49a5b23a..78479f063e8e 100644
> --- a/drivers/gpu/drm/ci/x86_64.config
> +++ b/drivers/gpu/drm/ci/x86_64.config
> @@ -91,7 +91,7 @@ CONFIG_KVM=y
> CONFIG_KVM_GUEST=y
> CONFIG_VIRT_DRIVERS=y
> CONFIG_VIRTIO_FS=y
> -CONFIG_DRM_VIRTIO_GPU=y
> +CONFIG_DRM_VIRTIO_GPU=m
> CONFIG_SERIAL_8250_CONSOLE=y
> CONFIG_VIRTIO_NET=y
> CONFIG_VIRTIO_CONSOLE=y
> --
> 2.40.1
>
--
With best wishes
Dmitry
Re: [PATCH 7/7] drm/i915: Remove bogus MST check in intel_dp_has_audio()
On Fri, 17 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No idea what this MST checks is doing in intel_dp_has_audio().
> Looks completely pointless, so get rid of it.
2e775f2d41ef ("drm/i915/display: update intel_dp_has_audio to support MST")
6297ee90f682 ("drm/i915/display: configure SDP split for DP-MST")
The division of changes here is not ideal, but I presume the goal was to
not do functional changes compared to intel_dp_mst_has_audio(). Which
may or may not be a good reason...
BR,
Jani.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index af298d5017d9..4a486bb6d48c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2806,7 +2806,6 @@ intel_dp_drrs_compute_config(struct intel_connector
> *connector,
> }
>
> static bool intel_dp_has_audio(struct intel_encoder *encoder,
> -struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> @@ -2815,8 +2814,7 @@ static bool intel_dp_has_audio(struct intel_encoder
> *encoder,
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
>
> - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> - !intel_dp_port_has_audio(i915, encoder->port))
> + if (!intel_dp_port_has_audio(i915, encoder->port))
> return false;
>
> if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
> @@ -2875,7 +2873,7 @@ intel_dp_audio_compute_config(struct intel_encoder
> *encoder,
> struct drm_connector_state *conn_state)
> {
> pipe_config->has_audio =
> - intel_dp_has_audio(encoder, pipe_config, conn_state) &&
> + intel_dp_has_audio(encoder, conn_state) &&
> intel_audio_compute_config(encoder, pipe_config, conn_state);
>
> pipe_config->sdp_split_enable = pipe_config->has_audio &&
--
Jani Nikula, Intel
Re: [PATCH v2 2/6] drm/ci: generate testlist from build
On Fri, May 17, 2024 at 02:54:58PM +0530, Vignesh Raman wrote:
> Stop vendoring the testlist into the kernel. Instead, use the
> testlist from the IGT build to ensure we do not miss renamed
> or newly added tests.
>
> Signed-off-by: Vignesh Raman
> ---
>
> v2:
> - Fix testlist generation for arm and arm64 builds.
>
> ---
> drivers/gpu/drm/ci/build-igt.sh | 34 +
> drivers/gpu/drm/ci/igt_runner.sh |9 +-
> drivers/gpu/drm/ci/testlist.txt | 2761 --
> 3 files changed, 39 insertions(+), 2765 deletions(-)
> delete mode 100644 drivers/gpu/drm/ci/testlist.txt
>
> diff --git a/drivers/gpu/drm/ci/build-igt.sh b/drivers/gpu/drm/ci/build-igt.sh
> index 7859554756c4..e62244728613 100644
> --- a/drivers/gpu/drm/ci/build-igt.sh
> +++ b/drivers/gpu/drm/ci/build-igt.sh
[...]
> @@ -26,6 +50,16 @@ meson build $MESON_OPTIONS $EXTRA_MESON_ARGS
> ninja -C build -j${FDO_CI_CONCURRENT:-4} || ninja -C build -j 1
> ninja -C build install
>
> +if [[ "$KERNEL_ARCH" = "arm64" ]]; then
> +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib/aarch64-linux-gnu
> +elif [[ "$KERNEL_ARCH" = "arm" ]]; then
> +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib
> +else
> +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib64
Could you please clarify this part? The arm64 vs arm don't look logical
from my point of view.
The rest LGTM.
> +fi
> +
> +generate_testlist
> +
> mkdir -p artifacts/
> tar -cf artifacts/igt.tar /igt
>
--
With best wishes
Dmitry
Re: [PATCH 2/7] drm/i915: Extract intel_dp_has_dsc()
On Fri, 17 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract a helper to check whether the source+sink combo
> supports DSC. That basic check is needed both during mode
> validation and compute config. We'll also need to add extra
> checks to both places, so having a single place for it is nicer.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1e88449fe5f2..7bf283b4df7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1220,6 +1220,19 @@ bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> connector->force_bigjoiner_enable;
> }
>
> +static bool intel_dp_has_dsc(struct intel_connector *connector)
Why not const?
> +{
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +
> + if (!HAS_DSC(i915))
> + return false;
> +
> + if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
> + return false;
> +
> + return true;
> +}
> +
> static enum drm_mode_status
> intel_dp_mode_valid(struct drm_connector *_connector,
> struct drm_display_mode *mode)
> @@ -1274,8 +1287,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> mode_rate = intel_dp_link_required(target_clock,
>
> intel_dp_mode_min_output_bpp(connector, mode));
>
> - if (HAS_DSC(dev_priv) &&
> - drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
> + if (intel_dp_has_dsc(connector)) {
> enum intel_output_format sink_format, output_format;
> int pipe_bpp;
--
Jani Nikula, Intel
Re: [PATCH v2 1/6] drm/ci: uprev mesa version
On Fri, May 17, 2024 at 02:54:57PM +0530, Vignesh Raman wrote:
> zlib.net is not allowing tarball download anymore and results
> in below error in kernel+rootfs_arm32 container build,
> urllib.error.HTTPError: HTTP Error 403: Forbidden
> urllib.error.HTTPError: HTTP Error 415: Unsupported Media Type
>
> Uprev mesa to latest version which includes a fix for this issue.
> https://gitlab.freedesktop.org/mesa/mesa/-/commit/908f444e
>
> Use id_tokens for JWT authentication. Since s3 bucket is migrated to
> mesa-rootfs, update the variables accordingly. Also copy helper scripts
> to install, so that the ci jobs can use these scripts for logging.
>
> Signed-off-by: Vignesh Raman
> ---
>
> v2:
> - Uprev to recent version and use id_tokens for JWT authentication
>
> ---
> drivers/gpu/drm/ci/build-igt.sh | 2 +-
> drivers/gpu/drm/ci/build.sh | 6 +++--
> drivers/gpu/drm/ci/container.yml | 12 +++--
> drivers/gpu/drm/ci/gitlab-ci.yml | 44 +--
> drivers/gpu/drm/ci/image-tags.yml | 2 +-
> drivers/gpu/drm/ci/lava-submit.sh | 4 +--
> drivers/gpu/drm/ci/test.yml | 2 ++
> 7 files changed, 44 insertions(+), 28 deletions(-)
>
[skipped]
> diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml
> index 8bc63912fddb..612c9ede3507 100644
> --- a/drivers/gpu/drm/ci/test.yml
> +++ b/drivers/gpu/drm/ci/test.yml
> @@ -150,6 +150,8 @@ msm:sdm845:
> BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel
> GPU_VERSION: sdm845
> RUNNER_TAG: google-freedreno-cheza
> +DEVICE_TYPE: sdm845-cheza-r3
> +FARM: google
I see that this is the only user of the FARM: tag. Is it correct?
Also we miss DEVICE_TYPE for several other boards. Should we be adding
them?
>script:
> - ./install/bare-metal/cros-servo.sh
>
> --
> 2.40.1
>
--
With best wishes
Dmitry
✓ Fi.CI.BAT: success for Ultrajoiner basic functionality series
== Series Details ==
Series: Ultrajoiner basic functionality series
URL : https://patchwork.freedesktop.org/series/133800/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14784 -> Patchwork_133800v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/index.html
Participating hosts (40 -> 40)
--
Additional (3): fi-kbl-7567u fi-kbl-8809g fi-elk-e7500
Missing(3): fi-cfl-8109u fi-snb-2520m bat-arls-3
Known issues
Here are the changes found in Patchwork_133800v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-7567u: NOTRUN -> [SKIP][1] ([i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/fi-kbl-7567u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-7567u: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/fi-kbl-7567u/igt@gem_lmem_swapp...@basic.html
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-7567u: NOTRUN -> [SKIP][5] +11 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/fi-kbl-7567u/igt@kms_force_connector_ba...@force-load-detect.html
- fi-kbl-8809g: NOTRUN -> [SKIP][6] +30 other tests skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- fi-elk-e7500: NOTRUN -> [SKIP][7] +24 other tests skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/fi-elk-e7500/igt@kms_pm_...@basic-pci-d3-state.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [WARN][8] ([i915#10436]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14784/bat-mtlp-9/igt@i915_pm_...@module-reload.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/bat-mtlp-9/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@workarounds:
- bat-dg2-9: [DMESG-FAIL][10] ([i915#9500]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14784/bat-dg2-9/igt@i915_selftest@l...@workarounds.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/bat-dg2-9/igt@i915_selftest@l...@workarounds.html
* igt@kms_flip@basic-plain-flip@a-dp6:
- {bat-mtlp-9}: [DMESG-WARN][12] ([i915#10435]) -> [PASS][13] +1
other test pass
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14784/bat-mtlp-9/igt@kms_flip@basic-plain-f...@a-dp6.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/bat-mtlp-9/igt@kms_flip@basic-plain-f...@a-dp6.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-mtlp-9}: [DMESG-WARN][14] ([i915#10435] / [i915#9157]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14784/bat-mtlp-9/igt@kms_frontbuffer_track...@basic.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133800v1/bat-mtlp-9/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
[i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#10435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10435
[i915#10436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10436
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157
[i915#9500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9500
Build changes
-
* Linux: CI_DRM_14784 -> Patchwork_133800v1
CI-20190529: 20190529
CI_DRM_14784: 5e9e7440f7d7efd64079148c738fc83600fb477b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7861: 7861
Patchwork_133800v1: 5e9e7440f7d7efd64079148c738fc83600fb477b @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-t
Re: [PATCH] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Bspec lists the mas TMDS bitrate as 6 Gbps on ADL/DG2. *max There's also ADL-S with display 12 and 6 Gbps support? BR, Jani. > Bump our limit to match. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c > b/drivers/gpu/drm/i915/display/intel_hdmi.c > index 0faf2afa1c09..bd0ba4edcd1d 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -1784,7 +1784,9 @@ static int intel_hdmi_source_max_tmds_clock(struct > intel_encoder *encoder) > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > int max_tmds_clock, vbt_max_tmds_clock; > > - if (DISPLAY_VER(dev_priv) >= 10) > + if (DISPLAY_VER(dev_priv) >= 13) > + max_tmds_clock = 60; > + else if (DISPLAY_VER(dev_priv) >= 10) > max_tmds_clock = 594000; > else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) > max_tmds_clock = 30; -- Jani Nikula, Intel
✗ Fi.CI.CHECKPATCH: warning for Ultrajoiner basic functionality series
== Series Details ==
Series: Ultrajoiner basic functionality series
URL : https://patchwork.freedesktop.org/series/133800/
State : warning
== Summary ==
Error: dim checkpatch failed
f1c5de795401 drm/i915: Rename all bigjoiner to joiner
-:200: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#200: FILE: drivers/gpu/drm/i915/display/intel_display.c:2320:
+static void intel_joiner_adjust_timings(const struct intel_crtc_state
*crtc_state,
struct drm_display_mode *mode)
-:299: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#299: FILE: drivers/gpu/drm/i915/display/intel_display.c:3496:
+static void enabled_joiner_pipes(struct drm_i915_private *dev_priv,
u8 *master_pipes, u8 *slave_pipes)
-:415: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#415: FILE: drivers/gpu/drm/i915/display/intel_display.c:4501:
+copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state,
struct intel_crtc *slave_crtc)
-:424: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#424: FILE: drivers/gpu/drm/i915/display/intel_display.c:4521:
+copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
struct intel_crtc *slave_crtc)
-:471: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#471: FILE: drivers/gpu/drm/i915/display/intel_display.c:5735:
+static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state,
struct intel_crtc *crtc,
-:514: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#514: FILE: drivers/gpu/drm/i915/display/intel_display.c:5891:
+static int intel_atomic_check_joiner(struct intel_atomic_state *state,
struct intel_crtc *master_crtc)
-:577: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#577: FILE: drivers/gpu/drm/i915/display/intel_display.c:5962:
+static void kill_joiner_slave(struct intel_atomic_state *state,
struct intel_crtc *master_crtc)
-:971: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#971: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1211:
+bool intel_dp_need_joiner(struct intel_dp *intel_dp,
struct intel_connector *connector,
-:1001: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1001: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1259:
+ if (intel_dp_need_joiner(intel_dp, connector,
mode->hdisplay, target_clock)) {
-:1073: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1073: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2436:
+ if (intel_dp_need_joiner(intel_dp, connector,
adjusted_mode->crtc_hdisplay,
-:1122: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1122: FILE: drivers/gpu/drm/i915/display/intel_dp.h:154:
+bool intel_dp_need_joiner(struct intel_dp *intel_dp,
struct intel_connector *connector,
-:1144: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1144: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:571:
+ if (intel_dp_need_joiner(intel_dp, connector,
adjusted_mode->crtc_hdisplay,
-:1173: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1173: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:1422:
+ if (intel_dp_need_joiner(intel_dp, intel_connector,
mode->hdisplay, target_clock)) {
-:1313: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1313: FILE: drivers/gpu/drm/i915/display/intel_modeset_setup.c:278:
+ joiner_slaves_mask = get_joiner_slave_pipes(i915,
portsync_master_mask |
-:1372: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#1372: FILE: drivers/gpu/drm/i915/display/intel_modeset_setup.c:739:
+
intel_crtc_joiner_slave_pipes(crtc_state)) {
total: 0 errors, 1 warnings, 14 checks, 1283 lines checked
8e8e3298a19d drm/i915: Implement basic functions for ultrajoiner support
c30500d06cf7 drm/i915: Implement hw state readout for ultrajoiner
-:9: WARNING:BAD_SIGN_OFF: 'Signed-off-by:' is the preferred signature form
#9:
SIgned-off-by: Stanislav Lisovskiy
-:48: CHECK:LINE_SPACING: Please don't use multiple blank lines
#48: FILE: drivers/gpu/drm/i915/display/intel_display.c:3577:
+
+
-:71: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#71: FILE: drivers/gpu/drm/i915/display/intel_display.c:3616:
+ return fls(master_pipes) - 1;
+ } else {
total: 0 errors, 2 warnings, 1 checks, 130 lines c
Re: [PATCH 2/2] drm/i915/hdcp: Check mst_port to determine connector type
On Mon, May 20, 2024 at 06:58:19AM +0300, Kandpal, Suraj wrote: > > > > -Original Message- > > From: Deak, Imre > > Sent: Friday, May 17, 2024 6:19 PM > > To: Kandpal, Suraj > > Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar > > ; Shankar, Uma > > ; Nautiyal, Ankit K > > Subject: Re: [PATCH 2/2] drm/i915/hdcp: Check mst_port to determine > > connector type > > > > On Tue, May 07, 2024 at 09:20:37AM +0530, Suraj Kandpal wrote: > > > Check mst_port field in intel_connector to check connector type rather > > > than rely on encoder as it may not be attached to connector at times. > > > > > > Signed-off-by: Suraj Kandpal > > > --- > > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > > b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > > index 551c862ed7a6..2edffe62f360 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > > @@ -693,7 +693,7 @@ int intel_dp_hdcp_get_remote_capability(struct > > > intel_connector *connector, > > > > > > *hdcp_capable = false; > > > *hdcp2_capable = false; > > > - if (!intel_encoder_is_mst(connector->encoder)) > > > + if (!connector->mst_port) > > > > I suppose this fixes > > https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10898 > > > > Could you add the Closes: line for it? > > > > Sure Imre will add that. > > > Can this function be called for anything else than an MST connector? > > > > Afaics it's only called from > > > > intel_connector_info() -> > > intel_hdcp_info(..., remote_req = true) > > > > only for MST connectors, which makes sense since only MST connectors would > > have remote caps. In that case it would be enough to simply remove the > > encoder check which leads to the NULL deref in case the output is disabled. > > Right this function is not invoked from anywhere but hdcp_info() since > this was Created just to have a sense of the actual HDCP capability of > remote monitor rather than having to display the first monitor's HDCP > capability and repeating it for the second monitor specially when in > daisy chain setup. I meant that it's strange to check connector->mst_port in intel_connector_info() and then check the same condition again in the above function, which is always true and thus redundant. In any case the change does fix the issue, so on the patchset: Reviewed-by: Imre Deak > Regards, > Suraj Kandpal > > > > return -EINVAL; > > > > > > aux = &connector->port->aux; > > > -- > > > 2.43.2 > > >
Re: [PATCH 1/5] drm/i915: Rename all bigjoiner to joiner
On Mon, 20 May 2024, Stanislav Lisovskiy wrote:
> Lets unify both bigjoiner and ultrajoiner under simple "joiner" name,
> because in future we might have multiple configurations, involving
> multiple bigjoiners, ultrajoiner, however it is possible to use
> same api for handling both.
If you're doing a big rename, might as well do the master/slave ->
primary/secondary rename too.
BR,
Jani.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 4 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c| 8 +-
> .../drm/i915/display/intel_crtc_state_dump.c | 8 +-
> drivers/gpu/drm/i915/display/intel_cursor.c | 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_display.c | 204 +-
> drivers/gpu/drm/i915/display/intel_display.h | 8 +-
> .../drm/i915/display/intel_display_debugfs.c | 10 +-
> .../drm/i915/display/intel_display_types.h| 4 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 60 +++---
> drivers/gpu/drm/i915/display/intel_dp.h | 8 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +-
> drivers/gpu/drm/i915/display/intel_drrs.c | 6 +-
> .../drm/i915/display/intel_modeset_setup.c| 38 ++--
> drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +-
> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
> .../drm/i915/display/skl_universal_plane.c| 4 +-
> 19 files changed, 207 insertions(+), 207 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 27224ecdc94c..7a0b2f3a672e 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -335,7 +335,7 @@ void intel_plane_copy_uapi_to_hw_state(struct
> intel_plane_state *plane_state,
> intel_plane_clear_hw_state(plane_state);
>
> /*
> - * For the bigjoiner slave uapi.crtc will point at
> + * For the joiner slave uapi.crtc will point at
>* the master crtc. So we explicitly assign the right
>* slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
>* the plane is logically enabled on the uapi level.
> @@ -720,7 +720,7 @@ int intel_plane_atomic_check(struct intel_atomic_state
> *state,
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
> + if (new_crtc_state && intel_crtc_is_joiner_slave(new_crtc_state)) {
> struct intel_crtc *master_crtc =
> intel_master_crtc(new_crtc_state);
> struct intel_plane *master_plane =
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index b78154c82a71..36fb7ad1d871 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2731,7 +2731,7 @@ static int intel_vdsc_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> min_cdclk = max_t(int, min_cdclk,
> DIV_ROUND_UP(crtc_state->pixel_rate,
> num_vdsc_instances));
>
> - if (crtc_state->bigjoiner_pipes) {
> + if (crtc_state->joiner_pipes) {
> int pixel_clock =
> intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
>
> /*
> @@ -2743,13 +2743,13 @@ static int intel_vdsc_min_cdclk(const struct
> intel_crtc_state *crtc_state)
>*
>* => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner
> Interface bits)
>*
> - * Since PPC = 2 with bigjoiner
> + * Since PPC = 2 with joiner
>* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner
> Interface bits
>*/
> - int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 :
> 24;
> + int joiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
> int min_cdclk_bj =
> (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16)
> *
> - pixel_clock) / (2 * bigjoiner_interface_bits);
> + pixel_clock) / (2 * joiner_interface_bits);
>
> min_cdclk = max(min_cdclk, min_cdclk_bj);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index ccaa4cb2809b..a999c37293bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -222,10 +222,10 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> transcoder_name(pipe_config->master_transcoder),
>
✗ Fi.CI.BAT: failure for Fixes in hdcp remote capability (rev3)
== Series Details ==
Series: Fixes in hdcp remote capability (rev3)
URL : https://patchwork.freedesktop.org/series/133047/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14784 -> Patchwork_133047v3
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_133047v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133047v3, please notify your bug team
(i915-ci-in...@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/index.html
Participating hosts (40 -> 38)
--
Additional (2): fi-kbl-7567u bat-jsl-3
Missing(4): bat-dg2-11 fi-cfl-8109u fi-snb-2520m bat-adlp-6
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_133047v3:
### IGT changes ###
Possible regressions
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- bat-arls-1: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14784/bat-arls-1/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-arls-1/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
Known issues
Here are the changes found in Patchwork_133047v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-jsl-3: NOTRUN -> [SKIP][3] ([i915#9318])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-7567u: NOTRUN -> [SKIP][4] ([i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/fi-kbl-7567u/igt@gem_huc_c...@huc-copy.html
- bat-jsl-3: NOTRUN -> [SKIP][5] ([i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-jsl-3/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-jsl-3: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-jsl-3/igt@gem_lmem_swapp...@basic.html
- fi-kbl-7567u: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/fi-kbl-7567u/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@guc_hang:
- bat-arls-3: [PASS][8] -> [DMESG-FAIL][9] ([i915#10262]) +13 other
tests dmesg-fail
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14784/bat-arls-3/igt@i915_selftest@live@guc_hang.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-arls-3/igt@i915_selftest@live@guc_hang.html
* igt@i915_selftest@live@hugepages:
- bat-arls-3: [PASS][10] -> [DMESG-WARN][11] ([i915#10341])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14784/bat-arls-3/igt@i915_selftest@l...@hugepages.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-arls-3/igt@i915_selftest@l...@hugepages.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3: NOTRUN -> [SKIP][12] ([i915#4103]) +1 other test skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-jsl-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-jsl-3: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#9886])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-jsl-3/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-7567u: NOTRUN -> [SKIP][14] +11 other tests skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/fi-kbl-7567u/igt@kms_force_connector_ba...@force-load-detect.html
- bat-jsl-3: NOTRUN -> [SKIP][15]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-jsl-3/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-3: NOTRUN -> [SKIP][16] ([i915#3555])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-jsl-3/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [WARN][17] ([i915#10436]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14784/bat-mtlp-9/igt@i915_pm_...@module-reload.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133047v3/bat-mtlp-9/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@workarounds:
- bat-dg2-9: [DMESG-FAIL][19] ([i915#9500]) -> [PA
Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
On Mon, 2024-05-20 at 12:37 +0300, Jani Nikula wrote:
> On Mon, 20 May 2024, Jani Nikula wrote:
> > On Thu, 16 May 2024, Ville Syrjala
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7
> > > range.
> > > so using _MMIO_TRANS2() for it is not really correct. Also since
> > > this
> > > is a pipe register, and not present on CHV, the registers will be
> > > equally spaced out, so we can use the simpler _MMIO_PIPE()
> > > instead
> > > of _MMIO_PIPE2().
> > >
> > > Signed-off-by: Ville Syrjälä
> >
> > Reviewed-by: Jani Nikula
>
> Side note, while reviewing this I found this monstrosity:
>
> static bool intel_psr2_sel_fetch_config_valid(struct intel_dp
> *intel_dp,
> struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> if (!dev_priv->display.params.enable_psr2_sel_fetch &&
> intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR2 sel fetch not enabled, disabled by
> parameter\n");
> return false;
> }
>
> if (crtc_state->uapi.async_flip) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR2 sel fetch not enabled, async flip
> enabled\n");
> return false;
> }
>
> return crtc_state->enable_psr2_sel_fetch = true;
>
> }
>
> Judging by name, a predicate function to check if config is valid,
> actually modifies the config in what looks like a typoed return
> statement. Ugh.
Yes, I have inhaled this already enough that it begun to look like
normal.
BR,
Jouni Högander
>
> BR,
> Jani.
>
>
Re: [PATCH 05/13] drm/i915: Rename selective fetch plane registers
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Rename the selective fetch plane registers to match the spec. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++-- > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index 47e3a2e2977c..f0bd0a726d7a 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -276,23 +276,23 @@ > _SEL_FETCH_PLANE_BASE_A(plane)) > > #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 > -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > +#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > _SEL_FETCH_PLANE_CTL_1_A - \ > _SEL_FETCH_PLANE_BASE_1_A) > -#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) > +#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) > > #define _SEL_FETCH_PLANE_POS_1_A 0x70894 > -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > +#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > _SEL_FETCH_PLANE_POS_1_A - \ > _SEL_FETCH_PLANE_BASE_1_A) > > #define _SEL_FETCH_PLANE_SIZE_1_A0x70898 > -#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > +#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > _SEL_FETCH_PLANE_SIZE_1_A - \ > _SEL_FETCH_PLANE_BASE_1_A) > > #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C > -#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > +#define SEL_FETCH_PLANE_OFFSET(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > _SEL_FETCH_PLANE_OFFSET_1_A - > \ > _SEL_FETCH_PLANE_BASE_1_A) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index d0bfee2ca643..6601baf18ae4 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -705,7 +705,7 @@ static void icl_plane_disable_sel_fetch_arm(struct > intel_plane *plane, > if (!crtc_state->enable_psr2_sel_fetch) > return; > > - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); > } > > static void > @@ -1304,7 +1304,7 @@ static void icl_plane_update_sel_fetch_noarm(struct > intel_plane *plane, > > val = (clip->y1 + plane_state->uapi.dst.y1) << 16; > val |= plane_state->uapi.dst.x1; > - intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val); > > x = plane_state->view.color_plane[color_plane].x; > > @@ -1319,13 +1319,13 @@ static void icl_plane_update_sel_fetch_noarm(struct > intel_plane *plane, > > val = y << 16 | x; > > - intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > + intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), > val); > > /* Sizes are 0 based */ > val = (drm_rect_height(clip) - 1) << 16; > val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; > - intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val); > } > > static void > @@ -1414,8 +1414,8 @@ static void icl_plane_update_sel_fetch_arm(struct > intel_plane *plane, > return; > > if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) > - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), > - PLANE_SEL_FETCH_CTL_ENABLE); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), > + SEL_FETCH_PLANE_CTL_ENABLE); > else > icl_plane_disable_sel_fetch_arm(plane, crtc_state); > } -- Jani Nikula, Intel
Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
On Mon, 20 May 2024, Jani Nikula wrote:
> On Thu, 16 May 2024, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7 range.
>> so using _MMIO_TRANS2() for it is not really correct. Also since this
>> is a pipe register, and not present on CHV, the registers will be
>> equally spaced out, so we can use the simpler _MMIO_PIPE() instead
>> of _MMIO_PIPE2().
>>
>> Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Jani Nikula
Side note, while reviewing this I found this monstrosity:
static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
if (!dev_priv->display.params.enable_psr2_sel_fetch &&
intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 sel fetch not enabled, disabled by
parameter\n");
return false;
}
if (crtc_state->uapi.async_flip) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 sel fetch not enabled, async flip enabled\n");
return false;
}
return crtc_state->enable_psr2_sel_fetch = true;
}
Judging by name, a predicate function to check if config is valid,
actually modifies the config in what looks like a typoed return
statement. Ugh.
BR,
Jani.
--
Jani Nikula, Intel
