[Intel-gfx] [PATCH 2/2] drm/i915/icl: implement icl_digital_port_connected()
From: Paulo Zanoni
Do like the other functions and check for the ISR bits. We have plans
to add a few more checks in this code in the next patches, that's why
it's a little more verbose than it could be.
v2:
- Change the register names, to be consistent with
the rest of the platforms.
Cc: Animesh Manna
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 5
drivers/gpu/drm/i915/intel_dp.c | 57 +
2 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e347055..f55e889 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7093,6 +7093,7 @@ enum {
#define GEN11_TC3_HOTPLUG (1 << 18)
#define GEN11_TC2_HOTPLUG (1 << 17)
#define GEN11_TC1_HOTPLUG (1 << 16)
+#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
GEN11_TC3_HOTPLUG | \
GEN11_TC2_HOTPLUG | \
@@ -7101,6 +7102,7 @@ enum {
#define GEN11_TBT3_HOTPLUG(1 << 2)
#define GEN11_TBT2_HOTPLUG(1 << 1)
#define GEN11_TBT1_HOTPLUG(1 << 0)
+#define GEN11_TBT_HOTPLUG(tc_port)(1 << (tc_port))
#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
GEN11_TBT3_HOTPLUG | \
GEN11_TBT2_HOTPLUG | \
@@ -7525,6 +7527,9 @@ enum {
#define SDE_GMBUS_ICP(1 << 23)
#define SDE_DDIB_HOTPLUG_ICP (1 << 17)
#define SDE_DDIA_HOTPLUG_ICP (1 << 16)
+#define SDE_TC_HOTPLUG_ICP(tc_port)(1 << ((tc_port) + 24))
+#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
+
#define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \
SDE_DDIA_HOTPLUG_ICP)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6ac6c87..cc6c190 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4750,6 +4750,61 @@ static bool bxt_digital_port_connected(struct
intel_encoder *encoder)
return I915_READ(GEN8_DE_PORT_ISR) & bit;
}
+static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
+struct intel_digital_port *intel_dig_port)
+{
+ enum port port = intel_dig_port->base.port;
+
+ return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
+}
+
+static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *intel_dig_port)
+{
+ enum port port = intel_dig_port->base.port;
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ u32 legacy_bit = ICP_TC_HOTPLUG(tc_port);
+ u32 typec_bit = GEN11_TC_HOTPLUG(tc_port);
+ u32 tbt_bit = GEN11_TBT_HOTPLUG(tc_port);
+ bool is_legacy = false, is_typec = false, is_tbt = false;
+ u32 cpu_isr;
+
+ if (I915_READ(SDEISR) & legacy_bit)
+ is_legacy = true;
+
+ cpu_isr = I915_READ(GEN11_DE_HPD_ISR);
+ if (cpu_isr & typec_bit)
+ is_typec = true;
+ if (cpu_isr & tbt_bit)
+ is_tbt = true;
+
+ WARN_ON(is_legacy + is_typec + is_tbt > 1);
+ if (!is_legacy && !is_typec && !is_tbt)
+ return false;
+
+ return true;
+}
+
+static bool icl_digital_port_connected(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(>base);
+
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
+ case HPD_PORT_B:
+ return icl_combo_port_connected(dev_priv, dig_port);
+ case HPD_PORT_C:
+ case HPD_PORT_D:
+ case HPD_PORT_E:
+ case HPD_PORT_F:
+ return icl_tc_port_connected(dev_priv, dig_port);
+ default:
+ MISSING_CASE(encoder->hpd_pin);
+ return false;
+ }
+}
+
/*
* intel_digital_port_connected - is the specified port connected?
* @encoder: intel_encoder
@@ -4777,6 +4832,8 @@ bool intel_digital_port_connected(struct intel_encoder
*encoder)
return bdw_digital_port_connected(encoder);
else if (IS_GEN9_LP(dev_priv))
return bxt_digital_port_connected(encoder);
+ else if (IS_ICELAKE(dev_priv))
+ return icl_digital_port_connected(encoder);
else
ret
[Intel-gfx] [PATCH 3/4] firmware/huc/glk: Load HuC v03.00.2225 for Geminilake.
load the v03.00.2225 huC on geminilake.
v2:
- rebased.
- Load the correct the version. (John Spotswood)
v3:
- rebased.
v4: Change subject subject prefix.(Anusha)
Cc: John Spotswood
Cc: Tomi Sarvela
Cc: Jani Saarinen
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index f93d238..b8efbff 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
+#define GLK_HUC_FW_MAJOR 03
+#define GLK_HUC_FW_MINOR 00
+#define GLK_BLD_NUM 2225
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
+ GLK_HUC_FW_MINOR, GLK_BLD_NUM)
+MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ huc_fw->path = I915_GLK_HUC_UCODE;
+ huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(huc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH 4/4] Enable guc loading for Geminilake.
Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index aebe046..3e4e128 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -47,7 +47,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, -1) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] firmware/dmc/icl: load v1.05 on icelake.
Add Support to load DMC on Icelake.
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index cf9b600..dfc2b7f 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -34,6 +34,9 @@
* low-power state and comes back to normal.
*/
+#define I915_CSR_ICL "i915/icl_dmc_ver1_05.bin"
+#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 5)
+
#define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
MODULE_FIRMWARE(I915_CSR_GLK);
#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
@@ -301,6 +304,8 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
if (csr->fw_path == i915_modparams.dmc_firmware_path) {
/* Bypass version check for firmware override. */
required_version = csr->version;
+ } else if (IS_ICELAKE(dev_priv)) {
+ required_version = ICL_CSR_VERSION_REQUIRED;
} else if (IS_CANNONLAKE(dev_priv)) {
required_version = CNL_CSR_VERSION_REQUIRED;
} else if (IS_GEMINILAKE(dev_priv)) {
@@ -458,6 +463,8 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
if (i915_modparams.dmc_firmware_path)
csr->fw_path = i915_modparams.dmc_firmware_path;
+ else if (IS_ICELAKE(dev_priv))
+ csr->fw_path = I915_CSR_ICL;
else if (IS_CANNONLAKE(dev_priv))
csr->fw_path = I915_CSR_CNL;
else if (IS_GEMINILAKE(dev_priv))
--
2.7.4
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[Intel-gfx] [PATCH 0/4] Geminilake GuC(11.98), HuC(3.0.2225); Icelake DMC v1.05
Resending Geminilake GuC,HuC to trigger new CI runs. Adding Icelake DMC Support. The following changes since commit d1147327232ec4616a66ab898df84f9700c816c1: Merge branch 'for-upstreaming-v1.7.2-vsw' of https://github.com/felix-cavium/linux-firmware (2018-06-06 13:23:36 -0400) are available in the git repository at: git://anongit.freedesktop.org/drm/drm-firmware master for you to fetch changes up to 57ffda274ed80b057f6d1e2a84a9a866b2d52b7d: firmware/icl/dmc: Add DMC v1.05 for Icelake. (2018-06-19 14:53:21 -0700) Anusha Srivatsa (14): linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678 Revert "linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678" Revert "linux-firmware/i915: GuC firmware for Cannonlake v11.102" Merge remote-tracking branch 'official/master' into drm-firmware linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2719 Merge remote-tracking branch 'official/master' linux-firmware: Add GuC v11.98 for geminilake linux-firmware: Add HuC v3.00.2225 for geminilake Revert "linux-firmware/i915: GuC firmware for Cannonlake v11.102" Revert "linux-firmware/i915: HuC firmware for Cannonlake v9.01.2719" Merge remote-tracking branch 'official/master' Merge remote-tracking branch 'official/master' firmware/icl/dmc: Add DMC v1.05 for Icelake. WHENCE | 9 + i915/glk_guc_ver11_98.bin | Bin 0 -> 154240 bytes i915/glk_huc_ver03_00_2225.bin | Bin 0 -> 220032 bytes i915/icl_dmc_ver1_05.bin | Bin 0 -> 25836 bytes 4 files changed, 9 insertions(+) create mode 100644 i915/glk_guc_ver11_98.bin create mode 100644 i915/glk_huc_ver03_00_2225.bin create mode 100644 i915/icl_dmc_ver1_05.bin Anusha Srivatsa (3): firmware/dmc/icl: load v1.05 on icelake. firmware/huc/glk: Load HuC v03.00.2225 for Geminilake. Enable guc loading for Geminilake. John Spotswood (1): firmware/guc/glk: Load GuC v11.98 for Geminilake. drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_csr.c| 7 +++ drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++ drivers/gpu/drm/i915/intel_huc_fw.c | 12 4 files changed, 30 insertions(+), 1 deletion(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] firmware/guc/glk: Load GuC v11.98 for Geminilake.
From: John Spotswood
load the v11.98 guC on geminilake.
v2: rebased.
v3: Change subject prefix. (Anusha)
Cc: Tomi Sarvela
Cc: Jani Saarinen
Signed-off-by: Anusha Srivatsa
Signed-off-by: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index a9e6fcc..29b1d92 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -39,6 +39,9 @@
#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 39
+#define GLK_FW_MAJOR 11
+#define GLK_FW_MINOR 98
+
#define GUC_FW_PATH(platform, major, minor) \
"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
@@ -51,6 +54,9 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
+MODULE_FIRMWARE(I915_GLK_GUC_UCODE);
+
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -77,6 +83,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = I915_KBL_GUC_UCODE;
guc_fw->major_ver_wanted = KBL_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ guc_fw->path = I915_GLK_GUC_UCODE;
+ guc_fw->major_ver_wanted = GLK_FW_MAJOR;
+ guc_fw->minor_ver_wanted = GLK_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(guc_fw->type));
--
2.7.4
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Re: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
>-Original Message-
>From: Zanoni, Paulo R
>Sent: Wednesday, June 13, 2018 2:19 PM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL
>registers
>
>Em Sex, 2018-06-08 às 13:19 -0700, Srivatsa, Anusha escreveu:
>> > -Original Message-
>> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
>> > Behalf Of Paulo Zanoni
>> > Sent: Monday, May 21, 2018 5:26 PM
>> > To: intel-gfx@lists.freedesktop.org
>> > Cc: Zanoni, Paulo R
>> > Subject: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL
>> > registers
>> >
>> > Use the hardcoded tables provided by our spec.
>> >
>> > Signed-off-by: Paulo Zanoni
>> > ---
>> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 25
>> > -
>> > 1 file changed, 24 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> > index 72f15e727d07..8a34733de1ea 100644
>> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> > @@ -2452,6 +2452,16 @@ static const struct skl_wrpll_params
>> > icl_dp_combo_pll_19_2MHz_values[] = {
>> > .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
>> > };
>> >
>> > +static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
>> > + .dco_integer = 0x151, .dco_fraction = 0x4000,
>> > + .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0,
>> > .qdiv_ratio = 0, };
>> > +
>> > +static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values =
>> > {
>> > + .dco_integer = 0x1A5, .dco_fraction = 0x7000,
>> > + .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0,
>> > .qdiv_ratio = 0, };
>> > +
>> > static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv,
>> > int clock,
>> > struct skl_wrpll_params
>> > *pll_params) { @@ -
>> > 2494,6 +2504,14 @@ static bool icl_calc_dp_combo_pll(struct
>> > drm_i915_private *dev_priv, int clock,
>> >return true;
>> > }
>> >
>> > +static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv,
>> > int clock,
>> > + struct skl_wrpll_params *pll_params)
>> > {
>> > + *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
>> > + icl_tbt_pll_24MHz_values :
>> > icl_tbt_pll_19_2MHz_values;
>> > + return true;
>> > +}
>> > +
>> > static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
>> >struct intel_encoder *encoder, int clock,
>> >struct intel_dpll_hw_state *pll_state) @@ -
>> > 2501,9 +2519,12 @@ static bool icl_calc_dpll_state(struct
>> > intel_crtc_state *crtc_state,
>> >struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> >uint32_t cfgcr0, cfgcr1;
>> >struct skl_wrpll_params pll_params = { 0 };
>> > + bool is_tbt = encoder->port >= PORT_C;
>> >bool ret;
>> >
>> > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>> > + if (is_tbt)
>> > + ret = icl_calc_tbt_pll(dev_priv, clock,
>> > _params);
>> > + else if (intel_crtc_has_type(crtc_state,
>> > INTEL_OUTPUT_HDMI))
>> >ret = cnl_ddi_calculate_wrpll(clock, dev_priv,
>> > _params);
>> >else
>> >ret = icl_calc_dp_combo_pll(dev_priv, clock,
>> > _params); @@ -
>> > 2513,6 +2534,8 @@ static bool icl_calc_dpll_state(struct
>> > intel_crtc_state
>> > *crtc_state,
>> >
>> > cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
>> > pll_params.dco_integer;
>> > + if (is_tbt)
>> > + cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
>>
>> Paulo,
>> TBT has some TBT specific CFGCR0 registers which needs to be
>> configured here.
>
>I did recheck the spec and it says to disable SSC, so the line above is
>clearly wrong (did it change since I wrote it?), but I don't see
>anything we're failing to set on CFGCR0. Can you please clarify what
>you think is missing? Maybe you're referring to something that's on
>patch 14?
Sorry, my mistake. The cfgcro0 registers are being configured here. But yes,
like you pointed out, the TBT cfgcr0 register has to be configured by
disabling the DDC and enabling dco frequency.
Anusha
>Thanks,
>Paulo
>
>>
>> Anusha
>> >cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
>> > DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
>> > --
>> > 2.14.3
>> >
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>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support
On Wed, Jun 13, 2018 at 07:21:54PM -0700, Dhinakaran Pandiyan wrote:
> On Wed, 2018-06-13 at 15:23 -0700, Lucas De Marchi wrote:
> > On Tue, May 29, 2018 at 05:04:58PM -0700, Lucas De Marchi wrote:
> > >
> > > On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> > > >
> > > > On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan
> > > > wrote:
> > > > >
> > > > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > > >
> > > > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > > > >
> > > > > > >
> > > > > > > From: Anusha Srivatsa
> > > > > > >
> > > > > > > This patch addresses Interrupts from south display engine
> > > > > > > (SDE).
> > > > > > >
> > > > > > > ICP has two registers - SHOTPLUG_CTL_DDI and
> > > > > > > SHOTPLUG_CTL_TC.
> > > > > > > Introduce these registers and their intended values.
> > > > > > >
> > > > > > > Introduce icp_irq_handler().
> > > > > > >
> > > > > > > Cc: Paulo Zanoni
> > > > > > > Cc: Dhinakaran Pandiyan
> > > > > > > Cc: Ville Syrjala
> > > > > > > Signed-off-by: Anusha Srivatsa
> > > > > > > [Paulo: coding style bikesheds and rebases].
> > > > > > > Signed-off-by: Paulo Zanoni
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > > > > +++-
> > > > > > > drivers/gpu/drm/i915/i915_reg.h | 40
> > > > > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > @@ -122,6 +122,15 @@ static const u32
> > > > > > > hpd_tc_gen11[HPD_NUM_PINS] =
> > > > > > > {
> > > > > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > > > > };
> > > > > > >
> > > > > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > > > > +};
> > > > > > > +
> > > > > > > /* IIR can theoretically queue up two events. Be paranoid.
> > > > > > > */
> > > > > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > > > > I915_WRITE(GEN8_##type##_IMR(which), 0x);
> > > > > > > \
> > > > > > > @@ -1586,6 +1595,34 @@ static bool
> > > > > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > > > > }
> > > > > > > }
> > > > > > >
> > > > > > > +static bool icp_ddi_port_hotplug_long_detect(enum port
> > > > > > > port, u32
> > > > > > > val)
> > > > > > > +{
> > > > > > > + switch (port) {
> > > > > > > + case PORT_A:
> > > > > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > > > > + case PORT_B:
> > > > > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > > > > + default:
> > > > > > > + return false;
> > > > > > > + }
> > > > > > > +}
> > > > > > > +
> > > > > > > +static bool icp_tc_port_hotplug_long_detect(enum port
> > > > > > > port, u32
> > > > > > > val)
> > > > > > > +{
> >
Re: [Intel-gfx] [RFC PATCH] drm/i915/guc: New interface files for GuC starting in Gen11
>-Original Message-
>From: Mateo Lozano, Oscar
>Sent: Wednesday, June 13, 2018 3:08 PM
>To: Wajdeczko, Michal ; intel-
>g...@lists.freedesktop.org
>Cc: Joonas Lahtinen ; Rogovin, Kevin
>; Spotswood, John A ;
>Srivatsa, Anusha ; Ceraolo Spurio, Daniele
>; Thierry, Michel ;
>Chris Wilson ; Winiarski, Michal
>; Lis, Tomasz ; Ewins, Jon
>; Sundaresan, Sujaritha
>; Patel, Jalpa ; Li,
>Yaodong
>Subject: Re: [RFC PATCH] drm/i915/guc: New interface files for GuC starting in
>Gen11
>
>
>
>On 5/29/2018 7:59 AM, Michal Wajdeczko wrote:
>> Hi,
>>
>> On Fri, 25 May 2018 23:59:35 +0200, Oscar Mateo
>> wrote:
>>
>>> GuC interface has been redesigned (or cleaned up, rather) starting
>>> with Gen11, as a stepping stone towards a new branching strategy
>>> that helps maintain backwards compatibility with previous Gens, as
>>> well as sideward compatibility with other OSes.
>>>
>>> The interface is split in two header files: one for the KMD and one
>>> for clients of the GuC (which, in our case, happens to be the KMD
>>> as well). SLPC interface files will come at a later date.
>>>
>>> Could we get eyes on the new interface header files, to make sure the
>>> GuC team is moving in the right direction?
>>>
>>> Signed-off-by: Oscar Mateo
>>> Cc: Joonas Lahtinen
>>> Cc: Kevin Rogovin
>>> Cc: John A Spotswood
>>> Cc: Anusha Srivatsa
>>> Cc: Daniele Ceraolo Spurio
>>> Cc: Michal Wajdeczko
>>> Cc: Michel Thierry
>>> Cc: Chris Wilson
>>> Cc: Michał Winiarski
>>> Cc: Tomasz Lis
>>> Cc: Jon Ewins
>>> Cc: Sujaritha Sundaresan
>>> Cc: Jalpa Patel
>>> Cc: Jackie Li
>>> ---
>>> drivers/gpu/drm/i915/intel_guc_client_interface.h | 255 +++
>>> drivers/gpu/drm/i915/intel_guc_kmd_interface.h | 847
>>> ++
>>> 2 files changed, 1102 insertions(+)
>>> create mode 100644 drivers/gpu/drm/i915/intel_guc_client_interface.h
>>> create mode 100644 drivers/gpu/drm/i915/intel_guc_kmd_interface.h
>>
>> can we name these files as:
>>
>> drivers/gpu/drm/i915/intel_guc_interface.h
>> drivers/gpu/drm/i915/intel_guc_interface_client.h
>> or
>> drivers/gpu/drm/i915/intel_guc_defs.h
>> drivers/gpu/drm/i915/intel_guc_defs_client.h
>> or
>> drivers/gpu/drm/i915/guc/guc.h
>> drivers/gpu/drm/i915/guc/guc_client.h
>
>I'm fine with any of these names.
>
>>
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_guc_client_interface.h
>>> b/drivers/gpu/drm/i915/intel_guc_client_interface.h
>>> new file mode 100644
>>> index 000..1ef91a7
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_guc_client_interface.h
>>> @@ -0,0 +1,255 @@
>>> +/*
>>> + * SPDX-License-Identifier: MIT
>>> + *
>>> + * Copyright © 2018 Intel Corporation
>>> + */
>>> +
>>> +#ifndef _INTEL_GUC_CLIENT_INTERFACE_H_
>>> +#define _INTEL_GUC_CLIENT_INTERFACE_H_
>>> +
>>
>> need to include types.h for u32
>
>Will do.
>
>>
>>> +#pragma pack(1)
>>> +
>>>
>+/
>*
>>>
>>> + ** Engines
>>> **
>>> +
>>>
>**
>***/
>>
>> no fancy markups, please
>>
>
>Ok.
>
>>> +
>>> +#define GUC_MAX_ENGINE_INSTANCE_PER_CLASS 4
>>> +#define GUC_MAX_SCHEDULABLE_ENGINE_CLASS 5
>>> +#define GUC_MAX_ENGINE_CLASS_COUNT 6
>>> +#define GUC_ENGINE_INVALID 6
>>
>> hmm, why not 7 or 127 ?
>> maybe if we need value for INVALID we should use 0 or -1 (~0)
>
>I'll pass this comment to the GuC team.
>
>>
>>> +
>>> +/* Engine Class that uKernel can schedule on. This is just a SW
>>> enumeration.
>>> + * HW configuration will depend on the Platform and SKU
>>> + */
>>> +enum uk_engine_class {
>>
>> why there is new prefix "uk" ?
>
>uk stands for uKernel. In this case, I'm guessing it is used to
>differentiate between the engine class defined by hardware vs. the one
>defined by the uKernel.
>>
>>> + UK_RENDER_ENGINE_CLASS = 0,
>>> + UK_VDECENC_ENGINE_CLASS = 1,
>>> + UK_VE_ENG
Re: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Paulo Zanoni
>Sent: Monday, May 21, 2018 5:26 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Zanoni, Paulo R
>Subject: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
>
>Use the hardcoded tables provided by our spec.
>
>Signed-off-by: Paulo Zanoni
>---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 -
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>index 72f15e727d07..8a34733de1ea 100644
>--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>@@ -2452,6 +2452,16 @@ static const struct skl_wrpll_params
>icl_dp_combo_pll_19_2MHz_values[] = {
> .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, };
>
>+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
>+ .dco_integer = 0x151, .dco_fraction = 0x4000,
>+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, };
>+
>+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
>+ .dco_integer = 0x1A5, .dco_fraction = 0x7000,
>+ .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, };
>+
> static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int
> clock,
> struct skl_wrpll_params *pll_params) { @@ -
>2494,6 +2504,14 @@ static bool icl_calc_dp_combo_pll(struct drm_i915_private
>*dev_priv, int clock,
> return true;
> }
>
>+static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,
>+ struct skl_wrpll_params *pll_params) {
>+ *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
>+ icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
>+ return true;
>+}
>+
> static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder, int clock,
> struct intel_dpll_hw_state *pll_state) @@ -
>2501,9 +2519,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
>*crtc_state,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> uint32_t cfgcr0, cfgcr1;
> struct skl_wrpll_params pll_params = { 0 };
>+ bool is_tbt = encoder->port >= PORT_C;
> bool ret;
>
>- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>+ if (is_tbt)
>+ ret = icl_calc_tbt_pll(dev_priv, clock, _params);
>+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> ret = cnl_ddi_calculate_wrpll(clock, dev_priv, _params);
> else
> ret = icl_calc_dp_combo_pll(dev_priv, clock, _params); @@ -
>2513,6 +2534,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
>*crtc_state,
>
> cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
>pll_params.dco_integer;
>+ if (is_tbt)
>+ cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
Paulo,
TBT has some TBT specific CFGCR0 registers which needs to be configured here.
Anusha
> cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
>DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
>--
>2.14.3
>
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>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
>-Original Message-
>From: Navare, Manasi D
>Sent: Wednesday, May 23, 2018 9:47 AM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Zanoni, Paulo R
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/icl: Add remaining registers and
>bitfields for MG PHY DDI
>
>On Tue, May 22, 2018 at 11:04:57PM -0700, Srivatsa, Anusha wrote:
>>
>>
>> >-Original Message-
>> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
>> >Behalf Of Manasi Navare
>> >Sent: Tuesday, May 15, 2018 5:53 PM
>> >To: intel-gfx@lists.freedesktop.org
>> >Cc: Zanoni, Paulo R
>> >Subject: [Intel-gfx] [PATCH] drm/i915/icl: Add remaining registers
>> >and bitfields for MG PHY DDI
>> >
>> >This patch adds the remaining register definitions and bit fields
>> >required for MG PHy DDI buffer initializations and voltage swing
>> >programming for MG PHy DDI ports.
>> >
>> >While at it this patch also fixes the naming for previously defined
>> >MG PHY registers in original commit id (c92f47b5ec977a "drm/i915/icl:
>> >Add register defs for voltage swing sequences for MG PHY DDI").
>> >Since the MG PHY registers are first defined in ICL platform, there
>> >is no need for _ICL prefix.
>> >
>> >Signed-off-by: Manasi Navare
>> >Cc: Paulo Zanoni
>> >Cc: James Ausmus
>> >---
>> > drivers/gpu/drm/i915/i915_reg.h | 243
>> >+++
>> >-
>> > 1 file changed, 142 insertions(+), 101 deletions(-)
>> >
>> >diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> >b/drivers/gpu/drm/i915/i915_reg.h index f11bb21..a93b796 100644
>> >--- a/drivers/gpu/drm/i915/i915_reg.h
>> >+++ b/drivers/gpu/drm/i915/i915_reg.h
>> >@@ -1827,121 +1827,162 @@ enum i915_power_well_id {
>> > #define N_SCALAR(x) ((x) << 24)
>> > #define N_SCALAR_MASK(0x7F << 24)
>> >
>> >-#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
>> >+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
>> >_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) -
>> > (ln0p1)))
>> >
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT10x16812C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT10x16852C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT20x16912C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT20x16952C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT30x16A12C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT30x16A52C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT40x16B12C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT40x16B52C
>> >-#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
>> >- _ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
>> >-
>> >_ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
>> >-
>> >_ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>> >-
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT10x1680AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT10x1684AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT20x1690AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT20x1694AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT30x16A0AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT30x16A4AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT40x16B0AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT40x16B4AC
>> >-#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
>> >- _ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
>> >-
>> >_ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
>> >-
>> >_ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
>> >+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
>> >+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
>> >+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
>> >+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
>> >+#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
>> >+#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
>> >+#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
>> >+#define _MG_TX_LINK_PARAMS_TX1LN1_PORT40x16B52C
>> >+#defi
[Intel-gfx] [PATCH 2/3] drm/i915/huc: Load HuC v03.00.2225 for Geminilake.
load the v03.00.2225 huC on geminilake.
v2:
- rebased.
- Load the correct the version. (John Spotswood)
v3:
- rebased.
Cc: John Spotswood <john.a.spotsw...@intel.com>
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index f93d238..b8efbff 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
+#define GLK_HUC_FW_MAJOR 03
+#define GLK_HUC_FW_MINOR 00
+#define GLK_BLD_NUM 2225
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
+ GLK_HUC_FW_MINOR, GLK_BLD_NUM)
+MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ huc_fw->path = I915_GLK_HUC_UCODE;
+ huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(huc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH 3/3] Enable guc loading for Geminilake.
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index aebe046..3e4e128 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -47,7 +47,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, -1) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/3] Load Guc and huC on Geminilake
The following changes since commit 2a9b2cf50fb32e36e4fc1586c2f6f1421913b553: Merge branch 'for-upstreaming-v1.7.2' of https://github.com/felix-cavium/linux-firmware (2018-05-18 08:35:22 -0400) are available in the git repository at: git://anongit.freedesktop.org/drm/drm-firmware master for you to fetch changes up to e2d61f2778f808d4c4ad1b860e0ad8fe871eccc3: Merge remote-tracking branch 'official/master' (2018-05-22 21:57:10 -0700) Anusha Srivatsa (12): linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678 Revert "linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678" Revert "linux-firmware/i915: GuC firmware for Cannonlake v11.102" Merge remote-tracking branch 'official/master' into drm-firmware linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2719 Merge remote-tracking branch 'official/master' linux-firmware: Add GuC v11.98 for geminilake linux-firmware: Add HuC v3.00.2225 for geminilake Revert "linux-firmware/i915: GuC firmware for Cannonlake v11.102" Revert "linux-firmware/i915: HuC firmware for Cannonlake v9.01.2719" Merge remote-tracking branch 'official/master' WHENCE | 7 +++ i915/glk_guc_ver11_98.bin | Bin 0 -> 154240 bytes i915/glk_huc_ver03_00_2225.bin | Bin 0 -> 220032 bytes 3 files changed, 7 insertions(+) create mode 100644 i915/glk_guc_ver11_98.bin create mode 100644 i915/glk_huc_ver03_00_2225.bin Anusha Srivatsa (2): drm/i915/huc: Load HuC v03.00.2225 for Geminilake. Enable guc loading for Geminilake. John Spotswood (1): drm/i915/guc: Load GuC v11.98 for Geminilake. drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++ drivers/gpu/drm/i915/intel_huc_fw.c | 12 3 files changed, 23 insertions(+), 1 deletion(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915/guc: Load GuC v11.98 for Geminilake.
From: John Spotswood <john.a.spotsw...@intel.com>
load the v11.98 guC on geminilake.
v2: rebased.
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
Signed-off-by: John Spotswood <john.a.spotsw...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index a9e6fcc..29b1d92 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -39,6 +39,9 @@
#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 39
+#define GLK_FW_MAJOR 11
+#define GLK_FW_MINOR 98
+
#define GUC_FW_PATH(platform, major, minor) \
"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
@@ -51,6 +54,9 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
+MODULE_FIRMWARE(I915_GLK_GUC_UCODE);
+
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -77,6 +83,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = I915_KBL_GUC_UCODE;
guc_fw->major_ver_wanted = KBL_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ guc_fw->path = I915_GLK_GUC_UCODE;
+ guc_fw->major_ver_wanted = GLK_FW_MAJOR;
+ guc_fw->minor_ver_wanted = GLK_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(guc_fw->type));
--
2.7.4
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Re: [Intel-gfx] [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL
>-Original Message-
>From: Zanoni, Paulo R
>Sent: Monday, May 21, 2018 5:26 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>; Zanoni, Paulo R
><paulo.r.zan...@intel.com>; Srivatsa, Anusha <anusha.sriva...@intel.com>
>Subject: [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL
>
>From: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
>
>ICL has AUX F.
>
>Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
>Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
>Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
>Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
Looks good.
Reviewed-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index f9bc3aaa90d0..2fd92a886789 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -2640,7 +2640,8 @@ gen8_de_irq_handler(struct drm_i915_private
>*dev_priv, u32 master_ctl)
> GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
>
>- if (IS_CNL_WITH_PORT_F(dev_priv))
>+ if (IS_CNL_WITH_PORT_F(dev_priv) ||
>+ INTEL_GEN(dev_priv) >= 11)
> tmp_mask |= CNL_AUX_CHANNEL_F;
>
> if (iir & tmp_mask) {
>@@ -3920,7 +3921,7 @@ static void gen8_de_irq_postinstall(struct
>drm_i915_private *dev_priv)
> de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> }
>
>- if (IS_CNL_WITH_PORT_F(dev_priv))
>+ if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
> de_port_masked |= CNL_AUX_CHANNEL_F;
>
> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>--
>2.14.3
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[Intel-gfx] [PATCH 2/3] drm/i915/huc: Load HuC v03.00.2555 for Geminilake.
load the v03.00.2555 huC on geminilake.
v2:
- rebased.
- Load the correct the version. (John Spotswood)
Cc: John Spotswood <john.a.spotsw...@intel.com>
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index f93d238..ae293f9 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
+#define GLK_HUC_FW_MAJOR 03
+#define GLK_HUC_FW_MINOR 00
+#define GLK_BLD_NUM 2555
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
+ GLK_HUC_FW_MINOR, GLK_BLD_NUM)
+MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ huc_fw->path = I915_GLK_HUC_UCODE;
+ huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(huc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH 0/3] Load Guc and huC on Geminilake
The following changes since commit 2a9b2cf50fb32e36e4fc1586c2f6f1421913b553: Merge branch 'for-upstreaming-v1.7.2' of https://github.com/felix-cavium/linux-firmware (2018-05-18 08:35:22 -0400) are available in the git repository at: git://anongit.freedesktop.org/drm/drm-firmware master for you to fetch changes up to e2d61f2778f808d4c4ad1b860e0ad8fe871eccc3: Merge remote-tracking branch 'official/master' (2018-05-22 21:57:10 -0700) Anusha Srivatsa (12): linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678 Revert "linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678" Revert "linux-firmware/i915: GuC firmware for Cannonlake v11.102" Merge remote-tracking branch 'official/master' into drm-firmware linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2719 Merge remote-tracking branch 'official/master' linux-firmware: Add GuC v11.98 for geminilake linux-firmware: Add HuC v3.00.2225 for geminilake Revert "linux-firmware/i915: GuC firmware for Cannonlake v11.102" Revert "linux-firmware/i915: HuC firmware for Cannonlake v9.01.2719" Merge remote-tracking branch 'official/master' WHENCE | 7 +++ i915/glk_guc_ver11_98.bin | Bin 0 -> 154240 bytes i915/glk_huc_ver03_00_2225.bin | Bin 0 -> 220032 bytes 3 files changed, 7 insertions(+) create mode 100644 i915/glk_guc_ver11_98.bin create mode 100644 i915/glk_huc_ver03_00_2225.bin Anusha Srivatsa (2): drm/i915/huc: Load HuC v03.00.2555 for Geminilake. Enable guc loading for Geminilake. John Spotswood (1): drm/i915/guc: Load GuC v11.98 for Geminilake. drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++ drivers/gpu/drm/i915/intel_huc_fw.c | 12 3 files changed, 23 insertions(+), 1 deletion(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915/guc: Load GuC v11.98 for Geminilake.
From: John Spotswood <john.a.spotsw...@intel.com>
load the v11.98 guC on geminilake.
v2: rebased.
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
Signed-off-by: John Spotswood <john.a.spotsw...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index a9e6fcc..29b1d92 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -39,6 +39,9 @@
#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 39
+#define GLK_FW_MAJOR 11
+#define GLK_FW_MINOR 98
+
#define GUC_FW_PATH(platform, major, minor) \
"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
@@ -51,6 +54,9 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
+MODULE_FIRMWARE(I915_GLK_GUC_UCODE);
+
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -77,6 +83,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = I915_KBL_GUC_UCODE;
guc_fw->major_ver_wanted = KBL_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ guc_fw->path = I915_GLK_GUC_UCODE;
+ guc_fw->major_ver_wanted = GLK_FW_MAJOR;
+ guc_fw->minor_ver_wanted = GLK_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(guc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH 3/3] Enable guc loading for Geminilake.
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index aebe046..3e4e128 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -47,7 +47,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, -1) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Manasi Navare
>Sent: Tuesday, May 15, 2018 5:53 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Zanoni, Paulo R <paulo.r.zan...@intel.com>
>Subject: [Intel-gfx] [PATCH] drm/i915/icl: Add remaining registers and
>bitfields for
>MG PHY DDI
>
>This patch adds the remaining register definitions and bit fields required for
>MG
>PHy DDI buffer initializations and voltage swing programming for MG PHy DDI
>ports.
>
>While at it this patch also fixes the naming for previously defined MG PHY
>registers in original commit id (c92f47b5ec977a "drm/i915/icl:
>Add register defs for voltage swing sequences for MG PHY DDI").
>Since the MG PHY registers are first defined in ICL platform, there is no need
>for
>_ICL prefix.
>
>Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
>Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
>Cc: James Ausmus <james.aus...@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 243 +++
>-
> 1 file changed, 142 insertions(+), 101 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index f11bb21..a93b796 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -1827,121 +1827,162 @@ enum i915_power_well_id {
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
>-#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
>+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
> _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
>
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
>-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
>-#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
>-
>_ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
>-
>_ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>-
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
>-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
>-#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
>- _ICL_MG_PHY_PORT_LN(port, ln,
>_ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
>-
>_ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
>-
>_ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
>+#define MG_TX_LINK_PARAMS_TX1LN0_PORT10x16812C
>+#define MG_TX_LINK_PARAMS_TX1LN1_PORT10x16852C
>+#define MG_TX_LINK_PARAMS_TX1LN0_PORT20x16912C
>+#define MG_TX_LINK_PARAMS_TX1LN1_PORT20x16952C
>+#define MG_TX_LINK_PARAMS_TX1LN0_PORT30x16A12C
>+#define MG_TX_LINK_PARAMS_TX1LN1_PORT30x16A52C
>+#define MG_TX_LINK_PARAMS_TX1LN0_PORT40x16B12C
>+#define _MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
>+#define MG_TX1_LINK_PARAMS(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
>+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
>+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>+
>+#define MG_TX_LINK_PARAMS_TX2LN0_PORT10x1680AC
>+#define MG_TX_LINK_PARAMS_TX2LN1_PORT10x1684AC
>+#define MG_TX_LINK_PARAMS_TX2LN0_PORT20x1690AC
>+#define MG_TX_LINK_PARAMS_TX2LN1_PORT20x1694AC
>+#define MG_TX_LINK_PARAMS_TX2LN0_PORT30x16A0AC
>+#define MG_TX_LINK_PARAMS_TX2LN1_PORT30x16A4AC
>+#define MG_TX_LINK_PARAMS_TX2LN0_PORT40x16B0AC
>+#define MG_TX_LINK_PARAMS_TX2LN1_PORT40x16B4AC
>+#define MG_TX2_LINK_PARAMS(port, ln) \
>+ MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
>+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
>+ MG_TX_LINK_PARAM
Re: [Intel-gfx] [PATCH] drm/i915/firmware: Correct URL for firmware
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Monday, April 30, 2018 5:36 PM
>To: Srivatsa, Anusha <anusha.sriva...@intel.com>
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/i915/firmware: Correct URL for firmware
>
>On Mon, Apr 30, 2018 at 03:59:28PM -0700, Anusha Srivatsa wrote:
>> Replace 01.org URL with upstream linux-firmware repo URL.
>> We no longer release firmware to 01.org.
>> linux-firmware.git is the ultimate place to find the i915 firmwares.
>>
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_uc_fw.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h
>> b/drivers/gpu/drm/i915/intel_uc_fw.h
>> index dc33b12..87910aa 100644
>> --- a/drivers/gpu/drm/i915/intel_uc_fw.h
>> +++ b/drivers/gpu/drm/i915/intel_uc_fw.h
>> @@ -30,7 +30,7 @@ struct drm_i915_private; struct i915_vma;
>>
>> /* Home of GuC, HuC and DMC firmwares */ -#define
>> INTEL_UC_FIRMWARE_URL
>"https://01.org/linuxgraphics/downloads/firmware;
>> +#define INTEL_UC_FIRMWARE_URL
>"https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-
>firmware.git/tree/i915"
>
>this or drm-firmware where we release first before our pull requests are
>accepted
>on linux-firmware.git?
Linux-firmware .git should be where users should refer to. Drm-firmware might
have blobs that might fail in the CI runs and not make it to the upstream repo
at all.
>Either way
>
>Acked-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Thanks for the ack.
>just let me know what you want to do...
I think that we need to have linux-firmware repo here But let me know if
you feel otherwise.
Regards,
Anusha
>>
>> enum intel_uc_fw_status {
>> INTEL_UC_FIRMWARE_FAIL = -1,
>> --
>> 2.7.4
>>
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[Intel-gfx] [PATCH] drm/i915/firmware: Correct URL for firmware
Replace 01.org URL with upstream linux-firmware repo URL.
We no longer release firmware to 01.org.
linux-firmware.git is the ultimate place to find
the i915 firmwares.
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_uc_fw.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h
b/drivers/gpu/drm/i915/intel_uc_fw.h
index dc33b12..87910aa 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -30,7 +30,7 @@ struct drm_i915_private;
struct i915_vma;
/* Home of GuC, HuC and DMC firmwares */
-#define INTEL_UC_FIRMWARE_URL "https://01.org/linuxgraphics/downloads/firmware;
+#define INTEL_UC_FIRMWARE_URL
"https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915;
enum intel_uc_fw_status {
INTEL_UC_FIRMWARE_FAIL = -1,
--
2.7.4
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Re: [Intel-gfx] [PATCH v2 RESEND] drm/i915: add support for specifying DMC firmware override by module param
>-Original Message-
>From: Nikula, Jani
>Sent: Monday, April 30, 2018 3:47 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Srivatsa, Anusha <anusha.sriva...@intel.com>; David Weinehall
><david.weineh...@linux.intel.com>
>Subject: Re: [PATCH v2 RESEND] drm/i915: add support for specifying DMC
>firmware override by module param
>
>On Tue, 24 Apr 2018, Jani Nikula <jani.nik...@intel.com> wrote:
>> Use i915.dmc_firmware_path to override default firmware for the
>> platform and bypassing version checks.
>>
>> v2: add missing param struct member declaration (David)
>>
>> Tested-by: David Weinehall <david.weineh...@linux.intel.com>
>> Reviewed-by: David Weinehall <david.weineh...@linux.intel.com>
>> Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
>> Cc: David Weinehall <david.weineh...@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
Ack-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>So *I* don't need this patch. Please someone tell me this is useful to you,
>and I'll
>merge.
>
>Thanks,
>Jani.
>
>
>> ---
>> drivers/gpu/drm/i915/i915_params.c | 3 +++
>> drivers/gpu/drm/i915/i915_params.h | 1 +
>> drivers/gpu/drm/i915/intel_csr.c | 9 +++--
>> 3 files changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_params.c
>> b/drivers/gpu/drm/i915/i915_params.c
>> index 08108ce5be21..66ea3552c63e 100644
>> --- a/drivers/gpu/drm/i915/i915_params.c
>> +++ b/drivers/gpu/drm/i915/i915_params.c
>> @@ -164,6 +164,9 @@ i915_param_named_unsafe(guc_firmware_path,
>charp,
>> 0400, i915_param_named_unsafe(huc_firmware_path, charp, 0400,
>> "HuC firmware path to use instead of the default one");
>>
>> +i915_param_named_unsafe(dmc_firmware_path, charp, 0400,
>> +"DMC firmware path to use instead of the default one");
>> +
>> i915_param_named_unsafe(enable_dp_mst, bool, 0600,
>> "Enable multi-stream transport (MST) for new DisplayPort sinks.
>> (default: true)");
>>
>> diff --git a/drivers/gpu/drm/i915/i915_params.h
>> b/drivers/gpu/drm/i915/i915_params.h
>> index c96360398072..6684025b7af8 100644
>> --- a/drivers/gpu/drm/i915/i915_params.h
>> +++ b/drivers/gpu/drm/i915/i915_params.h
>> @@ -51,6 +51,7 @@ struct drm_printer;
>> param(int, guc_log_level, -1) \
>> param(char *, guc_firmware_path, NULL) \
>> param(char *, huc_firmware_path, NULL) \
>> +param(char *, dmc_firmware_path, NULL) \
>> param(int, mmio_debug, 0) \
>> param(int, edp_vswing, 0) \
>> param(int, reset, 2) \
>> diff --git a/drivers/gpu/drm/i915/intel_csr.c
>> b/drivers/gpu/drm/i915/intel_csr.c
>> index 41e6c75a7f3c..d81673250d3b 100644
>> --- a/drivers/gpu/drm/i915/intel_csr.c
>> +++ b/drivers/gpu/drm/i915/intel_csr.c
>> @@ -297,7 +297,10 @@ static uint32_t *parse_csr_fw(struct
>> drm_i915_private *dev_priv,
>>
>> csr->version = css_header->version;
>>
>> -if (IS_CANNONLAKE(dev_priv)) {
>> +if (csr->fw_path == i915_modparams.dmc_firmware_path) {
>> +/* Bypass version check for firmware override. */
>> +required_version = csr->version;
>> +} else if (IS_CANNONLAKE(dev_priv)) {
>> required_version = CNL_CSR_VERSION_REQUIRED;
>> } else if (IS_GEMINILAKE(dev_priv)) {
>> required_version = GLK_CSR_VERSION_REQUIRED; @@ -452,7
>+455,9 @@
>> void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>> if (!HAS_CSR(dev_priv))
>> return;
>>
>> -if (IS_CANNONLAKE(dev_priv))
>> +if (i915_modparams.dmc_firmware_path)
>> +csr->fw_path = i915_modparams.dmc_firmware_path;
>> +else if (IS_CANNONLAKE(dev_priv))
>> csr->fw_path = I915_CSR_CNL;
>> else if (IS_GEMINILAKE(dev_priv))
>> csr->fw_path = I915_CSR_GLK;
>
>--
>Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH v2 RESEND] drm/i915: add support for specifying DMC firmware override by module param
>-Original Message-
>From: Nikula, Jani
>Sent: Monday, April 30, 2018 3:47 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Srivatsa, Anusha <anusha.sriva...@intel.com>; David Weinehall
><david.weineh...@linux.intel.com>
>Subject: Re: [PATCH v2 RESEND] drm/i915: add support for specifying DMC
>firmware override by module param
>
>On Tue, 24 Apr 2018, Jani Nikula <jani.nik...@intel.com> wrote:
>> Use i915.dmc_firmware_path to override default firmware for the
>> platform and bypassing version checks.
>>
>> v2: add missing param struct member declaration (David)
>>
>> Tested-by: David Weinehall <david.weineh...@linux.intel.com>
>> Reviewed-by: David Weinehall <david.weineh...@linux.intel.com>
>> Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
>> Cc: David Weinehall <david.weineh...@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
>
>So *I* don't need this patch. Please someone tell me this is useful to you,
>and I'll
>merge.
Jani, we need this patch!. This will be very useful. I am glad it made back to
the ML.
Anusha
>Thanks,
>Jani.
>
>
>> ---
>> drivers/gpu/drm/i915/i915_params.c | 3 +++
>> drivers/gpu/drm/i915/i915_params.h | 1 +
>> drivers/gpu/drm/i915/intel_csr.c | 9 +++--
>> 3 files changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_params.c
>> b/drivers/gpu/drm/i915/i915_params.c
>> index 08108ce5be21..66ea3552c63e 100644
>> --- a/drivers/gpu/drm/i915/i915_params.c
>> +++ b/drivers/gpu/drm/i915/i915_params.c
>> @@ -164,6 +164,9 @@ i915_param_named_unsafe(guc_firmware_path,
>charp,
>> 0400, i915_param_named_unsafe(huc_firmware_path, charp, 0400,
>> "HuC firmware path to use instead of the default one");
>>
>> +i915_param_named_unsafe(dmc_firmware_path, charp, 0400,
>> +"DMC firmware path to use instead of the default one");
>> +
>> i915_param_named_unsafe(enable_dp_mst, bool, 0600,
>> "Enable multi-stream transport (MST) for new DisplayPort sinks.
>> (default: true)");
>>
>> diff --git a/drivers/gpu/drm/i915/i915_params.h
>> b/drivers/gpu/drm/i915/i915_params.h
>> index c96360398072..6684025b7af8 100644
>> --- a/drivers/gpu/drm/i915/i915_params.h
>> +++ b/drivers/gpu/drm/i915/i915_params.h
>> @@ -51,6 +51,7 @@ struct drm_printer;
>> param(int, guc_log_level, -1) \
>> param(char *, guc_firmware_path, NULL) \
>> param(char *, huc_firmware_path, NULL) \
>> +param(char *, dmc_firmware_path, NULL) \
>> param(int, mmio_debug, 0) \
>> param(int, edp_vswing, 0) \
>> param(int, reset, 2) \
>> diff --git a/drivers/gpu/drm/i915/intel_csr.c
>> b/drivers/gpu/drm/i915/intel_csr.c
>> index 41e6c75a7f3c..d81673250d3b 100644
>> --- a/drivers/gpu/drm/i915/intel_csr.c
>> +++ b/drivers/gpu/drm/i915/intel_csr.c
>> @@ -297,7 +297,10 @@ static uint32_t *parse_csr_fw(struct
>> drm_i915_private *dev_priv,
>>
>> csr->version = css_header->version;
>>
>> -if (IS_CANNONLAKE(dev_priv)) {
>> +if (csr->fw_path == i915_modparams.dmc_firmware_path) {
>> +/* Bypass version check for firmware override. */
>> +required_version = csr->version;
>> +} else if (IS_CANNONLAKE(dev_priv)) {
>> required_version = CNL_CSR_VERSION_REQUIRED;
>> } else if (IS_GEMINILAKE(dev_priv)) {
>> required_version = GLK_CSR_VERSION_REQUIRED; @@ -452,7
>+455,9 @@
>> void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>> if (!HAS_CSR(dev_priv))
>> return;
>>
>> -if (IS_CANNONLAKE(dev_priv))
>> +if (i915_modparams.dmc_firmware_path)
>> +csr->fw_path = i915_modparams.dmc_firmware_path;
>> +else if (IS_CANNONLAKE(dev_priv))
>> csr->fw_path = I915_CSR_CNL;
>> else if (IS_GEMINILAKE(dev_priv))
>> csr->fw_path = I915_CSR_GLK;
>
>--
>Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 1/3] drm/i915/guc: Load GuC v11.98 for Geminilake.
From: John Spotswood <john.a.spotsw...@intel.com>
load the v11.98 guC on geminilake.
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
Signed-off-by: John Spotswood <john.a.spotsw...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index a9e6fcc..29b1d92 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -39,6 +39,9 @@
#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 39
+#define GLK_FW_MAJOR 11
+#define GLK_FW_MINOR 98
+
#define GUC_FW_PATH(platform, major, minor) \
"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
@@ -51,6 +54,9 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
+MODULE_FIRMWARE(I915_GLK_GUC_UCODE);
+
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -77,6 +83,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = I915_KBL_GUC_UCODE;
guc_fw->major_ver_wanted = KBL_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ guc_fw->path = I915_GLK_GUC_UCODE;
+ guc_fw->major_ver_wanted = GLK_FW_MAJOR;
+ guc_fw->minor_ver_wanted = GLK_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(guc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH 0/3] GuC, HuC Loading Support for Geminilake
The following changes since commit b562d2f3583f19ecda22b08e514ced57dd1e5f4d: linux-firmware: update wil6210 firmware to 5.2.0.18 (2018-04-16 09:55:50 -0400) are available in the git repository at: https://cgit.freedesktop.org/drm/drm-firmware/ master for you to fetch changes up to 68bc5ce062a70bbc852e782e481d69ee6d1e1635: linux-firmware: Add HuC v3.00.2225 for geminilake (2018-04-27 12:41:10 -0700) Anusha Srivatsa (10): linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678 Revert "linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678" Revert "linux-firmware/i915: GuC firmware for Cannonlake v11.102" Merge remote-tracking branch 'official/master' into drm-firmware linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2719 Merge remote-tracking branch 'official/master' linux-firmware: Add GuC v11.98 for geminilake linux-firmware: Add HuC v3.00.2225 for geminilake WHENCE | 7 +++ i915/glk_guc_ver11_98.bin | Bin 0 -> 154240 bytes i915/glk_huc_ver03_00_2225.bin | Bin 0 -> 220032 bytes 3 files changed, 7 insertions(+) create mode 100644 i915/glk_guc_ver11_98.bin create mode 100644 i915/glk_huc_ver03_00_2225.bin Anusha Srivatsa (2): drm/i915/huc: Load HuC v03.00.2555 for Geminilake. HAX enable guc, huc for CI John Spotswood (1): drm/i915/guc: Load GuC v11.98 for Geminilake. drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++ drivers/gpu/drm/i915/intel_huc_fw.c | 12 3 files changed, 23 insertions(+), 1 deletion(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] HAX enable guc, huc for CI
Enable guc loading for Geminilake. Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c963603..1d23c41 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -47,7 +47,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, 2) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/huc: Load HuC v03.00.2555 for Geminilake.
load the v03.00.2555 huC on geminilake.
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index f93d238..5e96690 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
+#define GLK_HUC_FW_MAJOR 02
+#define GLK_HUC_FW_MINOR 00
+#define GLK_BLD_NUM 1810
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
+ GLK_HUC_FW_MINOR, GLK_BLD_NUM)
+MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ huc_fw->path = I915_GLK_HUC_UCODE;
+ huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(huc_fw->type));
--
2.7.4
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Re: [Intel-gfx] [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for Geminilake
>-Original Message- >From: Vivi, Rodrigo >Sent: Friday, April 20, 2018 11:04 AM >To: Jani Nikula <jani.nik...@linux.intel.com> >Cc: Srivatsa, Anusha <anusha.sriva...@intel.com>; Ian W MORRISON ><ianwmorri...@gmail.com>; airl...@linux.ie; Greg KH ><gre...@linuxfoundation.org>; intel-gfx@lists.freedesktop.org; linux- >ker...@vger.kernel.org; sta...@vger.kernel.org; dri- >de...@lists.freedesktop.org; Wajdeczko, Michal <michal.wajdec...@intel.com> >Subject: Re: [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for >Geminilake > >On Tue, Apr 17, 2018 at 12:02:52PM +0300, Jani Nikula wrote: >> On Mon, 16 Apr 2018, "Srivatsa, Anusha" <anusha.sriva...@intel.com> wrote: >> >>-Original Message- >> >>From: Jani Nikula [mailto:jani.nik...@linux.intel.com] >> >>Sent: Wednesday, April 11, 2018 5:27 AM >> >>To: Ian W MORRISON <ianwmorri...@gmail.com> >> >>Cc: Vivi, Rodrigo <rodrigo.v...@intel.com>; Srivatsa, Anusha >> >><anusha.sriva...@intel.com>; Wajdeczko, Michal >> >><michal.wajdec...@intel.com>; Greg KH <gre...@linuxfoundation.org>; >> >>airl...@linux.ie; joonas.lahti...@linux.intel.com; >> >>linux-ker...@vger.kernel.org; sta...@vger.kernel.org; >> >>intel-gfx@lists.freedesktop.org; dri- de...@lists.freedesktop.org >> >>Subject: Re: [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE >> >>for Geminilake >> >> >> >>On Wed, 11 Apr 2018, Ian W MORRISON <ianwmorri...@gmail.com> wrote: >> >>> >> >>> >> >>>> >> >>>> NAK on indiscriminate Cc: stable. There are zero guarantees that >> >>>> older kernels will work with whatever firmware you throw at them. >> >>>> >> >>> >> >>> I included 'Cc: stable' so the patch would get added to the v4.16 >> >>> and >> >>> v4.15 kernels which I have tested with the patch. I found that >> >>> earlier kernels didn't support the 'linux-firmware' package >> >>> required to get wifi working on Intel's new Gemini Lake NUC. >> >> >> >>You realize that this patch should have nothing to do with wifi? >> >> >> >>Rodrigo, Anusha, if you think Cc: stable is appropriate, please >> >>indicate the specific versions of stable it is appropriate for. >> > >> > Hi Jani, >> > >> > The stable kernel version is 4.12 and beyond. >> > It is appropriate to add the CC: stable in my opinion >> >> Who tested the firmware with v4.12 and later? We only have the CI >> results against *current* drm-tip. We don't even know about v4.16. >> > >I understand your concerns, but the problem was that our old process was a bit >(lot?) messed and there was the unreliable time until the firmware really >lands on >linux-firmware.git. So MODULE_FIRMWARE call was only added after firmware >was really there on firmware repository but it wasn't about the testing. > >In other words, the bump version patch was merged after tested, but >MODULE_FIRMWARE was left behind because firmware blob took a while to get >pulled into linux-firmware.git and we end up forgetting to add it there. > >In my opinion it should be safe to add the MODULE_FIRMWARE there based on >the tests from when the version was bumped. Luis, Elio, can you guys confirm that this firmware is tested and healthy? And also, give a tested-by to this patch please? Thanks, Anusha >> I'm not going to ack and take responsibility for the stable backports >> unless someone actually comes forward with credible Tested-bys. >> >> BR, >> Jani. >> >> >> > >> > Anusha >> >>BR, >> >>Jani. >> >> >> >>> >> >>>> >> >>>> PS. How is this a "RESEND"? I haven't seen this before. >> >>>> >> >>> >> >>> It is a 'RESEND' for that very reason. I initially sent the patch >> >>> to the same people as a similar patch >> >>> (https://patchwork.kernel.org/patch/10143637/) however after >> >>> realising this omitted required addresses I added them and resent the >patch. >> >>> >> >>> Best regards, >> >>> Ian >> >> >> >>-- >> >>Jani Nikula, Intel Open Source Technology Center >> >> -- >> Jani Nikula, Intel Open Source Technology Center >> ___ >> dri-devel mailing list >> dri-de...@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for Geminilake
>-Original Message- >From: Jani Nikula [mailto:jani.nik...@linux.intel.com] >Sent: Wednesday, April 11, 2018 5:27 AM >To: Ian W MORRISON <ianwmorri...@gmail.com> >Cc: Vivi, Rodrigo <rodrigo.v...@intel.com>; Srivatsa, Anusha ><anusha.sriva...@intel.com>; Wajdeczko, Michal ><michal.wajdec...@intel.com>; Greg KH <gre...@linuxfoundation.org>; >airl...@linux.ie; joonas.lahti...@linux.intel.com; >linux-ker...@vger.kernel.org; >sta...@vger.kernel.org; intel-gfx@lists.freedesktop.org; dri- >de...@lists.freedesktop.org >Subject: Re: [RESEND PATCH 1/1] drm/i915/glk: Add MODULE_FIRMWARE for >Geminilake > >On Wed, 11 Apr 2018, Ian W MORRISON <ianwmorri...@gmail.com> wrote: >> >> >>> >>> NAK on indiscriminate Cc: stable. There are zero guarantees that >>> older kernels will work with whatever firmware you throw at them. >>> >> >> I included 'Cc: stable' so the patch would get added to the v4.16 and >> v4.15 kernels which I have tested with the patch. I found that earlier >> kernels didn't support the 'linux-firmware' package required to get >> wifi working on Intel's new Gemini Lake NUC. > >You realize that this patch should have nothing to do with wifi? > >Rodrigo, Anusha, if you think Cc: stable is appropriate, please indicate the >specific >versions of stable it is appropriate for. Hi Jani, The stable kernel version is 4.12 and beyond. It is appropriate to add the CC: stable in my opinion Anusha >BR, >Jani. > >> >>> >>> PS. How is this a "RESEND"? I haven't seen this before. >>> >> >> It is a 'RESEND' for that very reason. I initially sent the patch to >> the same people as a similar patch >> (https://patchwork.kernel.org/patch/10143637/) however after realising >> this omitted required addresses I added them and resent the patch. >> >> Best regards, >> Ian > >-- >Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Fix memory leak in intel_hdcp auth
Earlier, I responded to the wrong version of the patch :(
Apologies.
>-Original Message-
>From: Sripada, Radhakrishna
>Sent: Wednesday, April 4, 2018 4:00 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Sripada, Radhakrishna <radhakrishna.srip...@intel.com>; Jani Nikula
><jani.nik...@linux.intel.com>; Srivatsa, Anusha <anusha.sriva...@intel.com>
>Subject: [PATCH v2] drm/i915: Fix memory leak in intel_hdcp auth
>
>Static code analysis tool reported memory leak in intel_hdcp_auth_downstream.
>Fixing the memory leak.
>
>v2: Rebase, move free to a cleanup label(Jani)
>
>Cc: Jani Nikula <jani.nik...@linux.intel.com>
>Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>---
> drivers/gpu/drm/i915/intel_hdcp.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
>b/drivers/gpu/drm/i915/intel_hdcp.c
>index 98a9c81e2dc1..2db5da550a1c 100644
>--- a/drivers/gpu/drm/i915/intel_hdcp.c
>+++ b/drivers/gpu/drm/i915/intel_hdcp.c
>@@ -435,7 +435,7 @@ int intel_hdcp_auth_downstream(struct intel_digital_port
>*intel_dig_port,
>
> ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
> if (ret)
>- return ret;
>+ goto err;
>
> /*
>* When V prime mismatches, DP Spec mandates re-read of @@ -451,12
>+451,15 @@ int intel_hdcp_auth_downstream(struct intel_digital_port
>*intel_dig_port,
>
> if (i == tries) {
> DRM_ERROR("V Prime validation failed.(%d)\n", ret);
>- return ret;
>+ goto err;
> }
>
> DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
> num_downstream);
>- return 0;
>+ ret = 0;
>+err:
>+ kfree(ksv_fifo);
>+ return ret;
> }
>
> /* Implements Part 1 of the HDCP authorization procedure */
>--
>2.9.3
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix memory leak in intel_hdcp auth
Thanks for fixing this.
>-Original Message-
>From: Sripada, Radhakrishna
>Sent: Tuesday, April 3, 2018 5:05 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Sripada, Radhakrishna <radhakrishna.srip...@intel.com>; Srivatsa, Anusha
><anusha.sriva...@intel.com>
>Subject: [PATCH 1/2] drm/i915: Fix memory leak in intel_hdcp auth
>
>Static code analysis tool reported memory leak in intel_hdcp_auth_downstream.
>Fixing the memory leak.
>
>Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>---
> drivers/gpu/drm/i915/intel_hdcp.c | 19 +++
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
>b/drivers/gpu/drm/i915/intel_hdcp.c
>index 14ca5d3057a7..ce771f6c1a5a 100644
>--- a/drivers/gpu/drm/i915/intel_hdcp.c
>+++ b/drivers/gpu/drm/i915/intel_hdcp.c
>@@ -186,14 +186,18 @@ int intel_hdcp_auth_downstream(struct
>intel_digital_port *intel_dig_port,
> return -ENOMEM;
>
> ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
>- if (ret)
>+ if (ret) {
>+ kfree(ksv_fifo);
> return ret;
>+ }
>
> /* Process V' values from the receiver */
> for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
> ret = shim->read_v_prime_part(intel_dig_port, i, );
>- if (ret)
>+ if (ret) {
>+ kfree(ksv_fifo);
> return ret;
>+ }
> I915_WRITE(HDCP_SHA_V_PRIME(i), vprime);
> }
>
>@@ -222,8 +226,10 @@ int intel_hdcp_auth_downstream(struct
>intel_digital_port *intel_dig_port,
> sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8);
>
> ret = intel_write_sha_text(dev_priv, sha_text);
>- if (ret < 0)
>+ if (ret < 0) {
>+ kfree(ksv_fifo);
> return ret;
>+ }
>
> /* Programming guide writes this every 64 bytes */
> sha_idx += sizeof(sha_text);
>@@ -245,13 +251,18 @@ int intel_hdcp_auth_downstream(struct
>intel_digital_port *intel_dig_port,
> continue;
>
> ret = intel_write_sha_text(dev_priv, sha_text);
>- if (ret < 0)
>+ if (ret < 0) {
>+ kfree(ksv_fifo);
> return ret;
>+ }
>+
> sha_leftovers = 0;
> sha_text = 0;
> sha_idx += sizeof(sha_text);
> }
>
>+ kfree(ksv_fifo);
>+
> /*
>* We need to write BINFO/BSTATUS, and M0 now. Depending on how
>many
>* bytes are leftover from the last ksv, we might be able to fit them
>--
>2.9.3
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[Intel-gfx] [PATCH 3/3] HAX enable guc, huc for CI
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c963603..1d23c41 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -47,7 +47,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, 2) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] linux-firmware/guc/cnl: Load GuC on Cannonlake
GuC is now available for Cannonlake.
Load GuC v11.102 on Cannonlake.
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Cc: Rodrigo vivi <rodrigo.v...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index a9e6fcc..6c59649d1 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -39,6 +39,9 @@
#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 39
+#define CNL_FW_MAJOR 11
+#define CNL_FW_MINOR 102
+
#define GUC_FW_PATH(platform, major, minor) \
"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
@@ -51,6 +54,9 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define I915_CNL_GUC_UCODE GUC_FW_PATH(cnl, CNL_FW_MAJOR, CNL_FW_MINOR)
+MODULE_FIRMWARE(I915_CNL_GUC_UCODE);
+
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -77,6 +83,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = I915_KBL_GUC_UCODE;
guc_fw->major_ver_wanted = KBL_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+ } else if (IS_CANNONLAKE(dev_priv)) {
+ guc_fw->path = I915_CNL_GUC_UCODE;
+ guc_fw->major_ver_wanted = CNL_FW_MAJOR;
+ guc_fw->minor_ver_wanted = CNL_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(guc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH 2/3] linux-firmware/huc/cnl: Load HuC on Cannonlake
Huc is available now for cannonlake.
Load v9.01.2719 on Cannonlake.
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index f93d238..107b9cf 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
+#define CNL_HUC_FW_MAJOR 9
+#define CNL_HUC_FW_MINOR 01
+#define CNL_BLD_NUM 2719
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+#define I915_CNL_HUC_UCODE HUC_FW_PATH(cnl, CNL_HUC_FW_MAJOR, \
+ CNL_HUC_FW_MINOR, CNL_BLD_NUM)
+MODULE_FIRMWARE(I915_CNL_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+ } else if (IS_CANNONLAKE(dev_priv)) {
+ huc_fw->path = I915_CNL_HUC_UCODE;
+ huc_fw->major_ver_wanted = CNL_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = CNL_HUC_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(huc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH 0/3] GuC, HuC Loading Support for Cannonlake.
Load the latest version of GuC and HuC. Pull Request: The following changes since commit a3be6d433f843d71edaa0f9a291297589d571ce4: Merge https://github.com/Netronome/linux-firmware into netro (2018-03-30 10:10:27 -0400) are available in the git repository at: git://anongit.freedesktop.org/drm/drm-firmware master for you to fetch changes up to 3e3bbec105af9141755db8eac768ac829cc9cfff: linux-firmware/i915: HuC firmware for Cannonlake v9.01.2719 (2018-03-30 10:38:34 -0700) Anusha Srivatsa (7): linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678 Revert "linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678" Revert "linux-firmware/i915: GuC firmware for Cannonlake v11.102" Merge remote-tracking branch 'official/master' into drm-firmware linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2719 WHENCE| 7 +++ i915/cnl_guc_ver11_102.bin| Bin 0 -> 215936 bytes i915/cnl_huc_ver9_01_2719.bin | Bin 0 -> 430528 bytes 3 files changed, 7 insertions(+) create mode 100644 i915/cnl_guc_ver11_102.bin create mode 100644 i915/cnl_huc_ver9_01_2719.bin Anusha Srivatsa (3): linux-firmware/guc/cnl: Load GuC on Cannonlake linux-firmware/huc/cnl: Load HuC on Cannonlake HAX enable guc, huc for CI drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++ drivers/gpu/drm/i915/intel_huc_fw.c | 12 3 files changed, 23 insertions(+), 1 deletion(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v3] tests/kms_rotation_crc: Move platform checks to one place for non exhaust fence cases
The rework looks good to me.
Thanks Mika for testing this.
>-Original Message-
>From: Kahola, Mika
>Sent: Wednesday, March 28, 2018 1:26 AM
>To: Sripada, Radhakrishna <radhakrishna.srip...@intel.com>; igt-
>d...@lists.freedesktop.org
>Cc: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
><anusha.sriva...@intel.com>; Ville Syrjälä <ville.syrj...@linux.intel.com>;
>Vetter,
>Daniel <daniel.vet...@intel.com>; Vivi, Rodrigo <rodrigo.v...@intel.com>;
>Maarten Lankhorst <maarten.lankho...@linux.intel.com>; Navare, Manasi D
><manasi.d.nav...@intel.com>
>Subject: Re: [PATCH i-g-t v3] tests/kms_rotation_crc: Move platform checks to
>one place for non exhaust fence cases
>
>On Thu, 2018-03-22 at 15:10 -0700, Radhakrishna Sripada wrote:
>> From: Anusha Srivatsa <anusha.sriva...@intel.com>
>>
>> Cleanup the testcases by moving the platform checks to a single
>> function.
>>
>> The earlier version of the path is posted here [1]
>>
>> v2: Make use of the property enums to get the supported rotations
>> v3: Move hardcodings to a single function(Ville)
>>
>> [1]: https://patchwork.freedesktop.org/patch/209647/
>>
>> Cc: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
>> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
>> Cc: Daniel Vetter <daniel.vet...@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
>> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
>> Cc: Mika Kahola <mika.kah...@intel.com>
>> Cc: Manasi Navare <manasi.d.nav...@intel.com>
>
>Tested-by: Mika Kahola <mika.kah...@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
>> ---
>> tests/kms_rotation_crc.c | 31 ---
>> 1 file changed, 16 insertions(+), 15 deletions(-)
>>
>> diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c index
>> 0cd5c6e52b57..60fb9012e14e 100644
>> --- a/tests/kms_rotation_crc.c
>> +++ b/tests/kms_rotation_crc.c
>> @@ -43,6 +43,7 @@ typedef struct {
>> uint32_t override_fmt;
>> uint64_t override_tiling;
>> int devid;
>> +int gen;
>> } data_t;
>>
>> typedef struct {
>> @@ -301,6 +302,17 @@ static void wait_for_pageflip(int fd)
>> igt_assert(drmHandleEvent(fd, ) == 0);
>> }
>>
>> +static void igt_check_rotation(data_t *data) {
>> +if (data->rotation & (IGT_ROTATION_90 | IGT_ROTATION_270))
>> +igt_require(data->gen >= 9);
>> +else if (data->rotation & IGT_REFLECT_X)
>> +igt_require(data->gen >= 10 ||
>> +(IS_CHERRYVIEW(data->devid) && (data-
>> >rotation & IGT_ROTATION_0)));
>> +else if (data->rotation & IGT_ROTATION_180)
>> +igt_require(data->gen >= 4);
>> +}
>> +
>> static void test_single_case(data_t *data, enum pipe pipe,
>> igt_output_t *output, igt_plane_t *plane,
>> enum rectangle_type rect,
>> @@ -369,13 +381,12 @@ static void test_plane_rotation(data_t *data,
>> int plane_type, bool test_bad_form
>>
>> igt_display_require_output(display);
>>
>> +igt_check_rotation(data);
>> +
>> for_each_pipe_with_valid_output(display, pipe, output) {
>> igt_plane_t *plane;
>> int i, j;
>>
>> -if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
>> -continue;
>> -
>> igt_output_set_pipe(output, pipe);
>>
>> plane = igt_output_get_plane_type(output, plane_type); @@ -
>538,14
>> +549,13 @@ igt_main
>> };
>>
>> data_t data = {};
>> -int gen = 0;
>>
>> igt_skip_on_simulation();
>>
>> igt_fixture {
>> data.gfx_fd = drm_open_driver_master(DRIVER_INTEL);
>> data.devid = intel_get_drm_devid(data.gfx_fd);
>> -gen = intel_gen(data.devid);
>> +data.gen = intel_gen(data.devid);
>>
>> kmstest_set_vt_graphics_mode();
>>
>> @@ -558,16 +568,12 @@ igt_main
>> igt_subtest_f("%s-rotation-%s",
>> plane_test_str(subtest->plane),
>> rot_test_str(subte
[Intel-gfx] [PATCH 1/2] linux-firmware/guc/cnl: Load GuC on Cannonlake
GuC is now available for Cannonlake.
Load GuC v11.102 on Cannonlake.
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Cc: Rodrigo vivi <rodrigo.v...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 978668c..e03a1ec 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -39,6 +39,9 @@
#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 39
+#define CNL_FW_MAJOR 11
+#define CNL_FW_MINOR 102
+
#define GUC_FW_PATH(platform, major, minor) \
"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
@@ -51,6 +54,9 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define I915_CNL_GUC_UCODE GUC_FW_PATH(cnl, CNL_FW_MAJOR, CNL_FW_MINOR)
+MODULE_FIRMWARE(I915_CNL_GUC_UCODE);
+
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -77,6 +83,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = I915_KBL_GUC_UCODE;
guc_fw->major_ver_wanted = KBL_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+ } else if (IS_CANNONLAKE(dev_priv)) {
+ guc_fw->path = I915_CNL_GUC_UCODE;
+ guc_fw->major_ver_wanted = CNL_FW_MAJOR;
+ guc_fw->minor_ver_wanted = CNL_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(guc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH 2/2] linux-firmware/huc/cnl: Load HuC on Cannonlake
Huc is available now for cannonlake.
Load v9.01.2678 on Cannonlake
Cc: Tomi Sarvela <tomi.p.sarv...@intel.com>
Cc: Jani Saarinen <jani.saari...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index bb0f8b7..57e8816 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
+#define CNL_HUC_FW_MAJOR 9
+#define CNL_HUC_FW_MINOR 01
+#define CNL_BLD_NUM 2678
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+#define I915_CNL_HUC_UCODE HUC_FW_PATH(cnl, CNL_HUC_FW_MAJOR, \
+ CNL_HUC_FW_MINOR, CNL_BLD_NUM)
+MODULE_FIRMWARE(I915_CNL_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+ } else if (IS_CANNONLAKE(dev_priv)) {
+ huc_fw->path = I915_CNL_HUC_UCODE;
+ huc_fw->major_ver_wanted = CNL_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = CNL_HUC_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(huc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH 0/2] Guc and HuC for Cannonlake
Adding the Pull request: The following changes since commit 4c0bf113a55975d702673e57c5542f150807ad66: linux-firmware: intel: Update Kabylake audio firmware (2018-03-14 16:23:08 +0530) are available in the git repository at: ssh://git.freedesktop.org/git/drm/drm-firmware master for you to fetch changes up to 2c66d104c2c3d18260539ae68a72e439dea2df20: linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678 (2018-03-14 16:28:37 -0700) Anusha Srivatsa (2): linux-firmware/i915: GuC firmware for Cannonlake v11.102 linux-firmware/i915: HuC firmware for Cannonlake v9.01.2678 WHENCE| 7 +++ i915/cnl_guc_ver11_102.bin| Bin 0 -> 215936 bytes i915/cnl_huc_ver9_01_2678.bin | Bin 0 -> 430336 bytes 3 files changed, 7 insertions(+) create mode 100644 i915/cnl_guc_ver11_102.bin create mode 100644 i915/cnl_huc_ver9_01_2678.bin Anusha Srivatsa (2): linux-firmware/guc/cnl: Load GuC on Cannonlake linux-firmware/huc/cnl: Load HuC on Cannonlake drivers/gpu/drm/i915/intel_guc_fw.c | 10 ++ drivers/gpu/drm/i915/intel_huc_fw.c | 12 2 files changed, 22 insertions(+) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature
Forward Error Correction is supported on DP 1.4. This patch adds corresponding DPCD register definitions. v2: Add dri-devel mailing list to the CC list(Jani) v3: Change names, add missing masks (Manasi) v4: Add missing shifts to mask (Manasi) v5: Arrange the definitions in ascending order of the address (Jani) v6: remove unnecessary definitions. Add missing masks, add "/* 1.4 */" to offset definitions. (Jani) Cc: dri-de...@lists.freedesktop.org Cc: Ville Syrjala <ville.syrj...@linux.intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Cc: Manasi Navare <manasi.d.nav...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- include/drm/drm_dp_helper.h | 30 ++ 1 file changed, 30 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index c239e6e..4de97e9 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -329,6 +329,13 @@ # define DP_DS_12BPC 2 # define DP_DS_16BPC 3 +/* DP Forward error Correction Registers */ +#define DP_FEC_CAPABILITY 0x090/* 1.4 */ +# define DP_FEC_CAPABLE(1 << 0) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2) +# define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3) + /* link configuration */ #defineDP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */ @@ -445,6 +452,19 @@ #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ # define DP_PWR_NOT_NEEDED (1 << 0) +#define DP_FEC_CONFIGURATION 0x120/* 1.4 */ +# define DP_FEC_READY (1 << 0) +# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) +# define DP_FEC_ERR_COUNT_DIS (0 << 1) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) +# define DP_FEC_BIT_ERROR_COUNT(3 << 1) +# define DP_FEC_LANE_SELECT_MASK (3 << 4) +# define DP_FEC_LANE_0_SELECT (0 << 4) +# define DP_FEC_LANE_1_SELECT (1 << 4) +# define DP_FEC_LANE_2_SELECT (2 << 4) +# define DP_FEC_LANE_3_SELECT (3 << 4) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) @@ -620,6 +640,16 @@ #define DP_TEST_SINK 0x270 # define DP_TEST_SINK_START(1 << 0) +#define DP_FEC_STATUS 0x280/* 1.4 */ +# define DP_FEC_DECODE_EN_DETECTED (1 << 0) +# define DP_FEC_DECODE_DIS_DETECTED(1 << 1) + +#define DP_FEC_ERROR_COUNT_LSB 0x0281/* 1.4 */ + +#define DP_FEC_ERROR_COUNT_MSB 0x0282/* 1.4 */ +# define DP_FEC_ERROR_COUNT_MASK 0x7F +# define DP_FEC_ERR_COUNT_VALID(1 << 7) + #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) # define DP_PAYLOAD_ACT_HANDLED (1 << 1) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature
Forward Error Correction is supported on DP 1.4. This patch adds corresponding DPCD register definitions. v2: Add dri-devel mailing list to the CC list(Jani) v3: Change names, add missing masks (Manasi) v4: Add missing shifts to mask (Manasi) v5: Arrange the definitions in ascending order of the address (Jani) Cc: dri-de...@lists.freedesktop.org Cc: Ville Syrjala <ville.syrj...@linux.intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Cc: Manasi Navare <manasi.d.nav...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- include/drm/drm_dp_helper.h | 30 ++ 1 file changed, 30 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index c239e6e..a19d6fb 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -329,6 +329,13 @@ # define DP_DS_12BPC 2 # define DP_DS_16BPC 3 +/* DP Forward error Correction Registers */ +#define DP_FEC_CAPABILITY (0x090) +# define DP_FEC_CAPABLE(1 << 0) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2) +# define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3) + /* link configuration */ #defineDP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */ @@ -445,6 +452,18 @@ #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ # define DP_PWR_NOT_NEEDED (1 << 0) +#define DP_FEC_CONFIGURATION 0x120 +# define DP_FEC_READY (1 << 0) +# define DP_FEC_ERR_COUNT_DIS (0 << 1) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) +# define DP_FEC_BIT_ERROR_COUNT(3 << 1) +# define DP_FEC_ERR_COUNT_SEL_MASK (0xff << 4) +# define DP_FEC_LANE_0_SELECT (0 << 4) +# define DP_FEC_LANE_1_SELECT (1 << 4) +# define DP_FEC_LANE_2_SELECT (2 << 4) +# define DP_FEC_LANE_3_SELECT (3 << 4) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) @@ -620,6 +639,17 @@ #define DP_TEST_SINK 0x270 # define DP_TEST_SINK_START(1 << 0) +#define DP_FEC_STATUS 0x280 +# define DP_FEC_DECODE_EN_DETECTED (1 << 0) +# define DP_FEC_DECODE_DIS_DETECTED(1 << 1) + +#define DP_FEC_ERROR_COUNT_LSB 0x0281 + +#define DP_FEC_ERROR_COUNT_MSB 0x0282 +# define DP_FEC_ERROR_COUNT_MASK 0x7F +# define DP_FEC_ERR_COUNT_SHIFT8 +# define DP_FEC_ERR_COUNT_VALID(1 << 7) + #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) # define DP_PAYLOAD_ACT_HANDLED (1 << 1) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] Forward Error Correction is supported on DP 1.4. This patch adds corresponding DPCD register definitions.
v2: Add dri-devel mailing list to the CC list(Jani) v3: Change names, add missing masks (Manasi) v4: Add missing shifts to mask (Manasi) v5: Arrange the definitions in ascending order of the address (Jani) Cc: dri-de...@lists.freedesktop.org Cc: Ville Syrjala <ville.syrj...@linux.intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Cc: Manasi Navare <manasi.d.nav...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- include/drm/drm_dp_helper.h | 30 ++ 1 file changed, 30 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index c239e6e..a19d6fb 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -329,6 +329,13 @@ # define DP_DS_12BPC 2 # define DP_DS_16BPC 3 +/* DP Forward error Correction Registers */ +#define DP_FEC_CAPABILITY (0x090) +# define DP_FEC_CAPABLE(1 << 0) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2) +# define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3) + /* link configuration */ #defineDP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */ @@ -445,6 +452,18 @@ #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ # define DP_PWR_NOT_NEEDED (1 << 0) +#define DP_FEC_CONFIGURATION 0x120 +# define DP_FEC_READY (1 << 0) +# define DP_FEC_ERR_COUNT_DIS (0 << 1) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) +# define DP_FEC_BIT_ERROR_COUNT(3 << 1) +# define DP_FEC_ERR_COUNT_SEL_MASK (0xff << 4) +# define DP_FEC_LANE_0_SELECT (0 << 4) +# define DP_FEC_LANE_1_SELECT (1 << 4) +# define DP_FEC_LANE_2_SELECT (2 << 4) +# define DP_FEC_LANE_3_SELECT (3 << 4) + #define DP_AUX_FRAME_SYNC_VALUE0x15c /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) @@ -620,6 +639,17 @@ #define DP_TEST_SINK 0x270 # define DP_TEST_SINK_START(1 << 0) +#define DP_FEC_STATUS 0x280 +# define DP_FEC_DECODE_EN_DETECTED (1 << 0) +# define DP_FEC_DECODE_DIS_DETECTED(1 << 1) + +#define DP_FEC_ERROR_COUNT_LSB 0x0281 + +#define DP_FEC_ERROR_COUNT_MSB 0x0282 +# define DP_FEC_ERROR_COUNT_MASK 0x7F +# define DP_FEC_ERR_COUNT_SHIFT8 +# define DP_FEC_ERR_COUNT_VALID(1 << 7) + #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) # define DP_PAYLOAD_ACT_HANDLED (1 << 1) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [i-g-t] tests/kms_rotation_crc: Remove hardcoding of platforms in igt_require()
Rework the rotate and reflect subtests by checking the
crtc supported properties against the ones that the
test is testing. Remove the hardcoded platform names in
igt_require()
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Cc: Mika Kahola <mika.kah...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
tests/kms_rotation_crc.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 0cd5c6e..49d57a2 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -373,9 +373,6 @@ static void test_plane_rotation(data_t *data, int
plane_type, bool test_bad_form
igt_plane_t *plane;
int i, j;
- if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
- continue;
-
igt_output_set_pipe(output, pipe);
plane = igt_output_get_plane_type(output, plane_type);
@@ -558,9 +555,7 @@ igt_main
igt_subtest_f("%s-rotation-%s",
plane_test_str(subtest->plane),
rot_test_str(subtest->rot)) {
- igt_require(!(subtest->rot &
- (IGT_ROTATION_90 | IGT_ROTATION_270)) ||
- gen >= 9);
+
igt_require(igt_plane_get_prop(data.display.pipes->planes, IGT_PLANE_ROTATION)
& subtest->rot);
data.rotation = subtest->rot;
test_plane_rotation(, subtest->plane, false);
}
@@ -596,9 +591,8 @@ igt_main
igt_subtest_f("primary-%s-reflect-x-%s",
tiling_test_str(reflect_x->tiling),
rot_test_str(reflect_x->rot)) {
- igt_require(gen >= 10 ||
- (IS_CHERRYVIEW(data.devid) &&
reflect_x->rot == IGT_ROTATION_0
-&& reflect_x->tiling ==
LOCAL_I915_FORMAT_MOD_X_TILED));
+
igt_require((igt_plane_get_prop(data.display.pipes->planes, IGT_PLANE_ROTATION)
& subtest->rot) &&
+ (reflect_x->rot == IGT_ROTATION_0 &&
reflect_x->tiling == LOCAL_I915_FORMAT_MOD_X_TILED));
data.rotation = (IGT_REFLECT_X | reflect_x->rot);
data.override_tiling = reflect_x->tiling;
test_plane_rotation(, DRM_PLANE_TYPE_PRIMARY,
false);
--
2.7.4
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Re: [Intel-gfx] [PATCH] drm/i915: Remove Firmware URL.
>-Original Message- >From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] >Sent: Tuesday, January 30, 2018 1:06 AM >To: Vivi, Rodrigo <rodrigo.v...@intel.com> >Cc: Srivatsa, Anusha <anusha.sriva...@intel.com>; intel- >g...@lists.freedesktop.org >Subject: Re: [Intel-gfx] [PATCH] drm/i915: Remove Firmware URL. > >Quoting Rodrigo Vivi (2018-01-29 21:40:27) >> On Mon, Jan 29, 2018 at 08:45:24PM +, Chris Wilson wrote: >> > Quoting Srivatsa, Anusha (2018-01-29 20:17:25) >> > > >> > > >> > > >-Original Message- >> > > >From: Vivi, Rodrigo >> > > >Sent: Friday, January 26, 2018 10:22 AM >> > > >To: intel-gfx@lists.freedesktop.org >> > > >Cc: Vivi, Rodrigo <rodrigo.v...@intel.com>; Srivatsa, Anusha >> > > ><anusha.sriva...@intel.com> >> > > >Subject: [PATCH] drm/i915: Remove Firmware URL. >> > > > >> > > >The right place for the firmware is linux-firmware.git. >> > > >We shouldn't advertise anywhere to users to start downloading >> > > >firmware blobs manually. >> > > > >> > > >Also it seems that 01.org page is outdated and it doesn't contain >> > > >DMC 1.27 for SKL, for instance. Probably other firmware releases >> > > >are missing there, while they are part of the official >> > > >linux-firmware.git. >> > >> > Then get them onto 01.org. If Intel cannot be relied on to provide >> > their own firmwares, the alternative is to stop shipping blobs entirely. >> >> I understand your point. But the goal is to have only one place and >> this place is linux-firmware.git. > >If a user sees this message, then linux-firmware has failed them... > >> The web-page will still have the information about the firmware and a >> text explaining the linux-firmware repository. >> >> But what I want is to avoid any users with the impression they have to >> manually go there and install anything. > >Since we tie firmware to kernel version, I think it behooves us to carry a >complete >history; and redundancy is never a bad idea. Fwiw, the local storage should be >a >linux-firmware.git branch so that files are tracked universally. Rodrigo, instead of removing the URL of 01.org, it will be a good idea to add the drm-firmware git repo which is Intel's repo of all firmwares. I understand users should not be encouraged to manually download the firmware. But maybe pointing out the location where we maintain all firmwares would be good. Anusha >-Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: Add horizontal flip subtest.
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Tuesday, December 19, 2017 1:50 PM
>To: Srivatsa, Anusha <anusha.sriva...@intel.com>
>Cc: Daniel Vetter <dan...@ffwll.ch>; Strano, Luis <luis.str...@intel.com>;
>Latvala, Petri <petri.latv...@intel.com>; Lofstedt, Marta
><marta.lofst...@intel.com>; Saarinen, Jani <jani.saari...@intel.com>; intel-gfx
><intel-gfx@lists.freedesktop.org>; Joseph Garvey <joseph1.gar...@intel.com>
>Subject: Re: [Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: Add horizontal
>flip
>subtest.
>
>On Tue, Dec 19, 2017 at 12:20:18AM +, Srivatsa, Anusha wrote:
>>
>>
>> >-Original Message-
>> >From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On
>> >Behalf Of Daniel Vetter
>> >Sent: Thursday, December 14, 2017 2:14 AM
>> >To: Srivatsa, Anusha <anusha.sriva...@intel.com>; Strano, Luis
>> ><luis.str...@intel.com>; Latvala, Petri <petri.latv...@intel.com>;
>> >Lofstedt, Marta <marta.lofst...@intel.com>; Saarinen, Jani
>> ><jani.saari...@intel.com>
>> >Cc: intel-gfx <intel-gfx@lists.freedesktop.org>; Joseph Garvey
>> ><joseph1.gar...@intel.com>
>> >Subject: Re: [Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: Add
>> >horizontal flip subtest.
>> >
>> >On Thu, Nov 23, 2017 at 12:05 AM, Anusha Srivatsa
>> ><anusha.sriva...@intel.com>
>> >wrote:
>> >> From: Joseph Garvey <joseph1.gar...@intel.com>
>> >>
>> >> Test that horizontal flip works with supported rotations. Includes
>> >> a fix for the unrotated fb which was not being positioned correctly
>> >> with portrait and landscape rectangles.
>> >>
>> >> v2:(from Anusha)
>> >> - Change 180 degree rotation to follow the rest, use igt_swap(),
>> >> make flip variable a bool. Format the patch correctly (Ville, Petri
>> >> Latvala)
>> >>
>> >> v3: (From Anusha)
>> >> - Correct the name of subtests in order to avoid duplication of
>> >> names
>> >> (Arek)
>> >>
>> >> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> >> Signed-off-by: Joseph Garvey <joseph1.gar...@intel.com>
>> >> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
>> >> Cc: Petri Latvala <petri.latv...@intel.com>
>> >> Cc: Arkadiusz Hiler <arkadiusz.hi...@intel.com>
>> >
>> >I didn't see this patch fly by originally, but now Marta pointed out
>> >that this skips everywhere. We need to rework it.
>> >
>> >General principle is that in kms tests we should _not_ have any
>> >platform/feature checks encoded in the test. Instead, the testcase
>> >should check properties to figure out whether something should work or not.
>> >
>> >
>> >> ---
>> >> lib/igt_kms.c| 2 +-
>> >> lib/igt_kms.h| 5 ++
>> >> tests/kms_rotation_crc.c | 198
>> >> +--
>> >> 3 files changed, 164 insertions(+), 41 deletions(-)
>> >>
>> >> diff --git a/lib/igt_kms.c b/lib/igt_kms.c index a572fc6..3034e44
>> >> 100644
>> >> --- a/lib/igt_kms.c
>> >> +++ b/lib/igt_kms.c
>> >> @@ -3050,7 +3050,7 @@ void igt_fb_set_size(struct igt_fb *fb,
>> >> igt_plane_t *plane,
>> >>
>> >> static const char *rotation_name(igt_rotation_t rotation) {
>> >> - switch (rotation) {
>> >> + switch (rotation & IGT_ROTATION_MASK) {
>> >> case IGT_ROTATION_0:
>> >> return "0°";
>> >> case IGT_ROTATION_90:
>> >> diff --git a/lib/igt_kms.h b/lib/igt_kms.h index 8dc118c..b83a828
>> >> 100644
>> >> --- a/lib/igt_kms.h
>> >> +++ b/lib/igt_kms.h
>> >> @@ -281,8 +281,13 @@ typedef enum {
>> >> IGT_ROTATION_90 = 1 << 1,
>> >> IGT_ROTATION_180 = 1 << 2,
>> >> IGT_ROTATION_270 = 1 << 3,
>> >> + IGT_REFLECT_X= 1 << 4,
>> >> + IGT_REFLECT_Y= 1 << 5,
>> >> } igt_rotation_t;
>> >>
>> >> +#define IGT_ROTATION_MASK \
>> >> + (IGT_ROTATION_0 | IGT_ROTATION_90 | IGT_ROTATION_180 |
>> >> +IGT_ROTATION_270)
>> >> +
>> >> ty
Re: [Intel-gfx] [PATCH] drm/i915: Remove Firmware URL.
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, January 26, 2018 10:22 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo <rodrigo.v...@intel.com>; Srivatsa, Anusha
><anusha.sriva...@intel.com>
>Subject: [PATCH] drm/i915: Remove Firmware URL.
>
>The right place for the firmware is linux-firmware.git.
>We shouldn't advertise anywhere to users to start downloading firmware blobs
>manually.
>
>Also it seems that 01.org page is outdated and it doesn't contain DMC 1.27 for
>SKL, for instance. Probably other firmware releases are missing there, while
>they
>are part of the official linux-firmware.git.
>
>So, let's stop advertising that place here.
>But also let's work in parallel to kill that page for good and maybe with a
>message
>explaining to users that they don't need to install manually, but rely on their
>distros for getting linux-firmware package updates.
>
>Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Thanks for this much needed patch.
Reviewed-by: Anusha Srivatsa<anusha.sriva...@intel.com>
>---
> drivers/gpu/drm/i915/intel_csr.c | 2 --
> drivers/gpu/drm/i915/intel_uc_fw.c | 2 -- drivers/gpu/drm/i915/intel_uc_fw.h
> |
>3 ---
> 3 files changed, 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_csr.c
>b/drivers/gpu/drm/i915/intel_csr.c
>index 41e6c75a7f3c..05761ffbf2ec 100644
>--- a/drivers/gpu/drm/i915/intel_csr.c
>+++ b/drivers/gpu/drm/i915/intel_csr.c
>@@ -429,8 +429,6 @@ static void csr_load_work_fn(struct work_struct *work)
> "Failed to load DMC firmware %s."
> " Disabling runtime power management.\n",
> csr->fw_path);
>- dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
>- INTEL_UC_FIRMWARE_URL);
> }
>
> release_firmware(fw);
>diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c
>b/drivers/gpu/drm/i915/intel_uc_fw.c
>index 784eff9cdfc8..f2c4ddb4b91d 100644
>--- a/drivers/gpu/drm/i915/intel_uc_fw.c
>+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
>@@ -189,8 +189,6 @@ void intel_uc_fw_fetch(struct drm_i915_private
>*dev_priv,
>
> DRM_WARN("%s: Failed to fetch firmware %s (error %d)\n",
>intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, err);
>- DRM_INFO("%s: Firmware can be downloaded from %s\n",
>- intel_uc_fw_type_repr(uc_fw->type),
>INTEL_UC_FIRMWARE_URL);
>
> release_firmware(fw); /* OK even if fw is NULL */
> }
>diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h
>b/drivers/gpu/drm/i915/intel_uc_fw.h
>index d5fd4609c785..ee40852f2250 100644
>--- a/drivers/gpu/drm/i915/intel_uc_fw.h
>+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
>@@ -29,9 +29,6 @@ struct drm_printer;
> struct drm_i915_private;
> struct i915_vma;
>
>-/* Home of GuC, HuC and DMC firmwares */ -#define
>INTEL_UC_FIRMWARE_URL "https://01.org/linuxgraphics/downloads/firmware;
>-
> enum intel_uc_fw_status {
> INTEL_UC_FIRMWARE_FAIL = -1,
> INTEL_UC_FIRMWARE_NONE = 0,
>--
>2.13.6
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Re: [Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP
>-Original Message-
>From: Zanoni, Paulo R
>Sent: Friday, January 19, 2018 10:25 AM
>To: Vivi, Rodrigo <rodrigo.v...@intel.com>; Srivatsa, Anusha
><anusha.sriva...@intel.com>
>Cc: Ausmus, James <james.aus...@intel.com>; Nikula, Jani
><jani.nik...@intel.com>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for
>ICP
>
>Em Sex, 2018-01-19 às 09:56 -0800, Rodrigo Vivi escreveu:
>> On Fri, Jan 19, 2018 at 05:26:02PM +, Anusha Srivatsa wrote:
>> > On Fri, Jan 19, 2018 at 02:40:41PM -0200, Paulo Zanoni wrote:
>> > > Em Qui, 2018-01-11 às 15:57 -0800, Rodrigo Vivi escreveu:
>> > > > On Thu, Jan 11, 2018 at 09:48:57PM +, James Ausmus wrote:
>> > > > > On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote:
>> > > > > > From: Anusha Srivatsa <anusha.sriva...@intel.com>
>> > > > > >
>> > > > > > ICP has two backlight controllers - similar to previous
>> > > > > > platforms like BXT.
>> > > > > >
>> > > > > > v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT
>> > > > > > register.(Jani)
>> > > > > > Reuse BXT code since it is very similar.(Ville)
>> > > > > >
>> > > > > > v3 (from Paulo): Rebase.
>> > > > > >
>> > > > > > Cc: Jani Nikula <jani.nik...@intel.com>
>> > > > > > Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
>> > > > > > Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
>> > > > > > Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> > > > > > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
>> > > > > > ---
>> > > > > > drivers/gpu/drm/i915/intel_panel.c | 2 +-
>> > > > > > 1 file changed, 1 insertion(+), 1 deletion(-)
>> > > > > >
>> > > > > > diff --git a/drivers/gpu/drm/i915/intel_panel.c
>> > > > > > b/drivers/gpu/drm/i915/intel_panel.c
>> > > > > > index fa6831f8c004..ad80cca8c110 100644
>> > > > > > --- a/drivers/gpu/drm/i915/intel_panel.c
>> > > > > > +++ b/drivers/gpu/drm/i915/intel_panel.c
>> > > > > > @@ -1865,7 +1865,7 @@
>> > > > > > intel_panel_init_backlight_funcs(struct
>> > > > > > intel_panel *panel)
>> > > > > >panel->backlight.set = bxt_set_backlight;
>> > > > > >panel->backlight.get = bxt_get_backlight;
>> > > > > >panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
>> > > > > > - } else if (HAS_PCH_CNP(dev_priv)) {
>> > > > > > + } else if (HAS_PCH_CNP(dev_priv) ||
>> > > > > > HAS_PCH_ICP(dev_priv)) {
>> > > > >
>> > > > > The commit message says reuse BXT, but the code says reuse CNP
>> > > > > - which one should it be?
>> > > >
>> > > > well,
>> > > > CNP is like BXT, but with only one controller.
>> > > > ICP is like BXT, including 2 controllers.
>> > > >
>> > > > I don't know if it makes more sense re-use the cnp or bxt
>> > > > functions
>> > > >
>> > > > But one way or another we have to address these lines from
>> > > > cnp_setup:
>> > > >
>> > > > /*
>> > > > * CNP has the BXT implementation of backlight, but with
>> > > > only
>> > > > * one controller. Future platforms could have multiple
>> > > > controll\ ers
>> > > > * so let's make this extensible and prepared for the
>> > > > future.
>> > > > */
>> > > > panel->backlight.controller = 0;
>> > >
>> > > My understanding is that we're only using one of the controllers
>> > > on ICP on purpose, so we can perfectly reuse the CNP code.
>> > >
>> > > But I'll let Anusha comment on this.
>> >
>> > This is intentional. Commit message is trying to tell the similarity
>> > in backlight support. But we need to reuse CNP code ultimstely.
>>
>> So it is probably better to update this comment here explaining that
>> we know it has more
Re: [Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP
On Fri, Jan 19, 2018 at 02:40:41PM -0200, Paulo Zanoni wrote:
> Em Qui, 2018-01-11 às 15:57 -0800, Rodrigo Vivi escreveu:
> > On Thu, Jan 11, 2018 at 09:48:57PM +, James Ausmus wrote:
> > > On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote:
> > > > From: Anusha Srivatsa <anusha.sriva...@intel.com>
> > > >
> > > > ICP has two backlight controllers - similar to previous platforms
> > > > like
> > > > BXT.
> > > >
> > > > v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani)
> > > > Reuse BXT code since it is very similar.(Ville)
> > > >
> > > > v3 (from Paulo): Rebase.
> > > >
> > > > Cc: Jani Nikula <jani.nik...@intel.com>
> > > > Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
> > > > Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> > > > Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
> > > > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_panel.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_panel.c
> > > > b/drivers/gpu/drm/i915/intel_panel.c
> > > > index fa6831f8c004..ad80cca8c110 100644
> > > > --- a/drivers/gpu/drm/i915/intel_panel.c
> > > > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > > > @@ -1865,7 +1865,7 @@ intel_panel_init_backlight_funcs(struct
> > > > intel_panel *panel)
> > > > panel->backlight.set = bxt_set_backlight;
> > > > panel->backlight.get = bxt_get_backlight;
> > > > panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> > > > - } else if (HAS_PCH_CNP(dev_priv)) {
> > > > + } else if (HAS_PCH_CNP(dev_priv) ||
> > > > HAS_PCH_ICP(dev_priv)) {
> > >
> > > The commit message says reuse BXT, but the code says reuse CNP -
> > > which
> > > one should it be?
> >
> > well,
> > CNP is like BXT, but with only one controller.
> > ICP is like BXT, including 2 controllers.
> >
> > I don't know if it makes more sense re-use the cnp or bxt functions
> >
> > But one way or another we have to address these lines from cnp_setup:
> >
> > /*
> > * CNP has the BXT implementation of backlight, but with only
> > * one controller. Future platforms could have multiple
> > controll\
> > ers
> > * so let's make this extensible and prepared for the future.
> > */
> > panel->backlight.controller = 0;
>
> My understanding is that we're only using one of the controllers on ICP
> on purpose, so we can perfectly reuse the CNP code.
>
> But I'll let Anusha comment on this.
This is intentional. Commit message is trying to tell the similarity
in backlight support. But we need to reuse CNP code ultimstely.
Regards,
Anusha
> >
> > >
> > > > panel->backlight.setup = cnp_setup_backlight;
> > > > panel->backlight.enable = cnp_enable_backlight;
> > > > panel->backlight.disable =
> > > > cnp_disable_backlight;
> > > > --
> > > > 2.14.3
> > > >
> > > > ___
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Anusha Srivatsa
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[Intel-gfx] [PATCH i-g-t] igt/kms-crc-rotation: Fix flip subtests to follow kms guidelines.
Fix flip subtest that used plaform names
in igt_require() instead of testing if rotation
property is supported on given combination of
rotation/flips.
Suggested-by: Daniel Vetter
Cc: Daniel Vetter <daniel.vet...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
tests/kms_rotation_crc.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 799cf11..63f3b5b 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -394,9 +394,6 @@ static void __test_plane_rotation(data_t *data, int
plane_type, bool test_bad_fo
igt_plane_t *plane;
int i;
- if (IS_CHERRYVIEW(data->devid) && pipe != PIPE_B)
- continue;
-
igt_output_set_pipe(output, pipe);
plane = igt_output_get_plane_type(output, plane_type);
@@ -837,9 +834,7 @@ igt_main
tiling_test_str(reflect_x->tiling),
rot_test_str(reflect_x->rot),
flip_test_str(reflect_x->flips)) {
- igt_require(gen >= 10 ||
- (IS_CHERRYVIEW(data.devid) &&
reflect_x->rot == IGT_ROTATION_0
-&& reflect_x->tiling ==
LOCAL_I915_FORMAT_MOD_X_TILED));
+ igt_require(subtest->flips);
data.rotation = (IGT_REFLECT_X | reflect_x->rot);
data.override_tiling = reflect_x->tiling;
data.flips = reflect_x->flips;
--
2.7.4
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Re: [Intel-gfx] [PATCH] drm/i915: add support for specifying DMC firmware override by module param
Hi,
This patch could be really helpful Is there any issue with it? It's not
merged yet.
Regards,
Anusha
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Jani Nikula
>Sent: Wednesday, November 22, 2017 8:20 AM
>To: Joonas Lahtinen <joonas.lahti...@linux.intel.com>; David Weinehall
><david.weineh...@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH] drm/i915: add support for specifying DMC
>firmware override by module param
>
>On Wed, 22 Nov 2017, Joonas Lahtinen <joonas.lahti...@linux.intel.com>
>wrote:
>> On Tue, 2017-11-21 at 23:54 +0200, Jani Nikula wrote:
>>> On Tue, 21 Nov 2017, David Weinehall <david.weineh...@linux.intel.com>
>wrote:
>>> > On Tue, Nov 21, 2017 at 01:51:29PM +0200, Jani Nikula wrote:
>>> > > Use i915.dmc_firmware_path to override default firmware for the
>>> > > platform and bypassing version checks.
>>> > >
>>> > > Signed-off-by: Jani Nikula <jani.nik...@intel.com>
>>> > >
>>> > > ---
>>> > >
>>> > > Untested.
>>> >
>>> > Yeah, it kind of shows. It fails to compile :D
>>>
>>> Oops. I was anxious to get the patch on the list in the heat of IRC
>>> discussion, and just added the disclaimer instead of doing this
>>> properly... *blush*
>>>
>>> >
>>> > But if you chuck in:
>>> >
>>> > param(char *, dmc_firmware_path, NULL) \
>>
>> I think I already raised my suggestion earlier, but here it goes again.
>> Maybe we should consider consolidating these into:
>>
>> i915.firmware=guc:whatever.bin i915.firmware=dmc:whatever.bin
>
>I don't think that's possible. I didn't double check but I think you only get
>one
>value from the module param code. Unless you roll your own modparam hooks,
>which is best avoided.
>
>> Then something like "i915.firmware=guc:disable" could be supported,
>> too.
>
>i915.dmc_firmware_path="" could mean disable.
>
>BR,
>Jani.
>
>
>>
>> Regards, Joonas
>>
>>> >
>>> > in i915_params.h
>>> >
>>> > Things work correctly and you can use:
>>> >
>>> > Tested-by: David Weinehall <david.weineh...@linux.intel.com>
>>> > Reviewed-by: David Weinehall <david.weineh...@linux.intel.com>
>>>
>>> Thanks. But let's wait for more input on whether this is really what
>>> people want. Perhaps this is useful *regardless* of the outcome of
>>> the other discussions.
>>>
>>> BR,
>>> Jani.
>>>
>>>
>>> >
>>> > > ---
>>> > > drivers/gpu/drm/i915/i915_params.c | 3 +++
>>> > > drivers/gpu/drm/i915/intel_csr.c | 9 +++--
>>> > > 2 files changed, 10 insertions(+), 2 deletions(-)
>>> > >
>>> > > diff --git a/drivers/gpu/drm/i915/i915_params.c
>>> > > b/drivers/gpu/drm/i915/i915_params.c
>>> > > index 3328147b4863..c11ad6d67fa9 100644
>>> > > --- a/drivers/gpu/drm/i915/i915_params.c
>>> > > +++ b/drivers/gpu/drm/i915/i915_params.c
>>> > > @@ -171,6 +171,9 @@ i915_param_named_unsafe(guc_firmware_path,
>>> > > charp, 0400, i915_param_named_unsafe(huc_firmware_path, charp,
>0400,
>>> > > "HuC firmware path to use instead of the default one");
>>> > >
>>> > > +i915_param_named_unsafe(dmc_firmware_path, charp, 0400,
>>> > > + "DMC firmware path to use instead of the default one");
>>> > > +
>>> > > i915_param_named_unsafe(enable_dp_mst, bool, 0600,
>>> > > "Enable multi-stream transport (MST) for new DisplayPort sinks.
>>> > > (default: true)");
>>> > >
>>> > > diff --git a/drivers/gpu/drm/i915/intel_csr.c
>>> > > b/drivers/gpu/drm/i915/intel_csr.c
>>> > > index 77d8b3d483ca..82db376ec7e1 100644
>>> > > --- a/drivers/gpu/drm/i915/intel_csr.c
>>> > > +++ b/drivers/gpu/drm/i915/intel_csr.c
>>> > > @@ -296,7 +296,10 @@ static uint32_t *parse_csr_fw(struct
>>> > > drm_i915_private *dev_priv,
>>> > >
>>> > > csr->version = css_header->version;
>>> > >
>>> > > - if (IS_CANNONLAKE(dev_priv)) {
>>>
[Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake
From: "Srivatsa, Anusha" <anusha.sriva...@intel.com> There is a new version of DMC available for CNL. The release notes mentions: 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption v2: Since the firmware is merged to linux-firmware.git, add MODULE_FIRMWARE. v3: rebased. Correct commit message(Jani) Cc: Jani Saarinen <jani.saari...@intel.com> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 7fe4aac0..41e6c75 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -37,8 +37,9 @@ #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) +#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin" +MODULE_FIRMWARE(I915_CSR_CNL); +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin" MODULE_FIRMWARE(I915_CSR_KBL); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake
>-Original Message- >From: Saarinen, Jani >Sent: Wednesday, January 3, 2018 11:52 PM >To: Srivatsa, Anusha <anusha.sriva...@intel.com>; intel- >g...@lists.freedesktop.org >Cc: Vivi, Rodrigo <rodrigo.v...@intel.com> >Subject: RE: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake > >HI, >> -Original Message- >> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On >> Behalf Of Anusha Srivatsa >> Sent: keskiviikko 3. tammikuuta 2018 23.22 >> To: intel-gfx@lists.freedesktop.org >> Cc: Vivi, Rodrigo <rodrigo.v...@intel.com> >> Subject: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake >> >> There is a new version of DMC available for CNL. >> >> The release notes mentions: >> 1. Fix for the issue where DC_STATE was getting enabled even when >> disabled by driver causing data corruption >> >> v2: Since the firmware is merged to linux-firmware.git, add >> MODUE_FIRMWARE. >Minor typo s/MODUE_/MODULE_ Thanks for noticing Jani. Anusha >> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> >> Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com> >> --- >> drivers/gpu/drm/i915/intel_csr.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_csr.c >> b/drivers/gpu/drm/i915/intel_csr.c >> index f417101..0d7b3b6 100644 >> --- a/drivers/gpu/drm/i915/intel_csr.c >> +++ b/drivers/gpu/drm/i915/intel_csr.c >> @@ -37,8 +37,9 @@ >> #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" >> #define GLK_CSR_VERSION_REQUIREDCSR_VERSION(1, 4) >> >> -#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" >> -#define CNL_CSR_VERSION_REQUIREDCSR_VERSION(1, 6) >> +#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin" >> +MODULE_FIRMWARE(I915_CSR_CNL); >> +#define CNL_CSR_VERSION_REQUIREDCSR_VERSION(1, 7) >> >> #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" >> MODULE_FIRMWARE(I915_CSR_KBL); >> -- >> 2.7.4 >> > >Br, > >Jani Saarinen >Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-firmware Pull Request (CNL:DMC)
>-Original Message- >From: Josh Boyer [mailto:jwbo...@kernel.org] >Sent: Wednesday, January 3, 2018 12:27 PM >To: Srivatsa, Anusha <anusha.sriva...@intel.com> >Cc: linux-firmw...@kernel.org; Intel Graphics Development g...@lists.freedesktop.org>; Ben Hutchings <b...@decadent.org.uk>; Kyle >McMartin <k...@kernel.org> >Subject: Re: linux-firmware Pull Request (CNL:DMC) > >On Tue, Jan 2, 2018 at 2:10 PM, Anusha Srivatsa <anusha.sriva...@intel.com> >wrote: >> Hi Josh, Ben, Kyle, >> >> Please consider pulling i915 updates to linux-firmware.git. >> The following changes since commit >2567e092339cd3403d697dc2e0967c31b7acb989: >> >> nvidia: add GP108 signed firmware (2017-12-21 08:08:05 -0500) >> >> are available in the git repository at: >> >> https://cgit.freedesktop.org/drm/drm-firmware/ master >> >> for you to fetch changes up to 4a77cab4a02712fc7b37b55c120eec61fe7e3f32: >> >> linux-firmware: DMC firmware for cannonlake v1.07 (2018-01-02 >> 10:52:43 -0800) >> >> >> Anusha Srivatsa (1): >> linux-firmware: DMC firmware for cannonlake v1.07 >> >> WHENCE | 2 ++ >> i915/cnl_dmc_ver1_07.bin | Bin 0 -> 11268 bytes >> 2 files changed, 2 insertions(+) >> create mode 100644 i915/cnl_dmc_ver1_07.bin > >Merged and pushed out. Thanks. Thanks a lot Josh. Anusha >josh ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake
There is a new version of DMC available for CNL. The release notes mentions: 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption v2: Since the firmware is merged to linux-firmware.git, add MODUE_FIRMWARE. Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index f417101..0d7b3b6 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -37,8 +37,9 @@ #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) +#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin" +MODULE_FIRMWARE(I915_CSR_CNL); +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" MODULE_FIRMWARE(I915_CSR_KBL); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake
There is a new version of DMC available for CNL. The release notes mentions: 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption v2: Since the firmware is merged to linux-firmware.git, add MODUE_FIRMWARE. Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index f417101..0d7b3b6 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -37,8 +37,9 @@ #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) +#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin" +MODULE_FIRMWARE(I915_CSR_CNL); +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" MODULE_FIRMWARE(I915_CSR_KBL); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
Since the firmwares are not yet released to public repo,
disable them on Geminilake.
v2: Remove the firmware versions (Michal)
v3: Remove unwanted defines (Rodrigo)
Correct commit message (Michal)
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: <sta...@vger.kernel.org>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
Fixes: 90f192c8241e ("drm/i915/GuC/GLK: Load GuC on GLK")
Fixes: db5ba0d8931e ("drm/i915/GLK/HuC: Load HuC on GLK")
Reviewed-by: Michal Wajdeczko <michal.wajdec...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 9 -
drivers/gpu/drm/i915/intel_huc.c| 11 ---
2 files changed, 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index cbc51c9..3b09329 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -39,9 +39,6 @@
#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 39
-#define GLK_FW_MAJOR 10
-#define GLK_FW_MINOR 56
-
#define GUC_FW_PATH(platform, major, minor) \
"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
@@ -54,8 +51,6 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
-#define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
-
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -82,10 +77,6 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = I915_KBL_GUC_UCODE;
guc_fw->major_ver_wanted = KBL_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_FW_MINOR;
- } else if (IS_GEMINILAKE(dev_priv)) {
- guc_fw->path = I915_GLK_GUC_UCODE;
- guc_fw->major_ver_wanted = GLK_FW_MAJOR;
- guc_fw->minor_ver_wanted = GLK_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(guc_fw->type));
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 974be3d..8ed0518 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -54,10 +54,6 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
-#define GLK_HUC_FW_MAJOR 02
-#define GLK_HUC_FW_MINOR 00
-#define GLK_BLD_NUM 1748
-
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -74,9 +70,6 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
-#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
- GLK_HUC_FW_MINOR, GLK_BLD_NUM)
-
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -103,10 +96,6 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
- } else if (IS_GEMINILAKE(dev_priv)) {
- huc_fw->path = I915_GLK_HUC_UCODE;
- huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
- huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(huc_fw->type));
--
2.7.4
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Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
>-Original Message- >From: Wajdeczko, Michal >Sent: Wednesday, December 27, 2017 12:53 PM >To: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha ><anusha.sriva...@intel.com> >Cc: Vivi, Rodrigo <rodrigo.v...@intel.com> >Subject: Re: [PATCH] drm/i915/glk: Disable Guc and HuC on GLK > >On Sat, 23 Dec 2017 01:05:14 +0100, Anusha Srivatsa ><anusha.sriva...@intel.com> wrote: > >> Since the firmwares are released yet to public repo, > ^^^ >s/released/not released Oooops Thanks a lot for the catch. Anusha >> disable them on Geminilake. >> >> v2: Remove the firmware versions (Michal) >> >> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> >> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> >> --- >Reviewed-by: Michal Wajdeczko <michal.wajdec...@intel.com> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Thursday, December 28, 2017 8:08 AM
>To: Srivatsa, Anusha <anusha.sriva...@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Wajdeczko, Michal
><michal.wajdec...@intel.com>
>Subject: Re: [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
>
>On Sat, Dec 23, 2017 at 12:05:14AM +, Anusha Srivatsa wrote:
>> Since the firmwares are released yet to public repo, disable them on
>> Geminilake.
>>
>> v2: Remove the firmware versions (Michal)
>>
>> Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>
>Fixes: 90f192c8241e ("drm/i915/GuC/GLK: Load GuC on GLK")
>Fixes: db5ba0d8931e ("drm/i915/GLK/HuC: Load HuC on GLK")
>Cc: <sta...@vger.kernel.org> # v4.13+
>
>What about a revert on those 2 patches?
Revert touches source files which no longer I would prefer having this
patch instead.
>I'm fine with one patch approach, but the fixes tag needs to be here anyways.
Yes, thanks for pointing the suitable tags.
>> ---
>> drivers/gpu/drm/i915/intel_guc_fw.c | 4
>> drivers/gpu/drm/i915/intel_huc.c| 4
>> 2 files changed, 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
>> b/drivers/gpu/drm/i915/intel_guc_fw.c
>> index cbc51c9..252b475 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
>> @@ -82,10 +82,6 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
>> guc_fw->path = I915_KBL_GUC_UCODE;
>> guc_fw->major_ver_wanted = KBL_FW_MAJOR;
>> guc_fw->minor_ver_wanted = KBL_FW_MINOR;
>> -} else if (IS_GEMINILAKE(dev_priv)) {
>> -guc_fw->path = I915_GLK_GUC_UCODE;
>> -guc_fw->major_ver_wanted = GLK_FW_MAJOR;
>> -guc_fw->minor_ver_wanted = GLK_FW_MINOR;
>
>But also, please it is mandatory to also remove the now unused
>I915_GLK_GUC_UCODE, GLK_FW_MAJOR, and GLK_FW_MINOR
Will change in next revision.
Thanks a lot for the feedback.
>> } else {
>> DRM_WARN("%s: No firmware known for this platform!\n",
>> intel_uc_fw_type_repr(guc_fw->type));
>> diff --git a/drivers/gpu/drm/i915/intel_huc.c
>> b/drivers/gpu/drm/i915/intel_huc.c
>> index 974be3d..3f28ae0 100644
>> --- a/drivers/gpu/drm/i915/intel_huc.c
>> +++ b/drivers/gpu/drm/i915/intel_huc.c
>> @@ -103,10 +103,6 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
>> huc_fw->path = I915_KBL_HUC_UCODE;
>> huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
>> huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
>> -} else if (IS_GEMINILAKE(dev_priv)) {
>> -huc_fw->path = I915_GLK_HUC_UCODE;
>> -huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
>> -huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
>
>and unused I915_GLK_HUC_UCODE, GLK_HUC_FW_MAJOR, and
>GLK_HUC_FW_MINOR.
Sure.
BR,
Anusha
>> } else {
>> DRM_WARN("%s: No firmware known for this platform!\n",
>> intel_uc_fw_type_repr(huc_fw->type));
>> --
>> 2.7.4
>>
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[Intel-gfx] linux-firmware Pull Request (CNL:DMC)
Hi Josh, Ben, Kyle, Please consider pulling i915 updates to linux-firmware.git. The following changes since commit 2567e092339cd3403d697dc2e0967c31b7acb989: nvidia: add GP108 signed firmware (2017-12-21 08:08:05 -0500) are available in the git repository at: https://cgit.freedesktop.org/drm/drm-firmware/ master for you to fetch changes up to 4a77cab4a02712fc7b37b55c120eec61fe7e3f32: linux-firmware: DMC firmware for cannonlake v1.07 (2018-01-02 10:52:43 -0800) Anusha Srivatsa (1): linux-firmware: DMC firmware for cannonlake v1.07 WHENCE | 2 ++ i915/cnl_dmc_ver1_07.bin | Bin 0 -> 11268 bytes 2 files changed, 2 insertions(+) create mode 100644 i915/cnl_dmc_ver1_07.bin Thanks In Advance, Anusha Srivatsa ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake
There is a new version of DMC available for CNL. The release notes mentions: 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 7fe4aac0..ed256de 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -37,8 +37,8 @@ #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) +#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin" +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin" MODULE_FIRMWARE(I915_CSR_KBL); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
Since the firmwares are released yet to public repo,
disable them on Geminilake.
v2: Remove the firmware versions (Michal)
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 4
drivers/gpu/drm/i915/intel_huc.c| 4
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index cbc51c9..252b475 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -82,10 +82,6 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = I915_KBL_GUC_UCODE;
guc_fw->major_ver_wanted = KBL_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_FW_MINOR;
- } else if (IS_GEMINILAKE(dev_priv)) {
- guc_fw->path = I915_GLK_GUC_UCODE;
- guc_fw->major_ver_wanted = GLK_FW_MAJOR;
- guc_fw->minor_ver_wanted = GLK_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(guc_fw->type));
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 974be3d..3f28ae0 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -103,10 +103,6 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
- } else if (IS_GEMINILAKE(dev_priv)) {
- huc_fw->path = I915_GLK_HUC_UCODE;
- huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
- huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
} else {
DRM_WARN("%s: No firmware known for this platform!\n",
intel_uc_fw_type_repr(huc_fw->type));
--
2.7.4
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[Intel-gfx] [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature
Forward Error Correction is supported on DP 1.4. This patch adds corresponding DPCD register definitions. v2: Add dri-devel mailing list to the CC list(Jani) v3: Change names, add missing masks (Manasi) Cc: dri-de...@lists.freedesktop.org Cc: Ville Syrjala <ville.syrj...@linux.intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Cc: Manasi Navare <manasi.d.nav...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- include/drm/drm_dp_helper.h | 30 ++ 1 file changed, 30 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index da58a42..4f75034 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -284,6 +284,36 @@ # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 # define DP_DSC_BITS_PER_PIXEL_10x4 +/* DP Forward error Correction Registers */ +#define DP_FEC_CAPABILITY 0x090 +# define DP_FEC_CAPABLE(1 << 0) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2) +# define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3) + +#define DP_FEC_CONFIGURATION 0x120 +# define DP_FEC_READY (1 << 0) +# define DP_FEC_ERR_COUNT_DIS (0 << 1) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) +# define DP_FEC_BIT_ERROR_COUNT(3 << 1) +# define DP_FEC_ERR_COUNT_SEL_MASK (0xFF) +# define DP_FEC_LANE_0_SELECT (0 << 4) +# define DP_FEC_LANE_1_SELECT (1 << 4) +# define DP_FEC_LANE_2_SELECT (2 << 4) +# define DP_FEC_LANE_3_SELECT (3 << 4) + +#define DP_FEC_STATUS 0x280 +# define DP_FEC_DECODE_EN_DETECTED (1 << 0) +# define DP_FEC_DECODE_DIS_DETECTED(1 << 1) + +#define DP_FEC_ERROR_COUNT_LSB 0x0281 + +#define DP_FEC_ERROR_COUNT_MSB 0x0282 +# define DP_FEC_ERROR_COUNT_MASK 0x7F +# define DP_FEC_ERR_COUNT_SHIFT8 +# define DP_FEC_ERR_COUNT_VALID(1 << 7) + #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED1 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature
>-Original Message- >From: Navare, Manasi D >Sent: Thursday, December 21, 2017 12:36 PM >To: Srivatsa, Anusha <anusha.sriva...@intel.com> >Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Ville >Syrjala ><ville.syrj...@linux.intel.com>; Jani Nikula <jani.nik...@linux.intel.com> >Subject: Re: [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature > >On Mon, Nov 27, 2017 at 04:55:44PM -0800, Anusha Srivatsa wrote: >> Forward Error Correction is supported on DP 1.4. >> This patch adds corresponding DPCD register definitions. >> >> v2: Add dri-devel to the CC list >> >> Cc: dri-de...@lists.freedesktop.org >> Cc: Ville Syrjala <ville.syrj...@linux.intel.com> >> Cc: Jani Nikula <jani.nik...@linux.intel.com> >> Cc: Manasi Navare <manasi.d.nav...@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> >> --- >> include/drm/drm_dp_helper.h | 29 + >> 1 file changed, 29 insertions(+) >> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >> index da58a42..bc816ea 100644 >> --- a/include/drm/drm_dp_helper.h >> +++ b/include/drm/drm_dp_helper.h >> @@ -284,6 +284,35 @@ >> # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 >> # define DP_DSC_BITS_PER_PIXEL_10x4 >> >> +/* DP Forward error Correction Registers */ >> +#define DP_FEC_CAPABILITY 0x090 >> +# define DP_FEC_CAPABLE (1 << 0) >> +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) >> +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2) >> +# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) >> + >> +#define DP_FEC_CONFIGURATION0x120 >> +# define DP_FEC_READY (1 << 0) >> +# define DP_FEC_ERR_COUNT_DIS (0 << 1) >> +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) >> +# define DP_FEC_CORR_BLK_ERROR_COUNT(2 << 1) >> +# define DP_FEC_BIT_ERROR_COUNT (3 << 1) > >These above values indicate the value of FEC_ERROR_COUNT_SEL. >I think we would need a mask for FEC_ERROR_COUNT_SEL field so that we can >read this field as drm_dpcd_read(DP_FEC_CONFIGURATION) & >FEC_ERROR_COUNT_SEL_MASK and then compare this to each of the values for >that field. >So we would need an extra #define for the MASK Sounds good >> +# define DP_FEC_LANE_0_SELECT (0 << 4) >> +# define DP_FEC_LANE_1_SELECT (1 << 4) >> +# define DP_FEC_LANE_2_SELECT (2 << 4) >> +# define DP_FEC_LANE_3_SELECT (3 << 4) >> + >> +#define DP_FEC_STATUS 0x280 >> +# define DP_FEC_EN_DETECTED (1 << 0) > >I think better name would be DP_FEC_DECODE_EN_DETECTED since this refers to >FEC_DECODE_EN link symbol sequence Now that you mentioned, I noticed that's the name used in spec too. I wonder why I went ahead with the above name. Shall change it. Thanks. >> +# define DP_FEC_DEC_DETECTED(1 << 1) > >And this should be DP_FEC_DECODE_DIS_DETECTED since this refers to >FEC_DECODE_DIS link symbol sequence > >> + >> +#define DP_FEC_ERROR_COUNT_10x0281 >> +# define DP_FEC_ERR_COUNT_7_0(err_count)(err_count << 0) > >So this is a RO register and so we wont be writing the err_count by passing it >as >an argument as above. >And this is the entire reister that indicates the LSB of ERR_COUNT you can just >rename the register as DP_FEC_ERR_COUNT_LSB So while reading you just pass >this register address and get LSB into a variable. Yes, good point. > >> + >> +#define DP_FEC_ERROR_COUNT_20x0282 >> +# define DP_FEC_ERR_COUNT_14_8(err_count) (err_count << 0) > >This could be DP_FEC_ERR_COUNT_MSB_MASK and SHIFT should be 8 since you >want to put this value at the 8th bit of a 16 bit value. This helps thanks! >> +# define DP_FEC_ERR_COUNT_VALID (1 << 7) > >Everything else looks good. Thanks Manasi. I will incorporate these changes in the next revision. Anusha >Manasi > >> + >> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ >> # define DP_PSR_IS_SUPPORTED1 >> # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ >> -- >> 2.7.4 >> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: add support for specifying DMC firmware override by module param
>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Jani Nikula >Sent: Wednesday, November 22, 2017 8:20 AM >To: Joonas Lahtinen <joonas.lahti...@linux.intel.com>; David Weinehall ><david.weineh...@linux.intel.com> >Cc: intel-gfx@lists.freedesktop.org >Subject: Re: [Intel-gfx] [PATCH] drm/i915: add support for specifying DMC >firmware override by module param > >On Wed, 22 Nov 2017, Joonas Lahtinen <joonas.lahti...@linux.intel.com> >wrote: >> On Tue, 2017-11-21 at 23:54 +0200, Jani Nikula wrote: >>> On Tue, 21 Nov 2017, David Weinehall <david.weineh...@linux.intel.com> >wrote: >>> > On Tue, Nov 21, 2017 at 01:51:29PM +0200, Jani Nikula wrote: >>> > > Use i915.dmc_firmware_path to override default firmware for the >>> > > platform and bypassing version checks. >>> > > >>> > > Signed-off-by: Jani Nikula <jani.nik...@intel.com> >>> > > >>> > > --- >>> > > >>> > > Untested. >>> > >>> > Yeah, it kind of shows. It fails to compile :D >>> >>> Oops. I was anxious to get the patch on the list in the heat of IRC >>> discussion, and just added the disclaimer instead of doing this >>> properly... *blush* >>> >>> > >>> > But if you chuck in: >>> > >>> > param(char *, dmc_firmware_path, NULL) \ >> >> I think I already raised my suggestion earlier, but here it goes again. >> Maybe we should consider consolidating these into: >> >> i915.firmware=guc:whatever.bin i915.firmware=dmc:whatever.bin > >I don't think that's possible. I didn't double check but I think you only get >one >value from the module param code. Unless you roll your own modparam hooks, >which is best avoided. > >> Then something like "i915.firmware=guc:disable" could be supported, >> too. > >i915.dmc_firmware_path="" could mean disable. > >BR, >Jani. > > >> >> Regards, Joonas >> >>> > >>> > in i915_params.h >>> > >>> > Things work correctly and you can use: >>> > >>> > Tested-by: David Weinehall <david.weineh...@linux.intel.com> >>> > Reviewed-by: David Weinehall <david.weineh...@linux.intel.com> >>> >>> Thanks. But let's wait for more input on whether this is really what >>> people want. Perhaps this is useful *regardless* of the outcome of >>> the other discussions. I believe this patch is going to be useful anyway IT would make things a lot easier for testing purpose. I think we should get this merged. Does anyone have any concerns? Anusha >>> BR, >>> Jani. >>> >>> >>> > >>> > > --- >>> > > drivers/gpu/drm/i915/i915_params.c | 3 +++ >>> > > drivers/gpu/drm/i915/intel_csr.c | 9 +++-- >>> > > 2 files changed, 10 insertions(+), 2 deletions(-) >>> > > >>> > > diff --git a/drivers/gpu/drm/i915/i915_params.c >>> > > b/drivers/gpu/drm/i915/i915_params.c >>> > > index 3328147b4863..c11ad6d67fa9 100644 >>> > > --- a/drivers/gpu/drm/i915/i915_params.c >>> > > +++ b/drivers/gpu/drm/i915/i915_params.c >>> > > @@ -171,6 +171,9 @@ i915_param_named_unsafe(guc_firmware_path, >>> > > charp, 0400, i915_param_named_unsafe(huc_firmware_path, charp, >0400, >>> > > "HuC firmware path to use instead of the default one"); >>> > > >>> > > +i915_param_named_unsafe(dmc_firmware_path, charp, 0400, >>> > > + "DMC firmware path to use instead of the default one"); >>> > > + >>> > > i915_param_named_unsafe(enable_dp_mst, bool, 0600, >>> > > "Enable multi-stream transport (MST) for new DisplayPort sinks. >>> > > (default: true)"); >>> > > >>> > > diff --git a/drivers/gpu/drm/i915/intel_csr.c >>> > > b/drivers/gpu/drm/i915/intel_csr.c >>> > > index 77d8b3d483ca..82db376ec7e1 100644 >>> > > --- a/drivers/gpu/drm/i915/intel_csr.c >>> > > +++ b/drivers/gpu/drm/i915/intel_csr.c >>> > > @@ -296,7 +296,10 @@ static uint32_t *parse_csr_fw(struct >>> > > drm_i915_private *dev_priv, >>> > > >>> > > csr->version = css_header->version; >>> > > >>> &g
[Intel-gfx] [PATCH] CNL DMC v1.07
Adding Pull Request to the cover letter. This is to trigger the CI systems and not the official Pull Request(which will be sent after ack from CI). The following changes since commit 2451bb228f6401ca3f2ecd498bf3bab613c532a7: linux-firmware: liquidio: add v1.7.0 vswitch firmware (2017-12-06 22:08:17 -0800) are available in the git repository at: https://github.com/anushasr/linux-firmware.git master for you to fetch changes up to cf9d4d63f87bf7c21a384d19b9af61d12153bbe9: linux-firmware: DMC firmware for Cannonlake v1.07 (2017-12-20 17:26:06 -0800) Anusha Srivatsa (1): linux-firmware: DMC firmware for Cannonlake v1.07 WHENCE | 3 +++ i915/cnl_dmc_ver1_07.bin | Bin 0 -> 11268 bytes 2 files changed, 3 insertions(+) create mode 100644 i915/cnl_dmc_ver1_07.bin P.S: Sending from private account, since fdo shared account is causing issues. (WIP) Anusha Srivatsa (1): drm/i915/dmc: DMC 1.07 for Cannonlake drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.07 for Cannonlake
There is a new version of DMC available for KBL. The release notes mentions: 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 7fe4aac0..ed256de 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -37,8 +37,8 @@ #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) +#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin" +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin" MODULE_FIRMWARE(I915_CSR_KBL); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cfl: Adding more Coffee Lake PCI IDs.
On Wed, Dec 20, 2017 at 10:29:19AM -0800, Rodrigo Vivi wrote:
> Spec has been updated with more reserved IDs for existent SKUs.
>
> Cc: Lucas De Marchi <lucas.demar...@intel.com>
> Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> Cc: Anuj Phogat <anuj.pho...@gmail.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
The IDs match with Spec.
Reviewed-by: Anusha Srivatsa<anusha.sriva...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> include/drm/i915_pciids.h | 28 ++--
> 2 files changed, 24 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index fa67d3dde20e..36d48422b475 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -633,6 +633,8 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_CFL_S_GT1_IDS(_coffeelake_gt1_info),
> INTEL_CFL_S_GT2_IDS(_coffeelake_gt2_info),
> INTEL_CFL_H_GT2_IDS(_coffeelake_gt2_info),
> + INTEL_CFL_U_GT1_IDS(_coffeelake_gt1_info),
> + INTEL_CFL_U_GT2_IDS(_coffeelake_gt2_info),
> INTEL_CFL_U_GT3_IDS(_coffeelake_gt3_info),
> INTEL_CNL_U_GT2_IDS(_cannonlake_gt2_info),
> INTEL_CNL_Y_GT2_IDS(_cannonlake_gt2_info),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index c65e4489006d..5db0458dd832 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -373,29 +373,45 @@
> /* CFL S */
> #define INTEL_CFL_S_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
> - INTEL_VGA_DEVICE(0x3E93, info) /* SRV GT1 */
> + INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
> + INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */
>
> #define INTEL_CFL_S_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
> INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */
> + INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
>
> /* CFL H */
> #define INTEL_CFL_H_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
> INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
>
> -/* CFL U */
> +/* CFL U GT1 */
> +#define INTEL_CFL_U_GT1_IDS(info) \
> + INTEL_VGA_DEVICE(0x3EA1, info), \
> + INTEL_VGA_DEVICE(0x3EA4, info)
> +
> +/* CFL U GT2 */
> +#define INTEL_CFL_U_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x3EA0, info), \
> + INTEL_VGA_DEVICE(0x3EA3, info), \
> + INTEL_VGA_DEVICE(0x3EA9, info)
> +
> +/* CFL U GT3 */
> #define INTEL_CFL_U_GT3_IDS(info) \
> + INTEL_VGA_DEVICE(0x3EA2, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
> INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
> INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x3EA5, info) /* ULT GT3 */
> + INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */
>
> -#define INTEL_CFL_IDS(info) \
> +#define INTEL_CFL_IDS(info) \
> INTEL_CFL_S_GT1_IDS(info), \
> INTEL_CFL_S_GT2_IDS(info), \
> INTEL_CFL_H_GT2_IDS(info), \
> + INTEL_CFL_U_GT1_IDS(info), \
> + INTEL_CFL_U_GT2_IDS(info), \
> INTEL_CFL_U_GT3_IDS(info)
>
> /* CNL U 2+2 */
> --
> 2.13.6
>
--
Anusha Srivatsa
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Re: [Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: Add horizontal flip subtest.
>-Original Message-
>From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
>Daniel
>Vetter
>Sent: Thursday, December 14, 2017 2:14 AM
>To: Srivatsa, Anusha <anusha.sriva...@intel.com>; Strano, Luis
><luis.str...@intel.com>; Latvala, Petri <petri.latv...@intel.com>; Lofstedt,
>Marta <marta.lofst...@intel.com>; Saarinen, Jani <jani.saari...@intel.com>
>Cc: intel-gfx <intel-gfx@lists.freedesktop.org>; Joseph Garvey
><joseph1.gar...@intel.com>
>Subject: Re: [Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: Add horizontal
>flip
>subtest.
>
>On Thu, Nov 23, 2017 at 12:05 AM, Anusha Srivatsa <anusha.sriva...@intel.com>
>wrote:
>> From: Joseph Garvey <joseph1.gar...@intel.com>
>>
>> Test that horizontal flip works with supported rotations. Includes a
>> fix for the unrotated fb which was not being positioned correctly with
>> portrait and landscape rectangles.
>>
>> v2:(from Anusha)
>> - Change 180 degree rotation to follow the rest, use igt_swap(), make
>> flip variable a bool. Format the patch correctly (Ville, Petri
>> Latvala)
>>
>> v3: (From Anusha)
>> - Correct the name of subtests in order to avoid duplication of names
>> (Arek)
>>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> Signed-off-by: Joseph Garvey <joseph1.gar...@intel.com>
>> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
>> Cc: Petri Latvala <petri.latv...@intel.com>
>> Cc: Arkadiusz Hiler <arkadiusz.hi...@intel.com>
>
>I didn't see this patch fly by originally, but now Marta pointed out that this
>skips
>everywhere. We need to rework it.
>
>General principle is that in kms tests we should _not_ have any
>platform/feature
>checks encoded in the test. Instead, the testcase should check properties to
>figure out whether something should work or not.
>
>
>> ---
>> lib/igt_kms.c| 2 +-
>> lib/igt_kms.h| 5 ++
>> tests/kms_rotation_crc.c | 198
>> +--
>> 3 files changed, 164 insertions(+), 41 deletions(-)
>>
>> diff --git a/lib/igt_kms.c b/lib/igt_kms.c index a572fc6..3034e44
>> 100644
>> --- a/lib/igt_kms.c
>> +++ b/lib/igt_kms.c
>> @@ -3050,7 +3050,7 @@ void igt_fb_set_size(struct igt_fb *fb,
>> igt_plane_t *plane,
>>
>> static const char *rotation_name(igt_rotation_t rotation) {
>> - switch (rotation) {
>> + switch (rotation & IGT_ROTATION_MASK) {
>> case IGT_ROTATION_0:
>> return "0°";
>> case IGT_ROTATION_90:
>> diff --git a/lib/igt_kms.h b/lib/igt_kms.h index 8dc118c..b83a828
>> 100644
>> --- a/lib/igt_kms.h
>> +++ b/lib/igt_kms.h
>> @@ -281,8 +281,13 @@ typedef enum {
>> IGT_ROTATION_90 = 1 << 1,
>> IGT_ROTATION_180 = 1 << 2,
>> IGT_ROTATION_270 = 1 << 3,
>> + IGT_REFLECT_X= 1 << 4,
>> + IGT_REFLECT_Y= 1 << 5,
>> } igt_rotation_t;
>>
>> +#define IGT_ROTATION_MASK \
>> + (IGT_ROTATION_0 | IGT_ROTATION_90 | IGT_ROTATION_180 |
>> +IGT_ROTATION_270)
>> +
>> typedef struct {
>> /*< private >*/
>> igt_pipe_t *pipe;
>> diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c index
>> 5aec8fa..9e13667 100644
>> --- a/tests/kms_rotation_crc.c
>> +++ b/tests/kms_rotation_crc.c
>> @@ -32,6 +32,7 @@ typedef struct {
>> igt_display_t display;
>> struct igt_fb fb;
>> struct igt_fb fb_reference;
>> + struct igt_fb fb_unrotated;
>> struct igt_fb fb_modeset;
>> struct igt_fb fb_flip;
>> igt_crc_t ref_crc;
>> @@ -43,8 +44,59 @@ typedef struct {
>> uint32_t override_fmt;
>> uint64_t override_tiling;
>> bool flips;
>> + int devid;
>> } data_t;
>>
>> +typedef struct {
>> + float r;
>> + float g;
>> + float b;
>> +} rgb_color_t;
>> +
>> +static void set_color(rgb_color_t *color, float r, float g, float b)
>> +{
>> + color->r = r;
>> + color->g = g;
>> + color->b = b;
>> +}
>> +
>> +static void rotate_colors(rgb_color_t *tl, rgb_color_t *tr, rgb_color_t *br,
>> + rgb_color_t *bl, igt_rotation_t rotation) {
>> + rgb_color_t bl_tmp, br_tmp, tl_tmp, tr_tmp;
>> +
>> + if (rotation &
Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, December 15, 2017 3:03 PM
>To: Wajdeczko, Michal <michal.wajdec...@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
><anusha.sriva...@intel.com>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
>
>On Fri, Dec 15, 2017 at 06:07:27AM +, Michal Wajdeczko wrote:
>> On Thu, 14 Dec 2017 23:30:56 +0100, Srivatsa, Anusha
>> <anusha.sriva...@intel.com> wrote:
>>
>> >
>> >
>> > > -Original Message-
>> > > From: Wajdeczko, Michal
>> > > Sent: Thursday, December 14, 2017 2:18 PM
>> > > To: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
>> > > <anusha.sriva...@intel.com>
>> > > Cc: Vivi, Rodrigo <rodrigo.v...@intel.com>
>> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC
>> > > on GLK
>> > >
>> > > On Thu, 14 Dec 2017 22:58:37 +0100, Anusha Srivatsa
>> > > <anusha.sriva...@intel.com> wrote:
>> > >
>> > > > Since the firmwares are released yet to public repo, disable
>> > > > them on Geminilake.
>> > > >
>> > > > Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
>> > > > Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> > > > ---
>> > > > drivers/gpu/drm/i915/i915_pci.c | 5 +
>> > > > 1 file changed, 5 insertions(+)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> > > > b/drivers/gpu/drm/i915/i915_pci.c index fa67d3d..ddf7530 100644
>> > > > --- a/drivers/gpu/drm/i915/i915_pci.c
>> > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
>> > > > @@ -521,6 +521,11 @@ static const struct intel_device_info
>> > > > intel_geminilake_info __initconst = {
>> > > >GEN9_LP_FEATURES,
>> > > >.platform = INTEL_GEMINILAKE,
>> > > >.ddb_size = 1024,
>> > > > + /* FIXME Geminilake supports GuC but currently firmwares
>> > > > + * have not made it to public repo. Lets disable the support
>> > > > + * as a temporary fix.
>> > > > + */
>> > > > + .has_guc = 0,
>> > >
>> > > Maybe better place to put this fix is __get_platform_enable_guc()
>> > > like in [1] [1] https://patchwork.freedesktop.org/patch/192006/
>> >
>> > Michal,
>> > Hmm the reference patch is controlling guc/huc through a module
>> > parameter but wont the above approach be neater platform wise?
>>
>> With your patch it would be impossible to check even preliminary
>> firmwares from non-public repo without recompilation of the driver.
>>
>> While with variant below it would just require changing modparams like:
>> enable_guc=1
>> guc_firmware_path=preliminary/glk.bin
>
>This is a fair point imo. With has_guc=0 you remove the possibility of testing
>preliminary GuC/HuC without a kernel patch...
>
>>
>> Note that auto mode (enable_guc=-1) will still keep GuC disabled for GLK.
>
>... but I believe that the main point here is that if we don't have a public
>image it
>doesn't exist from the upstream perspective.
Correct
>The ideal is not need this patch and releasing firmware sooner. I see same
>happening for all upcoming platforms...
>
>So, whatever we decide for this case needs to cover future cases as well.
I agree. While both the places discussed is good to make this change, I am
inclining towards making at the platform definition level. I do need more
feedback on this since we want that to be the norm moving forward.
Anusha
>Thanks,
>Rodrigo.
>
>>
>> Michal
>>
>> >
>> > Anusha
>> > > diff --git a/drivers/gpu/drm/i915/intel_uc.c
>> > > b/drivers/gpu/drm/i915/intel_uc.c index 49bccc9..22b0afe 100644
>> > > --- a/drivers/gpu/drm/i915/intel_uc.c
>> > > +++ b/drivers/gpu/drm/i915/intel_uc.c
>> > > @@ -60,6 +60,8 @@ static int __get_platform_enable_guc(struct
>> > > drm_i915_private *dev_priv)
>> > > enable_guc |= ENABLE_GUC_LOAD_HUC;
>> > >
>> > > /* Any platform specific fine-tuning can be done here */
>> > > +if (IS_GEMINILAKE(dev_priv))
>> > > +enable_guc = 0; /* no firmware on CI machines */
>> > >
>> > > return enable_guc;
>> > > }
>> > >
>> > >
>> > > >GLK_COLORS,
>> > > > };
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Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
>-Original Message-
>From: Wajdeczko, Michal
>Sent: Thursday, December 14, 2017 2:18 PM
>To: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
><anusha.sriva...@intel.com>
>Cc: Vivi, Rodrigo <rodrigo.v...@intel.com>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
>
>On Thu, 14 Dec 2017 22:58:37 +0100, Anusha Srivatsa
><anusha.sriva...@intel.com> wrote:
>
>> Since the firmwares are released yet to public repo, disable them on
>> Geminilake.
>>
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_pci.c | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> b/drivers/gpu/drm/i915/i915_pci.c index fa67d3d..ddf7530 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -521,6 +521,11 @@ static const struct intel_device_info
>> intel_geminilake_info __initconst = {
>> GEN9_LP_FEATURES,
>> .platform = INTEL_GEMINILAKE,
>> .ddb_size = 1024,
>> +/* FIXME Geminilake supports GuC but currently firmwares
>> + * have not made it to public repo. Lets disable the support
>> + * as a temporary fix.
>> + */
>> +.has_guc = 0,
>
>Maybe better place to put this fix is __get_platform_enable_guc() like in [1]
>[1]
>https://patchwork.freedesktop.org/patch/192006/
Michal,
Hmm the reference patch is controlling guc/huc through a module parameter
but wont the above approach be neater platform wise?
Anusha
>diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
>index 49bccc9..22b0afe 100644
>--- a/drivers/gpu/drm/i915/intel_uc.c
>+++ b/drivers/gpu/drm/i915/intel_uc.c
>@@ -60,6 +60,8 @@ static int __get_platform_enable_guc(struct
>drm_i915_private *dev_priv)
> enable_guc |= ENABLE_GUC_LOAD_HUC;
>
> /* Any platform specific fine-tuning can be done here */
>+ if (IS_GEMINILAKE(dev_priv))
>+ enable_guc = 0; /* no firmware on CI machines */
>
> return enable_guc;
> }
>
>
>> GLK_COLORS,
>> };
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[Intel-gfx] [PATCH] drm/i915/glk: Disable Guc and HuC on GLK
Since the firmwares are released yet to public repo,
disable them on Geminilake.
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fa67d3d..ddf7530 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -521,6 +521,11 @@ static const struct intel_device_info
intel_geminilake_info __initconst = {
GEN9_LP_FEATURES,
.platform = INTEL_GEMINILAKE,
.ddb_size = 1024,
+ /* FIXME Geminilake supports GuC but currently firmwares
+* have not made it to public repo. Lets disable the support
+* as a temporary fix.
+*/
+ .has_guc = 0,
GLK_COLORS,
};
--
2.7.4
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Re: [Intel-gfx] [IGT] IGT/tests/firmware: Test firmware loading by reading debugfs
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, December 1, 2017 2:33 PM
>To: Srivatsa, Anusha <anusha.sriva...@intel.com>
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [IGT] IGT/tests/firmware: Test firmware loading by reading debugfs
>
>On Fri, Dec 01, 2017 at 09:40:35PM +, Anusha Srivatsa wrote:
>> Read debugfs and sysfs entries to check for GuC loading conditions.
>>
>> The patch is still WIP. Once all check conditions are covered, it can
>> be extended to huc debugfs file too.
>>
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> ---
>> tests/Makefile.sources | 1 +
>> tests/test_firmware.c | 96
>> ++
>> 2 files changed, 97 insertions(+)
>> create mode 100644 tests/test_firmware.c
>>
>> diff --git a/tests/Makefile.sources b/tests/Makefile.sources index
>> 0f4e39a..841fc54 100644
>> --- a/tests/Makefile.sources
>> +++ b/tests/Makefile.sources
>> @@ -234,6 +234,7 @@ TESTS_progs = \
>> template \
>> tools_test \
>> vgem_basic \
>> +test_firmware \
>
>note that igt tests names are meaningful... _
>
>so probably better to use fw_basic
OK... fw_basic or fw_debugfs?
>> vgem_slow \
>
>and also they are more or less sorted out here...
>but you added on the middle of a vgem group...
Oops will change the order.
>> $(NULL)
>>
>> diff --git a/tests/test_firmware.c b/tests/test_firmware.c new file
>> mode 100644 index 000..a5d621a
>> --- /dev/null
>> +++ b/tests/test_firmware.c
>> @@ -0,0 +1,96 @@
>> +/*
>> + * Copyright (c) 2013 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person
>> +obtaining a
>> + * copy of this software and associated documentation files (the
>> +"Software"),
>> + * to deal in the Software without restriction, including without
>> +limitation
>> + * the rights to use, copy, modify, merge, publish, distribute,
>> +sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom
>> +the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including
>> +the next
>> + * paragraph) shall be included in all copies or substantial portions
>> +of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> +EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> +MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
>EVENT
>> +SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
>DAMAGES
>> +OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> +ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> +OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + * Authors: Anusha Srivatsa
>> + *
>> + */
>> +
>> +#include "igt.h"
>> +#include "stdio.h"
>> +#include "stdlib.h"
>> +#include "igt_sysfs.h"
>> +#include "igt_debugfs.h"
>> +#include "i915_drm.h"
>> +#include "fcntl.h"
>> +
>> +IGT_TEST_DESCRIPTION("Read contents of debugfs to check for firmware
>> +status.");
>> +
>> +static void guc_load(int drm_fd, int debugfs, int gen) {
>> +char firmware_buf[250];
>> +float fw_version_wanted;
>> +float fw_version_found;
>> +int ret;
>> +int enable_guc_loading;
>> +FILE *fp;
>> +
>> +igt_skip_on_f(gen < 6,
>> + "GuC not available on platforms prior to Skylake\n");
>> +
>> +igt_sysfs_scanf(debugfs, "i915_enable_guc_loading", "%d",
>_guc_loading);
>> +igt_skip_on_f(!(enable_guc_loading < 1), "GuC loading not
>> +enabled\n");
>> +
>> +ret = igt_debugfs_open(drm_fd, "i915_guc_load_status", O_RDONLY);
>> +fp = fdopen(ret, "r");
>> +igt_fail_on_f(ret < 0, "Not able to open the debugfs file\n");
>> +
>> +igt_debugfs_read(drm_fd, "i915_guc_load_status", firmware_buf);
>> +
>> +fseek(fp, 99, SEEK_CUR);
>
>This is risky/fragile imo... any small change on debugfs this will break...
I agree totall
Re: [Intel-gfx] linux-firmware pull request(SKL:DMC)
>-Original Message- >From: Josh Boyer [mailto:jwbo...@kernel.org] >Sent: Monday, December 4, 2017 6:37 AM >To: Srivatsa, Anusha <anusha.sriva...@intel.com> >Cc: linux-firmw...@kernel.org; Intel Graphics Development g...@lists.freedesktop.org>; Ben Hutchings <b...@decadent.org.uk>; Kyle >McMartin <k...@kernel.org> >Subject: Re: linux-firmware pull request(SKL:DMC) > >On Mon, Nov 27, 2017 at 6:13 PM, Anusha Srivatsa <anusha.sriva...@intel.com> >wrote: >> Hi Ben, Kyle, >> >> Please consider pulling i915 updates to linux-firmware.git. >> >> i915-firmware-2017-11-27 >> The following changes since commit >17e6288135d4500f9fe60224dce2b46d850c346b: >> >> brcm: update firmware for bcm4358 (2017-11-25 10:15:53 -0500) >> >> are available in the git repository at: >> >> ssh://git.freedesktop.org/git/drm/drm-firmware.git master >> >> for you to fetch changes up to 02d857ee316f6f611b6622ef78892d38d0909700: >> >> linux-firmware: DMC firmware for skylake v1.27 (2017-11-27 14:36:28 >> -0800) >> >> >> Anusha Srivatsa (1): >> linux-firmware: DMC firmware for skylake v1.27 >> >> WHENCE | 3 ++- >> i915/skl_dmc_ver1_27.bin | Bin 0 -> 8928 bytes >> 2 files changed, 2 insertions(+), 1 deletion(-) create mode 100644 >> i915/skl_dmc_ver1_27.bin > >Merged. Thanks! Thanks a lot Josh! Anusha >josh ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [IGT] IGT/tests/firmware: Test firmware loading by reading debugfs
Read debugfs and sysfs entries to check for GuC
loading conditions.
The patch is still WIP. Once all check conditions are
covered, it can be extended to huc debugfs file too.
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
tests/Makefile.sources | 1 +
tests/test_firmware.c | 96 ++
2 files changed, 97 insertions(+)
create mode 100644 tests/test_firmware.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 0f4e39a..841fc54 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -234,6 +234,7 @@ TESTS_progs = \
template \
tools_test \
vgem_basic \
+ test_firmware \
vgem_slow \
$(NULL)
diff --git a/tests/test_firmware.c b/tests/test_firmware.c
new file mode 100644
index 000..a5d621a
--- /dev/null
+++ b/tests/test_firmware.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors: Anusha Srivatsa
+ *
+ */
+
+#include "igt.h"
+#include "stdio.h"
+#include "stdlib.h"
+#include "igt_sysfs.h"
+#include "igt_debugfs.h"
+#include "i915_drm.h"
+#include "fcntl.h"
+
+IGT_TEST_DESCRIPTION("Read contents of debugfs to check for firmware status.");
+
+static void guc_load(int drm_fd, int debugfs, int gen)
+{
+ char firmware_buf[250];
+ float fw_version_wanted;
+ float fw_version_found;
+ int ret;
+ int enable_guc_loading;
+ FILE *fp;
+
+ igt_skip_on_f(gen < 6,
+ "GuC not available on platforms prior to Skylake\n");
+
+ igt_sysfs_scanf(debugfs, "i915_enable_guc_loading", "%d",
_guc_loading);
+ igt_skip_on_f(!(enable_guc_loading < 1), "GuC loading not enabled\n");
+
+ ret = igt_debugfs_open(drm_fd, "i915_guc_load_status", O_RDONLY);
+ fp = fdopen(ret, "r");
+ igt_fail_on_f(ret < 0, "Not able to open the debugfs file\n");
+
+ igt_debugfs_read(drm_fd, "i915_guc_load_status", firmware_buf);
+
+ fseek(fp, 99, SEEK_CUR);
+ fscanf(fp, "%f", _version_wanted);
+ fseek(fp, 119, SEEK_SET);
+ fscanf(fp, "%f", _version_found);
+
+ igt_fail_on_f((fw_version_wanted != fw_version_found),
+ "Firmware version found not the version wanted\n");
+ igt_fail_on_f(strstr(firmware_buf, "fetch: NONE"),
+ "Firmware not fetched\n");
+ igt_fail_on_f(strstr(firmware_buf, "fetch: SUCCESS") &&
+ strstr(firmware_buf, "load: NONE "),
+ "Firmware not loaded\n");
+}
+
+int drm_fd;
+int debugfs;
+int gen;
+
+igt_main
+{
+ igt_skip_on_simulation();
+ igt_fixture {
+ drm_fd = drm_open_driver(DRIVER_INTEL);
+ igt_require(drm_fd >= 0);
+
+ debugfs = igt_debugfs_dir(drm_fd);
+ gen = intel_gen(intel_get_drm_devid(drm_fd));
+ }
+
+ igt_subtest("guc-load-test")
+ guc_load(drm_fd, debugfs, gen);
+
+ igt_success();
+
+ igt_fixture {
+ close(debugfs);
+ close(drm_fd);
+ }
+}
--
2.7.4
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Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/guc: Change default GuC FW for SKL to v9.33
>-Original Message- >From: Kamble, Sagar A >Sent: Wednesday, November 29, 2017 8:19 AM >To: intel-gfx@lists.freedesktop.org >Cc: Kamble, Sagar A <sagar.a.kam...@intel.com>; Mcgee, Jeff ><jeff.mc...@intel.com>; Spotswood, John A <john.a.spotsw...@intel.com>; >Srivatsa, Anusha <anusha.sriva...@intel.com>; Wajdeczko, Michal ><michal.wajdec...@intel.com>; Vivi, Rodrigo <rodrigo.v...@intel.com>; Joonas >Lahtinen <joonas.lahti...@linux.intel.com> >Subject: [PATCH v2 1/3] drm/i915/guc: Change default GuC FW for SKL to v9.33 > >This patch makes v9.33 firmware as default firmware for SKL. > >Note: GuC logging control is changed with this firmware. GuC is expecting i915 >to >set control bit to enable "default logging" >while using GuC action UK_LOG_ENABLE_LOGGING. >However i915 is currently not doing this because it is version specific change >and >can be handled entirely in GuC. It will need to be fixed in future firmwares. > >This update includes (since v6.1): > >- HuC RSA Keys updated. >- Adding per engine preemption support in GuC scheduler >- Minor bug fixes. >- Added support to log media reset count for host to read it >- Sub-feature level control for power management features. >- Minor clean-up for power management interface. >- Unified power management interface and scheduler interface into > 1 file using same version. >- Bug Fix for multi context scheduler flag. >- DCC spec changes for BXT + DCT enabling >- SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC >- Moving GuC non_critical r/w data to lower SRAM 64KB >- Media engine Reset fix. Correctly marking context for resubmission in > Media Reset case. >- ABT Disable bug fix. Disabled Evaluation mode on context change. >- Async FW in Engine Schedule feature (not enabled from KMD) >- GuC clean up to align developer build in line to production build. >- DCC consistency fix for SKL >- Disable ARAT interrupt before programming ARAT delta. >- Memory range check in Parse to avoid failure due to overflow. >- Enabled WA for MSGCH hang issue >- Clear forcewake in CSB when SQ is empty. >- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. >- This is file location change.No functional change done as part of this > check in. >- Enable decoupled freq for SKL GT4 >- 3 tries of wake request needed from GuC2CSME for ME to wake up. Request > has come from ME spec >- During reset one parameter was not getting accounted >- Enabling Guc Log changes for ultra low logging for OCA >- Enabling build failure check to catch critical section overflow. >- Disable build.bat redundant prints. >- Move few least used functions to non-critical section. >- Rearrange GuC documentation folder structure. >- Synchronize SLPC internal debug interface with other branches. >- Fixing Issue with Default Guc Log changes for OCA using special Control > Bit > >v2: Rebase. Updated commit message. > >Signed-off-by: Jeff McGee <jeff.mc...@intel.com> >Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> >Cc: Spotswood John A <john.a.spotsw...@intel.com> >Cc: Anusha Srivatsa <anusha.sriva...@intel.com> >Cc: Michal Wajdeczko <michal.wajdec...@intel.com> >Cc: Rodrigo Vivi <rodrigo.v...@intel.com> >Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Reviewed-by: Anusha Srivatsa <anusha.sriva...@intel.com> > drivers/gpu/drm/i915/intel_guc_fw.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c >b/drivers/gpu/drm/i915/intel_guc_fw.c >index bbab4e1..631e932 100644 >--- a/drivers/gpu/drm/i915/intel_guc_fw.c >+++ b/drivers/gpu/drm/i915/intel_guc_fw.c >@@ -30,8 +30,8 @@ > #include "intel_guc_fw.h" > #include "i915_drv.h" > >-#define SKL_FW_MAJOR 6 >-#define SKL_FW_MINOR 1 >+#define SKL_FW_MAJOR 9 >+#define SKL_FW_MINOR 33 > > #define BXT_FW_MAJOR 8 > #define BXT_FW_MINOR 7 >-- >1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/guc: Change default GuC FW for BXT to v9.29
>-Original Message- >From: Kamble, Sagar A >Sent: Wednesday, November 29, 2017 8:19 AM >To: intel-gfx@lists.freedesktop.org >Cc: Kamble, Sagar A <sagar.a.kam...@intel.com>; Mcgee, Jeff ><jeff.mc...@intel.com>; Spotswood, John A <john.a.spotsw...@intel.com>; >Srivatsa, Anusha <anusha.sriva...@intel.com>; Wajdeczko, Michal ><michal.wajdec...@intel.com>; Vivi, Rodrigo <rodrigo.v...@intel.com>; Joonas >Lahtinen <joonas.lahti...@linux.intel.com> >Subject: [PATCH v2 2/3] drm/i915/guc: Change default GuC FW for BXT to v9.29 > >This patch makes v9.29 firmware as default firmware for BXT. > >Note: GuC logging control is changed with this firmware. GuC is expecting i915 >to >set control bit to enable "default logging" >while using GuC action UK_LOG_ENABLE_LOGGING. >However i915 is currently not doing this because it is version specific change >and >can be handled entirely in GuC. It will need to be fixed in future firmwares. > >This update includes (since v8.7): > >- Added support to log media reset count for host to read it >- BXT WA for fixing MTP hangs. WaDisableDOPRenderClkGatingAtSubmit >- Sub-feature level control for power management features. >- Minor clean-up for power management interface. >- Unified power management interface and scheduler interface into > 1 file using same version. >- Bug Fix for multi context scheduler flag. >- DCC spec changes for BXT + DCT enabling >- Springboard based Pre-ETM/ETM flow enabling for debug signed GuC/HuC >- Moving GuC non_critical r/w data to lower SRAM 64KB >- Enabled IBC for BXT >- Media engine Reset fix. Correctly marking context for resubmission in > Media Reset case. >- SLPC Dynamic RPe fix to resolve issues where incorrect frequency was set. >- ABT Disable bug fix. Disabled Evaluation mode on context change. >- GuC clean up to align developer build in line to production build. >- Disable ARAT interrupt before programming ARAT delta. >- Memory range check in Parse to avoid failure due to overflow. >- Clear forcewake in CSB when SQ is empty. >- SLPC IBC 1.6 for APL to ensure multiplier does not cap IA below Pe. >- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. >- This is file location change. No functional change done as part of this > check in. >- 3 tries of wake request needed from GuC2CSME for ME to wake up. Request > has come from ME spec >- During reset one parameter was not getting accounted >- Enabling Guc Log changes for ultra low logging for OCA >- Disable build.bat redundant prints. >- Move few least used functions to non-critical section. >- Rearrange GuC documentation folder structure. >- Fixing Issue with Default Guc Log changes for OCA using special Control > Bit > >v2: Rebase. Updated commit message. > >Signed-off-by: Jeff McGee <jeff.mc...@intel.com> >Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> >Cc: Spotswood John A <john.a.spotsw...@intel.com> >Cc: Anusha Srivatsa <anusha.sriva...@intel.com> >Cc: Michal Wajdeczko <michal.wajdec...@intel.com> >Cc: Rodrigo Vivi <rodrigo.v...@intel.com> >Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Reviewed-by: Anusha Srivatsa <anusha.sriva...@intel.com> > drivers/gpu/drm/i915/intel_guc_fw.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c >b/drivers/gpu/drm/i915/intel_guc_fw.c >index 631e932..df2ff96 100644 >--- a/drivers/gpu/drm/i915/intel_guc_fw.c >+++ b/drivers/gpu/drm/i915/intel_guc_fw.c >@@ -33,8 +33,8 @@ > #define SKL_FW_MAJOR 9 > #define SKL_FW_MINOR 33 > >-#define BXT_FW_MAJOR 8 >-#define BXT_FW_MINOR 7 >+#define BXT_FW_MAJOR 9 >+#define BXT_FW_MINOR 29 > > #define KBL_FW_MAJOR 9 > #define KBL_FW_MINOR 14 >-- >1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/guc: Change default GuC FW for KBL to v9.39
>-Original Message- >From: Kamble, Sagar A >Sent: Wednesday, November 29, 2017 8:19 AM >To: intel-gfx@lists.freedesktop.org >Cc: Kamble, Sagar A <sagar.a.kam...@intel.com>; Mcgee, Jeff ><jeff.mc...@intel.com>; Spotswood, John A <john.a.spotsw...@intel.com>; >Srivatsa, Anusha <anusha.sriva...@intel.com>; Wajdeczko, Michal ><michal.wajdec...@intel.com>; Vivi, Rodrigo <rodrigo.v...@intel.com>; Joonas >Lahtinen <joonas.lahti...@linux.intel.com> >Subject: [PATCH v2 3/3] drm/i915/guc: Change default GuC FW for KBL to v9.39 > >This patch makes v9.39 firmware as default firmware for KBL. > >Note: GuC logging control is changed with this firmware. GuC is expecting i915 >to >set control bit to enable "default logging" >while using GuC action UK_LOG_ENABLE_LOGGING. >However i915 is currently not doing this because it is version specific change >and >can be handled entirely in GuC. It will need to be fixed in future firmwares. > >This update includes (since v9.14): > >- DCC spec changes for BXT + DCT enabling >- Bug Fix for power conservation feature SLPC_DCC >- Scheduler 1-element submission during DCC cycles. >- SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC >- Moving GuC non_critical r/w data to lower SRAM 64KB >- Media engine Reset fix. Correctly marking context for resubmission in > Media Reset case. >- ABT Disable bug fix. Disabled Evaluation mode on context change. >- Async FW in Engine Schedule feature (not enabled from KMD) >- GuC clean up to align developer build in line to production build. >- Disable ARAT interrupt before programming ARAT delta. >- Memory range check in Parse to avoid failure due to overflow. >- GuC Msg Channel Hang WA - Stall GUC for mmio access when IDI is low > during CPD flow. >- Fix for submit queue over flow issue >- Enabling IBC on KBL GT3 15W, GT4 45W >- Disabling wrong device ID WA in production signed kernel >- Enabling WA for MSGCH hang issue upto required KBL stepping >- Clear forcewake in CSB when SQ is empty. >- 3Tries of GuC2CSME wake request >- During reset one parameter was not getting accounted >- Disable DCC 1-elem mode submission >- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. >- This is file location change.No functional change done as part of this > check in. >- Enabling Guc Log changes for ultra low logging for OCA >- Enabling Dynamic Render Power Well Hysteresis Programming for Compute > Worklaods >- Enabling build failure check to catch critical section overflow. >- Disable build.bat redundant prints. >- Move few least used functions to non-critical section. >- Rearrange GuC documentation folder structure. >- Synchronize SLPC internal debug interface with other branches. >- Fixing Issue with Default Guc Log changes for OCA using special Control > Bit >- Aggressive DCC implementation for supported platforms. > >v2: Rebase. Updated commit message. > >Signed-off-by: Jeff McGee <jeff.mc...@intel.com> >Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> >Cc: Spotswood John A <john.a.spotsw...@intel.com> >Cc: Anusha Srivatsa <anusha.sriva...@intel.com> >Cc: Michal Wajdeczko <michal.wajdec...@intel.com> >Cc: Rodrigo Vivi <rodrigo.v...@intel.com> >Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Reviewed-by: Anusha Srivatsa<anusha.sriva...@intel.com > > drivers/gpu/drm/i915/intel_guc_fw.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c >b/drivers/gpu/drm/i915/intel_guc_fw.c >index df2ff96..89862fa 100644 >--- a/drivers/gpu/drm/i915/intel_guc_fw.c >+++ b/drivers/gpu/drm/i915/intel_guc_fw.c >@@ -37,7 +37,7 @@ > #define BXT_FW_MINOR 29 > > #define KBL_FW_MAJOR 9 >-#define KBL_FW_MINOR 14 >+#define KBL_FW_MINOR 39 > > #define GLK_FW_MAJOR 10 > #define GLK_FW_MINOR 56 >-- >1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: Add horizontal flip subtest.
>-Original Message-
>From: Latvala, Petri
>Sent: Wednesday, November 29, 2017 1:55 AM
>To: Srivatsa, Anusha <anusha.sriva...@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Joseph Garvey <joseph1.gar...@intel.com>;
>Ville Syrjälä <ville.syrj...@linux.intel.com>; Hiler, Arkadiusz
><arkadiusz.hi...@intel.com>
>Subject: Re: [PATCH i-g-t] igt/kms_rotation_crc: Add horizontal flip subtest.
>
>On Wed, Nov 22, 2017 at 03:05:55PM -0800, Anusha Srivatsa wrote:
>> From: Joseph Garvey <joseph1.gar...@intel.com>
>>
>> Test that horizontal flip works with supported rotations. Includes a
>> fix for the unrotated fb which was not being positioned correctly with
>> portrait and landscape rectangles.
>>
>> v2:(from Anusha)
>> - Change 180 degree rotation to follow the rest, use igt_swap(), make
>> flip variable a bool. Format the patch correctly (Ville, Petri
>> Latvala)
>>
>> v3: (From Anusha)
>> - Correct the name of subtests in order to avoid duplication of names
>> (Arek)
>>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> Signed-off-by: Joseph Garvey <joseph1.gar...@intel.com>
>> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
>> Cc: Petri Latvala <petri.latv...@intel.com>
>> Cc: Arkadiusz Hiler <arkadiusz.hi...@intel.com>
>> ---
>> lib/igt_kms.c| 2 +-
>> lib/igt_kms.h| 5 ++
>> tests/kms_rotation_crc.c | 198
>> +--
>> 3 files changed, 164 insertions(+), 41 deletions(-)
>>
>> diff --git a/lib/igt_kms.c b/lib/igt_kms.c index a572fc6..3034e44
>> 100644
>> --- a/lib/igt_kms.c
>> +++ b/lib/igt_kms.c
>> @@ -3050,7 +3050,7 @@ void igt_fb_set_size(struct igt_fb *fb,
>> igt_plane_t *plane,
>>
>> static const char *rotation_name(igt_rotation_t rotation) {
>> -switch (rotation) {
>> +switch (rotation & IGT_ROTATION_MASK) {
>> case IGT_ROTATION_0:
>> return "0°";
>> case IGT_ROTATION_90:
>> diff --git a/lib/igt_kms.h b/lib/igt_kms.h index 8dc118c..b83a828
>> 100644
>> --- a/lib/igt_kms.h
>> +++ b/lib/igt_kms.h
>> @@ -281,8 +281,13 @@ typedef enum {
>> IGT_ROTATION_90 = 1 << 1,
>> IGT_ROTATION_180 = 1 << 2,
>> IGT_ROTATION_270 = 1 << 3,
>> +IGT_REFLECT_X= 1 << 4,
>> +IGT_REFLECT_Y= 1 << 5,
>> } igt_rotation_t;
>>
>> +#define IGT_ROTATION_MASK \
>> +(IGT_ROTATION_0 | IGT_ROTATION_90 | IGT_ROTATION_180 |
>> +IGT_ROTATION_270)
>> +
>> typedef struct {
>> /*< private >*/
>> igt_pipe_t *pipe;
>> diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c index
>> 5aec8fa..9e13667 100644
>> --- a/tests/kms_rotation_crc.c
>> +++ b/tests/kms_rotation_crc.c
>> @@ -32,6 +32,7 @@ typedef struct {
>> igt_display_t display;
>> struct igt_fb fb;
>> struct igt_fb fb_reference;
>> +struct igt_fb fb_unrotated;
>> struct igt_fb fb_modeset;
>> struct igt_fb fb_flip;
>> igt_crc_t ref_crc;
>> @@ -43,8 +44,59 @@ typedef struct {
>> uint32_t override_fmt;
>> uint64_t override_tiling;
>> bool flips;
>> +int devid;
>> } data_t;
>>
>> +typedef struct {
>> +float r;
>> +float g;
>> +float b;
>> +} rgb_color_t;
>> +
>> +static void set_color(rgb_color_t *color, float r, float g, float b)
>> +{
>> +color->r = r;
>> +color->g = g;
>> +color->b = b;
>> +}
>> +
>> +static void rotate_colors(rgb_color_t *tl, rgb_color_t *tr, rgb_color_t *br,
>> + rgb_color_t *bl, igt_rotation_t rotation) {
>> +rgb_color_t bl_tmp, br_tmp, tl_tmp, tr_tmp;
>> +
>> +if (rotation & IGT_REFLECT_X) {
>> +igt_swap(*tl, *tr);
>> +igt_swap(*bl, *br);
>> +}
>> +
>> +if (rotation & IGT_ROTATION_90) {
>> +bl_tmp = *bl;
>> +br_tmp = *br;
>> +tl_tmp = *tl;
>> +tr_tmp = *tr;
>> +*tl = tr_tmp;
>> +*bl = tl_tmp;
>> +*tr = br_tmp;
>> +*br = bl_tmp;
>> +} else if (rotation & IGT_ROTATION_180) {
>> +igt_swap(*tl, *br);
>> +igt_swap(*tr, *bl);
>> +} else if (rotation & IGT_ROTATION_270) {
>> +bl_tmp = *bl;
Re: [Intel-gfx] [PATCH v2 0/3] drm/i915/guc: Update default GuC FW for SKL/BXT/KBL
>-Original Message- >From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] >Sent: Tuesday, November 28, 2017 11:11 PM >To: Kamble, Sagar A <sagar.a.kam...@intel.com>; intel- >g...@lists.freedesktop.org >Cc: Spotswood, John A <john.a.spotsw...@intel.com>; Srivatsa, Anusha ><anusha.sriva...@intel.com>; Wajdeczko, Michal ><michal.wajdec...@intel.com>; Vivi, Rodrigo <rodrigo.v...@intel.com> >Subject: Re: [PATCH v2 0/3] drm/i915/guc: Update default GuC FW for >SKL/BXT/KBL > >On Wed, 2017-11-29 at 11:47 +0530, Sagar Arun Kamble wrote: >> With new GuC firmwares (SKL v9.33, BXT v9.29, KBL v9.39) available now >> at 01.org downloads, let us update the default firmware versions. > >I thought the agreement was for them to be at linux-firmware repo? Yes. @Sagar, slight change in commit message would be nice. Mention - linux-firware.git (since firmware is already merged there and that will be the one main point to find blobs moving forward) instead of 01.org. Anusha >Regards, Joonas >-- >Joonas Lahtinen >Open Source Technology Center >Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature
>-Original Message- >From: Jani Nikula [mailto:jani.nik...@linux.intel.com] >Sent: Wednesday, November 22, 2017 11:15 PM >To: Srivatsa, Anusha <anusha.sriva...@intel.com>; intel- >g...@lists.freedesktop.org >Cc: Srivatsa, Anusha <anusha.sriva...@intel.com>; Ville Syrjala ><ville.syrj...@linux.intel.com>; Navare, Manasi D <manasi.d.nav...@intel.com> >Subject: Re: [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature > >On Wed, 22 Nov 2017, Anusha Srivatsa <anusha.sriva...@intel.com> wrote: >> Forward Error Correction is supported on DP 1.4. >> This patch adds corresponding DPCD register definitions. > >Needs to be posted on dri-devel. Sent to dri-devel too. Thanks Jani. Anusha >BR, >Jani. > > >> >> Cc: Ville Syrjala <ville.syrj...@linux.intel.com> >> Cc: Jani Nikula <jani.nik...@linux.intel.com> >> Cc: Manasi Navare <manasi.d.nav...@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> >> --- >> include/drm/drm_dp_helper.h | 29 + >> 1 file changed, 29 insertions(+) >> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >> index 9049ef1..b0eee16 100644 >> --- a/include/drm/drm_dp_helper.h >> +++ b/include/drm/drm_dp_helper.h >> @@ -284,6 +284,35 @@ >> # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 >> # define DP_DSC_BITS_PER_PIXEL_10x4 >> >> +/* DP Forward error Correction Registers */ >> +#define DP_FEC_CAPABILITY 0x090 >> +# define DP_FEC_CAPABLE (1 << 0) >> +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) >> +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2) >> +# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) >> + >> +#define DP_FEC_CONFIGURATION0x120 >> +# define DP_FEC_READY (1 << 0) >> +# define DP_FEC_ERR_COUNT_DIS (0 << 1) >> +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) >> +# define DP_FEC_CORR_BLK_ERROR_COUNT(2 << 1) >> +# define DP_FEC_BIT_ERROR_COUNT (3 << 1) >> +# define DP_FEC_LANE_0_SELECT (0 << 4) >> +# define DP_FEC_LANE_1_SELECT (1 << 4) >> +# define DP_FEC_LANE_2_SELECT (2 << 4) >> +# define DP_FEC_LANE_3_SELECT (3 << 4) >> + >> +#define DP_FEC_STATUS 0x280 >> +# define DP_FEC_EN_DETECTED (1 << 0) >> +# define DP_FEC_DEC_DETECTED(1 << 1) >> + >> +#define DP_FEC_ERROR_COUNT_10x0281 >> +# define DP_FEC_ERR_COUNT_7_0(err_count)(err_count << 0) >> + >> +#define DP_FEC_ERROR_COUNT_20x0282 >> +# define DP_FEC_ERR_COUNT_14_8(err_count) (err_count << 0) >> +# define DP_FEC_ERR_COUNT_VALID (1 << 7) >> + >> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ >> # define DP_PSR_IS_SUPPORTED1 >> # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ > >-- >Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature
Forward Error Correction is supported on DP 1.4. This patch adds corresponding DPCD register definitions. v2: Add dri-devel to the CC list Cc: dri-de...@lists.freedesktop.org Cc: Ville Syrjala <ville.syrj...@linux.intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Cc: Manasi Navare <manasi.d.nav...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- include/drm/drm_dp_helper.h | 29 + 1 file changed, 29 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index da58a42..bc816ea 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -284,6 +284,35 @@ # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 # define DP_DSC_BITS_PER_PIXEL_10x4 +/* DP Forward error Correction Registers */ +#define DP_FEC_CAPABILITY 0x090 +# define DP_FEC_CAPABLE(1 << 0) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2) +# define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3) + +#define DP_FEC_CONFIGURATION 0x120 +# define DP_FEC_READY (1 << 0) +# define DP_FEC_ERR_COUNT_DIS (0 << 1) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) +# define DP_FEC_BIT_ERROR_COUNT(3 << 1) +# define DP_FEC_LANE_0_SELECT (0 << 4) +# define DP_FEC_LANE_1_SELECT (1 << 4) +# define DP_FEC_LANE_2_SELECT (2 << 4) +# define DP_FEC_LANE_3_SELECT (3 << 4) + +#define DP_FEC_STATUS 0x280 +# define DP_FEC_EN_DETECTED(1 << 0) +# define DP_FEC_DEC_DETECTED (1 << 1) + +#define DP_FEC_ERROR_COUNT_1 0x0281 +# define DP_FEC_ERR_COUNT_7_0(err_count)(err_count << 0) + +#define DP_FEC_ERROR_COUNT_2 0x0282 +# define DP_FEC_ERR_COUNT_14_8(err_count) (err_count << 0) +# define DP_FEC_ERR_COUNT_VALID(1 << 7) + #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED1 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] linux-firmware pull request(SKL:DMC)
Hi Ben, Kyle, Please consider pulling i915 updates to linux-firmware.git. i915-firmware-2017-11-27 The following changes since commit 17e6288135d4500f9fe60224dce2b46d850c346b: brcm: update firmware for bcm4358 (2017-11-25 10:15:53 -0500) are available in the git repository at: ssh://git.freedesktop.org/git/drm/drm-firmware.git master for you to fetch changes up to 02d857ee316f6f611b6622ef78892d38d0909700: linux-firmware: DMC firmware for skylake v1.27 (2017-11-27 14:36:28 -0800) Anusha Srivatsa (1): linux-firmware: DMC firmware for skylake v1.27 WHENCE | 3 ++- i915/skl_dmc_ver1_27.bin | Bin 0 -> 8928 bytes 2 files changed, 2 insertions(+), 1 deletion(-) create mode 100644 i915/skl_dmc_ver1_27.bin Thanks In Advance, Anusha -- Anusha Srivatsa ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-firmware pull request(KBL:DMC)
Thanks Ben. Anusha >-Original Message- >From: Ben Hutchings [mailto:b...@decadent.org.uk] >Sent: Wednesday, November 22, 2017 5:17 PM >To: Srivatsa, Anusha <anusha.sriva...@intel.com>; linux-firmw...@kernel.org >Cc: intel-gfx@lists.freedesktop.org; k...@kernel.org >Subject: Re: linux-firmware pull request(KBL:DMC) > >On Thu, 2017-11-09 at 16:47 -0800, Anusha Srivatsa wrote: >> Hi Kyle, >> >> Please consider pulling i915 updates to linux-firmware.git. >> >> i915-firmware-KBL-DMC-v1.04: >> >> The following changes since commit >bf04291309d3169c0ad3b8db52564235bbd08e30: >> >> WHENCE: Add new qed firmware (2017-10-09 18:03:26 +0100) >> >> are available in the git repository at: >> >> https://github.com/anushasr/linux-firmware.git >> >> for you to fetch changes up to >127a9d6eabee487176ad4e377c68199dbb264e08: >> >> linux-firmware: DMC firmware for kabylake v1.04 (2017-11-09 11:41:47 >> -0800) >> >> >> Anusha Srivatsa (1): >> linux-firmware: DMC firmware for kabylake v1.04 >> >> WHENCE | 4 >> i915/kbl_dmc_ver1_04.bin | Bin 0 -> 8840 bytes >> 2 files changed, 4 insertions(+) >> create mode 100644 i915/kbl_dmc_ver1_04.bin >> >> P.S: Kindly Consider these changes and the changes sent in the >> Previous pull request. > >I merged the master branch which was at commit >1156e62c5ec45061955a29e1b9299ffda58479d3, pulling in: > >Anusha Srivatsa (6): > linux-firmware/i915: Add Geminilake DMC version 1.04 > linux-firmware/i915: Add Cannonlake DMC version 1.06 > linux-firmware: GuC firmware for Skylake v9.33 > linux-firmware: GuC firmware for Broxton v9.29 > linux-firmware: GuC firmware for kabylake v9.39 > linux-firmware: DMC firmware for kabylake v1.04 > >Sorry for the delay. > >Ben. > >-- >Ben Hutchings >When in doubt, use brute force. - Ken Thompson ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] igt/kms_rotation_crc: Add horizontal flip subtest.
From: Joseph Garvey <joseph1.gar...@intel.com>
Test that horizontal flip works with supported rotations. Includes
a fix for the unrotated fb which was not being positioned correctly
with portrait and landscape rectangles.
v2:(from Anusha)
- Change 180 degree rotation to follow the rest, use
igt_swap(), make flip variable a bool. Format the
patch correctly (Ville, Petri Latvala)
v3: (From Anusha)
- Correct the name of subtests in order to avoid duplication
of names (Arek)
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
Signed-off-by: Joseph Garvey <joseph1.gar...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Petri Latvala <petri.latv...@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hi...@intel.com>
---
lib/igt_kms.c| 2 +-
lib/igt_kms.h| 5 ++
tests/kms_rotation_crc.c | 198 +--
3 files changed, 164 insertions(+), 41 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index a572fc6..3034e44 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -3050,7 +3050,7 @@ void igt_fb_set_size(struct igt_fb *fb, igt_plane_t
*plane,
static const char *rotation_name(igt_rotation_t rotation)
{
- switch (rotation) {
+ switch (rotation & IGT_ROTATION_MASK) {
case IGT_ROTATION_0:
return "0°";
case IGT_ROTATION_90:
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 8dc118c..b83a828 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -281,8 +281,13 @@ typedef enum {
IGT_ROTATION_90 = 1 << 1,
IGT_ROTATION_180 = 1 << 2,
IGT_ROTATION_270 = 1 << 3,
+ IGT_REFLECT_X= 1 << 4,
+ IGT_REFLECT_Y= 1 << 5,
} igt_rotation_t;
+#define IGT_ROTATION_MASK \
+ (IGT_ROTATION_0 | IGT_ROTATION_90 | IGT_ROTATION_180 | IGT_ROTATION_270)
+
typedef struct {
/*< private >*/
igt_pipe_t *pipe;
diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 5aec8fa..9e13667 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -32,6 +32,7 @@ typedef struct {
igt_display_t display;
struct igt_fb fb;
struct igt_fb fb_reference;
+ struct igt_fb fb_unrotated;
struct igt_fb fb_modeset;
struct igt_fb fb_flip;
igt_crc_t ref_crc;
@@ -43,8 +44,59 @@ typedef struct {
uint32_t override_fmt;
uint64_t override_tiling;
bool flips;
+ int devid;
} data_t;
+typedef struct {
+ float r;
+ float g;
+ float b;
+} rgb_color_t;
+
+static void set_color(rgb_color_t *color, float r, float g, float b)
+{
+ color->r = r;
+ color->g = g;
+ color->b = b;
+}
+
+static void rotate_colors(rgb_color_t *tl, rgb_color_t *tr, rgb_color_t *br,
+ rgb_color_t *bl, igt_rotation_t rotation)
+{
+ rgb_color_t bl_tmp, br_tmp, tl_tmp, tr_tmp;
+
+ if (rotation & IGT_REFLECT_X) {
+ igt_swap(*tl, *tr);
+ igt_swap(*bl, *br);
+ }
+
+ if (rotation & IGT_ROTATION_90) {
+ bl_tmp = *bl;
+ br_tmp = *br;
+ tl_tmp = *tl;
+ tr_tmp = *tr;
+ *tl = tr_tmp;
+ *bl = tl_tmp;
+ *tr = br_tmp;
+ *br = bl_tmp;
+ } else if (rotation & IGT_ROTATION_180) {
+ igt_swap(*tl, *br);
+ igt_swap(*tr, *bl);
+ } else if (rotation & IGT_ROTATION_270) {
+ bl_tmp = *bl;
+ br_tmp = *br;
+ tl_tmp = *tl;
+ tr_tmp = *tr;
+ *tl = bl_tmp;
+ *bl = br_tmp;
+ *tr = tl_tmp;
+ *br = tr_tmp;
+ }
+}
+
+#define RGB_COLOR(color) \
+ color.r, color.g, color.b
+
static void
paint_squares(data_t *data, igt_rotation_t rotation,
struct igt_fb *fb, float o)
@@ -52,35 +104,21 @@ paint_squares(data_t *data, igt_rotation_t rotation,
cairo_t *cr;
unsigned int w = fb->width;
unsigned int h = fb->height;
+ rgb_color_t tl, tr, bl, br;
cr = igt_get_cairo_ctx(data->gfx_fd, fb);
- if (rotation == IGT_ROTATION_180) {
- cairo_translate(cr, w, h);
- cairo_rotate(cr, M_PI);
- }
+ set_color(, o, 0.0f, 0.0f);
+ set_color(, 0.0f, o, 0.0f);
+ set_color(, o, o, o);
+ set_color(, 0.0f, 0.0f, o);
- if (rotation == IGT_ROTATION_90) {
- /* Paint 4 squares with width == height in Green, White,
- Blue, Red Clockwise order to look like 270 degree rotated*/
- igt_paint_color(cr, 0, 0, w / 2, h / 2, 0.0, o, 0.0);
- igt_paint_color(cr, w / 2, 0, w / 2, h / 2, o, o, o);
- igt_paint_color(cr, 0, h / 2, w / 2, h / 2, o, 0.0, 0.0);
- igt_paint_color(cr,
[Intel-gfx] [PATCH] drm: Add DPCD definitions for DP 1.4 FEC feature
Forward Error Correction is supported on DP 1.4. This patch adds corresponding DPCD register definitions. Cc: Ville Syrjala <ville.syrj...@linux.intel.com> Cc: Jani Nikula <jani.nik...@linux.intel.com> Cc: Manasi Navare <manasi.d.nav...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- include/drm/drm_dp_helper.h | 29 + 1 file changed, 29 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 9049ef1..b0eee16 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -284,6 +284,35 @@ # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 # define DP_DSC_BITS_PER_PIXEL_10x4 +/* DP Forward error Correction Registers */ +#define DP_FEC_CAPABILITY 0x090 +# define DP_FEC_CAPABLE(1 << 0) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2) +# define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3) + +#define DP_FEC_CONFIGURATION 0x120 +# define DP_FEC_READY (1 << 0) +# define DP_FEC_ERR_COUNT_DIS (0 << 1) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) +# define DP_FEC_BIT_ERROR_COUNT(3 << 1) +# define DP_FEC_LANE_0_SELECT (0 << 4) +# define DP_FEC_LANE_1_SELECT (1 << 4) +# define DP_FEC_LANE_2_SELECT (2 << 4) +# define DP_FEC_LANE_3_SELECT (3 << 4) + +#define DP_FEC_STATUS 0x280 +# define DP_FEC_EN_DETECTED(1 << 0) +# define DP_FEC_DEC_DETECTED (1 << 1) + +#define DP_FEC_ERROR_COUNT_1 0x0281 +# define DP_FEC_ERR_COUNT_7_0(err_count)(err_count << 0) + +#define DP_FEC_ERROR_COUNT_2 0x0282 +# define DP_FEC_ERR_COUNT_14_8(err_count) (err_count << 0) +# define DP_FEC_ERR_COUNT_VALID(1 << 7) + #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED1 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] Skylake DMC v1.27
Adding the pull request as part of the cover letter. Sending from personal account since getting the shared repo is WIP. Lets run this version on CI. i915-firmware-2017-11-09: The following changes since commit bf04291309d3169c0ad3b8db52564235bbd08e30: WHENCE: Add new qed firmware (2017-10-09 18:03:26 +0100) are available in the git repository at: https://github.com/anushasr/linux-firmware.git for you to fetch changes up to c0ddcecd44a61426dead86df9841ae47fb36e883: linux-firmware: DMC firmware for skylake v1.27 (2017-11-09 15:02:42 -0800) Anusha Srivatsa (1): linux-firmware: DMC firmware for skylake v1.27 WHENCE | 4 i915/skl_dmc_ver1_27.bin | Bin 0 -> 8928 bytes 2 files changed, 4 insertions(+) create mode 100644 i915/skl_dmc_ver1_27.bin Anusha Srivatsa (1): linux-firmware: DMC firmware for skylake v1.27 WHENCE | 4 i915/skl_dmc_ver1_27.bin | Bin 0 -> 8928 bytes 2 files changed, 4 insertions(+) create mode 100644 i915/skl_dmc_ver1_27.bin -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/skl: DMC firmware for skylake v1.27
There is a new version of dmc available for skylake. Following additions from ver1.27 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption. Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 77d8b3d..239b4c6 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -44,9 +44,9 @@ MODULE_FIRMWARE(I915_CSR_KBL); #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1) -#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" +#define I915_CSR_SKL "i915/skl_dmc_ver1_27.bin" MODULE_FIRMWARE(I915_CSR_SKL); -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26) +#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27) #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin" MODULE_FIRMWARE(I915_CSR_BXT); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] linux-firmware pull request(KBL:DMC)
Hi Kyle, Please consider pulling i915 updates to linux-firmware.git. i915-firmware-KBL-DMC-v1.04: The following changes since commit bf04291309d3169c0ad3b8db52564235bbd08e30: WHENCE: Add new qed firmware (2017-10-09 18:03:26 +0100) are available in the git repository at: https://github.com/anushasr/linux-firmware.git for you to fetch changes up to 127a9d6eabee487176ad4e377c68199dbb264e08: linux-firmware: DMC firmware for kabylake v1.04 (2017-11-09 11:41:47 -0800) Anusha Srivatsa (1): linux-firmware: DMC firmware for kabylake v1.04 WHENCE | 4 i915/kbl_dmc_ver1_04.bin | Bin 0 -> 8840 bytes 2 files changed, 4 insertions(+) create mode 100644 i915/kbl_dmc_ver1_04.bin P.S: Kindly Consider these changes and the changes sent in the Previous pull request. -- Anusha Srivatsa ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake
There is a new version of DMC available for KBL. The release notes mentions: 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption. Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 77d8b3d..07e4f7b 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -40,9 +40,9 @@ #define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) -#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" +#define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin" MODULE_FIRMWARE(I915_CSR_KBL); -#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1) +#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" MODULE_FIRMWARE(I915_CSR_SKL); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake
>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Daniel Stone >Sent: Friday, November 3, 2017 6:40 AM >To: Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com> >Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.v...@intel.com> >Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake > >Hi, > >On 2 November 2017 at 18:04, Pandiyan, Dhinakaran ><dhinakaran.pandi...@intel.com> wrote: >> On Thu, 2017-11-02 at 07:27 -0700, Rodrigo Vivi wrote: >>> That's intentional. The idea is to send to linux-firmware only after >>> it passes our CI. So, prepare already in a way that it is easy to >>> just forward when that happens. >>> >>> But what I believe we can change is to send that in the cover-letter >>> of the series. >>> So cover-letter with pull-request that CI would get automatically, >>> all related patches on the series, so right now it could be: >>> patch 0: pull-request >>> patch 1: kbl dmc 1.04 >>> patch 2: skl dmc 1.27 >> This patch updates only KBL firmware. Is there an upcoming 1.27 >> release for SKL? > >If there is, it hasn't yet made it to 01.org either. Daniel, The plan is to release the firmware to 01.org once we get ack from CI. Once we get ack, I will also send pull request to linux-firmware. I actually need your help in setting up a shared repo on freedesktop from where I can send pull requests I am currently doing that through my private github account. Regards, Anusha >Cheers, >Daniel >___ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake
>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Daniel Stone >Sent: Friday, November 3, 2017 6:40 AM >To: Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com> >Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.v...@intel.com> >Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake > >Hi, > >On 2 November 2017 at 18:04, Pandiyan, Dhinakaran ><dhinakaran.pandi...@intel.com> wrote: >> On Thu, 2017-11-02 at 07:27 -0700, Rodrigo Vivi wrote: >>> That's intentional. The idea is to send to linux-firmware only after >>> it passes our CI. So, prepare already in a way that it is easy to >>> just forward when that happens. >>> >>> But what I believe we can change is to send that in the cover-letter >>> of the series. >>> So cover-letter with pull-request that CI would get automatically, >>> all related patches on the series, so right now it could be: >>> patch 0: pull-request >>> patch 1: kbl dmc 1.04 >>> patch 2: skl dmc 1.27 >> This patch updates only KBL firmware. Is there an upcoming 1.27 >> release for SKL? 1.27 to be sent out to public soon. Anusha >If there is, it hasn't yet made it to 01.org either. > >Cheers, >Daniel >___ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.
On Wed, Nov 01, 2017 at 01:24:15PM +, Chris Wilson wrote:
> Quoting Michal Wajdeczko (2017-11-01 13:14:33)
> > On Wed, 01 Nov 2017 01:11:20 +0100, Anusha Srivatsa
> > > @@ -172,13 +174,18 @@ static int guc_ucode_xfer_dma(struct
> > > drm_i915_private *dev_priv,
> > >*/
> > > ret = wait_for(guc_ucode_response(dev_priv, ), 100);
> > > + load_time = ktime_ms_delta(ktime_get(), start_load);
> > > +
> > > DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
> > > I915_READ(DMA_CTRL), status);
> > > if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
> > > DRM_ERROR("GuC firmware signature verification failed\n");
> > > ret = -ENOEXEC;
> > > - }
> > > + } else if (load_time > 20)
> > > + DRM_NOTE("GuC load takes more than acceptable threshold\n");
> >
> > Please add threshold and actual load time to the message to let user
> > know that times
>
> The more important question is why are we telling the user this at all;
> a significant but normal condition. What do we expect them to do? It
> doesn't impair any functionality of the driver, it just took longer than
> you expected -- which may be simply because the system was doing
> something else and we slept for longer.
Chris, I am inclining to have this info more for us than the user. It is more of
a debug print to give us some data. We can see if firmware takes peculiarly
long time to load. We know its normal to be within 20ms range. So, alert
if it takes longer than that...
> -Chris
--
Anusha Srivatsa
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.
On Wed, Nov 01, 2017 at 02:14:33PM +0100, Michal Wajdeczko wrote:
> On Wed, 01 Nov 2017 01:11:20 +0100, Anusha Srivatsa
> <anusha.sriva...@intel.com> wrote:
>
> >Calculate the time that GuC takes to load using
> >jiffies. This information could be very useful in
> ^^^
> This is no longer true.
True. Will sending an all new patch with updated
approach(using ktime instead of jiffies) be good?
Or stick to this with change in commit message?
> >determining if GuC is taking unreasonably long time
> >to load in a certain platforms.
> >
> >v2: Calculate time before logs are collected.
> >Move the guc_load_time variable as a part of
> >intel_uc_fw struct. Store only final result
> >which is to be exported to debugfs. (Michal)
> >Add the load time in the print message as well.
> >
> >v3: Remove debugfs entry. Remove local variable
> >guc_finish_load. (Daniel, Tvrtko)
> >
> >v4: Use ktime_get() instead of jiffies. Use DRM_NOTE
> >if time taken to load is more than the threshold. On
> >load times within acceptable range, use DRM_DEBUG_DRIVER
> >(Tvrtko)
> >
> >v5: Rebased. Do not expose the load time variable in a global
> >struct (Tvrtko, Joonas)
> >
> >Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> >Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
> >Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
> >Cc: Oscar Mateo <oscar.ma...@intel.com>
> >Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
> >Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
> >Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
> >---
> > drivers/gpu/drm/i915/intel_guc_fw.c | 11 +--
> > 1 file changed, 9 insertions(+), 2 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
> >b/drivers/gpu/drm/i915/intel_guc_fw.c
> >index ef67a36..4ce9a30 100644
> >--- a/drivers/gpu/drm/i915/intel_guc_fw.c
> >+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> >@@ -133,7 +133,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
> >*dev_priv,
> > unsigned long offset;
> > struct sg_table *sg = vma->pages;
> > u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> >-int i, ret = 0;
> >+int i, ret = 0, load_time;
>
> Note that ktime_ms_delta() return type is s64 not int.
>
> >+ktime_t start_load;
>
> s/start_load/now ?
I think start_load is verbose.
> > /* where RSA signature starts */
> > offset = guc_fw->rsa_offset;
> >@@ -160,6 +161,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
> >*dev_priv,
> > I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> > /* Finally start the DMA */
> >+start_load = ktime_get();
>
> Maybe we should either update comment with note about taking start time
> or move ktime_get call before that comment to avoid confusion..
I prefer the latter.
> > I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> > /*
> >@@ -172,13 +174,18 @@ static int guc_ucode_xfer_dma(struct
> >drm_i915_private *dev_priv,
> > */
> > ret = wait_for(guc_ucode_response(dev_priv, ), 100);
> >+load_time = ktime_ms_delta(ktime_get(), start_load);
> >+
> > DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
> > I915_READ(DMA_CTRL), status);
> > if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
> > DRM_ERROR("GuC firmware signature verification failed\n");
> > ret = -ENOEXEC;
> >-}
> >+} else if (load_time > 20)
> >+DRM_NOTE("GuC load takes more than acceptable threshold\n");
>
> Please add threshold and actual load time to the message to let user
> know that times
> >+else
> >+DRM_DEBUG_DRIVER("GuC loaded in %d ms\n", load_time);
>
> And I'm not sure that we can rely on 'load_time' on timeout in wait_for.
Hmm we are checking the DMA status right after that which means
the firmware load should have happened by then thats why I
am calculating it there
> > DRM_DEBUG_DRIVER("returning %d\n", ret);
--
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Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake
>-Original Message- >From: Jani Nikula [mailto:jani.nik...@linux.intel.com] >Sent: Thursday, November 2, 2017 3:35 AM >To: Srivatsa, Anusha <anusha.sriva...@intel.com>; intel- >g...@lists.freedesktop.org >Cc: Vivi, Rodrigo <rodrigo.v...@intel.com> >Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake > >On Wed, 01 Nov 2017, Anusha Srivatsa <anusha.sriva...@intel.com> wrote: >> There is a new version of DMC available for KBL. > >Nobody's going to pull this to linux-firmware if you don't send it to the >linux- >firmware folks... > >> The release notes mentions: >> 1. Fix for the issue where DC_STATE was getting enabled even when >> disabled by driver causing data corruption. >> >> Adding the pull request here as an experiment- The following changes >> since commit bf04291309d3169c0ad3b8db52564235bbd08e30: >> >> WHENCE: Add new qed firmware (2017-10-09 18:03:26 +0100) >> >> are available in the git repository at: >> >> https://github.com/anushasr/linux-firmware.git KBL_DMC > >We should have a shared repo for this at freedesktop.org instead of your >private >repo at github. And we should use signed tags for pull requests. Hi Jani, I will see to it that a freedesktop repo is created for this purpose moving forward. I will use signed tags too. Thanks, Anusha >BR, >Jani. > >> >> for you to fetch changes up to 2f2b42764455856c2ba63d2154b3b2fbb7424236: >> >> linux-firmware: DMC firmware for kabylake v1.04 (2017-11-01 19:22:21 >> -0700) >> >> >> Anusha Srivatsa (1): >> linux-firmware: DMC firmware for kabylake v1.04 >> >> WHENCE | 4 >> i915/kbl_dmc_ver1_04.bin | Bin 0 -> 8840 bytes >> 2 files changed, 4 insertions(+) >> create mode 100644 i915/kbl_dmc_ver1_04.bin >> >> Cc: Rodrigo Vivi <rodrigo.v...@intel.com> >> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> >> --- >> drivers/gpu/drm/i915/intel_csr.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_csr.c >> b/drivers/gpu/drm/i915/intel_csr.c >> index 3e1f86d..5842777 100644 >> --- a/drivers/gpu/drm/i915/intel_csr.c >> +++ b/drivers/gpu/drm/i915/intel_csr.c >> @@ -40,9 +40,9 @@ >> #define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" >> #define CNL_CSR_VERSION_REQUIREDCSR_VERSION(1, 6) >> >> -#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" >> +#define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin" >> MODULE_FIRMWARE(I915_CSR_KBL); >> -#define KBL_CSR_VERSION_REQUIREDCSR_VERSION(1, 1) >> +#define KBL_CSR_VERSION_REQUIREDCSR_VERSION(1, 4) >> >> #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" >> MODULE_FIRMWARE(I915_CSR_SKL); > >-- >Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dmc: DMC 1.04 for Kabylake
There is a new version of DMC available for KBL. The release notes mentions: 1. Fix for the issue where DC_STATE was getting enabled even when disabled by driver causing data corruption. Adding the pull request here as an experiment- The following changes since commit bf04291309d3169c0ad3b8db52564235bbd08e30: WHENCE: Add new qed firmware (2017-10-09 18:03:26 +0100) are available in the git repository at: https://github.com/anushasr/linux-firmware.git KBL_DMC for you to fetch changes up to 2f2b42764455856c2ba63d2154b3b2fbb7424236: linux-firmware: DMC firmware for kabylake v1.04 (2017-11-01 19:22:21 -0700) Anusha Srivatsa (1): linux-firmware: DMC firmware for kabylake v1.04 WHENCE | 4 i915/kbl_dmc_ver1_04.bin | Bin 0 -> 8840 bytes 2 files changed, 4 insertions(+) create mode 100644 i915/kbl_dmc_ver1_04.bin Cc: Rodrigo Vivi <rodrigo.v...@intel.com> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 3e1f86d..5842777 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -40,9 +40,9 @@ #define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin" #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6) -#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" +#define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin" MODULE_FIRMWARE(I915_CSR_KBL); -#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1) +#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" MODULE_FIRMWARE(I915_CSR_SKL); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/huc: Add HuC Load time to dmesg log.
This patch uses jiffies to calculate the huc
load time.This information can be useful for testing
to know how much time huc takes to load.
v2: Remove debugfs entry. Remove local variable
huc_finish_load. (Daniel, Tvrtko)
v3: Use ktime_get() for more accurate timings.
Ensure the load is successful, before load times
is printed. (Tvrtko, Michal)
v4: Rebase. Do not expose the load time variable in a gobal
struct. Use int for load time (Tvrtko, Joonas)
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo Lozano <oscar.ma...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_huc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 98d1725..3e3ce14 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -127,7 +127,8 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw,
struct i915_vma *vma)
struct drm_i915_private *dev_priv = huc_to_i915(huc);
unsigned long offset = 0;
u32 size;
- int ret;
+ int ret, load_time;
+ ktime_t start_load;
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
@@ -148,13 +149,19 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw,
struct i915_vma *vma)
I915_WRITE(DMA_COPY_SIZE, size);
/* Start the DMA */
+ start_load = ktime_get();
I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
/* Wait for DMA to finish */
ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
+ load_time = ktime_ms_delta(ktime_get(), start_load);
+
DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
+ if (!ret)
+ DRM_DEBUG_DRIVER("HuC is loaded in %d ms\n", load_time);
+
/* Disable the bits once DMA is over */
I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
--
2.7.4
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[Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.
Calculate the time that GuC takes to load using
jiffies. This information could be very useful in
determining if GuC is taking unreasonably long time
to load in a certain platforms.
v2: Calculate time before logs are collected.
Move the guc_load_time variable as a part of
intel_uc_fw struct. Store only final result
which is to be exported to debugfs. (Michal)
Add the load time in the print message as well.
v3: Remove debugfs entry. Remove local variable
guc_finish_load. (Daniel, Tvrtko)
v4: Use ktime_get() instead of jiffies. Use DRM_NOTE
if time taken to load is more than the threshold. On
load times within acceptable range, use DRM_DEBUG_DRIVER
(Tvrtko)
v5: Rebased. Do not expose the load time variable in a global
struct (Tvrtko, Joonas)
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Cc: Oscar Mateo <oscar.ma...@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index ef67a36..4ce9a30 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -133,7 +133,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv,
unsigned long offset;
struct sg_table *sg = vma->pages;
u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
- int i, ret = 0;
+ int i, ret = 0, load_time;
+ ktime_t start_load;
/* where RSA signature starts */
offset = guc_fw->rsa_offset;
@@ -160,6 +161,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv,
I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
/* Finally start the DMA */
+ start_load = ktime_get();
I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
/*
@@ -172,13 +174,18 @@ static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv,
*/
ret = wait_for(guc_ucode_response(dev_priv, ), 100);
+ load_time = ktime_ms_delta(ktime_get(), start_load);
+
DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
I915_READ(DMA_CTRL), status);
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
DRM_ERROR("GuC firmware signature verification failed\n");
ret = -ENOEXEC;
- }
+ } else if (load_time > 20)
+ DRM_NOTE("GuC load takes more than acceptable threshold\n");
+ else
+ DRM_DEBUG_DRIVER("GuC loaded in %d ms\n", load_time);
DRM_DEBUG_DRIVER("returning %d\n", ret);
--
2.7.4
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[Intel-gfx] linux-firmware pull request (skl,kbl,bxt: guc; cnl,glk: dmc)
Hi, Please consider pulling i915 updates to linux-firmware.git. The following changes since commit bf04291309d3169c0ad3b8db52564235bbd08e30: WHENCE: Add new qed firmware (2017-10-09 18:03:26 +0100) are available in the git repository at: https://github.com/anushasr/linux-firmware.git master for you to fetch changes up to de8171590bc29196cb90b7e69b112a8ba26bcaf4: linux-firmware: GuC firmware for kabylake v9.39 (2017-10-25 16:15:42 -0700) Anusha Srivatsa (5): linux-firmware/i915: Add Geminilake DMC version 1.04 linux-firmware/i915: Add Cannonlake DMC version 1.06 linux-firmware: GuC firmware for Skylake v9.33 linux-firmware: GuC firmware for Broxton v9.29 linux-firmware: GuC firmware for kabylake v9.39 WHENCE | 15 +++ i915/bxt_guc_ver9_29.bin | Bin 0 -> 146432 bytes i915/cnl_dmc_ver1_06.bin | Bin 0 -> 11224 bytes i915/glk_dmc_ver1_04.bin | Bin 0 -> 8800 bytes i915/kbl_guc_ver9_39.bin | Bin 0 -> 147776 bytes i915/skl_guc_ver9_33.bin | Bin 0 -> 147520 bytes 6 files changed, 15 insertions(+) create mode 100644 i915/bxt_guc_ver9_29.bin create mode 100644 i915/cnl_dmc_ver1_06.bin create mode 100644 i915/glk_dmc_ver1_04.bin create mode 100644 i915/kbl_guc_ver9_39.bin create mode 100644 i915/skl_guc_ver9_33.bin This pull request has updates introduced by the previous two pull requests. Kindly ignore them and consider this. Thanks, Anusha Srivatsa ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
