[Intel-gfx] [PATCH IGT] dpio: Add back get_dpio_port which is needed for future platform.
Future platform require the phy input to determine which PHY to target for.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
lib/intel_iosf.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c
index f57212f..0c9f4d8 100644
--- a/lib/intel_iosf.c
+++ b/lib/intel_iosf.c
@@ -74,15 +74,26 @@ int intel_nc_write(uint8_t addr, uint32_t val)
return vlv_sideband_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_WRITE, addr,
val);
}
+static int get_dpio_port(int phy)
+{
+ struct pci_device *dev = intel_get_pci_device();
+ int dpio_port;
+
+ if (IS_VALLEYVIEW(dev-device_id))
+ dpio_port = IOSF_PORT_DPIO;
+
+ return dpio_port;
+}
+
uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
{
uint32_t val;
- vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_READ, reg, val);
+ vlv_sideband_rw(get_dpio_port(phy), DPIO_OPCODE_REG_READ, reg, val);
return val;
}
void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
{
- vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_WRITE, reg, val);
+ vlv_sideband_rw(get_dpio_port(phy), DPIO_OPCODE_REG_WRITE, reg, val);
}
--
1.8.3.1
___
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[Intel-gfx] [PATCH igt 1/2] tools/quick_dump: Update Baytrail DPIO names to reflect to the driver change.
DPIO name still using old name. Change it according to the driver name.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
tools/quick_dump/vlv_dpio.txt | 104 +-
1 file changed, 51 insertions(+), 53 deletions(-)
diff --git a/tools/quick_dump/vlv_dpio.txt b/tools/quick_dump/vlv_dpio.txt
index 28626da..2942d37 100644
--- a/tools/quick_dump/vlv_dpio.txt
+++ b/tools/quick_dump/vlv_dpio.txt
@@ -1,54 +1,52 @@
('DPIO_CTL', '0x182110', '')
-('DPIO_TX3_SWING_CTL4_A', '0x690', 'DPIO')
-('DPIO_TX3_SWING_CTL4_B', '0x2a90', 'DPIO')
-('DPIO_DIV_A', '0x800c', 'DPIO')
-('DPIO_DIV_B', '0x802c', 'DPIO')
-('DPIO_REFSFR_A', '0x8014', 'DPIO')
-('DPIO_REFSFR_B', '0x8034', 'DPIO')
-('DPIO_CORE_CLK_A', '0x801c', 'DPIO')
-('DPIO_CORE_CLK_B', '0x803c', 'DPIO')
-('DPIO_IREF_CTL_A', '0x8040', 'DPIO')
-('DPIO_IREF_CTL_B', '0x8060', 'DPIO')
-('DPIO_IREF_BCAST', '0xc044', 'DPIO')
-('DPIO_IREF_A', '0x8044', 'DPIO')
-('DPIO_IREF_B', '0x8064', 'DPIO')
-('DPIO_PLL_CML_A', '0x804c', 'DPIO')
-('DPIO_PLL_CML_B', '0x806c', 'DPIO')
-('DPIO_LPF_COEFF_A', '0x8048', 'DPIO')
-('DPIO_LPF_COEFF_B', '0x8068', 'DPIO')
-('DPIO_CALIBRATION', '0x80ac', 'DPIO')
-('DPIO_FASTCLK_DISABLE', '0x8100', 'DPIO')
-('DPIO_PCS_TX_0', '0x8200', 'DPIO')
-('DPIO_PCS_TX_1', '0x8400', 'DPIO')
-('DPIO_PCS_CLK_0', '0x8204', 'DPIO')
-('DPIO_PCS_CLK_1', '0x8404', 'DPIO')
-('DPIO_PCS_CTL_OVR1_A', '0x8224', 'DPIO')
-('DPIO_PCS_CTL_OVR1_B', '0x8424', 'DPIO')
-('DPIO_PCS_STAGGER0_A', '0x822c', 'DPIO')
-('DPIO_PCS_STAGGER0_B', '0x842c', 'DPIO')
-('DPIO_PCS_STAGGER1_A', '0x8230', 'DPIO')
-('DPIO_PCS_STAGGER1_B', '0x8430', 'DPIO')
-('DPIO_PCS_CLOCKBUF0_A', '0x8238', 'DPIO')
-('DPIO_PCS_CLOCKBUF0_B', '0x8438', 'DPIO')
-('DPIO_PCS_CLOCKBUF8_A', '0x825c', 'DPIO')
-('DPIO_PCS_CLOCKBUF8_B', '0x845c', 'DPIO')
-('DPIO_TX_SWING_CTL2_A', '0x8288', 'DPIO')
-('DPIO_TX_SWING_CTL2_B', '0x8488', 'DPIO')
-('DPIO_TX_SWING_CTL3_A', '0x828c', 'DPIO')
-('DPIO_TX_SWING_CTL3_B', '0x848c', 'DPIO')
-('DPIO_TX_SWING_CTL4_A', '0x8290', 'DPIO')
-('DPIO_TX_SWING_CTL4_B', '0x8490', 'DPIO')
-('DPIO_TX_OCALINIT_0', '0x8294', 'DPIO')
-('DPIO_TX_OCALINIT_1', '0x8494', 'DPIO')
-('DPIO_TX_CTL_0', '0x82ac', 'DPIO')
-('DPIO_TX_CTL_1', '0x84ac', 'DPIO')
-('DPIO_TX_LANE_0', '0x82b8', 'DPIO')
-('DPIO_TX_LANE_1', '0x84b8', 'DPIO')
-('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
-('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')
-('DPIO_PORT0_PCS0', '0x0220', 'DPIO')
-('DPIO_PORT0_PCS1', '0x0420', 'DPIO')
-('DPIO_PORT1_PCS2', '0x2620', 'DPIO')
-('DPIO_PORT1_PCS3', '0x2820', 'DPIO')
-('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
-('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')
+('DPIO_TX3_DW4_CH0', '0x690', 'DPIO')
+('DPIO_TX3_DW4_CH1', '0x2a90', 'DPIO')
+('DPIO_PLL_DW3_CH0', '0x800c', 'DPIO')
+('DPIO_PLL_DW3_CH1', '0x802c', 'DPIO')
+('DPIO_PLL_DW5_CH0', '0x8014', 'DPIO')
+('DPIO_PLL_DW5_CH1', '0x8034', 'DPIO')
+('DPIO_PLL_DW7_CH0', '0x801c', 'DPIO')
+('DPIO_PLL_DW7_CH1', '0x803c', 'DPIO')
+('DPIO_PLL_DW8_CH0', '0x8040', 'DPIO')
+('DPIO_PLL_DW8_CH1', '0x8060', 'DPIO')
+('DPIO_PLL_DW9_BCAST', '0xc044', 'DPIO')
+('DPIO_PLL_DW9_CH0', '0x8044', 'DPIO')
+('DPIO_PLL_DW9_CH1', '0x8064', 'DPIO')
+('DPIO_PLL_DW10_CH0', '0x8048', 'DPIO')
+('DPIO_PLL_DW10_CH1', '0x8068', 'DPIO')
+('DPIO_PLL_DW11_CH0', '0x804c', 'DPIO')
+('DPIO_PLL_DW11_CH1', '0x806c', 'DPIO')
+('DPIO_REF_DW13', '0x80ac', 'DPIO')
+('DPIO_CMN_DW0', '0x8100', 'DPIO')
+('DPIO_PCS_DW0_CH0', '0x8200', 'DPIO')
+('DPIO_PCS_DW0_CH1', '0x8400', 'DPIO')
+('DPIO_PCS_DW1_CH0', '0x8204', 'DPIO')
+('DPIO_PCS_DW1_CH1', '0x8404', 'DPIO')
+('DPIO_PCS01_DW8_CH0', '0x0220', 'DPIO')
+('DPIO_PCS23_DW8_CH0', '0x0420', 'DPIO')
+('DPIO_PCS01_DW8_CH1', '0x2620', 'DPIO')
+('DPIO_PCS23_DW8_CH1', '0x2820', 'DPIO')
+('DPIO_PCS_DW8_CH0', '0x8220', 'DPIO')
+('DPIO_PCS_DW8_CH1', '0x8420', 'DPIO')
+('DPIO_PCS_DW9_CH0', '0x8224', 'DPIO')
+('DPIO_PCS_DW9_CH1', '0x8424', 'DPIO')
+('DPIO_PCS_DW11_CH0', '0x822c', 'DPIO')
+('DPIO_PCS_DW11_CH1', '0x842c', 'DPIO')
+('DPIO_PCS_DW12_CH0', '0x8230', 'DPIO')
+('DPIO_PCS_DW12_CH1', '0x8430', 'DPIO')
+('DPIO_PCS_DW14_CH0', '0x8238', 'DPIO')
+('DPIO_PCS_DW14_CH1', '0x8438', 'DPIO')
+('DPIO_PCS_DW23_CH0', '0x825c', 'DPIO')
+('DPIO_PCS_DW23_CH1', '0x845c', 'DPIO')
+('DPIO_TX_DW2_CH0', '0x8288', 'DPIO')
+('DPIO_TX_DW2_CH1', '0x8488', 'DPIO')
+('DPIO_TX_DW3_CH0', '0x828c', 'DPIO')
+('DPIO_TX_DW3_CH1', '0x848c', 'DPIO')
+('DPIO_TX_DW4_CH0', '0x8290', 'DPIO')
+('DPIO_TX_DW4_CH1', '0x8490', 'DPIO')
+('DPIO_TX_DW5_CH0', '0x8294', 'DPIO')
+('DPIO_TX_DW5_CH1', '0x8494', 'DPIO')
+('DPIO_TX_DW11_CH0', '0x82ac', 'DPIO')
+('DPIO_TX_DW11_CH1', '0x84ac', 'DPIO')
+('DPIO_TX_DW14_CH0', '0x82b8', 'DPIO')
+('DPIO_TX_DW14_CH1', '0x84b8', 'DPIO')
--
1.8.3.1
___
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[Intel-gfx] [PATCH igt 2/2] Update dpio read/write to take in extra PHY parameter.
The extra parameter is for future platform.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
lib/intel_dpio.c | 19 +++
lib/intel_gpu_tools.h | 4 ++--
tools/intel_dpio_read.c| 2 +-
tools/intel_dpio_write.c | 2 +-
tools/quick_dump/chipset.i | 4 ++--
tools/quick_dump/quick_dump.py | 2 +-
tools/quick_dump/reg_access.py | 6 --
7 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/lib/intel_dpio.c b/lib/intel_dpio.c
index acfd201..7e22095 100644
--- a/lib/intel_dpio.c
+++ b/lib/intel_dpio.c
@@ -50,12 +50,23 @@ static void intel_display_reg_write(uint32_t reg, uint32_t
val)
*ptr = val;
}
+static int get_dpio_port(int phy) {
+
+ struct pci_device *dev = intel_get_pci_device();
+ int dpio_port;
+
+ if (IS_VALLEYVIEW(dev-device_id))
+ dpio_port = DPIO_PORTID;
+
+ return dpio_port;
+}
+
/*
* In SoCs like Valleyview some of the PLL Lane control registers
* can be accessed only through IO side band fabric called DPIO
*/
uint32_t
-intel_dpio_reg_read(uint32_t reg)
+intel_dpio_reg_read(uint32_t reg, int phy)
{
/* Check whether the side band fabric is ready to accept commands */
do {
@@ -64,7 +75,7 @@ intel_dpio_reg_read(uint32_t reg)
intel_display_reg_write(DPIO_REG, reg);
intel_display_reg_write(DPIO_PKT, DPIO_RID |
- DPIO_OP_READ | DPIO_PORTID |
DPIO_BYTE);
+ DPIO_OP_READ | get_dpio_port(phy) | DPIO_BYTE);
do {
usleep(1);
} while (intel_display_reg_read(DPIO_PKT) DPIO_BUSY);
@@ -77,7 +88,7 @@ intel_dpio_reg_read(uint32_t reg)
* can be accessed only through IO side band fabric called DPIO
*/
void
-intel_dpio_reg_write(uint32_t reg, uint32_t val)
+intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
{
/* Check whether the side band fabric is ready to accept commands */
do {
@@ -87,7 +98,7 @@ intel_dpio_reg_write(uint32_t reg, uint32_t val)
intel_display_reg_write(DPIO_DATA, val);
intel_display_reg_write(DPIO_REG, reg);
intel_display_reg_write(DPIO_PKT, DPIO_RID |
- DPIO_OP_WRITE | DPIO_PORTID |
DPIO_BYTE);
+ DPIO_OP_WRITE | get_dpio_port(phy) | DPIO_BYTE);
do {
usleep(1);
} while (intel_display_reg_read(DPIO_PKT) DPIO_BUSY);
diff --git a/lib/intel_gpu_tools.h b/lib/intel_gpu_tools.h
index 412e465..b242243 100644
--- a/lib/intel_gpu_tools.h
+++ b/lib/intel_gpu_tools.h
@@ -48,8 +48,8 @@ void intel_register_write(uint32_t reg, uint32_t val);
int intel_register_access_needs_fakewake(void);
/* Following functions are relevant only for SoCs like Valleyview */
-uint32_t intel_dpio_reg_read(uint32_t reg);
-void intel_dpio_reg_write(uint32_t reg, uint32_t val);
+uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
+void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy);
int intel_punit_read(uint8_t addr, uint32_t *val);
int intel_punit_write(uint8_t addr, uint32_t val);
diff --git a/tools/intel_dpio_read.c b/tools/intel_dpio_read.c
index c0c904a..6202ad9 100644
--- a/tools/intel_dpio_read.c
+++ b/tools/intel_dpio_read.c
@@ -56,7 +56,7 @@ int main(int argc, char** argv)
intel_register_access_init(dev, 0);
- val = intel_dpio_reg_read(reg);
+ val = intel_dpio_reg_read(reg, 0);
printf(Read DPIO register: 0x%x - Value : 0x%x\n, reg, val);
diff --git a/tools/intel_dpio_write.c b/tools/intel_dpio_write.c
index f842999..3d2f297 100644
--- a/tools/intel_dpio_write.c
+++ b/tools/intel_dpio_write.c
@@ -57,7 +57,7 @@ int main(int argc, char** argv)
intel_register_access_init(dev, 0);
- intel_dpio_reg_write(reg, val);
+ intel_dpio_reg_write(reg, val, 0);
intel_register_access_fini();
diff --git a/tools/quick_dump/chipset.i b/tools/quick_dump/chipset.i
index f1cc368..c5f4b56 100644
--- a/tools/quick_dump/chipset.i
+++ b/tools/quick_dump/chipset.i
@@ -16,7 +16,7 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t
val);
extern void intel_register_access_fini();
extern int intel_register_access_needs_fakewake();
extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
-extern uint32_t intel_dpio_reg_read(uint32_t reg);
+extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
%}
extern int is_sandybridge(unsigned short pciid);
@@ -30,4 +30,4 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t
val);
extern void intel_register_access_fini();
extern int intel_register_access_needs_fakewake();
extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
-extern uint32_t intel_dpio_reg_read(uint32_t reg);
+extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index ff151d1
[Intel-gfx] [PATCH v3 2/2] drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb document.
Some VLV PHY/PLL DPIO registers have group/lane/channel access. Current DPIO register definition doesn't have a structure way to break them down. As a result it is not easy to match the PHY/PLL registers with the configdb document. Rename those registers based on the configdb for easy cross references, and without the need to check the offset in the header file. New format is as following. platform name_DPIO componentoptional lane #_DWdword # in the doc_optional channel # For example, VLV_PCS_DW0 - Group access to PCS for lane 0 to 3 for PCS DWORD 0. VLV_PCS01_DW0_CH0 - PCS access to lane 0/1, channel 0 for PCS DWORD 0. Another example is VLV_TX_DW0 - Group access to TX lane 0 to 3 for TX DWORD 0 VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0. There is no functional change on this patch. v2: Rebase based on previous patch change. v3: There may be configdb different version that document the start DW differently. Add a comment to clarify. Fix up some mismatch start DW for second PLL block. (Ville) Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Chon Ming Lee chon.ming@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 40 drivers/gpu/drm/i915/i915_reg.h | 191 -- drivers/gpu/drm/i915/intel_display.c | 48 drivers/gpu/drm/i915/intel_dp.c | 32 +++--- drivers/gpu/drm/i915/intel_hdmi.c| 54 -- 5 files changed, 172 insertions(+), 193 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 7008aac..cae3e9c 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1650,28 +1650,28 @@ static int i915_dpio_info(struct seq_file *m, void *data) seq_printf(m, DPIO_CTL: 0x%08x\n, I915_READ(DPIO_CTL)); - seq_printf(m, DPIO_DIV_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); - seq_printf(m, DPIO_DIV_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); - - seq_printf(m, DPIO_REFSFR_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); - seq_printf(m, DPIO_REFSFR_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); - - seq_printf(m, DPIO_CORE_CLK_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); - seq_printf(m, DPIO_CORE_CLK_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); - - seq_printf(m, DPIO_LPF_COEFF_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); - seq_printf(m, DPIO_LPF_COEFF_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); + seq_printf(m, DPIO PLL DW3 CH0 : 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0))); + seq_printf(m, DPIO PLL DW3 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1))); + + seq_printf(m, DPIO PLL DW5 CH0: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0))); + seq_printf(m, DPIO PLL DW5 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1))); + + seq_printf(m, DPIO PLL DW7 CH0: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0))); + seq_printf(m, DPIO PLL DW7 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1))); + + seq_printf(m, DPIO PLL DW10 CH0: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0))); + seq_printf(m, DPIO PLL DW10 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1))); seq_printf(m, DPIO_FASTCLK_DISABLE: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); + vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0)); mutex_unlock(dev_priv-dpio_lock); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 969ca2e..d06db23 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -452,18 +452,13 @@ #define DPIO_SFR_BYPASS (11) #define DPIO_CMNRST (10) -#define _DPIO_TX3_SWING_CTL4_A 0x690 -#define _DPIO_TX3_SWING_CTL4_B 0x2a90 -#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \ - _DPIO_TX3_SWING_CTL4_B) - #define DPIO_PHY(pipe) ((pipe) 1) #define DPIO_PHY_IOSF_PORT(phy) (dev_priv-dpio_phy_iosf_port[phy]) /* * Per pipe/PLL DPIO regs */ -#define _DPIO_DIV_A0x800c +#define _VLV_PLL_DW3_CH0 0x800c #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ #define DPIO_POST_DIV_DAC0 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ @@ -476,10 +471,10
[Intel-gfx] [PATCH 2/2] drm/i915/vlv: For i915_cur_delayinfo, the max frequency reporting wrong value.
The max frequency reporting is not correct. But there is already an existing valleyview_rps_max_freq and valleyview_rps_min_freq to get the frequency. Use that for i915_cur_delayinfo. Signed-off-by: Chon Ming Lee chon.ming@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index cae3e9c..5254d95 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -972,11 +972,11 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) seq_printf(m, PUNIT_REG_GPU_FREQ_STS: 0x%08x\n, freq_sts); seq_printf(m, DDR freq: %d MHz\n, dev_priv-mem_freq); - val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); + val = valleyview_rps_max_freq(dev_priv); seq_printf(m, max GPU freq: %d MHz\n, vlv_gpu_freq(dev_priv-mem_freq, val)); - val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); + val = valleyview_rps_min_freq(dev_priv); seq_printf(m, min GPU freq: %d MHz\n, vlv_gpu_freq(dev_priv-mem_freq, val)); -- 1.7.7.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/vlv: Workaround a punit issue in DDR data rate for 1333.
For DDR data rate reporting by Punit in PUNIT_GPU_FREQ_STS, the actual data encoding is 00b=800, 01b=1066, 10b=1333, 11b=1333. Some premium VLV sku will get the DDR_DATA_RATE set as 11. As a result, the turbo frequency reporting will be incorrect without this workaround. Signed-off-by: Chon Ming Lee chon.ming@intel.com --- drivers/gpu/drm/i915/intel_pm.c |7 +-- 1 files changed, 1 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a5778e5..13fb7f8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5328,12 +5328,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) dev_priv-mem_freq = 1333; break; case 3: - /* -* Probably a BIOS/Punit bug, or a new platform we don't -* support yet. -*/ - WARN(1, invalid DDR freq detected, assuming 800MHz\n); - dev_priv-mem_freq = 800; + dev_priv-mem_freq = 1333; break; } DRM_DEBUG_DRIVER(DDR speed: %d MHz, dev_priv-mem_freq); -- 1.7.7.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/vlv: Make the vlv_dpio_read/vlv_dpio_write more PHY centric
vlv_dpio_read/write should be describe more in PHY centric instead of
display controller centric.
Create a enum dpio_channel for channel index and enum dpio_phy for PHY
index. This should better to gather for upcoming platform.
v2: Rebase the code based on
drm/i915/vlv: Fix typo in the DPIO register define.
v3: Rename vlv_phy to dpio_phy_iosf_port and define additional macro
DPIO_PHY, and remove unrelated change. (Ville)
Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/i915_reg.h |3 +++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c |8
drivers/gpu/drm/i915/intel_drv.h |7 ---
drivers/gpu/drm/i915/intel_hdmi.c |8
drivers/gpu/drm/i915/intel_sideband.c | 13 ++---
7 files changed, 42 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2aa7053..9fafc38 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -88,6 +88,18 @@ enum port {
};
#define port_name(p) ((p) + 'A')
+#define I915_NUM_PHYS_VLV 1
+
+enum dpio_channel {
+ DPIO_CH0,
+ DPIO_CH1
+};
+
+enum dpio_phy {
+ DPIO_PHY0,
+ DPIO_PHY1
+};
+
enum intel_display_power_domain {
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
@@ -1403,6 +1415,7 @@ typedef struct drm_i915_private {
int num_shared_dpll;
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
struct intel_ddi_plls ddi_plls;
+ int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
/* Reclocking support */
bool render_reclock_avail;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4dbc8da..969ca2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -457,6 +457,9 @@
#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \
_DPIO_TX3_SWING_CTL4_B)
+#define DPIO_PHY(pipe) ((pipe) 1)
+#define DPIO_PHY_IOSF_PORT(phy)
(dev_priv-dpio_phy_iosf_port[phy])
+
/*
* Per pipe/PLL DPIO regs
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 48f4990..b1d20b6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1361,6 +1361,7 @@ static void intel_init_dpio(struct drm_device *dev)
if (!IS_VALLEYVIEW(dev))
return;
+ DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
/*
* From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
* 6. De-assert cmn_reset/side_reset. Same as VLV X0.
@@ -1494,18 +1495,25 @@ static void vlv_disable_pll(struct drm_i915_private
*dev_priv, enum pipe pipe)
POSTING_READ(DPLL(pipe));
}
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
+void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *dport)
{
u32 port_mask;
- if (!port)
+ switch (dport-port) {
+ case PORT_B:
port_mask = DPLL_PORTB_READY_MASK;
- else
+ break;
+ case PORT_C:
port_mask = DPLL_PORTC_READY_MASK;
+ break;
+ default:
+ BUG();
+ }
if (wait_for((I915_READ(DPLL(0)) port_mask) == 0, 1000))
WARN(1, timed out waiting for port %c ready: 0x%08x\n,
-'B' + port, I915_READ(DPLL(0)));
+'B' + dport-port, I915_READ(DPLL(0)));
}
/**
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bcbdc7a..aea9e28 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1839,7 +1839,7 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder)
struct drm_device *dev = encoder-base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder-base.crtc);
- int port = vlv_dport_to_channel(dport);
+ enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc-pipe;
struct edp_power_seq power_seq;
u32 val;
@@ -1866,7 +1866,7 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder)
intel_enable_dp(encoder);
- vlv_wait_port_ready(dev_priv, port);
+ vlv_wait_port_ready(dev_priv, dport);
}
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
@@ -1876,7 +1876,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder-base.crtc);
- int port = vlv_dport_to_channel
[Intel-gfx] [PATCH 2/2] drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb document.
Some VLV PHY/PLL DPIO registers have group/lane/channel access. Current DPIO register definition doesn't have a structure way to break them down. As a result it is not easy to match the PHY/PLL registers with the configdb document. Rename those registers based on the configdb for easy cross references, and without the need to check the offset in the header file. New format is as following. platform name_DPIO componentoptional lane #_DWdword # in the doc_optional channel # For example, VLV_PCS_DW0 - Group access to PCS for lane 0 to 3 for PCS DWORD 0. VLV_PCS01_DW0_CH0 - PCS access to lane 0/1, channel 0 for PCS DWORD 0. Another example is VLV_TX_DW0 - Group access to TX lane 0 to 3 for TX DWORD 0 VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0. There is no functional change on this patch. v2: Rebase based on previous patch change. Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Chon Ming Lee chon.ming@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 40 drivers/gpu/drm/i915/i915_reg.h | 190 -- drivers/gpu/drm/i915/intel_display.c | 48 +- drivers/gpu/drm/i915/intel_dp.c | 32 +++--- drivers/gpu/drm/i915/intel_hdmi.c| 54 -- 5 files changed, 171 insertions(+), 193 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 7008aac..d756e23 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1650,28 +1650,28 @@ static int i915_dpio_info(struct seq_file *m, void *data) seq_printf(m, DPIO_CTL: 0x%08x\n, I915_READ(DPIO_CTL)); - seq_printf(m, DPIO_DIV_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); - seq_printf(m, DPIO_DIV_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); - - seq_printf(m, DPIO_REFSFR_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); - seq_printf(m, DPIO_REFSFR_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); - - seq_printf(m, DPIO_CORE_CLK_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); - seq_printf(m, DPIO_CORE_CLK_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); - - seq_printf(m, DPIO_LPF_COEFF_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); - seq_printf(m, DPIO_LPF_COEFF_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); + seq_printf(m, DPIO PLL DW3 CH0 : 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0))); + seq_printf(m, DPIO PLL DW3 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1))); + + seq_printf(m, DPIO PLL DW5 CH0: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0))); + seq_printf(m, DPIO PLL DW5 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1))); + + seq_printf(m, DPIO PLL DW7 CH0: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0))); + seq_printf(m, DPIO PLL DW7 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1))); + + seq_printf(m, DPIO PLL DW12 CH0: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(0))); + seq_printf(m, DPIO PLL DW12 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(1))); seq_printf(m, DPIO_FASTCLK_DISABLE: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); + vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0)); mutex_unlock(dev_priv-dpio_lock); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 969ca2e..c71b729 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -452,18 +452,13 @@ #define DPIO_SFR_BYPASS (11) #define DPIO_CMNRST (10) -#define _DPIO_TX3_SWING_CTL4_A 0x690 -#define _DPIO_TX3_SWING_CTL4_B 0x2a90 -#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \ - _DPIO_TX3_SWING_CTL4_B) - #define DPIO_PHY(pipe) ((pipe) 1) #define DPIO_PHY_IOSF_PORT(phy) (dev_priv-dpio_phy_iosf_port[phy]) /* * Per pipe/PLL DPIO regs */ -#define _DPIO_DIV_A0x800c +#define _VLV_PLL_DW3_CH0 0x800c #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ #define DPIO_POST_DIV_DAC0 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ @@ -476,10 +471,10 @@ #define DPIO_ENABLE_CALIBRATION (111) #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ #define DPIO_M2DIV_MASK 0xff -#define _DPIO_DIV_B
[Intel-gfx] [PATCH] drm/i915/vlv: Fix typo in the DPIO register define.
Incorrect definition DPIO_TX3_SWING_CTL4. Signed-off-by: Chon Ming Lee chon.ming@intel.com --- drivers/gpu/drm/i915/i915_reg.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6799d53..f7ecad2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -444,7 +444,7 @@ #define _DPIO_TX3_SWING_CTL4_A 0x690 #define _DPIO_TX3_SWING_CTL4_B 0x2a90 -#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \ +#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \ _DPIO_TX3_SWING_CTL4_B) /* -- 1.7.7.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb document.
Some VLV PHY/PLL DPIO registers have group/lane/channel access. Current DPIO register definition doesn't have a structure way to break them down. As a result it is not easy to match the PHY/PLL registers with the configdb document. Rename those registers based on the configdb for easy cross references, and without the need to check the offset in the header file. New format is as following. platform name_DPIO componentoptional lane #_DWdword # in the doc_optional channel # For example, VLV_PCS_DW0 - Group access to PCS for lane 0 to 3 for PCS DWORD 0. VLV_PCS01_DW0_CH0 - PCS access to lane 0/1, channel 0 for PCS DWORD 0. Another example is VLV_TX_DW0 - Group access to TX lane 0 to 3 for TX DWORD 0 VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0. There is no functional change on this patch. Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com Signed-off-by: Chon Ming Lee chon.ming@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 40 drivers/gpu/drm/i915/i915_reg.h | 189 -- drivers/gpu/drm/i915/intel_display.c | 48 +- drivers/gpu/drm/i915/intel_dp.c | 32 +++--- drivers/gpu/drm/i915/intel_hdmi.c| 54 -- 5 files changed, 171 insertions(+), 192 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5c45e9e..f6c4486 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1650,28 +1650,28 @@ static int i915_dpio_info(struct seq_file *m, void *data) seq_printf(m, DPIO_CTL: 0x%08x\n, I915_READ(DPIO_CTL)); - seq_printf(m, DPIO_DIV_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); - seq_printf(m, DPIO_DIV_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); - - seq_printf(m, DPIO_REFSFR_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); - seq_printf(m, DPIO_REFSFR_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); - - seq_printf(m, DPIO_CORE_CLK_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); - seq_printf(m, DPIO_CORE_CLK_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); - - seq_printf(m, DPIO_LPF_COEFF_A: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); - seq_printf(m, DPIO_LPF_COEFF_B: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); + seq_printf(m, DPIO PLL DW3 CH0 : 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0))); + seq_printf(m, DPIO PLL DW3 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1))); + + seq_printf(m, DPIO PLL DW5 CH0: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0))); + seq_printf(m, DPIO PLL DW5 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1))); + + seq_printf(m, DPIO PLL DW7 CH0: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0))); + seq_printf(m, DPIO PLL DW7 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1))); + + seq_printf(m, DPIO PLL DW12 CH0: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(0))); + seq_printf(m, DPIO PLL DW12 CH1: 0x%08x\n, + vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW12(1))); seq_printf(m, DPIO_FASTCLK_DISABLE: 0x%08x\n, - vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); + vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0)); mutex_unlock(dev_priv-dpio_lock); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dd8ff3b..98d0c78 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -442,17 +442,13 @@ #define DPIO_SFR_BYPASS (11) #define DPIO_CMNRST (10) -#define _DPIO_TX3_SWING_CTL4_A 0x690 -#define _DPIO_TX3_SWING_CTL4_B 0x2a90 -#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \ - _DPIO_TX3_SWING_CTL4_B) #define DPIO_PHY_PORT(pipe)(dev_priv-vlv_phy[pipe 1]) /* * Per pipe/PLL DPIO regs */ -#define _DPIO_DIV_A0x800c +#define _VLV_PLL_DW3_CH0 0x800c #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ #define DPIO_POST_DIV_DAC0 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ @@ -465,10 +461,10 @@ #define DPIO_ENABLE_CALIBRATION (111) #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ #define DPIO_M2DIV_MASK 0xff -#define _DPIO_DIV_B0x802c -#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) +#define _VLV_PLL_DW3_CH1
[Intel-gfx] [PATCH 1/2] drm/i915/vlv: Make the vlv_dpio_read/vlv_dpio_write more PHY centric
vlv_dpio_read/write should be describe more in PHY centric instead of
display controller centric.
Create a enum dpio_channel for channel index and enum dpio_phy for PHY
index. This should better to gather for upcoming platform.
v2: Rebase the code based on
drm/i915/vlv: Fix typo in the DPIO register define.
Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c |9 -
drivers/gpu/drm/i915/intel_drv.h |7 ---
drivers/gpu/drm/i915/intel_hdmi.c |9 -
drivers/gpu/drm/i915/intel_sideband.c | 13 ++---
7 files changed, 41 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2731fbb..b1609ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -88,6 +88,18 @@ enum port {
};
#define port_name(p) ((p) + 'A')
+#define I915_NUM_PHYS_VLV 1
+
+enum dpio_channel {
+ DPIO_CH0,
+ DPIO_CH1
+};
+
+enum dpio_phy {
+ DPIO_PHY0,
+ DPIO_PHY1
+};
+
enum intel_display_power_domain {
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
@@ -1401,6 +1413,7 @@ typedef struct drm_i915_private {
int num_shared_dpll;
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
struct intel_ddi_plls ddi_plls;
+ int vlv_phy[I915_NUM_PHYS_VLV];
/* Reclocking support */
bool render_reclock_avail;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f7ecad2..dd8ff3b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -447,6 +447,8 @@
#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \
_DPIO_TX3_SWING_CTL4_B)
+#define DPIO_PHY_PORT(pipe)(dev_priv-vlv_phy[pipe 1])
+
/*
* Per pipe/PLL DPIO regs
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8f40ae3..c08f9f8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1361,6 +1361,7 @@ static void intel_init_dpio(struct drm_device *dev)
if (!IS_VALLEYVIEW(dev))
return;
+ dev_priv-vlv_phy[DPIO_PHY0] = IOSF_PORT_DPIO;
/*
* From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
* 6. De-assert cmn_reset/side_reset. Same as VLV X0.
@@ -1494,18 +1495,25 @@ static void vlv_disable_pll(struct drm_i915_private
*dev_priv, enum pipe pipe)
POSTING_READ(DPLL(pipe));
}
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
+void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *dport)
{
u32 port_mask;
- if (!port)
+ switch (dport-port) {
+ case PORT_B:
port_mask = DPLL_PORTB_READY_MASK;
- else
+ break;
+ case PORT_C:
port_mask = DPLL_PORTC_READY_MASK;
+ break;
+ default:
+ BUG();
+ }
if (wait_for((I915_READ(DPLL(0)) port_mask) == 0, 1000))
WARN(1, timed out waiting for port %c ready: 0x%08x\n,
-'B' + port, I915_READ(DPLL(0)));
+'B' + dport-port, I915_READ(DPLL(0)));
}
/**
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b3cc333..5d00c83 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1831,7 +1831,7 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder)
struct drm_device *dev = encoder-base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder-base.crtc);
- int port = vlv_dport_to_channel(dport);
+ enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc-pipe;
struct edp_power_seq power_seq;
u32 val;
@@ -1839,7 +1839,6 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder)
mutex_lock(dev_priv-dpio_lock);
val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
- val = 0;
if (pipe)
val |= (121);
else
@@ -1858,7 +1857,7 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder)
intel_enable_dp(encoder);
- vlv_wait_port_ready(dev_priv, port);
+ vlv_wait_port_ready(dev_priv, dport);
}
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
@@ -1868,7 +1867,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc
[Intel-gfx] [PATCH] drm/i915: Make the vlv_dpio_read/vlv_dpio_write more PHY centric
vlv_dpio_read/write should be describe more in PHY centric instead of
display controller centric.
Create a enum dpio_channel for channel index and enum dpio_phy for PHY
index. This should better to gather for upcoming platform.
Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c |9 -
drivers/gpu/drm/i915/intel_drv.h |7 ---
drivers/gpu/drm/i915/intel_hdmi.c |9 -
drivers/gpu/drm/i915/intel_sideband.c | 13 ++---
7 files changed, 41 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80957ca..0ccfdc8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -88,6 +88,18 @@ enum port {
};
#define port_name(p) ((p) + 'A')
+#define I915_NUM_PHYS_VLV 1
+
+enum dpio_channel {
+ DPIO_CH0,
+ DPIO_CH1
+};
+
+enum dpio_phy {
+ DPIO_PHY0,
+ DPIO_PHY1
+};
+
enum intel_display_power_domain {
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
@@ -1390,6 +1402,7 @@ typedef struct drm_i915_private {
int num_shared_dpll;
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
struct intel_ddi_plls ddi_plls;
+ int vlv_phy[I915_NUM_PHYS_VLV];
/* Reclocking support */
bool render_reclock_avail;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b4f7b1..1fedde9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -447,6 +447,8 @@
#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \
_DPIO_TX3_SWING_CTL4_B)
+#define DPIO_PHY_PORT(pipe)(dev_priv-vlv_phy[pipe 1])
+
/*
* Per pipe/PLL DPIO regs
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3e79a2a..b401dbf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1361,6 +1361,7 @@ static void intel_init_dpio(struct drm_device *dev)
if (!IS_VALLEYVIEW(dev))
return;
+ dev_priv-vlv_phy[DPIO_PHY0] = IOSF_PORT_DPIO;
/*
* From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
* 6. De-assert cmn_reset/side_reset. Same as VLV X0.
@@ -1494,18 +1495,25 @@ static void vlv_disable_pll(struct drm_i915_private
*dev_priv, enum pipe pipe)
POSTING_READ(DPLL(pipe));
}
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
+void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *dport)
{
u32 port_mask;
- if (!port)
+ switch (dport-port) {
+ case PORT_B:
port_mask = DPLL_PORTB_READY_MASK;
- else
+ break;
+ case PORT_C:
port_mask = DPLL_PORTC_READY_MASK;
+ break;
+ default:
+ BUG();
+ }
if (wait_for((I915_READ(DPLL(0)) port_mask) == 0, 1000))
WARN(1, timed out waiting for port %c ready: 0x%08x\n,
-'B' + port, I915_READ(DPLL(0)));
+'B' + dport-port, I915_READ(DPLL(0)));
}
/**
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 749c605..4e72bc3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1831,7 +1831,7 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder)
struct drm_device *dev = encoder-base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder-base.crtc);
- int port = vlv_dport_to_channel(dport);
+ enum dpio_channel port = vlv_dport_to_channel(dport);
int pipe = intel_crtc-pipe;
struct edp_power_seq power_seq;
u32 val;
@@ -1839,7 +1839,6 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder)
mutex_lock(dev_priv-dpio_lock);
val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
- val = 0;
if (pipe)
val |= (121);
else
@@ -1858,7 +1857,7 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder)
intel_enable_dp(encoder);
- vlv_wait_port_ready(dev_priv, port);
+ vlv_wait_port_ready(dev_priv, dport);
}
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
@@ -1868,7 +1867,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc =
to_intel_crtc(encoder-base.crtc);
- int port = vlv_dport_to_channel(dport
[Intel-gfx] [PATCH] drm/i915: Move some hdmi enable function name to vlv specific.
There is no functional change on this patch. Only rename several
hdmi encoder function name which suppose to use only by valleyview from
intel_hdmi_pre_pll_enable to vlv_hdmi_pre_pll_enable, and etc.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/intel_hdmi.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 4f4d346..51a8336 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1074,7 +1074,7 @@ done:
return 0;
}
-static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
+static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
{
struct intel_digital_port *dport = enc_to_dig_port(encoder-base);
struct drm_device *dev = encoder-base.dev;
@@ -1127,7 +1127,7 @@ static void intel_hdmi_pre_enable(struct intel_encoder
*encoder)
vlv_wait_port_ready(dev_priv, port);
}
-static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
+static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
{
struct intel_digital_port *dport = enc_to_dig_port(encoder-base);
struct drm_device *dev = encoder-base.dev;
@@ -1163,7 +1163,7 @@ static void intel_hdmi_pre_pll_enable(struct
intel_encoder *encoder)
mutex_unlock(dev_priv-dpio_lock);
}
-static void intel_hdmi_post_disable(struct intel_encoder *encoder)
+static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
{
struct intel_digital_port *dport = enc_to_dig_port(encoder-base);
struct drm_i915_private *dev_priv = encoder-base.dev-dev_private;
@@ -1313,10 +1313,10 @@ void intel_hdmi_init(struct drm_device *dev, int
hdmi_reg, enum port port)
intel_encoder-get_hw_state = intel_hdmi_get_hw_state;
intel_encoder-get_config = intel_hdmi_get_config;
if (IS_VALLEYVIEW(dev)) {
- intel_encoder-pre_pll_enable = intel_hdmi_pre_pll_enable;
- intel_encoder-pre_enable = intel_hdmi_pre_enable;
+ intel_encoder-pre_pll_enable = vlv_hdmi_pre_pll_enable;
+ intel_encoder-pre_enable = vlv_hdmi_pre_enable;
intel_encoder-enable = vlv_enable_hdmi;
- intel_encoder-post_disable = intel_hdmi_post_disable;
+ intel_encoder-post_disable = vlv_hdmi_post_disable;
} else {
intel_encoder-enable = intel_enable_hdmi;
}
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/vlv: Turn off power gate for BIOS-less system.
During system boot up, by default, the power gate for render, media and
display well still power gated. Normally, BIOS will turn off the power
gate. In the BIOS-less system, the driver need to turn off the power
gate very early during driver load.
v2: Move this to intel_uncore_sanitize to allow it to get call during
resume path. (Daniel)
v3: Remove redundant write 0 to DPIO_CTL, and use DPIO_RESET instead of
just 0x1 (Ville)
Add turn of power gate for display 2d/render well/media well.
v4: Remove toggle cmnreset in intel_uncore_sanitize. Cmnreset should
toggle after CRI clock source has been selected. Jesse DPIO reset patch
which toggle the cmnreset in intel_modeset_init_hw() should handle it.
(Ville)
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |9 +
drivers/gpu/drm/i915/intel_uncore.c | 16
2 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3432de4..f14310b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -361,6 +361,15 @@
#define PUNIT_OPCODE_REG_READ 6
#define PUNIT_OPCODE_REG_WRITE 7
+#define PUNIT_REG_PWRGT_CTRL 0x60
+#define PUNIT_REG_PWRGT_STATUS 0x61
+#define PUNIT_CLK_GATE1
+#define PUNIT_PWR_RESET 2
+#define PUNIT_PWR_GATE3
+#define RENDER_PWRGT (PUNIT_PWR_GATE 0)
+#define MEDIA_PWRGT (PUNIT_PWR_GATE 2)
+#define DISP2D_PWRGT (PUNIT_PWR_GATE 6)
+
#define PUNIT_REG_GPU_LFM 0xd3
#define PUNIT_REG_GPU_FREQ_REQ 0xd4
#define PUNIT_REG_GPU_FREQ_STS 0xd8
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index f2753d9..288a3a6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -301,10 +301,26 @@ static void intel_uncore_forcewake_reset(struct
drm_device *dev)
void intel_uncore_sanitize(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 reg_val;
+
intel_uncore_forcewake_reset(dev);
/* BIOS often leaves RC6 enabled, but disable it for hw init */
intel_disable_gt_powersave(dev);
+
+ /* Turn off power gate, require especially for the BIOS less system */
+ if (IS_VALLEYVIEW(dev)) {
+
+ mutex_lock(dev_priv-rps.hw_lock);
+ reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
+
+ if (reg_val (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
+ vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
+
+ mutex_unlock(dev_priv-rps.hw_lock);
+
+ }
}
/*
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Program GMBUS Frequency based on the CDCLK for VLV.
CDCLK is used to generate the gmbus clock. This is normally done by
BIOS. Program the value if the BIOS-less system doesn't do it.
v2: Move this to intel_i2c_reset to allow reprogram the gmbus frequency
during resume. (Daniel)
v3: Change GMBUS_FREQ to GMBUSFREQ_VLV, and use VLV_DISPLAY_BASE.
(Ville).
Remove cdclk_ratio[] table, and calculate the cdclk ratio instead.
(Ville).
Change the shift then mask for reg read, to mask first, then shift.
(Ville).
Remove the gmbus frequency calculation = cdclk/1.01. Based on BIOS
programming, gmbus frequency = cdclk frequency. (Ville)
Add get_disp_clk_div, which can use to get cdclk/czclk divide.
v4: Fix the mmio_offset base for CZCLK_CDCLK_FREQ_RATIO, gmbus_freq
calculation, and duplicate check for gmbus_freq. (Ville)
In VLV, the spec is wrong about 4Mhz reference frequency for GMBUS. It
should be 1Mhz.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8 +
drivers/gpu/drm/i915/intel_i2c.c | 57 ++
2 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0a9811..b37dfd8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -391,6 +391,8 @@
#define FB_FMAX_VMIN_FREQ_LO_MASK0xf800
/* vlv2 north clock has */
+#define CCK_FUSE_REG 0x8
+#define CCK_FUSE_HPLL_FREQ_MASK 0x3
#define CCK_REG_DSI_PLL_FUSE 0x44
#define CCK_REG_DSI_PLL_CONTROL0x48
#define DSI_PLL_VCO_EN(1 31)
@@ -1438,6 +1440,12 @@
#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
+#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
+#define CDCLK_FREQ_SHIFT 4
+#define CDCLK_FREQ_MASK (0x1f CDCLK_FREQ_SHIFT)
+#define CZCLK_FREQ_MASK 0xf
+#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
+
/*
* Palette regs
*/
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d1c1e0f7..b579ffd 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -34,6 +34,11 @@
#include drm/i915_drm.h
#include i915_drv.h
+enum disp_clk {
+ CDCLK,
+ CZCLK
+};
+
struct gmbus_port {
const char *name;
int reg;
@@ -58,10 +63,62 @@ to_intel_gmbus(struct i2c_adapter *i2c)
return container_of(i2c, struct intel_gmbus, adapter);
}
+static int get_disp_clk_div(struct drm_i915_private *dev_priv, enum disp_clk
clk)
+{
+ u32 reg_val;
+ int clk_ratio;
+
+ reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
+
+ if (clk == CDCLK)
+ clk_ratio = ((reg_val CDCLK_FREQ_MASK) CDCLK_FREQ_SHIFT) +
1;
+ else
+ clk_ratio = (reg_val CZCLK_FREQ_MASK) + 1;
+
+ return clk_ratio;
+}
+
+static void gmbus_set_freq(struct drm_i915_private *dev_priv)
+{
+ int vco_freq[] = { 800, 1600, 2000, 2400 };
+ int gmbus_freq = 0, cdclk_div, hpll_freq;
+
+ BUG_ON(!IS_VALLEYVIEW(dev_priv-dev));
+
+ /* Skip setting the gmbus freq if BIOS has already programmed it */
+ if (I915_READ(GMBUSFREQ_VLV) != 0xA0)
+ return;
+
+ /* Obtain SKU information */
+ mutex_lock(dev_priv-dpio_lock);
+ hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG)
CCK_FUSE_HPLL_FREQ_MASK;
+ mutex_unlock(dev_priv-dpio_lock);
+
+ /* Get the CDCLK divide ratio */
+ cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
+
+ /* Program the gmbus_freq based on the cdclk frequency */
+ if (cdclk_div)
+ gmbus_freq = (vco_freq[hpll_freq] 1) / cdclk_div;
+
+ if (WARN_ON(gmbus_freq == 0))
+ return;
+
+ I915_WRITE(GMBUSFREQ_VLV, gmbus_freq);
+}
+
void
intel_i2c_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+
+ /*
+* In BIOS-less system, program the correct gmbus frequency
+* before reading edid.
+*/
+ if (IS_VALLEYVIEW(dev))
+ gmbus_set_freq(dev_priv);
+
I915_WRITE(dev_priv-gpio_mmio_base + GMBUS0, 0);
I915_WRITE(dev_priv-gpio_mmio_base + GMBUS4, 0);
}
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix VLV eDP timing
Fix the typo in previous commit for DP 1.62 divisor.
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
Reported-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/intel_dp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5e1de35..a8ceccf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -59,7 +59,7 @@ static const struct dp_link_dpll pch_dpll[] = {
static const struct dp_link_dpll vlv_dpll[] = {
{ DP_LINK_BW_1_62,
- { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } },
+ { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 81 } },
{ DP_LINK_BW_2_7,
{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix VLV eDP timing v2
Fix the typo in previous commit for DP 1.62 divisor.
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
v2: sigh, the m1 div is 3.
Reported-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/intel_dp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5e1de35..a5e4e61 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -59,7 +59,7 @@ static const struct dp_link_dpll pch_dpll[] = {
static const struct dp_link_dpll vlv_dpll[] = {
{ DP_LINK_BW_1_62,
- { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } },
+ { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
{ DP_LINK_BW_2_7,
{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Send a DPIO cmnreset during driver load or system resume.
Without the DPIO cmnreset, the PLL fail to lock. This should have
done by BIOS.
v2: Move this to intel_uncore_sanitize to allow it to get call during
resume path. (Daniel)
v3: Remove redundant write 0 to DPIO_CTL, and use DPIO_RESET instead of
just 0x1 (Ville)
Without BIOS, DPIO/render well/media well may still power gated.
Turn it off.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |9 +
drivers/gpu/drm/i915/intel_uncore.c | 23 +++
2 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4f9bef..c02f893 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -361,6 +361,15 @@
#define PUNIT_OPCODE_REG_READ 6
#define PUNIT_OPCODE_REG_WRITE 7
+#define PUNIT_REG_PWRGT_CTRL 0x60
+#define PUNIT_REG_PWRGT_STATUS 0x61
+#define PUNIT_CLK_GATE1
+#define PUNIT_PWR_RESET 2
+#define PUNIT_PWR_GATE3
+#define RENDER_PWRGT (PUNIT_PWR_GATE 0)
+#define MEDIA_PWRGT (PUNIT_PWR_GATE 2)
+#define DPIO_PWRGT(PUNIT_PWR_GATE 6)
+
#define PUNIT_REG_GPU_LFM 0xd3
#define PUNIT_REG_GPU_FREQ_REQ 0xd4
#define PUNIT_REG_GPU_FREQ_STS 0xd8
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8649f1c..6923b4d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -276,10 +276,33 @@ static void intel_uncore_forcewake_reset(struct
drm_device *dev)
void intel_uncore_sanitize(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 reg_val;
+
intel_uncore_forcewake_reset(dev);
/* BIOS often leaves RC6 enabled, but disable it for hw init */
intel_disable_gt_powersave(dev);
+
+ /* Trigger DPIO CMN RESET and turn off power gate, require
+* especially in BIOS less system
+*/
+ if (IS_VALLEYVIEW(dev)) {
+
+ mutex_lock(dev_priv-rps.hw_lock);
+ reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
+
+ if (reg_val (RENDER_PWRGT | MEDIA_PWRGT | DPIO_PWRGT))
+ vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
+
+ mutex_unlock(dev_priv-rps.hw_lock);
+
+ reg_val = I915_READ(DPIO_CTL);
+ if (!(reg_val DPIO_RESET)) {
+ I915_WRITE(DPIO_CTL, DPIO_RESET);
+ POSTING_READ(DPIO_CTL);
+ }
+ }
}
/*
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Send a DPIO cmnreset during driver load or system resume.
Without the DPIO cmnreset, the PLL fail to lock. This should have
done by BIOS.
v2: Move this to intel_uncore_sanitize to allow it to get call during
resume path. (Daniel)
v3: Remove redundant write 0 to DPIO_CTL, and use DPIO_RESET instead of
just 0x1 (Ville)
Without BIOS, DPIO/render well/media well may still power gated.
Turn it off.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |9 +
drivers/gpu/drm/i915/intel_uncore.c | 23 +++
2 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4f9bef..c02f893 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -361,6 +361,15 @@
#define PUNIT_OPCODE_REG_READ 6
#define PUNIT_OPCODE_REG_WRITE 7
+#define PUNIT_REG_PWRGT_CTRL 0x60
+#define PUNIT_REG_PWRGT_STATUS 0x61
+#define PUNIT_CLK_GATE1
+#define PUNIT_PWR_RESET 2
+#define PUNIT_PWR_GATE3
+#define RENDER_PWRGT (PUNIT_PWR_GATE 0)
+#define MEDIA_PWRGT (PUNIT_PWR_GATE 2)
+#define DPIO_PWRGT(PUNIT_PWR_GATE 6)
+
#define PUNIT_REG_GPU_LFM 0xd3
#define PUNIT_REG_GPU_FREQ_REQ 0xd4
#define PUNIT_REG_GPU_FREQ_STS 0xd8
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8649f1c..6923b4d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -276,10 +276,33 @@ static void intel_uncore_forcewake_reset(struct
drm_device *dev)
void intel_uncore_sanitize(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 reg_val;
+
intel_uncore_forcewake_reset(dev);
/* BIOS often leaves RC6 enabled, but disable it for hw init */
intel_disable_gt_powersave(dev);
+
+ /* Trigger DPIO CMN RESET and turn off power gate, require
+* especially in BIOS less system
+*/
+ if (IS_VALLEYVIEW(dev)) {
+
+ mutex_lock(dev_priv-rps.hw_lock);
+ reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
+
+ if (reg_val (RENDER_PWRGT | MEDIA_PWRGT | DPIO_PWRGT))
+ vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
+
+ mutex_unlock(dev_priv-rps.hw_lock);
+
+ reg_val = I915_READ(DPIO_CTL);
+ if (!(reg_val DPIO_RESET)) {
+ I915_WRITE(DPIO_CTL, DPIO_RESET);
+ POSTING_READ(DPIO_CTL);
+ }
+ }
}
/*
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Program GMBUS Frequency based on the CDCLK for VLV.
CDCLK is used to generate the gmbus clock. This is normally done by
BIOS. Program the value if the BIOS-less system doesn't do it.
v2: Move this to intel_i2c_reset to allow reprogram the gmbus frequency
during resume. (Daniel)
v3: Change GMBUS_FREQ to GMBUSFREQ_VLV, and use VLV_DISPLAY_BASE.
(Ville).
Remove cdclk_ratio[] table, and calculate the cdclk ratio instead.
(Ville).
Change the shift then mask for reg read, to mask first, then shift.
(Ville).
Remove the gmbus frequency calculation = cdclk/1.01. Based on BIOS
programming, gmbus frequency = cdclk frequency. (Ville)
Add get_disp_clk_div, which can use to get cdclk/czclk divide.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8 +
drivers/gpu/drm/i915/intel_i2c.c | 60 ++
2 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c02f893..e8315c6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -391,6 +391,8 @@
#define FB_FMAX_VMIN_FREQ_LO_MASK0xf800
/* vlv2 north clock has */
+#define CCK_FUSE_REG 0x8
+#define CCK_FUSE_HPLL_FREQ_MASK 0x3
#define CCK_REG_DSI_PLL_FUSE 0x44
#define CCK_REG_DSI_PLL_CONTROL0x48
#define DSI_PLL_VCO_EN(1 31)
@@ -1438,6 +1440,12 @@
#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
+#define CZCLK_CDCLK_FREQ_RATIO (dev_priv-info-display_mmio_offset + 0x6508)
+#define CDCLK_FREQ_SHIFT 4
+#define CDCLK_FREQ_MASK (0x1f CDCLK_FREQ_SHIFT)
+#define CZCLK_FREQ_MASK 0xf
+#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
+
/*
* Palette regs
*/
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d1c1e0f7..b225d60 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -34,6 +34,11 @@
#include drm/i915_drm.h
#include i915_drv.h
+enum disp_clk {
+ CDCLK = 0,
+ CZCLK
+};
+
struct gmbus_port {
const char *name;
int reg;
@@ -58,10 +63,65 @@ to_intel_gmbus(struct i2c_adapter *i2c)
return container_of(i2c, struct intel_gmbus, adapter);
}
+static int get_disp_clk_div(struct drm_i915_private *dev_priv, enum disp_clk
clk)
+{
+ u32 reg_val;
+ int clk_ratio;
+
+ reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
+
+ if (clk == CDCLK)
+ clk_ratio = ((reg_val CDCLK_FREQ_MASK) CDCLK_FREQ_SHIFT) +
1;
+ else
+ clk_ratio = (reg_val CZCLK_FREQ_MASK) + 1;
+
+ return clk_ratio * 5;
+}
+
+static void gmbus_set_freq(struct drm_i915_private *dev_priv)
+{
+ int vco_freq[] = { 800, 1600, 2000, 2400 };
+ int gmbus_freq = 0, cdclk_div, hpll_freq;
+ u32 reg_val;
+
+ BUG_ON(!IS_VALLEYVIEW(dev_priv-dev));
+
+ /* Skip setting the gmbus freq if BIOS has already programmed it */
+ if (I915_READ(GMBUSFREQ_VLV) != 0xA0)
+ return;
+
+ /* Obtain SKU information to determine the correct CDCLK */
+ mutex_lock(dev_priv-dpio_lock);
+ reg_val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
+ mutex_unlock(dev_priv-dpio_lock);
+
+ hpll_freq = reg_val CCK_FUSE_HPLL_FREQ_MASK;
+
+ /* Get the CDCLK divide ratio */
+ cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
+
+ /* Program the gmbus_freq based on the cdclk frequency */
+ if (cdclk_div)
+ gmbus_freq = vco_freq[hpll_freq] * 10 / cdclk_div;
+
+ WARN_ON(gmbus_freq == 0);
+
+ if (gmbus_freq != 0)
+ I915_WRITE(GMBUSFREQ_VLV, gmbus_freq);
+
+}
+
void
intel_i2c_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+
+ /* In BIOS-less system, program the correct gmbus frequency
+* before reading edid.
+*/
+ if (IS_VALLEYVIEW(dev))
+ gmbus_set_freq(dev_priv);
+
I915_WRITE(dev_priv-gpio_mmio_base + GMBUS0, 0);
I915_WRITE(dev_priv-gpio_mmio_base + GMBUS4, 0);
}
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Enable VLV to work in BIOS-less system.
In non PC system, such as IVI, may not use BIOS, instead it uses boot loader with only minimal system initialization. Most of the time, boot loader doesn't come with VBIOS, and depends on device driver to fully initialize the display controller and GPU. For Valleyview, without VBIOS, i915 fails to work. The patch add some missing init code, such as doing a DPIO CMNRESET and program the GMBUS frequency. Chon Ming Lee (2): drm/i915: Send a DPIO cmnreset during driver load or system resume. drm/i915: Program GMBUS Frequency based on the CDCLK drivers/gpu/drm/i915/i915_reg.h |8 ++ drivers/gpu/drm/i915/intel_i2c.c| 43 +++ drivers/gpu/drm/i915/intel_uncore.c | 15 3 files changed, 66 insertions(+), 0 deletions(-) -- 1.7.7.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Send a DPIO cmnreset during driver load or system resume.
Without the DPIO cmnreset, the PLL fail to lock. This should have
done by BIOS.
v2: Move this to intel_uncore_sanitize to allow it to get call during
resume path. (Daniel)
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8649f1c..b1f53f3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -276,10 +276,25 @@ static void intel_uncore_forcewake_reset(struct
drm_device *dev)
void intel_uncore_sanitize(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ u32 reg_val;
+
intel_uncore_forcewake_reset(dev);
/* BIOS often leaves RC6 enabled, but disable it for hw init */
intel_disable_gt_powersave(dev);
+
+ /* Trigger DPIO CMN RESET, require especially in BIOS less
+* system
+*/
+ if (IS_VALLEYVIEW(dev)) {
+ reg_val = I915_READ(DPIO_CTL);
+ if (!(reg_val 0x1)) {
+ I915_WRITE(DPIO_CTL, 0x0);
+ I915_WRITE(DPIO_CTL, 0x1);
+ POSTING_READ(DPIO_CTL);
+ }
+ }
}
/*
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Program GMBUS Frequency based on the CDCLK
CDCLK is used to generate the gmbus clock. This is normally done by
BIOS. This is only for valleyview platform.
v2: Move this to intel_i2c_reset to allow reprogram the gmbus frequency
during resume. (Daniel)
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8 +++
drivers/gpu/drm/i915/intel_i2c.c | 43 ++
2 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee89b..8ddf58a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -382,6 +382,8 @@
#define FB_FMAX_VMIN_FREQ_LO_MASK0xf800
/* vlv2 north clock has */
+#define CCK_FUSE_REG 0x8
+#define CCK_FUSE_HPLL_FREQ_MASK 0x3
#define CCK_REG_DSI_PLL_FUSE 0x44
#define CCK_REG_DSI_PLL_CONTROL0x48
#define DSI_PLL_VCO_EN(1 31)
@@ -1424,6 +1426,12 @@
#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
+#define CZCLK_CDCLK_FREQ_RATIO (dev_priv-info-display_mmio_offset + 0x6508)
+#define CDCLK_FREQ_SHIFT 4
+#define CDCLK_FREQ_MASK 0x1f
+#define CZCLK_FREQ_MASK 0xf
+#define GMBUS_FREQ (dev_priv-info-display_mmio_offset + 0x6510)
+
/*
* Palette regs
*/
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d1c1e0f7..a8c4165 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -58,10 +58,53 @@ to_intel_gmbus(struct i2c_adapter *i2c)
return container_of(i2c, struct intel_gmbus, adapter);
}
+static void gmbus_set_freq(struct drm_i915_private *dev_priv)
+{
+ int cdclk_ratio[] = { 10, 15, 20, 25, 30, 0, 40, 45, 50, 0,
+ 60, 0, 0, 75, 80, 0, 90, 0, 100, 0,
+ 0, 0, 120, 0, 0, 0, 0, 0, 150, 0, 160 };
+ int vco_freq[] = { 800, 1600, 2000, 2400 };
+ int gmbus_freq = 0, cdclk, hpll_freq;
+ u32 reg_val;
+
+ BUG_ON(!IS_VALLEYVIEW(dev_priv-dev));
+
+ /* Obtain SKU information to determine the correct CDCLK */
+ mutex_lock(dev_priv-dpio_lock);
+ reg_val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
+ mutex_unlock(dev_priv-dpio_lock);
+
+ hpll_freq = reg_val CCK_FUSE_HPLL_FREQ_MASK;
+
+ /* Get the CDCLK frequency */
+ reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
+
+ cdclk = ((reg_val CDCLK_FREQ_SHIFT) CDCLK_FREQ_MASK) - 1;
+
+ /* To enable hotplug detect, the gmbus frequency need to set as
+* cdclk/1.01
+*/
+ if (cdclk_ratio[cdclk])
+ gmbus_freq = vco_freq[hpll_freq] / cdclk_ratio[cdclk] * 101 /
10;
+
+ WARN_ON(gmbus_freq == 0);
+
+ if (gmbus_freq != 0)
+ I915_WRITE(GMBUS_FREQ, gmbus_freq);
+
+}
+
void
intel_i2c_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
+
+ /* In BIOS-less system, program the correct gmbus frequency
+* before reading edid.
+*/
+ if (IS_VALLEYVIEW(dev))
+ gmbus_set_freq(dev_priv);
+
I915_WRITE(dev_priv-gpio_mmio_base + GMBUS0, 0);
I915_WRITE(dev_priv-gpio_mmio_base + GMBUS4, 0);
}
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Enable VLV to work in BIOS-less system
In non PC system, such as IVI, may not use BIOS, instead it uses boot
loader with only minimal system initialization. Most of the time, boot
loader doesn't come with VBIOS, and depends on device driver to fully
initialize the display controller and GPU.
For Valleyview, without VBIOS, i915 fails to work. The patch add some
missing init code, such as doing a DPIO CMNRESET and program the GMBUS
frequency.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8 +
drivers/gpu/drm/i915/intel_display.c | 51 ++
2 files changed, 59 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee89b..8ddf58a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -382,6 +382,8 @@
#define FB_FMAX_VMIN_FREQ_LO_MASK0xf800
/* vlv2 north clock has */
+#define CCK_FUSE_REG 0x8
+#define CCK_FUSE_HPLL_FREQ_MASK 0x3
#define CCK_REG_DSI_PLL_FUSE 0x44
#define CCK_REG_DSI_PLL_CONTROL0x48
#define DSI_PLL_VCO_EN(1 31)
@@ -1424,6 +1426,12 @@
#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
+#define CZCLK_CDCLK_FREQ_RATIO (dev_priv-info-display_mmio_offset + 0x6508)
+#define CDCLK_FREQ_SHIFT 4
+#define CDCLK_FREQ_MASK 0x1f
+#define CZCLK_FREQ_MASK 0xf
+#define GMBUS_FREQ (dev_priv-info-display_mmio_offset + 0x6510)
+
/*
* Palette regs
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3c0e0cf..9ef1d28 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9497,6 +9497,31 @@ static bool has_edp_a(struct drm_device *dev)
return true;
}
+static void gmbus_set_freq(struct drm_i915_private *dev_priv, u32 hpll_freq)
+{
+ int cdclk_ratio[] = { 10, 15, 20, 25, 30, 0, 40, 45, 50, 0,
+ 60, 0, 0, 75, 80, 0, 90, 0, 100, 0,
+ 0, 0, 120, 0, 0, 0, 0, 0, 150, 0, 160 };
+ int vco_freq[] = { 800, 1600, 2000, 2400 };
+ int gmbus_freq = 0, cdclk;
+ u32 reg_val;
+
+ BUG_ON(hpll_freq ARRAY_SIZE(vco_freq));
+
+ reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
+
+ cdclk = ((reg_val CDCLK_FREQ_SHIFT) CDCLK_FREQ_MASK) - 1;
+
+ if (cdclk_ratio[cdclk])
+ gmbus_freq = vco_freq[hpll_freq] / cdclk_ratio[cdclk] * 10;
+
+ WARN_ON(gmbus_freq == 0);
+
+ if (gmbus_freq != 0)
+ I915_WRITE(GMBUS_FREQ, gmbus_freq);
+
+}
+
static void intel_setup_outputs(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -9555,6 +9580,32 @@ static void intel_setup_outputs(struct drm_device *dev)
if (I915_READ(PCH_DP_D) DP_DETECTED)
intel_dp_init(dev, PCH_DP_D, PORT_D);
} else if (IS_VALLEYVIEW(dev)) {
+ u32 reg_val;
+
+ /* Trigger DPIO CMN RESET, require especially in BIOS less
+* system
+*/
+ reg_val = I915_READ(DPIO_CTL);
+ if (!(reg_val 0x1)) {
+ I915_WRITE(DPIO_CTL, 0x0);
+ I915_WRITE(DPIO_CTL, 0x1);
+ POSTING_READ(DPIO_CTL);
+ }
+
+ /* In BIOS-less system, program the correct gmbus frequency
+* before reading edid.
+*/
+
+ /* Obtain SKU information to determine the correct CDCLK */
+ mutex_lock(dev_priv-dpio_lock);
+ reg_val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
+ mutex_unlock(dev_priv-dpio_lock);
+
+ reg_val = CCK_FUSE_HPLL_FREQ_MASK;
+
+ /* Write CDCLK to GMBUS freq for GMBUS clk generation. */
+ gmbus_set_freq(dev_priv, reg_val);
+
/* Check for built-in panel first. Shares lanes with HDMI on
SDVOC */
if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) SDVO_DETECTED) {
intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add additional pipe parameter for vlv_dpio_read and vlv_dpio_write.
The additional pipe parameter will use to select which phy to target
for.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++--
drivers/gpu/drm/i915/i915_drv.h |4 +-
drivers/gpu/drm/i915/intel_display.c | 51 +
drivers/gpu/drm/i915/intel_dp.c | 38 ++--
drivers/gpu/drm/i915/intel_hdmi.c | 48 +-
drivers/gpu/drm/i915/intel_sideband.c | 20 +---
6 files changed, 101 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a6f4cb5..9ac4e31 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1610,27 +1610,27 @@ static int i915_dpio_info(struct seq_file *m, void
*data)
seq_printf(m, DPIO_CTL: 0x%08x\n, I915_READ(DPIO_CTL));
seq_printf(m, DPIO_DIV_A: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_DIV_A));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
seq_printf(m, DPIO_DIV_B: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_DIV_B));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
seq_printf(m, DPIO_REFSFR_A: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
seq_printf(m, DPIO_REFSFR_B: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
seq_printf(m, DPIO_CORE_CLK_A: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
seq_printf(m, DPIO_CORE_CLK_B: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
seq_printf(m, DPIO_LPF_COEFF_A: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
seq_printf(m, DPIO_LPF_COEFF_B: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
seq_printf(m, DPIO_FASTCLK_DISABLE: 0x%08x\n,
- vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
+ vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
mutex_unlock(dev_priv-dpio_lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 769c138..e357995 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2282,8 +2282,8 @@ u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32
reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
-void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
+u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
+void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int
reg, u32 val);
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 67d841d..be1c4e6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4364,7 +4364,8 @@ static void i9xx_update_pll_dividers(struct intel_crtc
*crtc,
}
}
-static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
+static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
+ pipe)
{
u32 reg_val;
@@ -4372,24 +4373,24 @@ static void vlv_pllb_recal_opamp(struct
drm_i915_private *dev_priv)
* PLLB opamp always calibrates to max value of 0x3f, force enable it
* and set it to a reasonable value instead.
*/
- reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
+ reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
reg_val = 0xff00;
reg_val |= 0x0030;
- vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+ vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
- reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
+ reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
reg_val = 0x8cff;
reg_val = 0x8c00;
- vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
+ vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
- reg_val
[Intel-gfx] [PATCH] drm/i915: Add additional pipe parameter for vlv_dpio_read and vlv_dpio_write. v2
The patch doesn't contain functional change, but is to prepare for
future platform which has different DPIO phy. The additional pipe
parameter will use to select which phy to target for.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
v2: Update the commit message and add static for the new function.
(Jani/Ville)
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++--
drivers/gpu/drm/i915/i915_drv.h |4 +-
drivers/gpu/drm/i915/intel_display.c | 51 +
drivers/gpu/drm/i915/intel_dp.c | 38 ++--
drivers/gpu/drm/i915/intel_hdmi.c | 48 +-
drivers/gpu/drm/i915/intel_sideband.c | 18 ---
6 files changed, 99 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a6f4cb5..9ac4e31 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1610,27 +1610,27 @@ static int i915_dpio_info(struct seq_file *m, void
*data)
seq_printf(m, DPIO_CTL: 0x%08x\n, I915_READ(DPIO_CTL));
seq_printf(m, DPIO_DIV_A: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_DIV_A));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
seq_printf(m, DPIO_DIV_B: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_DIV_B));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
seq_printf(m, DPIO_REFSFR_A: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
seq_printf(m, DPIO_REFSFR_B: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
seq_printf(m, DPIO_CORE_CLK_A: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
seq_printf(m, DPIO_CORE_CLK_B: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
seq_printf(m, DPIO_LPF_COEFF_A: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
seq_printf(m, DPIO_LPF_COEFF_B: 0x%08x\n,
- vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B));
+ vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
seq_printf(m, DPIO_FASTCLK_DISABLE: 0x%08x\n,
- vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
+ vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
mutex_unlock(dev_priv-dpio_lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 769c138..e357995 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2282,8 +2282,8 @@ u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32
reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
-void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
+u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
+void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int
reg, u32 val);
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d88057e..bac7152 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4354,7 +4354,8 @@ static void i9xx_update_pll_dividers(struct intel_crtc
*crtc,
}
}
-static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
+static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
+ pipe)
{
u32 reg_val;
@@ -4362,24 +4363,24 @@ static void vlv_pllb_recal_opamp(struct
drm_i915_private *dev_priv)
* PLLB opamp always calibrates to max value of 0x3f, force enable it
* and set it to a reasonable value instead.
*/
- reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
+ reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
reg_val = 0xff00;
reg_val |= 0x0030;
- vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
+ vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
- reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
+ reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
reg_val
[Intel-gfx] [PATCH 1/2] drm/i915: Modify DP set clock to accomodate more eDP timings v2
eDP 1.4 supports 4-5 extra link rates in additional to current 2 link
rate. Create a structure to store the DPLL divisor data to improve
readability.
v2: Fix the gen4_dpll/pch_dpll initialization to C99
designated initializers, and use a single loop for all platforms. (Jani and
Daniel)
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 65 ++-
1 files changed, 37 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2151d13..fd09058 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -38,6 +38,27 @@
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
+struct dp_link_dpll {
+ int link_bw;
+ struct dpll dpll;
+};
+
+static const struct dp_link_dpll gen4_dpll[] =
+{
+ { DP_LINK_BW_1_62,
+ { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 }},
+ { DP_LINK_BW_2_7,
+ { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 }}
+};
+
+static const struct dp_link_dpll pch_dpll[] =
+{
+ { DP_LINK_BW_1_62,
+ { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 }},
+ { DP_LINK_BW_2_7,
+ { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 }}
+};
+
/**
* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
* @intel_dp: DP struct
@@ -649,42 +670,30 @@ intel_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config, int link_bw)
{
struct drm_device *dev = encoder-base.dev;
+ const struct dp_link_dpll *divisor = NULL;
+ int i, count = 0;
if (IS_G4X(dev)) {
- if (link_bw == DP_LINK_BW_1_62) {
- pipe_config-dpll.p1 = 2;
- pipe_config-dpll.p2 = 10;
- pipe_config-dpll.n = 2;
- pipe_config-dpll.m1 = 23;
- pipe_config-dpll.m2 = 8;
- } else {
- pipe_config-dpll.p1 = 1;
- pipe_config-dpll.p2 = 10;
- pipe_config-dpll.n = 1;
- pipe_config-dpll.m1 = 14;
- pipe_config-dpll.m2 = 2;
- }
- pipe_config-clock_set = true;
+ divisor = gen4_dpll;
+ count = ARRAY_SIZE(gen4_dpll);
} else if (IS_HASWELL(dev)) {
/* Haswell has special-purpose DP DDI clocks. */
} else if (HAS_PCH_SPLIT(dev)) {
- if (link_bw == DP_LINK_BW_1_62) {
- pipe_config-dpll.n = 1;
- pipe_config-dpll.p1 = 2;
- pipe_config-dpll.p2 = 10;
- pipe_config-dpll.m1 = 12;
- pipe_config-dpll.m2 = 9;
- } else {
- pipe_config-dpll.n = 2;
- pipe_config-dpll.p1 = 1;
- pipe_config-dpll.p2 = 10;
- pipe_config-dpll.m1 = 14;
- pipe_config-dpll.m2 = 8;
- }
- pipe_config-clock_set = true;
+ divisor = pch_dpll;
+ count = ARRAY_SIZE(pch_dpll);
} else if (IS_VALLEYVIEW(dev)) {
/* FIXME: Need to figure out optimized DP clocks for vlv. */
}
+
+ if (divisor count) {
+ for (i = 0; i count; i++) {
+ if (link_bw == divisor[i].link_bw) {
+ pipe_config-dpll = divisor[i].dpll;
+ pipe_config-clock_set = true;
+ break;
+ }
+ }
+ }
}
bool
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
For DP pll settings, there is only two golden configs. Instead of
running through the algorithm to determine it, hardcode the value and get it
determine in intel_dp_set_clock.
v2: Rework on the intel_limit compiler warning. (Jani)
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 20 +++-
drivers/gpu/drm/i915/intel_dp.c | 11 ++-
2 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f526ea9..1a567d2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -339,19 +339,6 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
.p2_slow = 2, .p2_fast = 20 },
};
-static const intel_limit_t intel_limits_vlv_dp = {
- .dot = { .min = 25000, .max = 27 },
- .vco = { .min = 400, .max = 600 },
- .n = { .min = 1, .max = 7 },
- .m = { .min = 22, .max = 450 },
- .m1 = { .min = 2, .max = 3 },
- .m2 = { .min = 11, .max = 156 },
- .p = { .min = 10, .max = 30 },
- .p1 = { .min = 1, .max = 3 },
- .p2 = { .dot_limit = 27,
- .p2_slow = 2, .p2_fast = 20 },
-};
-
static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
int refclk)
{
@@ -414,10 +401,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc
*crtc, int refclk)
} else if (IS_VALLEYVIEW(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
limit = intel_limits_vlv_dac;
- else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
- limit = intel_limits_vlv_hdmi;
else
- limit = intel_limits_vlv_dp;
+ limit = intel_limits_vlv_hdmi;
} else if (!IS_GEN2(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
limit = intel_limits_i9xx_lvds;
@@ -4890,7 +4875,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
refclk = i9xx_get_refclk(crtc, num_connectors);
- if (!is_dsi) {
+ if (!is_dsi !intel_crtc-config.clock_set) {
/*
* Returns a set of divisors for the desired target clock with
* the given refclk, or FALSE. The returned values represent
@@ -4917,6 +4902,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
* by using the FP0/FP1. In such case we will disable the LVDS
* downclock feature.
*/
+ limit = intel_limit(crtc, refclk);
has_reduced_clock =
dev_priv-display.find_dpll(limit, crtc,
dev_priv-lvds_downclock,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fd09058..76b4372 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -59,6 +59,14 @@ static const struct dp_link_dpll pch_dpll[] =
{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 }}
};
+static const struct dp_link_dpll vlv_dpll[] =
+{
+ { DP_LINK_BW_1_62,
+ { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 }},
+ { DP_LINK_BW_2_7,
+ { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 }}
+};
+
/**
* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
* @intel_dp: DP struct
@@ -682,7 +690,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
divisor = pch_dpll;
count = ARRAY_SIZE(pch_dpll);
} else if (IS_VALLEYVIEW(dev)) {
- /* FIXME: Need to figure out optimized DP clocks for vlv. */
+ divisor = vlv_dpll;
+ count = ARRAY_SIZE(vlv_dpll);
}
if (divisor count) {
--
1.7.7.6
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Modify DP set clock to accomodate more eDP timings.
eDP 1.4 supports 4-5 extra link rates in additional to current 2 link
rate. Create a structure to store the DPLL divisor data to improve
readability.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 48 +++---
1 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2151d13..ab8a5ff 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -38,6 +38,19 @@
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
+struct dp_link_dpll{
+ int link_bw;
+ struct dpll dpll;
+};
+
+static const struct dp_link_dpll gen4_dpll[] =
+ {{ DP_LINK_BW_1_62, {2,23,8,2,10,0,0,0,0}},
+ { DP_LINK_BW_2_7, {1,14,2,1,10,0,0,0,0}}};
+
+static const struct dp_link_dpll pch_dpll[] =
+ {{ DP_LINK_BW_1_62, {1,12,9,2,10,0,0,0,0}},
+ { DP_LINK_BW_2_7, {2,14,8,1,10,0,0,0,0}}};
+
/**
* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
* @intel_dp: DP struct
@@ -649,37 +662,24 @@ intel_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config, int link_bw)
{
struct drm_device *dev = encoder-base.dev;
+ int i;
if (IS_G4X(dev)) {
- if (link_bw == DP_LINK_BW_1_62) {
- pipe_config-dpll.p1 = 2;
- pipe_config-dpll.p2 = 10;
- pipe_config-dpll.n = 2;
- pipe_config-dpll.m1 = 23;
- pipe_config-dpll.m2 = 8;
- } else {
- pipe_config-dpll.p1 = 1;
- pipe_config-dpll.p2 = 10;
- pipe_config-dpll.n = 1;
- pipe_config-dpll.m1 = 14;
- pipe_config-dpll.m2 = 2;
+ for(i = 0; i sizeof(gen4_dpll) / sizeof(struct dp_link_dpll);
i++) {
+ if (link_bw == gen4_dpll[i].link_bw){
+ pipe_config-dpll = gen4_dpll[i].dpll;
+ break;
+ }
}
pipe_config-clock_set = true;
} else if (IS_HASWELL(dev)) {
/* Haswell has special-purpose DP DDI clocks. */
} else if (HAS_PCH_SPLIT(dev)) {
- if (link_bw == DP_LINK_BW_1_62) {
- pipe_config-dpll.n = 1;
- pipe_config-dpll.p1 = 2;
- pipe_config-dpll.p2 = 10;
- pipe_config-dpll.m1 = 12;
- pipe_config-dpll.m2 = 9;
- } else {
- pipe_config-dpll.n = 2;
- pipe_config-dpll.p1 = 1;
- pipe_config-dpll.p2 = 10;
- pipe_config-dpll.m1 = 14;
- pipe_config-dpll.m2 = 8;
+ for(i = 0; i sizeof(pch_dpll) / sizeof(struct dp_link_dpll);
i++) {
+ if (link_bw == pch_dpll[i].link_bw){
+ pipe_config-dpll = pch_dpll[i].dpll;
+ break;
+ }
}
pipe_config-clock_set = true;
} else if (IS_VALLEYVIEW(dev)) {
--
1.7.7.6
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[Intel-gfx] [PATCH 2/2] drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock
For DP pll settings, there is only two golden configs. Instead of running
through the algorithm to determine it, hardcode the value and get it
determine in intel_dp_set_clock.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 22 --
drivers/gpu/drm/i915/intel_dp.c | 12 +++-
2 files changed, 15 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f526ea9..453fa16 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -339,19 +339,6 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
.p2_slow = 2, .p2_fast = 20 },
};
-static const intel_limit_t intel_limits_vlv_dp = {
- .dot = { .min = 25000, .max = 27 },
- .vco = { .min = 400, .max = 600 },
- .n = { .min = 1, .max = 7 },
- .m = { .min = 22, .max = 450 },
- .m1 = { .min = 2, .max = 3 },
- .m2 = { .min = 11, .max = 156 },
- .p = { .min = 10, .max = 30 },
- .p1 = { .min = 1, .max = 3 },
- .p2 = { .dot_limit = 27,
- .p2_slow = 2, .p2_fast = 20 },
-};
-
static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
int refclk)
{
@@ -414,10 +401,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc
*crtc, int refclk)
} else if (IS_VALLEYVIEW(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
limit = intel_limits_vlv_dac;
- else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+ else
limit = intel_limits_vlv_hdmi;
- else
- limit = intel_limits_vlv_dp;
} else if (!IS_GEN2(dev)) {
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
limit = intel_limits_i9xx_lvds;
@@ -4889,15 +4874,16 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
}
refclk = i9xx_get_refclk(crtc, num_connectors);
+
+ limit = intel_limit(crtc, refclk);
- if (!is_dsi) {
+ if (!is_dsi !intel_crtc-config.clock_set) {
/*
* Returns a set of divisors for the desired target clock with
* the given refclk, or FALSE. The returned values represent
* the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
* 2) / p1 / p2.
*/
- limit = intel_limit(crtc, refclk);
ok = dev_priv-display.find_dpll(limit, crtc,
intel_crtc-config.port_clock,
refclk, NULL, clock);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ab8a5ff..89a2606 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -51,6 +51,10 @@ static const struct dp_link_dpll pch_dpll[] =
{{ DP_LINK_BW_1_62, {1,12,9,2,10,0,0,0,0}},
{ DP_LINK_BW_2_7, {2,14,8,1,10,0,0,0,0}}};
+static const struct dp_link_dpll vlv_dpll[] =
+ {{ DP_LINK_BW_1_62, {5,3,81,3,2,0,0,0,0}},
+ { DP_LINK_BW_2_7, {1,2,27,2,2,0,0,0,0}}};
+
/**
* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
* @intel_dp: DP struct
@@ -683,7 +687,13 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
pipe_config-clock_set = true;
} else if (IS_VALLEYVIEW(dev)) {
- /* FIXME: Need to figure out optimized DP clocks for vlv. */
+ for(i = 0; i sizeof(vlv_dpll) / sizeof(struct dp_link_dpll);
i++) {
+ if (link_bw == vlv_dpll[i].link_bw){
+ pipe_config-dpll = vlv_dpll[i].dpll;
+ break;
+ }
+ }
+ pipe_config-clock_set = true;
}
}
--
1.7.7.6
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