from:"Deepak M"

[Intel-gfx] [PATCH] drm/i915: Set the Z inversion overlap field

2016-11-01 Thread Deepak M

Dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the older platforms,
hence setting the same in this patch.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c | 17 +
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bdc7b35..7a79dd1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8350,6 +8350,8 @@ enum {
 #define _MIPIA_CTRL(dev_priv->mipi_mmio_base + 0xb104)
 #define _MIPIC_CTRL(dev_priv->mipi_mmio_base + 0xb904)
 #define MIPI_CTRL(port)_MMIO_MIPI(port, _MIPIA_CTRL, 
_MIPIC_CTRL)
+#define  BXT_PIXEL_OVERLAP_CNT_MASK(0xf << 10)
+#define  BXT_PIXEL_OVERLAP_CNT_SHIFT   10
 #define  ESCAPE_CLOCK_DIVIDER_SHIFT5 /* A only */
 #define  ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
 #define  ESCAPE_CLOCK_DIVIDER_1(0 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4e0d025..b1a4675 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -455,12 +455,21 @@ static void intel_dsi_port_enable(struct intel_encoder 
*encoder)
 
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
u32 temp;
-
-   temp = I915_READ(VLV_CHICKEN_3);
-   temp &= ~PIXEL_OVERLAP_CNT_MASK |
+   if (IS_BROXTON(dev_priv)) {
+   for_each_dsi_port(port, intel_dsi->ports) {
+   temp = I915_READ(MIPI_CTRL(port));
+   temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
+   intel_dsi->pixel_overlap <<
+   BXT_PIXEL_OVERLAP_CNT_SHIFT;
+   I915_WRITE(MIPI_CTRL(port), temp);
+   }
+   } else {
+   temp = I915_READ(VLV_CHICKEN_3);
+   temp &= ~PIXEL_OVERLAP_CNT_MASK |
intel_dsi->pixel_overlap <<
PIXEL_OVERLAP_CNT_SHIFT;
-   I915_WRITE(VLV_CHICKEN_3, temp);
+   I915_WRITE(VLV_CHICKEN_3, temp);
+   }
}
 
for_each_dsi_port(port, intel_dsi->ports) {
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915: Add ddb size field to device info structure

2016-09-15 Thread Deepak M

Adding the ddb size into the devide info will avoid
platform checks while computing wm.

v2: Added comment and WARN_ON if ddb size is zero.(Jani)
v3: Added WARN_ON at the right place.(Jani)

Suggested-by: Ander Conselvan de Oliveira 
<ander.conselvan.de.olive...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +
 drivers/gpu/drm/i915/intel_pm.c | 13 ++---
 3 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e2dda8..6014c3a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -710,6 +710,7 @@ struct intel_device_info {
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+   u16 ddb_size; /* in blocks */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
int trans_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d771870d..687c768 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
@@ -336,6 +337,7 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
.has_guc = 1,
+   .ddb_size = 512,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = 
{
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -377,6 +381,7 @@ static const struct intel_device_info 
intel_kabylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6af438f..2df06b7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE   896 /* in blocks */
-#define BXT_DDB_SIZE   512
 #define SKL_SAGV_BLOCK_TIME30 /* µs */
 
 /*
@@ -3057,10 +3050,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device 
*dev,
else
*num_active = hweight32(dev_priv->active_crtcs);
 
-   if (IS_BROXTON(dev))
-   ddb_size = BXT_DDB_SIZE;
-   else
-   ddb_size = SKL_DDB_SIZE;
+   ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+   WARN_ON(ddb_size == 0);
 
ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915: Add ddb size field to device info structure

2016-09-14 Thread Deepak M

Adding the ddb size into the devide info will avoid
platform checks while computing wm.

v2: Added comment and WARN_ON if ddb size is zero.(Jani)

Suggested-by: Ander Conselvan de Oliveira 
<ander.conselvan.de.olive...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +
 drivers/gpu/drm/i915/intel_pm.c | 15 +++
 3 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e2dda8..6014c3a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -710,6 +710,7 @@ struct intel_device_info {
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+   u16 ddb_size; /* in blocks */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
int trans_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d771870d..687c768 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
@@ -336,6 +337,7 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
.has_guc = 1,
+   .ddb_size = 512,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = 
{
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -377,6 +381,7 @@ static const struct intel_device_info 
intel_kabylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6af438f..9c5861e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE   896 /* in blocks */
-#define BXT_DDB_SIZE   512
 #define SKL_SAGV_BLOCK_TIME30 /* µs */
 
 /*
@@ -3057,13 +3050,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device 
*dev,
else
*num_active = hweight32(dev_priv->active_crtcs);
 
-   if (IS_BROXTON(dev))
-   ddb_size = BXT_DDB_SIZE;
-   else
-   ddb_size = SKL_DDB_SIZE;
-
+   ddb_size = INTEL_INFO(dev_priv)->ddb_size;
ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
+   WARN_ON(ddb_size == 0);
+
/*
 * If the state doesn't change the active CRTC's, then there's
 * no need to recalculate; the existing pipe allocation limits
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915: Add ddb size field to device info structure

2016-09-13 Thread Deepak M

Adding the ddb size into the devide info will avoid
platform checks while computing wm.

Suggested-by: Ander Conselvan de Oliveira 
<ander.conselvan.de.olive...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +
 drivers/gpu/drm/i915/intel_pm.c | 13 +
 3 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e2dda8..4518ef3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -710,6 +710,7 @@ struct intel_device_info {
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+   u16 ddb_size;
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
int trans_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d771870d..687c768 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
@@ -336,6 +337,7 @@ static const struct intel_device_info 
intel_skylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
.has_guc = 1,
+   .ddb_size = 512,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = 
{
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -377,6 +381,7 @@ static const struct intel_device_info 
intel_kabylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+   .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6af438f..7eeb73b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE   896 /* in blocks */
-#define BXT_DDB_SIZE   512
 #define SKL_SAGV_BLOCK_TIME30 /* µs */
 
 /*
@@ -3057,11 +3050,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device 
*dev,
else
*num_active = hweight32(dev_priv->active_crtcs);
 
-   if (IS_BROXTON(dev))
-   ddb_size = BXT_DDB_SIZE;
-   else
-   ddb_size = SKL_DDB_SIZE;
-
+   ddb_size = INTEL_INFO(dev_priv)->ddb_size;
ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
/*
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Get the i2c bus number from the ACPI

2016-04-19 Thread Deepak, M

Waiting for review comments.

> -Original Message-
> From: Deepak, M
> Sent: Friday, March 11, 2016 3:55 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Deepak, M <m.dee...@intel.com>; Nikula, Jani <jani.nik...@intel.com>;
> Ville Syrjälä <ville.syrj...@linux.intel.com>
> Subject: [PATCH 1/2] drm/i915: Get the i2c bus number from the ACPI
> 
> Currently for executing the i2c MIPI sequence, we are relaying on the i2c bus
> number which is specified in the VBT. But there are cases where different
> Fab versions of the board will drive the same chip with different i2c port, in
> which case the i2c bus number from the VBT cant be relied on. To overcome
> this the i2c bus number is read from the BIOS acpi table; BIOS can detect the
> Fab version in runtime and will store the correct i2c bus number in the ACPI
> table.
> 
> v2 by Deepak:
>  - Reading the i2c from the ACPI and storing them in list
> 
> Cc: Jani Nikula <jani.nik...@intel.com>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Deepak M <m.dee...@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c   |  2 ++
>  drivers/gpu/drm/i915/i915_drv.h   | 11 
>  drivers/gpu/drm/i915/intel_acpi.c | 59
> +++
>  3 files changed, 72 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c
> b/drivers/gpu/drm/i915/i915_dma.c index 4aa3db6..57be99b 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -387,6 +387,8 @@ static int i915_load_modeset_init(struct drm_device
> *dev)
> 
>   intel_register_dsm_handler();
> 
> + intel_acpi_find_i2c(dev_priv);
> +
>   ret = vga_switcheroo_register_client(dev->pdev,
> _switcheroo_ops, false);
>   if (ret)
>   goto cleanup_vga_client;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index f37ac12..5c6279d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -41,6 +41,7 @@
>  #include "intel_lrc.h"
>  #include "i915_gem_gtt.h"
>  #include "i915_gem_render_state.h"
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -1739,6 +1740,12 @@ struct intel_wm_config {
>   bool sprites_scaled;
>  };
> 
> +struct acpi_i2c_data_node {
> + struct list_head head;
> + int i2c_bus_number;
> + int i2c_slave_address;
> +};
> +
>  struct drm_i915_private {
>   struct drm_device *dev;
>   struct kmem_cache *objects;
> @@ -1823,6 +1830,8 @@ struct drm_i915_private {
>   /* backlight registers and fields in struct intel_panel */
>   struct mutex backlight_lock;
> 
> + struct list_head acpi_i2c_list;
> +
>   /* LVDS info */
>   bool no_aux_handshake;
> 
> @@ -1892,6 +1901,7 @@ struct drm_i915_private {
> 
>   struct i915_workarounds workarounds;
> 
> +
>   /* Reclocking support */
>   bool render_reclock_avail;
> 
> @@ -3439,6 +3449,7 @@ intel_opregion_notify_adapter(struct drm_device
> *dev, pci_power_t state)  #ifdef CONFIG_ACPI  extern void
> intel_register_dsm_handler(void);  extern void
> intel_unregister_dsm_handler(void);
> +extern acpi_status intel_acpi_find_i2c(struct drm_i915_private
> +*dev_priv);
>  #else
>  static inline void intel_register_dsm_handler(void) { return; }  static 
> inline
> void intel_unregister_dsm_handler(void) { return; } diff --git
> a/drivers/gpu/drm/i915/intel_acpi.c b/drivers/gpu/drm/i915/intel_acpi.c
> index eb638a1..afe42ab 100644
> --- a/drivers/gpu/drm/i915/intel_acpi.c
> +++ b/drivers/gpu/drm/i915/intel_acpi.c
> @@ -110,6 +110,65 @@ static void intel_dsm_platform_mux_info(void)
>   ACPI_FREE(pkg);
>  }
> 
> +static int i2c_acpi_get_name(struct acpi_resource *ares, void *data) {
> + struct drm_i915_private *dev_priv = data;
> + struct acpi_resource_i2c_serialbus *sb;
> + unsigned int val;
> + char *resource;
> + int error;
> +
> +
> + if (ares->type == ACPI_RESOURCE_TYPE_SERIAL_BUS) {
> + sb = >data.i2c_serial_bus;
> +
> + if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) {
> + struct acpi_i2c_data_node *i2c_entry = NULL;
> +
> + resource = sb->resource_source.string_ptr;
> + resource = strstr(resource, "I2C");
> + error = kstrtouint(resource+3, 0, );
> + if (error)
> + return error;
> +
> + i2c_entry = kzalloc(sizeof(struct
> acpi_i2c_data_node),
> +

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Parse LFP brightness control field in VBT

2016-03-29 Thread Deepak, M



> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, March 29, 2016 8:31 PM
> To: intel-gfx@lists.freedesktop.org; Deepak, M <m.dee...@intel.com>
> Cc: Nikula, Jani <jani.nik...@intel.com>
> Subject: [PATCH 3/5] drm/i915: Parse LFP brightness control field in VBT
> 
> From: Deepak M <m.dee...@intel.com>
> 
> These fields in VBT indicates the PWM source which is used and also the
> controller number.
> 
> v2 by Jani: check for out of bounds access, some renames, change default
> type, etc.
> 
> Signed-off-by: Deepak M <m.dee...@intel.com>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   | 1 +
>  drivers/gpu/drm/i915/intel_bios.c | 9 +
>  drivers/gpu/drm/i915/intel_bios.h | 8 
>  drivers/gpu/drm/i915/intel_vbt_defs.h | 6 ++
>  4 files changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 0906dfd7b1a9..4a76b7b2dbd9
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1472,6 +1472,7 @@ struct intel_vbt_data {
>   bool present;
>   bool active_low_pwm;
>   u8 min_brightness;  /* min_brightness/255 of max */
> + enum intel_backlight_type type;
>   } backlight;
> 
>   /* MIPI DSI */
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
> index 6985519921b4..2f639820aded 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -304,6 +304,15 @@ parse_lfp_backlight(struct drm_i915_private
> *dev_priv,
>   return;
>   }
> 
> + dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
> + if (bdb->version >= 191 &&
> + get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
> + const struct bdb_lfp_backlight_control_method *method;
> +
> + method = _data->backlight_control[panel_type];
> + dev_priv->vbt.backlight.type = method->type;
> + }
> +
>   dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
>   dev_priv->vbt.backlight.active_low_pwm = entry-
> >active_low_pwm;
>   dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
> diff --git a/drivers/gpu/drm/i915/intel_bios.h
> b/drivers/gpu/drm/i915/intel_bios.h
> index 149c3226e895..df6ce3e3d26f 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -30,6 +30,14 @@
>  #ifndef _INTEL_BIOS_H_
>  #define _INTEL_BIOS_H_
> 
> +enum intel_backlight_type {
> + INTEL_BACKLIGHT_PMIC,
> + INTEL_BACKLIGHT_LPSS,
> + INTEL_BACKLIGHT_DISPLAY_DDI,
> + INTEL_BACKLIGHT_CABC,
[Deepak, M] Better to rename CABC to PANEL_PWM, because CABC is not the source 
of the PWM. There may be some panel which have the panel PWM but may not 
support CABC.
> + INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
> +};
> +
>  struct edp_power_seq {
>   u16 t1_t3;
>   u16 t8;
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index 749dceab7c02..2191076c3ff6 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -440,10 +440,16 @@ struct bdb_lfp_backlight_data_entry {
>   u8 obsolete3;
>  } __packed;
> 
> +struct bdb_lfp_backlight_control_method {
> + u8 type:4;
> + u8 controller:4;
> +} __packed;
> +
>  struct bdb_lfp_backlight_data {
>   u8 entry_size;
>   struct bdb_lfp_backlight_data_entry data[16];
>   u8 level[16];
> + struct bdb_lfp_backlight_control_method backlight_control[16];
>  } __packed;
> 
>  struct aimdb_header {
> --
> 2.1.4

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[Intel-gfx] [PATCH 5/5] drm/i915: CABC support for Panel PWM backlight control

2016-03-29 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

CABC is supported only when the PWM source for backlight is
from the panel.

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c   | 19 
 drivers/gpu/drm/i915/intel_dsi.h   |  3 +++
 drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c | 30 ++
 3 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 1ba757a..a7b2949 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1229,9 +1229,28 @@ void intel_dsi_init(struct drm_device *dev)
default:
intel_dsi->panel_pwm_dcs_ports = BIT(PORT_A) | 
BIT(PORT_C);
}
+
+   /*
+* Based on the VBT value assign the ports on
+* which CABC ON/OFF comands needs to be sent
+*/
+   switch (dev_priv->vbt.dsi.config->dl_cabc_ports) {
+   case CABC_PORT_A:
+   intel_dsi->cabc_dcs_ports = BIT(PORT_A);
+   break;
+   case CABC_PORT_C:
+   intel_dsi->cabc_dcs_ports = BIT(PORT_C);
+   break;
+   case CABC_PORT_A_AND_C:
+   intel_dsi->cabc_dcs_ports = BIT(PORT_A) | BIT(PORT_C);
+   break;
+   default:
+   intel_dsi->cabc_dcs_ports = BIT(PORT_A) | BIT(PORT_C);
+   }
} else {
intel_dsi->ports = BIT(port);
intel_dsi->panel_pwm_dcs_ports = BIT(port);
+intel_dsi->cabc_dcs_ports = BIT(port);
}
 
/* Create a DSI host (and a device) for each port. */
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index dcd2265..322eebd 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -37,6 +37,9 @@
 #define PANEL_PWM_PORT_A   0x00
 #define PANEL_PWM_PORT_C   0x01
 #define PANEL_PWM_PORT_A_AND_C 0x02
+#define CABC_PORT_A0x00
+#define CABC_PORT_C0x01
+#define CABC_PORT_A_AND_C  0x02
 
 struct intel_dsi_host;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c 
b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
index 4d7f0eb..5417f80 100644
--- a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
@@ -33,6 +33,11 @@
 #define PANEL_PWM_DISP_DIMMING (1 << 3)
 #define PANEL_PWM_BCTRL(1 << 5)
 
+#define CABC_OFF   (0 << 0)
+#define CABC_USER_INTERFACE_IMAGE  (1 << 0)
+#define CABC_STILL_PICTURE (2 << 0)
+#define CABC_VIDEO_MODE(3 << 0)
+
 #define PANEL_PWM_MAX_VALUE0xFF
 
 static u32 panel_pwm_get_backlight(struct intel_connector *connector)
@@ -81,6 +86,8 @@ static void panel_pwm_set_backlight(struct intel_connector 
*connector, u32 level
 
 static void panel_pwm_disable_backlight(struct intel_connector *connector)
 {
+   struct drm_device *dev = connector->base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *encoder = connector->encoder;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
struct mipi_dsi_device *dsi_device;
@@ -89,6 +96,16 @@ static void panel_pwm_disable_backlight(struct 
intel_connector *connector)
 
panel_pwm_set_backlight(connector, 0);
 
+   if (dev_priv->vbt.dsi.config->cabc_supported) {
+   data = 0;
+   for_each_dsi_port(port, intel_dsi->cabc_dcs_ports) {
+   dsi_device = intel_dsi->dsi_hosts[port]->device;
+   data = CABC_OFF;
+   mipi_dsi_dcs_write(dsi_device, 
MIPI_DCS_WRITE_POWER_SAVE,
+   , sizeof(data));
+   }
+   }
+
for_each_dsi_port(port, intel_dsi->panel_pwm_dcs_ports) {
dsi_device = intel_dsi->dsi_hosts[port]->device;
data &= ~PANEL_PWM_BKL_EN; /* Turn Off Backlight */
@@ -101,6 +118,8 @@ static void panel_pwm_disable_backlight(struct 
intel_connector *connector)
 
 static void panel_pwm_enable_backlight(struct in

[Intel-gfx] [PATCH 1/5] drm: Add new DCS commands in the enum list

2016-03-29 Thread Deepak M

Adding new DCS commands which are specified in the
DCS 1.3 spec related to CABC.

v2: Sorted the Macro`s by value (Andrzej)

Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Suggested-by: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 include/video/mipi_display.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index ddcc8ca..6831c84 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -117,6 +117,14 @@ enum {
MIPI_DCS_GET_SCANLINE   = 0x45,
MIPI_DCS_READ_DDB_START = 0xA1,
MIPI_DCS_READ_DDB_CONTINUE  = 0xA8,
+   MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /*Spec 1.3*/
+   MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /*Spec 1.3*/
+   MIPI_DCS_WRITE_CONTROL_DISPLAY  = 0x53, /*Spec 1.3*/
+   MIPI_DCS_GET_CONTROL_DISPLAY= 0x54, /*Spec 1.3*/
+   MIPI_DCS_WRITE_POWER_SAVE   = 0x55, /*Spec 1.3*/
+   MIPI_DCS_GET_POWER_SAVE = 0x56, /*Spec 1.3*/
+   MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /*Spec 1.3*/
+   MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /*Spec 1.3*/
 };
 
 /* MIPI DCS pixel formats */
-- 
1.9.1

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[Intel-gfx] [PATCH 4/5] drm/i915: Add DCS control for Panel PWM

2016-03-29 Thread Deepak M

If the source of the backlight PWM is from the
panel then the PWM can be controlled by DCS
command, this patch adds the support to
enable/disbale panel PWM, control backlight level
etc...

v2: Moving the CABC bkl functions to new file.(Jani)

v3: Rebase

v4: Rebase

v5: Use mipi_dsi_dcs_write() instead of mipi_dsi_dcs_write_buffer() (Jani)
Move DCS macro`s to include/video/mipi_display.h (Jani)

v6: Rename the file to intel_dsi_dcs_backlight.c
Removing the CABC operations

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_drv.h|   1 -
 drivers/gpu/drm/i915/intel_drv.h   |   2 +
 drivers/gpu/drm/i915/intel_dsi.c   |  24 +++-
 drivers/gpu/drm/i915/intel_dsi.h   |   4 +
 drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c | 160 +
 drivers/gpu/drm/i915/intel_panel.c |   4 +
 7 files changed, 193 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..3f6a3cf 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += dvo_ch7017.o \
  intel_dp_mst.o \
  intel_dp.o \
  intel_dsi.o \
+ intel_dsi_dcs_backlight.o \
  intel_dsi_panel_vbt.o \
  intel_dsi_pll.o \
  intel_dvo.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 30321e6..7d6118d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3491,7 +3491,6 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
 enum intel_sbi_destination destination);
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 02a74b0..0603c9f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1330,6 +1330,8 @@ void intel_dp_mst_encoder_cleanup(struct 
intel_digital_port *intel_dig_port);
 /* intel_dsi.c */
 void intel_dsi_init(struct drm_device *dev);
 
+/* intel_dsi_panel_pwm.c */
+int intel_dsi_panel_pwm_init_backlight_funcs(struct intel_connector 
*intel_connector);
 
 /* intel_dvo.c */
 void intel_dvo_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 456676c..1ba757a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1209,10 +1209,30 @@ void intel_dsi_init(struct drm_device *dev)
else
intel_encoder->crtc_mask = BIT(PIPE_B);
 
-   if (dev_priv->vbt.dsi.config->dual_link)
+   if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
-   else
+
+   /*
+* Based on the VBT value assign the ports on
+* which Panel PWM On/OFF DCS coomands needs to be sent
+*/
+   switch (dev_priv->vbt.dsi.config->dl_panel_pwm_ports) {
+   case PANEL_PWM_PORT_A:
+   intel_dsi->panel_pwm_dcs_ports = BIT(PORT_A);
+   break;
+   case PANEL_PWM_PORT_C:
+   intel_dsi->panel_pwm_dcs_ports = BIT(PORT_C);
+   break;
+   case PANEL_PWM_PORT_A_AND_C:
+   intel_dsi->panel_pwm_dcs_ports = BIT(PORT_A) | 
BIT(PORT_C);
+   break;
+   default:
+   intel_dsi->panel_pwm_dcs_ports = BIT(PORT_A) | 
BIT(PORT_C);
+   }
+   } else {
intel_dsi->ports = BIT(port);
+   intel_dsi->panel_pwm_dcs_ports = BIT(port);
+   }
 
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index f54748d..dcd2265 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,10 @@
 #define DSI_DUAL_LINK_FRONT_BACK   1
 #define DSI_DUAL_LINK_PIXEL_ALT2
 
+#define PANEL_PWM_PORT_A   0x00
+#define PANEL_PWM_PORT_C   0x01
+#define PANEL_PWM_PORT_A_AND_C 0x02
+
 struct intel_dsi_host;
 
 struct intel_dsi {
diff --git a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c 
b/drivers/gpu/

[Intel-gfx] [PATCH 3/5] drm/i915: Parse LFP brightness control field in VBT

2016-03-29 Thread Deepak M

These fields in VBT indicates the PWM source which
is used and also the controller number.

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_bios.c | 12 
 drivers/gpu/drm/i915/intel_drv.h  |  5 +
 drivers/gpu/drm/i915/intel_vbt_defs.h |  6 ++
 4 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 050d860..30321e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1488,6 +1488,8 @@ struct intel_vbt_data {
bool present;
bool active_low_pwm;
u8 min_brightness;  /* min_brightness/255 of max */
+   u8 pwm_pin; /* Source of PWM */
+   u8 pwm_controller;  /* Controller used in particular PWM */
} backlight;
 
/* MIPI DSI */
diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 1af7074..1a5b124 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -284,6 +284,7 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
 {
const struct bdb_lfp_backlight_data *backlight_data;
const struct bdb_lfp_backlight_data_entry *entry;
+   const struct bdb_lfp_backlight_control_data *bl_ctrl_data;
 
backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
if (!backlight_data)
@@ -296,6 +297,7 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
}
 
entry = _data->data[panel_type];
+   bl_ctrl_data = _data->blc_ctl[panel_type];
 
dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
if (!dev_priv->vbt.backlight.present) {
@@ -304,6 +306,16 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
return;
}
 
+   /*
+* IF the VBT version is less than 191, set the
+* pwm controller as PMIC by default.
+*/
+   dev_priv->vbt.backlight.pwm_pin = BLC_CONTROL_PIN_PMIC;
+   if (bdb->version >= 191) {
+   dev_priv->vbt.backlight.pwm_pin = bl_ctrl_data->pin;
+   dev_priv->vbt.backlight.pwm_controller = 
bl_ctrl_data->controller;
+   }
+
dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c87b450..02a74b0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -124,6 +124,11 @@
 #define INTEL_I2C_BUS_DVO 1
 #define INTEL_I2C_BUS_SDVO 2
 
+#define BLC_CONTROL_PIN_PMIC   0
+#define BLC_CONTROL_PIN_LPSS_PWM   1
+#define BLC_CONTROL_PIN_DDI2
+#define BLC_CONTROL_PIN_PANEL_PWM  3
+
 /* these are outputs from the chip - integrated only
external chips are via DVO or SDVO output */
 enum intel_output_type {
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 749dcea..f6744dc 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -440,10 +440,16 @@ struct bdb_lfp_backlight_data_entry {
u8 obsolete3;
 } __packed;
 
+struct bdb_lfp_backlight_control_data {
+   u8 pin:4;
+   u8 controller:4;
+} __packed;
+
 struct bdb_lfp_backlight_data {
u8 entry_size;
struct bdb_lfp_backlight_data_entry data[16];
u8 level[16];
+   struct bdb_lfp_backlight_control_data blc_ctl[16];
 } __packed;
 
 struct aimdb_header {
-- 
1.9.1

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[Intel-gfx] [PATCH 2/5] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fields in VBT

2016-03-29 Thread Deepak M

For dual link panel scenarios there are new fields added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

v2: Moving the comment to intel_dsi.h(Jani)

v3: Renaming the field names (Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 10 ++
 drivers/gpu/drm/i915/intel_bios.h |  5 -
 drivers/gpu/drm/i915/intel_dsi.h  |  9 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 083003b..1af7074 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -749,6 +749,16 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
return;
}
 
+   /*
+* These fileds are introduced from the VBT version 197 onwards,
+* so making sure that these bits are set zero in the pervious
+* versions.
+*/
+   if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+   dev_priv->vbt.dsi.config->dl_cabc_ports = 0;
+   dev_priv->vbt.dsi.config->dl_panel_pwm_ports = 0;
+   }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 }
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index ab0ea31..fdfb634 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -113,7 +113,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
-   u16 rsvd3:9;
+   u16 rgb_flip:1;
+   u16 dl_cabc_ports:2;
+   u16 dl_panel_pwm_ports:2;
+   u16 rsvd3:4;
 
u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e582ef8..f54748d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -78,6 +78,15 @@ struct intel_dsi {
 
u8 escape_clk_div;
u8 dual_link;
+
+   /*
+* Below field will inform us on which port the panel blk_cntrl
+* and CABC ON/OFF commands needs to be sent in case of dual link
+* panels
+*/
+   u8 cabc_dcs_ports;
+   u8 panel_pwm_dcs_ports;
+
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
-- 
1.9.1

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[Intel-gfx] [PATCH 5/5] CABC support for Panel PWM backlight control

2016-03-28 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

CABC is supported only when the PWM source for backlight is
from the panel.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c   | 19 +++
 drivers/gpu/drm/i915/intel_dsi.h   |  3 +++
 drivers/gpu/drm/i915/intel_dsi_panel_pwm.c | 30 ++
 3 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 1ba757a..a7b2949 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1229,9 +1229,28 @@ void intel_dsi_init(struct drm_device *dev)
default:
intel_dsi->panel_pwm_dcs_ports = BIT(PORT_A) | 
BIT(PORT_C);
}
+
+   /*
+* Based on the VBT value assign the ports on
+* which CABC ON/OFF comands needs to be sent
+*/
+   switch (dev_priv->vbt.dsi.config->dl_cabc_ports) {
+   case CABC_PORT_A:
+   intel_dsi->cabc_dcs_ports = BIT(PORT_A);
+   break;
+   case CABC_PORT_C:
+   intel_dsi->cabc_dcs_ports = BIT(PORT_C);
+   break;
+   case CABC_PORT_A_AND_C:
+   intel_dsi->cabc_dcs_ports = BIT(PORT_A) | BIT(PORT_C);
+   break;
+   default:
+   intel_dsi->cabc_dcs_ports = BIT(PORT_A) | BIT(PORT_C);
+   }
} else {
intel_dsi->ports = BIT(port);
intel_dsi->panel_pwm_dcs_ports = BIT(port);
+intel_dsi->cabc_dcs_ports = BIT(port);
}
 
/* Create a DSI host (and a device) for each port. */
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index dcd2265..322eebd 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -37,6 +37,9 @@
 #define PANEL_PWM_PORT_A   0x00
 #define PANEL_PWM_PORT_C   0x01
 #define PANEL_PWM_PORT_A_AND_C 0x02
+#define CABC_PORT_A0x00
+#define CABC_PORT_C0x01
+#define CABC_PORT_A_AND_C  0x02
 
 struct intel_dsi_host;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_pwm.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_pwm.c
index 4d7f0eb..5417f80 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_pwm.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_pwm.c
@@ -33,6 +33,11 @@
 #define PANEL_PWM_DISP_DIMMING (1 << 3)
 #define PANEL_PWM_BCTRL(1 << 5)
 
+#define CABC_OFF   (0 << 0)
+#define CABC_USER_INTERFACE_IMAGE  (1 << 0)
+#define CABC_STILL_PICTURE (2 << 0)
+#define CABC_VIDEO_MODE(3 << 0)
+
 #define PANEL_PWM_MAX_VALUE0xFF
 
 static u32 panel_pwm_get_backlight(struct intel_connector *connector)
@@ -81,6 +86,8 @@ static void panel_pwm_set_backlight(struct intel_connector 
*connector, u32 level
 
 static void panel_pwm_disable_backlight(struct intel_connector *connector)
 {
+   struct drm_device *dev = connector->base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *encoder = connector->encoder;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
struct mipi_dsi_device *dsi_device;
@@ -89,6 +96,16 @@ static void panel_pwm_disable_backlight(struct 
intel_connector *connector)
 
panel_pwm_set_backlight(connector, 0);
 
+   if (dev_priv->vbt.dsi.config->cabc_supported) {
+   data = 0;
+   for_each_dsi_port(port, intel_dsi->cabc_dcs_ports) {
+   dsi_device = intel_dsi->dsi_hosts[port]->device;
+   data = CABC_OFF;
+   mipi_dsi_dcs_write(dsi_device, 
MIPI_DCS_WRITE_POWER_SAVE,
+   , sizeof(data));
+   }
+   }
+
for_each_dsi_port(port, intel_dsi->panel_pwm_dcs_ports) {
dsi_device = intel_dsi->dsi_hosts[port]->device;
data &= ~PANEL_PWM_BKL_EN; /* Turn Off Backlight */
@@ -101,6 +118,8 @@ static void panel_pwm_disable_backlight(struct 
intel_connector *connector)
 
 static void panel_pwm_enable_backlight(struct intel_connector *connector)
 {
+   struct drm_device *dev = connector->base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
struct inte

[Intel-gfx] [PATCH 4/5] drm/i915: Add DCS control for Panel PWM

2016-03-28 Thread Deepak M

If the source of the backlight PWM is from the
panel then the PWM can be controlled by DCS
command, this patch adds the support to
enable/disbale panel PWM, control backlight level
etc...

v2: Moving the CABC bkl functions to new file.(Jani)

v3: Rebase

v4: Rebase

v5: Use mipi_dsi_dcs_write() instead of mipi_dsi_dcs_write_buffer() (Jani)
Move DCS macro`s to include/video/mipi_display.h (Jani)

v6: Rename the file to intel_dsi_panel_pwm.c
Removing the CABC operations

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---

Should this below check be moved to intel_panel.c before calling the
intel_dsi_panel_pwm_init_backlight_funcs() ??
  
 if (dev_priv->vbt.backlight.pwm_pin ==
   BLC_CONTROL_PIN_PANEL_PWM)

 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_drv.h|   1 -
 drivers/gpu/drm/i915/intel_drv.h   |   2 +
 drivers/gpu/drm/i915/intel_dsi.c   |  24 -
 drivers/gpu/drm/i915/intel_dsi.h   |   4 +
 drivers/gpu/drm/i915/intel_dsi_panel_pwm.c | 160 +
 drivers/gpu/drm/i915/intel_panel.c |   4 +
 7 files changed, 193 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_panel_pwm.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..92abbee 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += dvo_ch7017.o \
  intel_dp_mst.o \
  intel_dp.o \
  intel_dsi.o \
+ intel_dsi_panel_pwm.o \
  intel_dsi_panel_vbt.o \
  intel_dsi_pll.o \
  intel_dvo.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 30321e6..7d6118d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3491,7 +3491,6 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
 enum intel_sbi_destination destination);
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 02a74b0..0603c9f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1330,6 +1330,8 @@ void intel_dp_mst_encoder_cleanup(struct 
intel_digital_port *intel_dig_port);
 /* intel_dsi.c */
 void intel_dsi_init(struct drm_device *dev);
 
+/* intel_dsi_panel_pwm.c */
+int intel_dsi_panel_pwm_init_backlight_funcs(struct intel_connector 
*intel_connector);
 
 /* intel_dvo.c */
 void intel_dvo_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 456676c..1ba757a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1209,10 +1209,30 @@ void intel_dsi_init(struct drm_device *dev)
else
intel_encoder->crtc_mask = BIT(PIPE_B);
 
-   if (dev_priv->vbt.dsi.config->dual_link)
+   if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
-   else
+
+   /*
+* Based on the VBT value assign the ports on
+* which Panel PWM On/OFF DCS coomands needs to be sent
+*/
+   switch (dev_priv->vbt.dsi.config->dl_panel_pwm_ports) {
+   case PANEL_PWM_PORT_A:
+   intel_dsi->panel_pwm_dcs_ports = BIT(PORT_A);
+   break;
+   case PANEL_PWM_PORT_C:
+   intel_dsi->panel_pwm_dcs_ports = BIT(PORT_C);
+   break;
+   case PANEL_PWM_PORT_A_AND_C:
+   intel_dsi->panel_pwm_dcs_ports = BIT(PORT_A) | 
BIT(PORT_C);
+   break;
+   default:
+   intel_dsi->panel_pwm_dcs_ports = BIT(PORT_A) | 
BIT(PORT_C);
+   }
+   } else {
intel_dsi->ports = BIT(port);
+   intel_dsi->panel_pwm_dcs_ports = BIT(port);
+   }
 
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index f54748d..dcd2265 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,10 @@
 #define DSI_DUAL_LINK_FRONT_BACK   1
 #define DSI_DUAL_LINK_PIXEL_ALT2
 
+#define PANEL_PWM_PORT_A   0x00
+#define PANEL_PWM_PORT_C

[Intel-gfx] [PATCH 2/5] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fields in VBT

2016-03-28 Thread Deepak M

For dual link panel scenarios there are new fields added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

v2: Moving the comment to intel_dsi.h(Jani)

v3: Renaming the field names (Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---

DCS commands 0x53h and 0x54h controls the panel
PWM operations and therfore we should send these
commands to the ports mentioned in the field
"dl_panel_pwm_ports" in the VBT

DCS commands 55h and 56h controls the CABC operation
and therfore we should be sending these commands to
the ports specified in the field "dl_cabc_ports"
in the VBT.

 drivers/gpu/drm/i915/intel_bios.c | 10 ++
 drivers/gpu/drm/i915/intel_bios.h |  5 -
 drivers/gpu/drm/i915/intel_dsi.h  |  9 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 083003b..1af7074 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -749,6 +749,16 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
return;
}
 
+   /*
+* These fields are introduced from the VBT version 197 onwards,
+* so making sure that these bits are set zero in the previous
+* versions.
+*/
+   if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+   dev_priv->vbt.dsi.config->dl_cabc_ports = 0;
+   dev_priv->vbt.dsi.config->dl_panel_pwm_ports = 0;
+   }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 }
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index ab0ea31..fdfb634 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -113,7 +113,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
-   u16 rsvd3:9;
+   u16 rgb_flip:1;
+   u16 dl_cabc_ports:2;
+   u16 dl_panel_pwm_ports:2;
+   u16 rsvd3:4;
 
u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e582ef8..f54748d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -78,6 +78,15 @@ struct intel_dsi {
 
u8 escape_clk_div;
u8 dual_link;
+
+   /*
+* Below field will inform us on which port the panel blk_cntrl
+* and CABC ON/OFF commands needs to be sent in case of dual link
+* panels
+*/
+   u8 cabc_dcs_ports;
+   u8 panel_pwm_dcs_ports;
+
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
-- 
1.9.1

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[Intel-gfx] [PATCH 3/5] drm/i915: Parse LFP brightness control field in VBT

2016-03-28 Thread Deepak M

These fields in VBT indicates the PWM source which
is used and also the controller number.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  2 ++
 drivers/gpu/drm/i915/intel_bios.c | 12 
 drivers/gpu/drm/i915/intel_drv.h  |  5 +
 drivers/gpu/drm/i915/intel_vbt_defs.h |  6 ++
 4 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 050d860..30321e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1488,6 +1488,8 @@ struct intel_vbt_data {
bool present;
bool active_low_pwm;
u8 min_brightness;  /* min_brightness/255 of max */
+   u8 pwm_pin; /* Source of PWM */
+   u8 pwm_controller;  /* Controller used in particular PWM */
} backlight;
 
/* MIPI DSI */
diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 1af7074..1a5b124 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -284,6 +284,7 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
 {
const struct bdb_lfp_backlight_data *backlight_data;
const struct bdb_lfp_backlight_data_entry *entry;
+   const struct bdb_lfp_backlight_control_data *bl_ctrl_data;
 
backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
if (!backlight_data)
@@ -296,6 +297,7 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
}
 
entry = _data->data[panel_type];
+   bl_ctrl_data = _data->blc_ctl[panel_type];
 
dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
if (!dev_priv->vbt.backlight.present) {
@@ -304,6 +306,16 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
return;
}
 
+   /*
+* IF the VBT version is less than 191, set the
+* pwm controller as PMIC by default.
+*/
+   dev_priv->vbt.backlight.pwm_pin = BLC_CONTROL_PIN_PMIC;
+   if (bdb->version >= 191) {
+   dev_priv->vbt.backlight.pwm_pin = bl_ctrl_data->pin;
+   dev_priv->vbt.backlight.pwm_controller = 
bl_ctrl_data->controller;
+   }
+
dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c87b450..02a74b0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -124,6 +124,11 @@
 #define INTEL_I2C_BUS_DVO 1
 #define INTEL_I2C_BUS_SDVO 2
 
+#define BLC_CONTROL_PIN_PMIC   0
+#define BLC_CONTROL_PIN_LPSS_PWM   1
+#define BLC_CONTROL_PIN_DDI2
+#define BLC_CONTROL_PIN_PANEL_PWM  3
+
 /* these are outputs from the chip - integrated only
external chips are via DVO or SDVO output */
 enum intel_output_type {
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 749dcea..f6744dc 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -440,10 +440,16 @@ struct bdb_lfp_backlight_data_entry {
u8 obsolete3;
 } __packed;
 
+struct bdb_lfp_backlight_control_data {
+   u8 pin:4;
+   u8 controller:4;
+} __packed;
+
 struct bdb_lfp_backlight_data {
u8 entry_size;
struct bdb_lfp_backlight_data_entry data[16];
u8 level[16];
+   struct bdb_lfp_backlight_control_data blc_ctl[16];
 } __packed;
 
 struct aimdb_header {
-- 
1.9.1

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[Intel-gfx] [PATCH 1/5] drm: Add new DCS commands in the enum list

2016-03-28 Thread Deepak M

Adding new DCS commands which are specified in the
DCS 1.3 spec related to CABC.

v2: Sorted the Macro`s by value (Andrzej)

Cc: Andrzej Hajda <a.ha...@samsung.com>
Cc: Thierry Reding <thierry.red...@gmail.com>
Cc: David Airlie <airl...@linux.ie>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Suggested-by: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 include/video/mipi_display.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index ddcc8ca..6831c84 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -117,6 +117,14 @@ enum {
MIPI_DCS_GET_SCANLINE   = 0x45,
MIPI_DCS_READ_DDB_START = 0xA1,
MIPI_DCS_READ_DDB_CONTINUE  = 0xA8,
+   MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /*Spec 1.3*/
+   MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /*Spec 1.3*/
+   MIPI_DCS_WRITE_CONTROL_DISPLAY  = 0x53, /*Spec 1.3*/
+   MIPI_DCS_GET_CONTROL_DISPLAY= 0x54, /*Spec 1.3*/
+   MIPI_DCS_WRITE_POWER_SAVE   = 0x55, /*Spec 1.3*/
+   MIPI_DCS_GET_POWER_SAVE = 0x56, /*Spec 1.3*/
+   MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /*Spec 1.3*/
+   MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /*Spec 1.3*/
 };
 
 /* MIPI DCS pixel formats */
-- 
1.9.1

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[Intel-gfx] [PATCH 3/3] drm/i915: CABC support for backlight control

2016-03-24 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

In this design there will be no PWM signal from the SoC and DCS
commands are sent to enable and control the backlight brightness.

v2: Moving the CABC bkl functions to new file.(Jani)

v3: Rebase

v4: Rebase

v5: Use mipi_dsi_dcs_write() instead of mipi_dsi_dcs_write_buffer() (Jani)
Move DCS macro`s to include/video/mipi_display.h (Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |   1 -
 drivers/gpu/drm/i915/intel_drv.h  |   2 +
 drivers/gpu/drm/i915/intel_dsi.c  |  19 -
 drivers/gpu/drm/i915/intel_dsi.h  |   4 +
 drivers/gpu/drm/i915/intel_dsi_cabc.c | 154 ++
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 7 files changed, 182 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..065c410 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += dvo_ch7017.o \
  intel_dp_mst.o \
  intel_dp.o \
  intel_dsi.o \
+ intel_dsi_cabc.o \
  intel_dsi_panel_vbt.o \
  intel_dsi_pll.o \
  intel_dvo.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 050d860..9ed60f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3489,7 +3489,6 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
 enum intel_sbi_destination destination);
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c87b450..9e49396 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1325,6 +1325,8 @@ void intel_dp_mst_encoder_cleanup(struct 
intel_digital_port *intel_dig_port);
 /* intel_dsi.c */
 void intel_dsi_init(struct drm_device *dev);
 
+/* intel_dsi_cabc.c */
+int intel_dsi_cabc_init_backlight_funcs(struct intel_connector 
*intel_connector);
 
 /* intel_dvo.c */
 void intel_dvo_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 456676c..7aa707f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1209,10 +1209,25 @@ void intel_dsi_init(struct drm_device *dev)
else
intel_encoder->crtc_mask = BIT(PIPE_B);
 
-   if (dev_priv->vbt.dsi.config->dual_link)
+   if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
-   else
+   switch (dev_priv->vbt.dsi.config->dl_cabc_port) {
+   case CABC_PORT_A:
+   intel_dsi->bkl_dcs_ports = BIT(PORT_A);
+   break;
+   case CABC_PORT_C:
+   intel_dsi->bkl_dcs_ports = BIT(PORT_C);
+   break;
+   case CABC_PORT_A_AND_C:
+   intel_dsi->bkl_dcs_ports = BIT(PORT_A) | BIT(PORT_C);
+   break;
+   default:
+   DRM_ERROR("Unknown MIPI ports for sending DCS\n");
+   }
+   } else {
intel_dsi->ports = BIT(port);
+   intel_dsi->bkl_dcs_ports = BIT(port);
+   }
 
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 0e758f1..5c07d59 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,10 @@
 #define DSI_DUAL_LINK_FRONT_BACK   1
 #define DSI_DUAL_LINK_PIXEL_ALT2
 
+#define CABC_PORT_A 0x00
+#define CABC_PORT_C 0x01
+#define CABC_PORT_A_AND_C   0x02
+
 struct intel_dsi_host;
 
 struct intel_dsi {
diff --git a/drivers/gpu/drm/i915/intel_dsi_cabc.c 
b/drivers/gpu/drm/i915/intel_dsi_cabc.c
new file mode 100644
index 000..230ee4f
--- /dev/null
+++

[Intel-gfx] [PATCH 1/3] drm: Add new DCS commands in the enum list

2016-03-24 Thread Deepak M

Adding new DCS commands which are specified in the
DCS 1.3 spec related to CABC.

Cc: Thierry Reding <thierry.red...@gmail.com>
Cc: David Airlie <airl...@linux.ie>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Suggested-by: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 include/video/mipi_display.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index ddcc8ca..bb8195b 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -117,6 +117,14 @@ enum {
MIPI_DCS_GET_SCANLINE   = 0x45,
MIPI_DCS_READ_DDB_START = 0xA1,
MIPI_DCS_READ_DDB_CONTINUE  = 0xA8,
+   MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52,
+   MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F,
+   MIPI_DCS_GET_POWER_SAVE = 0x56,
+   MIPI_DCS_GET_CONTROL_DISPLAY= 0x54,
+   MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51,
+   MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E,
+   MIPI_DCS_WRITE_POWER_SAVE   = 0x55,
+   MIPI_DCS_WRITE_CONTROL_DISPLAY  = 0x53,
 };
 
 /* MIPI DCS pixel formats */
-- 
1.9.1

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[Intel-gfx] [PATCH 2/3] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT

2016-03-24 Thread Deepak M

For dual link panel scenarios there are new fileds added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

v2: Moving the comment to intel_dsi.h(Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 10 ++
 drivers/gpu/drm/i915/intel_bios.h |  5 -
 drivers/gpu/drm/i915/intel_dsi.h  |  9 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 083003b..587c06f 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -749,6 +749,16 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
return;
}
 
+   /*
+* These fileds are introduced from the VBT version 197 onwards,
+* so making sure that these bits are set zero in the pervious
+* versions.
+*/
+   if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+   dev_priv->vbt.dsi.config->dl_cabc_port = 0;
+   dev_priv->vbt.dsi.config->pwm_bkl_ctrl = 0;
+   }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 }
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index ab0ea31..7a89f79 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -113,7 +113,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
-   u16 rsvd3:9;
+   u16 rgb_flip:1;
+   u16 dl_cabc_port:2;
+   u16 pwm_bkl_ctrl:2;
+   u16 rsvd3:4;
 
u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e582ef8..0e758f1 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -78,6 +78,15 @@ struct intel_dsi {
 
u8 escape_clk_div;
u8 dual_link;
+
+   /*
+* Below field will inform us on which port the panel blk_cntrl
+* and CABC ON/OFF commands needs to be sent in case of dual link
+* panels
+*/
+   u8 bkl_dcs_ports;
+   u8 pwm_blk_ctrl;
+
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: CABC support for backlight control

2016-03-24 Thread Deepak, M



> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, March 24, 2016 3:11 PM
> To: Deepak, M <m.dee...@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deepak, M <m.dee...@intel.com>; Vetter, Daniel
> <daniel.vet...@intel.com>; Adebisi, YetundeX
> <yetundex.adeb...@intel.com>
> Subject: Re: [PATCH 2/2] drm/i915: CABC support for backlight control
> 
> On Thu, 24 Mar 2016, Deepak M <m.dee...@intel.com> wrote:
> > [ text/plain ]
> > In CABC (Content Adaptive Brightness Control) content grey level scale
> > can be increased while simultaneously decreasing brightness of the
> > backlight to achieve same perceived brightness.
> >
> > The CABC is not standardized and panel vendors are free to follow
> > their implementation. The CABC implementaion here assumes that the
> > panels use standard SW register for control.
> >
> > In this design there will be no PWM signal from the SoC and DCS
> > commands are sent to enable and control the backlight brightness.
> >
> > v2: Moving the CABC bkl functions to new file.(Jani)
> >
> > v3: Rebase
> >
> > v4: Rebase
> >
> > v5: Use mipi_dsi_dcs_write() instead of mipi_dsi_dcs_write_buffer() (Jani)
> > Move DCS macro`s to include/video/mipi_display.h (Jani)
> 
> Where's the patch actually adding the macros? We need that in the same
> series to have CI actually build and run this; this fails without them.
> 
> BR,
> Jani.
> 
> 
[Deepak, M] Okay will resend these patches including that patch also.
> >
> > Cc: Jani Nikula <jani.nik...@intel.com>
> > Cc: Daniel Vetter <daniel.vet...@intel.com>
> > Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
> > Signed-off-by: Deepak M <m.dee...@intel.com>
> > ---
> >
> > The DCS command macro`s are defined in the patch which is posted in
> > the dri-devel list.
> >
> >  drivers/gpu/drm/i915/Makefile |   1 +
> >  drivers/gpu/drm/i915/i915_drv.h   |   1 -
> >  drivers/gpu/drm/i915/intel_drv.h  |   2 +
> >  drivers/gpu/drm/i915/intel_dsi.c  |  19 -
> >  drivers/gpu/drm/i915/intel_dsi.h  |   4 +
> >  drivers/gpu/drm/i915/intel_dsi_cabc.c | 154
> ++
> >  drivers/gpu/drm/i915/intel_panel.c|   4 +
> >  7 files changed, 182 insertions(+), 3 deletions(-)  create mode
> > 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index 7ffb51b..065c410 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -83,6 +83,7 @@ i915-y += dvo_ch7017.o \
> >   intel_dp_mst.o \
> >   intel_dp.o \
> >   intel_dsi.o \
> > + intel_dsi_cabc.o \
> >   intel_dsi_panel_vbt.o \
> >   intel_dsi_pll.o \
> >   intel_dvo.o \
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 050d860..9ed60f8 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3489,7 +3489,6 @@ void intel_sbi_write(struct drm_i915_private
> *dev_priv, u16 reg, u32 value,
> >  enum intel_sbi_destination destination);
> >  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> > void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32
> > val);
> > -
> >  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);  int
> > intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index c87b450..9e49396 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1325,6 +1325,8 @@ void intel_dp_mst_encoder_cleanup(struct
> > intel_digital_port *intel_dig_port);
> >  /* intel_dsi.c */
> >  void intel_dsi_init(struct drm_device *dev);
> >
> > +/* intel_dsi_cabc.c */
> > +int intel_dsi_cabc_init_backlight_funcs(struct intel_connector
> > +*intel_connector);
> >
> >  /* intel_dvo.c */
> >  void intel_dvo_init(struct drm_device *dev); diff --git
> > a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > index 456676c..7aa707f 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -1209,10 +1209,25 @@ void intel_dsi_init(struct drm_device *dev)
> > else
> > intel_encoder->crtc_mask = BIT(PIPE_B);
> &g

[Intel-gfx] [PATCH 1/2] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT

2016-03-24 Thread Deepak M

For dual link panel scenarios there are new fileds added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

v2: Moving the comment to intel_dsi.h(Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 10 ++
 drivers/gpu/drm/i915/intel_bios.h |  5 -
 drivers/gpu/drm/i915/intel_dsi.h  |  9 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 083003b..587c06f 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -749,6 +749,16 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
return;
}
 
+   /*
+* These fileds are introduced from the VBT version 197 onwards,
+* so making sure that these bits are set zero in the pervious
+* versions.
+*/
+   if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+   dev_priv->vbt.dsi.config->dl_cabc_port = 0;
+   dev_priv->vbt.dsi.config->pwm_bkl_ctrl = 0;
+   }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 }
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index ab0ea31..7a89f79 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -113,7 +113,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
-   u16 rsvd3:9;
+   u16 rgb_flip:1;
+   u16 dl_cabc_port:2;
+   u16 pwm_bkl_ctrl:2;
+   u16 rsvd3:4;
 
u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e582ef8..0e758f1 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -78,6 +78,15 @@ struct intel_dsi {
 
u8 escape_clk_div;
u8 dual_link;
+
+   /*
+* Below field will inform us on which port the panel blk_cntrl
+* and CABC ON/OFF commands needs to be sent in case of dual link
+* panels
+*/
+   u8 bkl_dcs_ports;
+   u8 pwm_blk_ctrl;
+
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
-- 
1.9.1

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[Intel-gfx] [PATCH 2/2] drm/i915: CABC support for backlight control

2016-03-24 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

In this design there will be no PWM signal from the SoC and DCS
commands are sent to enable and control the backlight brightness.

v2: Moving the CABC bkl functions to new file.(Jani)

v3: Rebase

v4: Rebase

v5: Use mipi_dsi_dcs_write() instead of mipi_dsi_dcs_write_buffer() (Jani)
Move DCS macro`s to include/video/mipi_display.h (Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---

The DCS command macro`s are defined in the patch which is posted in the
dri-devel list.

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |   1 -
 drivers/gpu/drm/i915/intel_drv.h  |   2 +
 drivers/gpu/drm/i915/intel_dsi.c  |  19 -
 drivers/gpu/drm/i915/intel_dsi.h  |   4 +
 drivers/gpu/drm/i915/intel_dsi_cabc.c | 154 ++
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 7 files changed, 182 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..065c410 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += dvo_ch7017.o \
  intel_dp_mst.o \
  intel_dp.o \
  intel_dsi.o \
+ intel_dsi_cabc.o \
  intel_dsi_panel_vbt.o \
  intel_dsi_pll.o \
  intel_dvo.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 050d860..9ed60f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3489,7 +3489,6 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
 enum intel_sbi_destination destination);
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c87b450..9e49396 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1325,6 +1325,8 @@ void intel_dp_mst_encoder_cleanup(struct 
intel_digital_port *intel_dig_port);
 /* intel_dsi.c */
 void intel_dsi_init(struct drm_device *dev);
 
+/* intel_dsi_cabc.c */
+int intel_dsi_cabc_init_backlight_funcs(struct intel_connector 
*intel_connector);
 
 /* intel_dvo.c */
 void intel_dvo_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 456676c..7aa707f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1209,10 +1209,25 @@ void intel_dsi_init(struct drm_device *dev)
else
intel_encoder->crtc_mask = BIT(PIPE_B);
 
-   if (dev_priv->vbt.dsi.config->dual_link)
+   if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
-   else
+   switch (dev_priv->vbt.dsi.config->dl_cabc_port) {
+   case CABC_PORT_A:
+   intel_dsi->bkl_dcs_ports = BIT(PORT_A);
+   break;
+   case CABC_PORT_C:
+   intel_dsi->bkl_dcs_ports = BIT(PORT_C);
+   break;
+   case CABC_PORT_A_AND_C:
+   intel_dsi->bkl_dcs_ports = BIT(PORT_A) | BIT(PORT_C);
+   break;
+   default:
+   DRM_ERROR("Unknown MIPI ports for sending DCS\n");
+   }
+   } else {
intel_dsi->ports = BIT(port);
+   intel_dsi->bkl_dcs_ports = BIT(port);
+   }
 
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 0e758f1..5c07d59 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,10 @@
 #define DSI_DUAL_LINK_FRONT_BACK   1
 #define DSI_DUAL_LINK_PIXEL_ALT2
 
+#define CABC_PORT_A 0x00
+#define CABC_PORT_C 0x01
+#define CABC_PORT_A_AND_C   0x02
+
 struct intel_dsi_host;
 
 struct intel_dsi {
diff --git a/drivers/gpu/drm/i915/intel_dsi_cabc.c 
b/drivers/gpu/dr

Re: [Intel-gfx] [MIPI CABC 2/2] drm/i915: CABC support for backlight control

2016-03-23 Thread Deepak, M



> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, March 22, 2016 7:19 PM
> To: Deepak, M <m.dee...@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deepak, M <m.dee...@intel.com>; Vetter, Daniel
> <daniel.vet...@intel.com>; Adebisi, YetundeX
> <yetundex.adeb...@intel.com>
> Subject: Re: [MIPI CABC 2/2] drm/i915: CABC support for backlight control
> 
> On Tue, 22 Mar 2016, Deepak M <m.dee...@intel.com> wrote:
> > In CABC (Content Adaptive Brightness Control) content grey level scale
> > can be increased while simultaneously decreasing brightness of the
> > backlight to achieve same perceived brightness.
> >
> > The CABC is not standardized and panel vendors are free to follow
> > their implementation. The CABC implementaion here assumes that the
> > panels use standard SW register for control.
> >
> > In this design there will be no PWM signal from the SoC and DCS
> > commands are sent to enable and control the backlight brightness.
> >
> > v2: Moving the CABC bkl functions to new file.(Jani)
> >
> > v3: Rebase
> >
> > v4: Rebase
> >
> > Cc: Jani Nikula <jani.nik...@intel.com>
> > Cc: Daniel Vetter <daniel.vet...@intel.com>
> > Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
> > Signed-off-by: Deepak M <m.dee...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/Makefile |   1 +
> >  drivers/gpu/drm/i915/i915_drv.h   |   2 +-
> >  drivers/gpu/drm/i915/intel_dsi.c  |  19 +++-
> >  drivers/gpu/drm/i915/intel_dsi.h  |   4 +
> >  drivers/gpu/drm/i915/intel_dsi_cabc.c | 179
> ++
> >  drivers/gpu/drm/i915/intel_panel.c|   4 +
> >  6 files changed, 206 insertions(+), 3 deletions(-)  create mode
> > 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index 7ffb51b..065c410 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -83,6 +83,7 @@ i915-y += dvo_ch7017.o \
> >   intel_dp_mst.o \
> >   intel_dp.o \
> >   intel_dsi.o \
> > + intel_dsi_cabc.o \
> >   intel_dsi_panel_vbt.o \
> >   intel_dsi_pll.o \
> >   intel_dvo.o \
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 050d860..d196404 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3489,7 +3489,7 @@ void intel_sbi_write(struct drm_i915_private
> *dev_priv, u16 reg, u32 value,
> >  enum intel_sbi_destination destination);
> >  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> > void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32
> > val);
> > -
> > +int intel_dsi_cabc_init_backlight_funcs(struct intel_connector
> > +*intel_connector);
> 
> This probably fits better in intel_drv.h under a /* intel_dsi_cabc.c */
> comment, see the file for examples.
> 
> >  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);  int
> > intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 456676c..7aa707f 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -1209,10 +1209,25 @@ void intel_dsi_init(struct drm_device *dev)
> > else
> > intel_encoder->crtc_mask = BIT(PIPE_B);
> >
> > -   if (dev_priv->vbt.dsi.config->dual_link)
> > +   if (dev_priv->vbt.dsi.config->dual_link) {
> > intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
> > -   else
> > +   switch (dev_priv->vbt.dsi.config->dl_cabc_port) {
> > +   case CABC_PORT_A:
> > +   intel_dsi->bkl_dcs_ports = BIT(PORT_A);
> > +   break;
> > +   case CABC_PORT_C:
> > +   intel_dsi->bkl_dcs_ports = BIT(PORT_C);
> > +   break;
> > +   case CABC_PORT_A_AND_C:
> > +   intel_dsi->bkl_dcs_ports = BIT(PORT_A) |
> BIT(PORT_C);
> > +   break;
> > +   default:
> > +   DRM_ERROR("Unknown MIPI ports for sending
> DCS\n");
> > +   }
> > +   } else {
> > intel_dsi->ports = BIT(port);
> > +   intel_dsi->bkl_dcs_ports = BIT(port);
> > +   }
> &

[Intel-gfx] [MIPI CABC 2/2] drm/i915: CABC support for backlight control

2016-03-21 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

In this design there will be no PWM signal from the SoC and DCS
commands are sent to enable and control the backlight brightness.

v2: Moving the CABC bkl functions to new file.(Jani)

v3: Rebase

v4: Rebase

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +-
 drivers/gpu/drm/i915/intel_dsi.c  |  19 +++-
 drivers/gpu/drm/i915/intel_dsi.h  |   4 +
 drivers/gpu/drm/i915/intel_dsi_cabc.c | 179 ++
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 6 files changed, 206 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b..065c410 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += dvo_ch7017.o \
  intel_dp_mst.o \
  intel_dp.o \
  intel_dsi.o \
+ intel_dsi_cabc.o \
  intel_dsi_panel_vbt.o \
  intel_dsi_pll.o \
  intel_dvo.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 050d860..d196404 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3489,7 +3489,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
 enum intel_sbi_destination destination);
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-
+int intel_dsi_cabc_init_backlight_funcs(struct intel_connector 
*intel_connector);
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 456676c..7aa707f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1209,10 +1209,25 @@ void intel_dsi_init(struct drm_device *dev)
else
intel_encoder->crtc_mask = BIT(PIPE_B);
 
-   if (dev_priv->vbt.dsi.config->dual_link)
+   if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
-   else
+   switch (dev_priv->vbt.dsi.config->dl_cabc_port) {
+   case CABC_PORT_A:
+   intel_dsi->bkl_dcs_ports = BIT(PORT_A);
+   break;
+   case CABC_PORT_C:
+   intel_dsi->bkl_dcs_ports = BIT(PORT_C);
+   break;
+   case CABC_PORT_A_AND_C:
+   intel_dsi->bkl_dcs_ports = BIT(PORT_A) | BIT(PORT_C);
+   break;
+   default:
+   DRM_ERROR("Unknown MIPI ports for sending DCS\n");
+   }
+   } else {
intel_dsi->ports = BIT(port);
+   intel_dsi->bkl_dcs_ports = BIT(port);
+   }
 
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 0e758f1..5c07d59 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,10 @@
 #define DSI_DUAL_LINK_FRONT_BACK   1
 #define DSI_DUAL_LINK_PIXEL_ALT2
 
+#define CABC_PORT_A 0x00
+#define CABC_PORT_C 0x01
+#define CABC_PORT_A_AND_C   0x02
+
 struct intel_dsi_host;
 
 struct intel_dsi {
diff --git a/drivers/gpu/drm/i915/intel_dsi_cabc.c 
b/drivers/gpu/drm/i915/intel_dsi_cabc.c
new file mode 100644
index 000..d14a669
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cabc.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright © 2006-2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission no

[Intel-gfx] [MIPI CABC 1/2] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT

2016-03-21 Thread Deepak M

For dual link panel scenarios there are new fileds added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

v2: Moving the comment to intel_dsi.h(Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 10 ++
 drivers/gpu/drm/i915/intel_bios.h |  5 -
 drivers/gpu/drm/i915/intel_dsi.h  |  9 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 083003b..587c06f 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -749,6 +749,16 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
return;
}
 
+   /*
+* These fileds are introduced from the VBT version 197 onwards,
+* so making sure that these bits are set zero in the pervious
+* versions.
+*/
+   if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+   dev_priv->vbt.dsi.config->dl_cabc_port = 0;
+   dev_priv->vbt.dsi.config->pwm_bkl_ctrl = 0;
+   }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 }
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index ab0ea31..7a89f79 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -113,7 +113,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
-   u16 rsvd3:9;
+   u16 rgb_flip:1;
+   u16 dl_cabc_port:2;
+   u16 pwm_bkl_ctrl:2;
+   u16 rsvd3:4;
 
u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e582ef8..0e758f1 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -78,6 +78,15 @@ struct intel_dsi {
 
u8 escape_clk_div;
u8 dual_link;
+
+   /*
+* Below field will inform us on which port the panel blk_cntrl
+* and CABC ON/OFF commands needs to be sent in case of dual link
+* panels
+*/
+   u8 bkl_dcs_ports;
+   u8 pwm_blk_ctrl;
+
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
-- 
1.9.1

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[Intel-gfx] [MIPI CABC 0/2] CABC patch list

2016-03-21 Thread Deepak M

CABC stands for the Content Adaptive Backlight Control.
In the normal display the backlight which we see is due to the
backlight which is being modulated by the filter, which is inturn
dependent on the image. In brief the CABC does the histogram
analysis of the image and then controls the filter and backlight.
For example in CABC to display the dark image the backlight is dimmed
and then controlls the filter to allow more light, because of
which is power consuption will be reduced.

Below are the initial set of patches which supports the CABC.
A field exists in the mipi configuration of the VBT which
when enabled indicates the CABC is supported. Depending on
this field the backlight control function pointer are
initialized in the intel_panel.c file.

In case of dual link panels depending on the panel
the DCS commands have to be send to either PORT A,
PORT C or both PORT A and PORT C. Again a field is
added in the VBT to get this data from the version 197 onwards.
One of the below patches parses these fields from the
VBT.

Addressed the review comments of Jani, which were mentioned in
the below link
https://lists.freedesktop.org/archives/intel-gfx/2015-November/081233.html

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>

Deepak M (2):
  drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT
  drm/i915: CABC support for backlight control

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +-
 drivers/gpu/drm/i915/intel_bios.c |  10 ++
 drivers/gpu/drm/i915/intel_bios.h |   5 +-
 drivers/gpu/drm/i915/intel_dsi.c  |  19 +++-
 drivers/gpu/drm/i915/intel_dsi.h  |  13 +++
 drivers/gpu/drm/i915/intel_dsi_cabc.c | 179 ++
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 8 files changed, 229 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c

-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915: GPIO for BXT generic MIPI

2016-03-11 Thread Deepak M

Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.

v2 by Deepak
  - Added the GPIO table for BXT.
  - Added gpio_free

v3 by Deepak
  - requesting the gpio once
  - freeing the gpio while unloading

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---

GPIO mapping table can be found in the below link:
https://drive.google.com/drive/folders/0BxSYm2johowAaE94S0ZvbE1wTG8

 drivers/gpu/drm/i915/intel_dsi.c   |   6 +
 drivers/gpu/drm/i915/intel_dsi.h   |   2 +-
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 687 +
 3 files changed, 694 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b928c50..30994f5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -39,10 +39,12 @@
 static const struct {
u16 panel_id;
struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
+   void (*exit)(struct intel_dsi *intel_dsi);
 } intel_dsi_drivers[] = {
{
.panel_id = MIPI_DSI_GENERIC_PANEL_ID,
.init = vbt_panel_init,
+   .exit = vbt_panel_exit,
},
 };
 
@@ -1073,6 +1075,7 @@ static void intel_dsi_connector_destroy(struct 
drm_connector *connector)
 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
 {
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+   int i;
 
if (intel_dsi->panel) {
drm_panel_detach(intel_dsi->panel);
@@ -1084,6 +1087,9 @@ static void intel_dsi_encoder_destroy(struct drm_encoder 
*encoder)
if (intel_dsi->gpio_panel)
gpiod_put(intel_dsi->gpio_panel);
 
+   for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++)
+   intel_dsi_drivers[i].exit(intel_dsi);
+
intel_encoder_destroy(encoder);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index de7be7f..2f833b0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -131,5 +131,5 @@ extern void intel_dsi_reset_clocks(struct intel_encoder 
*encoder,
enum port port);
 
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
-
+void vbt_panel_exit(struct intel_dsi *intel_dsi);
 #endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 6b9a1f7..f8b126b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -615,6 +616,635 @@ static struct gpio_table gtable[] = {
{ VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, 
VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
 };
 
+struct bxt_gpio_table {
+   u16 gpio_pin;
+   u16 offset;
+   bool pin_requested;
+};
+
+#define  BXT_HV_DDI0_DDC_SDA_PIN187
+#define  BXT_HV_DDI0_DDC_SCL_PIN188
+#define  BXT_HV_DDI1_DDC_SDA_PIN189
+#define  BXT_HV_DDI1_DDC_SCL_PIN190
+#define  BXT_DBI_SDA_PIN191
+#define  BXT_DBI_SCL_PIN192
+#define  BXT_PANEL0_VDDEN_PIN   193
+#define  BXT_PANEL0_BKLTEN_PIN  194
+#define  BXT_PANEL0_BKLTCTL_PIN 195
+#define  BXT_PANEL1_VDDEN_PIN   196
+#define  BXT_PANEL1_BKLTEN_PIN  197
+#define  BXT_PANEL1_BKLTCTL_PIN 198
+#define  BXT_DBI_CSX_PIN199
+#define  BXT_DBI_RESX_PIN   200
+#define  BXT_GP_INTD_DSI_TE1_PIN201
+#define  BXT_GP_INTD_DSI_TE2_PIN202
+#define  BXT_USB_OC0_B_PIN  203
+#define  BXT_USB_OC1_B_PIN  204
+#define  BXT_MEX_WAKE0_B_PIN205
+#define  BXT_MEX_WAKE1_B_PIN206
+#define  BXT_EMMC0_CLK_PIN  156
+#define  BXT_EMMC0_D0_PIN   157
+#define  BXT_EMMC0_D1_PIN   158
+#define  BXT_EMMC0_D2_PIN   159
+#define  BXT_EMMC0_D3_PIN   160
+#define  BXT_EMMC0_D4_PIN   161
+#define  BXT_EMMC0_D5_PIN   162
+#define  BXT_EMMC0_D6_PIN   163
+#define  BXT_EMMC0_D7_PIN   164
+#define  BXT_EMMC0_CMD_PIN  165
+#define  BXT_SDIO_CLK_PIN   166
+#define  BXT_SDIO_D0_PIN167
+#define  BXT_SDIO_D1_PIN168
+#define  BXT_SDIO_D2_PIN169
+#define  BXT_SDIO_D3_

[Intel-gfx] [PATCH 2/2] drm/i915: Adding the parsing logic for the i2c element

2016-03-11 Thread Deepak M

From: vkorjani <vikas.korj...@intel.com>

New sequence element for i2c is been added in the
mipi sequence block of the VBT. This patch parses
and executes the i2c sequence.

v2: Add i2c_put_adapter call(Jani), rebase

v3: corrected the retry loop(Jani), rebase

v4 by Jani:
 - don't put the adapter if get fails
 - print an error message if all retries exhausted
 - use a for loop
 - fix warnings for unused variables

v5 by Jani:
 - rebase on the skip i2c element patch

v6: by Jani:
 - ignore the gmbus i2c elements (Ville)

v7: by Deepak
 - Use the i2c port number which is read from ACPI.

Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: vkorjani <vikas.korj...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 84 --
 1 file changed, 81 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 7f145b4..be92cf3 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "i915_drv.h"
@@ -249,9 +250,86 @@ out:
return data;
 }
 
-static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 
*data)
+static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
 {
-   return data + *(data + 6) + 7;
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct i2c_adapter *adapter;
+   int ret, i;
+   u8 reg_offset, payload_size;
+   struct i2c_msg msg;
+   struct acpi_i2c_data_node *i2c_entry = NULL;
+   u8 *transmit_buffer;
+   u8 flag, resource_id, bus_number;
+   u16 slave_add;
+   u8 count = 0;
+
+   flag = *data++;
+   resource_id = *data++;
+   bus_number = *data++;
+   slave_add = *(u16 *)(data);
+   data += 2;
+   reg_offset = *data++;
+   payload_size = *data++;
+
+   if (resource_id == 0xff || bus_number == 0xff) {
+   DRM_DEBUG_KMS("ignoring gmbus (resource id %02x, bus %02x)\n",
+ resource_id, bus_number);
+   goto out;
+   }
+
+   /* Parse the list and get the required i2c bus number */
+   list_for_each_entry(i2c_entry, _priv->acpi_i2c_list,
+   head) {
+   if (count == resource_id) {
+   /* override the busnumber */
+   bus_number = i2c_entry->i2c_bus_number;
+   break;
+   }
+   count++;
+   }
+
+   /*
+* Since the i2c bus number indexing in BIOS starts from 1
+* decrementing the bus number which we are reading.
+*/
+   bus_number--;
+
+   adapter = i2c_get_adapter(bus_number);
+   if (!adapter) {
+   DRM_ERROR("i2c_get_adapter(%u)\n", bus_number);
+   goto out;
+   }
+
+   transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
+   if (!transmit_buffer)
+   goto out_put;
+
+   transmit_buffer[0] = reg_offset;
+   memcpy(_buffer[1], data, payload_size);
+
+   msg.addr = slave_add;
+   msg.flags = 0;
+   msg.len = payload_size + 1;
+   msg.buf = _buffer[0];
+
+   for (i = 0; i < 6; i++) {
+   ret = i2c_transfer(adapter, , 1);
+   if (ret == 1)
+   goto out_free;
+   else if (ret == -EAGAIN)
+   usleep_range(1000, 2500);
+   else
+   break;
+   }
+
+   DRM_ERROR("i2c transfer failed: %d\n", ret);
+out_free:
+   kfree(transmit_buffer);
+out_put:
+   i2c_put_adapter(adapter);
+out:
+   return data + payload_size;
 }
 
 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
@@ -260,7 +338,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
[MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
[MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
[MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
-   [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip,
+   [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
 };
 
 /*
-- 
1.9.1

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[Intel-gfx] [PATCH 2/2] drm/i915: Adding the parsing logic for the i2c element

2016-03-11 Thread Deepak M

From: vkorjani <vikas.korj...@intel.com>

New sequence element for i2c is been added in the
mipi sequence block of the VBT. This patch parses
and executes the i2c sequence.

v2: Add i2c_put_adapter call(Jani), rebase

v3: corrected the retry loop(Jani), rebase

v4 by Jani:
 - don't put the adapter if get fails
 - print an error message if all retries exhausted
 - use a for loop
 - fix warnings for unused variables

v5 by Jani:
 - rebase on the skip i2c element patch

v6: by Jani:
 - ignore the gmbus i2c elements (Ville)

v7: by Deepak
 - Use the i2c port number which is read from ACPI
   based on the resource id.

Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: vkorjani <vikas.korj...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 84 --
 1 file changed, 81 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 7f145b4..5a7690d 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "i915_drv.h"
@@ -249,9 +250,86 @@ out:
return data;
 }
 
-static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 
*data)
+static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
 {
-   return data + *(data + 6) + 7;
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct i2c_adapter *adapter;
+   int ret, i;
+   u8 reg_offset, payload_size;
+   struct i2c_msg msg;
+   struct acpi_i2c_data_node *i2c_entry = NULL;
+   u8 *transmit_buffer;
+   u8 flag, resource_id, bus_number;
+   u16 slave_add;
+   u8 count = 0;
+
+   flag = *data++;
+   resource_id = *data++;
+   bus_number = *data++;
+   slave_add = *(u16 *)(data);
+   data += 2;
+   reg_offset = *data++;
+   payload_size = *data++;
+
+   if (resource_id == 0xff || bus_number == 0xff) {
+   DRM_DEBUG_KMS("ignoring gmbus (resource id %02x, bus %02x)\n",
+ resource_id, bus_number);
+   goto out;
+   }
+
+   /* Parse the list and get the required i2c bus number */
+   list_for_each_entry(i2c_entry, _priv->acpi_i2c_list,
+   head) {
+   if (count == resource_id) {
+   /* override the busnumber */
+   bus_number = i2c_entry->i2c_bus_number;
+   break;
+   }
+   count++;
+   }
+
+   /*
+* Since the i2c bus number indexing in BIOS starts from 1
+* decrementing the bus number which we are reading.
+*/
+   bus_number--;
+
+   adapter = i2c_get_adapter(bus_number);
+   if (!adapter) {
+   DRM_ERROR("i2c_get_adapter(%u)\n", bus_number);
+   goto out;
+   }
+
+   transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
+   if (!transmit_buffer)
+   goto out_put;
+
+   transmit_buffer[0] = reg_offset;
+   memcpy(_buffer[1], data, payload_size);
+
+   msg.addr = slave_add;
+   msg.flags = 0;
+   msg.len = payload_size + 1;
+   msg.buf = _buffer[0];
+
+   for (i = 0; i < 6; i++) {
+   ret = i2c_transfer(adapter, , 1);
+   if (ret == 1)
+   goto out_free;
+   else if (ret == -EAGAIN) {
+   usleep_range(1000, 2500);
+   else
+   break;
+   }
+
+   DRM_ERROR("i2c transfer failed: %d\n", ret);
+out_free:
+   kfree(transmit_buffer);
+out_put:
+   i2c_put_adapter(adapter);
+out:
+   return data + payload_size;
 }
 
 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
@@ -260,7 +338,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
[MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
[MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
[MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
-   [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip,
+   [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
 };
 
 /*
-- 
1.9.1

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[Intel-gfx] [PATCH 1/2] drm/i915: Get the i2c bus number from the ACPI

2016-03-11 Thread Deepak M

Currently for executing the i2c MIPI sequence, we are
relaying on the i2c bus bunmber which is specified in the
VBT. But there are cases where different Fab versions of
the board will drive the same chip with different i2c port,
in which case the i2c bus number from the VBT cant be relied
on. To overcome this the i2c bus number is read from the
BIOS acpi table; BIOS can detect the Fab version in runtime
and will store the correct i2c bus number in the ACPI table.

v2 by Deepak:
 - Reading the i2c from the ACPI and storing them in list

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c   |  2 ++
 drivers/gpu/drm/i915/i915_drv.h   | 11 
 drivers/gpu/drm/i915/intel_acpi.c | 59 +++
 3 files changed, 72 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4aa3db6..57be99b 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -387,6 +387,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
intel_register_dsm_handler();
 
+   intel_acpi_find_i2c(dev_priv);
+
ret = vga_switcheroo_register_client(dev->pdev, _switcheroo_ops, 
false);
if (ret)
goto cleanup_vga_client;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..5c6279d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -41,6 +41,7 @@
 #include "intel_lrc.h"
 #include "i915_gem_gtt.h"
 #include "i915_gem_render_state.h"
+#include 
 #include 
 #include 
 #include 
@@ -1739,6 +1740,12 @@ struct intel_wm_config {
bool sprites_scaled;
 };
 
+struct acpi_i2c_data_node {
+   struct list_head head;
+   int i2c_bus_number;
+   int i2c_slave_address;
+};
+
 struct drm_i915_private {
struct drm_device *dev;
struct kmem_cache *objects;
@@ -1823,6 +1830,8 @@ struct drm_i915_private {
/* backlight registers and fields in struct intel_panel */
struct mutex backlight_lock;
 
+   struct list_head acpi_i2c_list;
+
/* LVDS info */
bool no_aux_handshake;
 
@@ -1892,6 +1901,7 @@ struct drm_i915_private {
 
struct i915_workarounds workarounds;
 
+
/* Reclocking support */
bool render_reclock_avail;
 
@@ -3439,6 +3449,7 @@ intel_opregion_notify_adapter(struct drm_device *dev, 
pci_power_t state)
 #ifdef CONFIG_ACPI
 extern void intel_register_dsm_handler(void);
 extern void intel_unregister_dsm_handler(void);
+extern acpi_status intel_acpi_find_i2c(struct drm_i915_private *dev_priv);
 #else
 static inline void intel_register_dsm_handler(void) { return; }
 static inline void intel_unregister_dsm_handler(void) { return; }
diff --git a/drivers/gpu/drm/i915/intel_acpi.c 
b/drivers/gpu/drm/i915/intel_acpi.c
index eb638a1..afe42ab 100644
--- a/drivers/gpu/drm/i915/intel_acpi.c
+++ b/drivers/gpu/drm/i915/intel_acpi.c
@@ -110,6 +110,65 @@ static void intel_dsm_platform_mux_info(void)
ACPI_FREE(pkg);
 }
 
+static int i2c_acpi_get_name(struct acpi_resource *ares, void *data)
+{
+   struct drm_i915_private *dev_priv = data;
+   struct acpi_resource_i2c_serialbus *sb;
+   unsigned int val;
+   char *resource;
+   int error;
+
+
+   if (ares->type == ACPI_RESOURCE_TYPE_SERIAL_BUS) {
+   sb = >data.i2c_serial_bus;
+
+   if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) {
+   struct acpi_i2c_data_node *i2c_entry = NULL;
+
+   resource = sb->resource_source.string_ptr;
+   resource = strstr(resource, "I2C");
+   error = kstrtouint(resource+3, 0, );
+   if (error)
+   return error;
+
+   i2c_entry = kzalloc(sizeof(struct acpi_i2c_data_node),
+   GFP_NOWAIT);
+   i2c_entry->i2c_bus_number = val;
+   i2c_entry->i2c_slave_address = sb->slave_address;
+
+   list_add_tail(_entry->head,
+   _priv->acpi_i2c_list);
+   }
+   }
+
+   return 1;
+}
+
+acpi_status intel_acpi_find_i2c(struct drm_i915_private *dev_priv)
+{
+   struct pci_dev *pdev = dev_priv->dev->pdev;
+   struct list_head resource_list;
+   struct acpi_device *adev;
+   acpi_handle dhandle;
+
+   dhandle = ACPI_HANDLE(>dev);
+   if (!dhandle)
+   return false;
+
+   if (acpi_bus_get_device(dhandle, ))
+   return AE_OK;
+   if (acpi_bus_get_status(adev) || !adev->status.present)
+   return AE_OK;
+
+   INIT_LIST_HEAD(_list);
+   INIT_LIST_HEAD(_priv-&g

[Intel-gfx] [PATCH 2/2] drm/i915: CABC support for backlight control

2016-03-08 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

In this design there will be no PWM signal from the SoC and DCS
commands are sent to enable and control the backlight brightness.

v2: Moving the CABC bkl functions to new file.(Jani)

v3: Rebase

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +-
 drivers/gpu/drm/i915/intel_dsi.c  |  17 +++-
 drivers/gpu/drm/i915/intel_dsi.h  |   4 +
 drivers/gpu/drm/i915/intel_dsi_cabc.c | 179 ++
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 6 files changed, 205 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..d5031df 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -81,6 +81,7 @@ i915-y += dvo_ch7017.o \
  intel_dp_mst.o \
  intel_dp.o \
  intel_dsi.o \
+ intel_dsi_cabc.o \
  intel_dsi_panel_vbt.o \
  intel_dsi_pll.o \
  intel_dvo.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..d77eb1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3501,7 +3501,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
 enum intel_sbi_destination destination);
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-
+int intel_dsi_cabc_init_backlight_funcs(struct intel_connector 
*intel_connector);
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 01b8e9f..18ed902 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1170,8 +1170,23 @@ void intel_dsi_init(struct drm_device *dev)
intel_dsi->ports = (1 << PORT_C);
}
 
-   if (dev_priv->vbt.dsi.config->dual_link)
+   if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
+   switch (dev_priv->vbt.dsi.config->dl_cabc_port) {
+   case CABC_PORT_A:
+   intel_dsi->bkl_dcs_ports = (1 << PORT_A);
+   break;
+   case CABC_PORT_C:
+   intel_dsi->bkl_dcs_ports = (1 << PORT_C);
+   break;
+   case CABC_PORT_A_AND_C:
+   intel_dsi->bkl_dcs_ports = intel_dsi->ports;
+   break;
+   default:
+   DRM_ERROR("Unknown MIPI ports for sending DCS\n");
+   }
+   } else
+   intel_dsi->bkl_dcs_ports = intel_dsi->ports;
 
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e9fdfec..c51fd22 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -36,6 +36,10 @@
 
 int dsi_pixel_format_bpp(int pixel_format);
 
+#define CABC_PORT_A 0x00
+#define CABC_PORT_C 0x01
+#define CABC_PORT_A_AND_C   0x02
+
 struct intel_dsi_host;
 
 struct intel_dsi {
diff --git a/drivers/gpu/drm/i915/intel_dsi_cabc.c 
b/drivers/gpu/drm/i915/intel_dsi_cabc.c
new file mode 100644
index 000..d14a669
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cabc.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright © 2006-2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial porti

[Intel-gfx] [CABC PATCH 1/2] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT

2016-03-08 Thread Deepak M

For dual link panel scenarios there are new fileds added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

v2: Moving the comment to intel_dsi.h(Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 10 ++
 drivers/gpu/drm/i915/intel_bios.h |  5 -
 drivers/gpu/drm/i915/intel_dsi.h  |  9 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index bf62a19..4f5c0df 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -747,6 +747,16 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
return;
}
 
+   /*
+* These fileds are introduced from the VBT version 197 onwards,
+* so making sure that these bits are set zero in the pervious
+* versions.
+*/
+   if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+   dev_priv->vbt.dsi.config->dl_cabc_port = 0;
+   dev_priv->vbt.dsi.config->pwm_bkl_ctrl = 0;
+   }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 }
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index 350d4e0..8f295fd 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -846,7 +846,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
-   u16 rsvd3:9;
+   u16 rgb_flip:1;
+   u16 dl_cabc_port:2;
+   u16 pwm_bkl_ctrl:2;
+   u16 rsvd3:4;
 
u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index de7be7f..6dfa0e3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -74,6 +74,15 @@ struct intel_dsi {
 
u8 escape_clk_div;
u8 dual_link;
+
+   /*
+* Below field will inform us on which port the panel blk_cntrl
+* and CABC ON/OFF commands needs to be sent in case of dual link
+* panels
+*/
+   u8 bkl_dcs_ports;
+   u8 pwm_blk_ctrl;
+
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
-- 
1.9.1

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[Intel-gfx] [CABC PATCH 2/2] drm/i915: CABC support for backlight control

2016-03-08 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

In this design there will be no PWM signal from the SoC and DCS
commands are sent to enable and control the backlight brightness.

v2: Moving the CABC bkl functions to new file.(Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +-
 drivers/gpu/drm/i915/intel_dsi.c  |  17 +++-
 drivers/gpu/drm/i915/intel_dsi.h  |   4 +
 drivers/gpu/drm/i915/intel_dsi_cabc.c | 179 ++
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 6 files changed, 205 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..2c69ed4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -82,6 +82,7 @@ i915-y += dvo_ch7017.o \
  intel_dp.o \
  intel_dsi.o \
  intel_dsi_panel_vbt.o \
+ intel_dsi_cabc.o \
  intel_dsi_pll.o \
  intel_dvo.o \
  intel_hdmi.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6644c2e..43dd10e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3488,7 +3488,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
 enum intel_sbi_destination destination);
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-
+int intel_dsi_cabc_init_backlight_funcs(struct intel_connector 
*intel_connector);
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b928c50..caa65df 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1171,8 +1171,23 @@ void intel_dsi_init(struct drm_device *dev)
intel_dsi->ports = (1 << PORT_C);
}
 
-   if (dev_priv->vbt.dsi.config->dual_link)
+   if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
+   switch (dev_priv->vbt.dsi.config->dl_cabc_port) {
+   case CABC_PORT_A:
+   intel_dsi->bkl_dcs_ports = (1 << PORT_A);
+   break;
+   case CABC_PORT_C:
+   intel_dsi->bkl_dcs_ports = (1 << PORT_C);
+   break;
+   case CABC_PORT_A_AND_C:
+   intel_dsi->bkl_dcs_ports = intel_dsi->ports;
+   break;
+   default:
+   DRM_ERROR("Unknown MIPI ports for sending DCS\n");
+   }
+   } else
+   intel_dsi->bkl_dcs_ports = intel_dsi->ports;
 
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 6dfa0e3..466da2d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,10 @@
 #define DSI_DUAL_LINK_FRONT_BACK   1
 #define DSI_DUAL_LINK_PIXEL_ALT2
 
+#define CABC_PORT_A 0x00
+#define CABC_PORT_C 0x01
+#define CABC_PORT_A_AND_C   0x02
+
 struct intel_dsi_host;
 
 struct intel_dsi {
diff --git a/drivers/gpu/drm/i915/intel_dsi_cabc.c 
b/drivers/gpu/drm/i915/intel_dsi_cabc.c
new file mode 100644
index 000..d14a669
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cabc.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright © 2006-2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in al

[Intel-gfx] [CABC PATCH 0/2] CABC patch list

2016-03-08 Thread Deepak M

CABC stands for the Content Adaptive Backlight Control.
In the normal display the backlight which we see is due to the
backlight which is being modulated by the filter, which is inturn
dependent on the image. In brief the CABC does the histogram
analysis of the image and then controls the filter and backlight.
For example in CABC to display the dark image the backlight is dimmed
and then controlls the filter to allow more light, because of
which is power consuption will be reduced.

Below are the initial set of patches which supports the CABC.
A field exists in the mipi configuration of the VBT which
when enabled indicates the CABC is supported. Depending on
this field the backlight control function pointer are
initialized in the intel_panel.c file.

In case of dual link panels depending on the panel
the DCS commands have to be send to either PORT A,
PORT C or both PORT A and PORT C. Again a field is
added in the VBT to get this data from the version 197 onwards.
One of the below patches parses these fields from the
VBT.

Addressed the review comments of Jani, which were mentioned in
the below
https://lists.freedesktop.org/archives/intel-gfx/2015-November/081233.html

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>


Deepak M (2):
  drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT
  drm/i915: CABC support for backlight control

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +-
 drivers/gpu/drm/i915/intel_bios.c |  10 ++
 drivers/gpu/drm/i915/intel_bios.h |   5 +-
 drivers/gpu/drm/i915/intel_dsi.c  |  17 +++-
 drivers/gpu/drm/i915/intel_dsi.h  |  13 +++
 drivers/gpu/drm/i915/intel_dsi_cabc.c | 179 ++
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 8 files changed, 228 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c

-- 
1.9.1

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Re: [Intel-gfx] [PATCH] drm/i915: GPIO for BXT generic MIPI

2016-03-02 Thread Deepak, M

Attached is the GPIO table for the BXT, most of the GPIO`s numberings are 
sequential except few of them in the northwest core because of which complete 
table is added in the file.

> -Original Message-
> From: Deepak, M
> Sent: Wednesday, March 2, 2016 8:14 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Deepak, M <m.dee...@intel.com>; Nikula, Jani <jani.nik...@intel.com>;
> Ville Syrjälä <ville.syrj...@linux.intel.com>; Shankar, Uma
> <uma.shan...@intel.com>
> Subject: [PATCH] drm/i915: GPIO for BXT generic MIPI
> 
> Added the BXT GPIO pin configuration and programming logic for backlight
> and panel control.
> 
> v2 by Deepak
>   - Added the GPIO table got BXT.
>   - Added gpio_free
> 
> v3 by Deepak
>   - requesting the gpio once
>   - freeing the gpio while unloading
> 
> Cc: Jani Nikula <jani.nik...@intel.com>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Uma Shankar <uma.shan...@intel.com>
> Signed-off-by: Deepak M <m.dee...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c   |   6 +
>  drivers/gpu/drm/i915/intel_dsi.h   |   2 +-
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 686
> +
>  3 files changed, 693 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index b928c50..30994f5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -39,10 +39,12 @@
>  static const struct {
>   u16 panel_id;
>   struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
> + void (*exit)(struct intel_dsi *intel_dsi);
>  } intel_dsi_drivers[] = {
>   {
>   .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
>   .init = vbt_panel_init,
> + .exit = vbt_panel_exit,
>   },
>  };
> 
> @@ -1073,6 +1075,7 @@ static void intel_dsi_connector_destroy(struct
> drm_connector *connector)  static void intel_dsi_encoder_destroy(struct
> drm_encoder *encoder)  {
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + int i;
> 
>   if (intel_dsi->panel) {
>   drm_panel_detach(intel_dsi->panel);
> @@ -1084,6 +1087,9 @@ static void intel_dsi_encoder_destroy(struct
> drm_encoder *encoder)
>   if (intel_dsi->gpio_panel)
>   gpiod_put(intel_dsi->gpio_panel);
> 
> + for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++)
> + intel_dsi_drivers[i].exit(intel_dsi);
> +
>   intel_encoder_destroy(encoder);
>  }
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h
> b/drivers/gpu/drm/i915/intel_dsi.h
> index de7be7f..2f833b0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -131,5 +131,5 @@ extern void intel_dsi_reset_clocks(struct
> intel_encoder *encoder,
>   enum port port);
> 
>  struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
> -
> +void vbt_panel_exit(struct intel_dsi *intel_dsi);
>  #endif /* _INTEL_DSI_H */
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 6b9a1f7..43146f5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -29,6 +29,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -615,6 +616,635 @@ static struct gpio_table gtable[] = {
>   { VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0,
> VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}  };
> 
> +struct bxt_gpio_table {
> + u16 gpio_pin;
> + u16 offset;
> + bool pin_requested;
> +};
> +
> +#define  BXT_HV_DDI0_DDC_SDA_PIN187
> +#define  BXT_HV_DDI0_DDC_SCL_PIN188
> +#define  BXT_HV_DDI1_DDC_SDA_PIN189
> +#define  BXT_HV_DDI1_DDC_SCL_PIN190
> +#define  BXT_DBI_SDA_PIN191
> +#define  BXT_DBI_SCL_PIN192
> +#define  BXT_PANEL0_VDDEN_PIN   193
> +#define  BXT_PANEL0_BKLTEN_PIN  194
> +#define  BXT_PANEL0_BKLTCTL_PIN 195
> +#define  BXT_PANEL1_VDDEN_PIN   196
> +#define  BXT_PANEL1_BKLTEN_PIN  197
> +#define  BXT_PANEL1_BKLTCTL_PIN 198
> +#define  BXT_DBI_CSX_PIN199
> +#define  BXT_DBI_RESX_PIN   200
> +#define  BXT_GP_INTD_DSI_TE1_PIN201
> +#define  BXT_GP_INTD_DSI_TE2_PIN202
> +#define  BXT_USB_OC0_

[Intel-gfx] [PATCH] drm/i915: GPIO for BXT generic MIPI

2016-03-02 Thread Deepak M

Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.

v2 by Deepak
  - Added the GPIO table got BXT.
  - Added gpio_free

v3 by Deepak
  - requesting the gpio once
  - freeing the gpio while unloading

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c   |   6 +
 drivers/gpu/drm/i915/intel_dsi.h   |   2 +-
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 686 +
 3 files changed, 693 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b928c50..30994f5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -39,10 +39,12 @@
 static const struct {
u16 panel_id;
struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
+   void (*exit)(struct intel_dsi *intel_dsi);
 } intel_dsi_drivers[] = {
{
.panel_id = MIPI_DSI_GENERIC_PANEL_ID,
.init = vbt_panel_init,
+   .exit = vbt_panel_exit,
},
 };
 
@@ -1073,6 +1075,7 @@ static void intel_dsi_connector_destroy(struct 
drm_connector *connector)
 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
 {
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+   int i;
 
if (intel_dsi->panel) {
drm_panel_detach(intel_dsi->panel);
@@ -1084,6 +1087,9 @@ static void intel_dsi_encoder_destroy(struct drm_encoder 
*encoder)
if (intel_dsi->gpio_panel)
gpiod_put(intel_dsi->gpio_panel);
 
+   for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++)
+   intel_dsi_drivers[i].exit(intel_dsi);
+
intel_encoder_destroy(encoder);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index de7be7f..2f833b0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -131,5 +131,5 @@ extern void intel_dsi_reset_clocks(struct intel_encoder 
*encoder,
enum port port);
 
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
-
+void vbt_panel_exit(struct intel_dsi *intel_dsi);
 #endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 6b9a1f7..43146f5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -615,6 +616,635 @@ static struct gpio_table gtable[] = {
{ VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, 
VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
 };
 
+struct bxt_gpio_table {
+   u16 gpio_pin;
+   u16 offset;
+   bool pin_requested;
+};
+
+#define  BXT_HV_DDI0_DDC_SDA_PIN187
+#define  BXT_HV_DDI0_DDC_SCL_PIN188
+#define  BXT_HV_DDI1_DDC_SDA_PIN189
+#define  BXT_HV_DDI1_DDC_SCL_PIN190
+#define  BXT_DBI_SDA_PIN191
+#define  BXT_DBI_SCL_PIN192
+#define  BXT_PANEL0_VDDEN_PIN   193
+#define  BXT_PANEL0_BKLTEN_PIN  194
+#define  BXT_PANEL0_BKLTCTL_PIN 195
+#define  BXT_PANEL1_VDDEN_PIN   196
+#define  BXT_PANEL1_BKLTEN_PIN  197
+#define  BXT_PANEL1_BKLTCTL_PIN 198
+#define  BXT_DBI_CSX_PIN199
+#define  BXT_DBI_RESX_PIN   200
+#define  BXT_GP_INTD_DSI_TE1_PIN201
+#define  BXT_GP_INTD_DSI_TE2_PIN202
+#define  BXT_USB_OC0_B_PIN  203
+#define  BXT_USB_OC1_B_PIN  204
+#define  BXT_MEX_WAKE0_B_PIN205
+#define  BXT_MEX_WAKE1_B_PIN206
+#define  BXT_EMMC0_CLK_PIN  156
+#define  BXT_EMMC0_D0_PIN   157
+#define  BXT_EMMC0_D1_PIN   158
+#define  BXT_EMMC0_D2_PIN   159
+#define  BXT_EMMC0_D3_PIN   160
+#define  BXT_EMMC0_D4_PIN   161
+#define  BXT_EMMC0_D5_PIN   162
+#define  BXT_EMMC0_D6_PIN   163
+#define  BXT_EMMC0_D7_PIN   164
+#define  BXT_EMMC0_CMD_PIN  165
+#define  BXT_SDIO_CLK_PIN   166
+#define  BXT_SDIO_D0_PIN167
+#define  BXT_SDIO_D1_PIN168
+#define  BXT_SDIO_D2_PIN169
+#define  BXT_SDIO_D3_PIN170
+#define  BXT_SDIO_CMD_PIN   171
+#define  BXT_SDCARD_CLK_PIN

Re: [Intel-gfx] [PATCH 2/2] drm/i915: GPIO for CHT generic MIPI

2016-02-29 Thread Deepak, M



> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Monday, February 29, 2016 7:20 PM
> To: Deepak, M <m.dee...@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Mohan Marimuthu, Yogesh
> <yogesh.mohan.marimu...@intel.com>; Nikula, Jani
> <jani.nik...@intel.com>
> Subject: Re: [PATCH 2/2] drm/i915: GPIO for CHT generic MIPI
> 
> On Mon, Feb 29, 2016 at 11:00:34AM +, Deepak, M wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > Sent: Thursday, February 25, 2016 9:07 PM
> > > To: Deepak, M <m.dee...@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Mohan Marimuthu, Yogesh
> > > <yogesh.mohan.marimu...@intel.com>; Nikula, Jani
> > > <jani.nik...@intel.com>
> > > Subject: Re: [PATCH 2/2] drm/i915: GPIO for CHT generic MIPI
> > >
> > > On Wed, Feb 24, 2016 at 07:13:46PM +0530, Deepak M wrote:
> > > > From: Yogesh Mohan Marimuthu
> <yogesh.mohan.marimu...@intel.com>
> > > >
> > > > The GPIO configuration and register offsets are different from
> > > > baytrail for cherrytrail. Port the gpio programming accordingly
> > > > for cherrytrail in this patch.
> > > >
> > > > v2: Removing the duplication of parsing
> > > >
> > > > v3: Moved the macro def to panel_vbt.c file
> > > >
> > > > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > > > Cc: Jani Nikula <jani.nik...@intel.com>
> > > > Signed-off-by: Yogesh Mohan Marimuthu
> > > > <yogesh.mohan.marimu...@intel.com>
> > > > Signed-off-by: Deepak M <m.dee...@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 123
> > > > +++--
> > > >  1 file changed, 98 insertions(+), 25 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > > > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > > > index 794bd1f..6b9a1f7 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > > > @@ -58,6 +58,28 @@ static inline struct vbt_panel
> > > > *to_vbt_panel(struct drm_panel *panel)
> > > >
> > > >  #define NS_KHZ_RATIO 100
> > > >
> > > > +#define CHV_IOSF_PORT_GPIO_N 0x13
> > > > +#define CHV_IOSF_PORT_GPIO_SE0x48
> > > > +#define CHV_IOSF_PORT_GPIO_SW0xB2
> > > > +#define CHV_IOSF_PORT_GPIO_E 0xA8
> > >
> > > These should have remained where the other ports were defined.
> > >
> > > > +#define CHV_MAX_GPIO_NUM_N   72
> > > > +#define CHV_MAX_GPIO_NUM_SE  99
> > > > +#define CHV_MAX_GPIO_NUM_SW  197
> > > > +#define CHV_MIN_GPIO_NUM_SE  73
> > > > +#define CHV_MIN_GPIO_NUM_SW  100
> > > > +#define CHV_MIN_GPIO_NUM_E   198
> > >
> > > I never got any explanation where the block sizes came from on VLV.
> > > IIRC when I checked them against configdb they didn't match the
> > > actual number of pins in the hardware block. And the same story
> continues here.
> > > Eg. if I check configfb the number of pins in each block is:
> > > N 59, SE 55, SW 56, E 24.
> > >
> > > So I can't review this until someone explains where this stuff comes from.
> > > And there should probably be a comment next to the defines to remind
> > > the next guy who gets totally confused by this.
> > >
> > > Also I don't like the fact that VLV and CHV are now implemented in
> > > two totally different ways. Can you eliminate the massive gpio table
> > > from the VLV code to make it more similar to this?
> > >
> > [Deepak, M] In CHV the GPIO numberings are sequential but in VLV that
> > is not the case, hence the complete table is copied here. I have
> > attached the VLV GPIO mapping table which can clear your doubts. Pfa,
> 
> Any chance someone could try to get this table included in the spec, or at
> least have a link to it? Having the information spread around this way is not
> productive.
[Deepak, M] Sure, will try to put this doc in sharepoint. 
> 
> --
> Ville Syrjälä
> Intel OTC
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: GPIO for CHT generic MIPI

2016-02-29 Thread Deepak, M



> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, February 25, 2016 9:07 PM
> To: Deepak, M <m.dee...@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Mohan Marimuthu, Yogesh
> <yogesh.mohan.marimu...@intel.com>; Nikula, Jani
> <jani.nik...@intel.com>
> Subject: Re: [PATCH 2/2] drm/i915: GPIO for CHT generic MIPI
> 
> On Wed, Feb 24, 2016 at 07:13:46PM +0530, Deepak M wrote:
> > From: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>
> >
> > The GPIO configuration and register offsets are different from
> > baytrail for cherrytrail. Port the gpio programming accordingly for
> > cherrytrail in this patch.
> >
> > v2: Removing the duplication of parsing
> >
> > v3: Moved the macro def to panel_vbt.c file
> >
> > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > Cc: Jani Nikula <jani.nik...@intel.com>
> > Signed-off-by: Yogesh Mohan Marimuthu
> > <yogesh.mohan.marimu...@intel.com>
> > Signed-off-by: Deepak M <m.dee...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 123
> > +++--
> >  1 file changed, 98 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > index 794bd1f..6b9a1f7 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > @@ -58,6 +58,28 @@ static inline struct vbt_panel *to_vbt_panel(struct
> > drm_panel *panel)
> >
> >  #define NS_KHZ_RATIO 100
> >
> > +#define CHV_IOSF_PORT_GPIO_N 0x13
> > +#define CHV_IOSF_PORT_GPIO_SE0x48
> > +#define CHV_IOSF_PORT_GPIO_SW0xB2
> > +#define CHV_IOSF_PORT_GPIO_E 0xA8
> 
> These should have remained where the other ports were defined.
> 
> > +#define CHV_MAX_GPIO_NUM_N   72
> > +#define CHV_MAX_GPIO_NUM_SE  99
> > +#define CHV_MAX_GPIO_NUM_SW  197
> > +#define CHV_MIN_GPIO_NUM_SE  73
> > +#define CHV_MIN_GPIO_NUM_SW  100
> > +#define CHV_MIN_GPIO_NUM_E   198
> 
> I never got any explanation where the block sizes came from on VLV.
> IIRC when I checked them against configdb they didn't match the actual
> number of pins in the hardware block. And the same story continues here.
> Eg. if I check configfb the number of pins in each block is:
> N 59, SE 55, SW 56, E 24.
> 
> So I can't review this until someone explains where this stuff comes from.
> And there should probably be a comment next to the defines to remind the
> next guy who gets totally confused by this.
> 
> Also I don't like the fact that VLV and CHV are now implemented in two
> totally different ways. Can you eliminate the massive gpio table from the VLV
> code to make it more similar to this?
> 
[Deepak, M] In CHV the GPIO numberings are sequential but in VLV that is not 
the case, hence the complete table is copied here. I have attached the VLV GPIO 
mapping table which can clear your doubts. Pfa, 
> > +
> > +#define CHV_PAD_FMLY_BASE0x4400
> > +#define CHV_PAD_FMLY_SIZE0x400
> > +#define CHV_PAD_CFG_0_1_REG_SIZE 0x8
> > +#define CHV_PAD_CFG_REG_SIZE 0x4
> > +#define CHV_VBT_MAX_PINS_PER_FMLY15
> 
> I take it this magic 15 must be specified in some VBT spec or something?
> 
> > +
> > +#define CHV_GPIO_CFG_UNLOCK0x
> > +#define CHV_GPIO_CFG_HIZ   0x8100
> 
> That's not really hi-z is it? It's GPO mode actually w/ txstate=0.
> I would suggest adding separate defines for each bit so it's easier to see 
> what
> is really set and what isn't.
> 
> > +#define CHV_GPIO_CFG_TX_STATE_SHIFT1
> 
> Could be something like
> #define CHV_GPIO_CFG0_TX_STATE(state) ((state) << 1)
> 
> > +
> > +
> >  #define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
> >  #define VLV_HV_DDI0_HPD_GPIONC_0_PAD0x4138
> >  #define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
> > @@ -685,34 +707,13 @@ static const u8 *mipi_exec_delay(struct intel_dsi
> *intel_dsi, const u8 *data)
> > return data;
> >  }
> >
> > -static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8
> > *data)
> > +void vlv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8
> > +action)
> >  {

[Intel-gfx] [PATCH 1/2] drm/i915/dsi: Added the generic gpio sequence support and gpio table

2016-02-24 Thread Deepak M

The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.

v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)

v3 by Jani
- rebase on previous patches
- don't return null on errors

v4 by Deepak
- rebase
- prefixed the VLV_ to all the GPIO macros

v5 by deepak
- readded the checks which were removed in the
  earlier patchset (Jani)

Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h|   6 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 592 ++---
 2 files changed, 555 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3774870..606dc71 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   IOSF_PORT_FLISDSI0x1b
 #define   IOSF_PORT_GPIO_SC0x48
 #define   IOSF_PORT_GPIO_SUS   0xa8
+#define   IOSF_MAX_GPIO_NUM_NC 26
+#define   IOSF_MAX_GPIO_NUM_SC 128
+#define   IOSF_MAX_GPIO_NUM172
 #define   IOSF_PORT_CCU0xa9
 #define VLV_IOSF_DATA  _MMIO(VLV_DISPLAY_BASE + 0x2104)
 #define VLV_IOSF_ADDR  _MMIO(VLV_DISPLAY_BASE + 0x2108)
 
+#define VLV_GPIO_CFG   0x2000CC00
+#define VLV_GPIO_INPUT_DIS 0x04
+
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC0x11
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 787f01c..794bd1f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -58,30 +58,356 @@ static inline struct vbt_panel *to_vbt_panel(struct 
drm_panel *panel)
 
 #define NS_KHZ_RATIO 100
 
-#define GPI0_NC_0_HV_DDI0_HPD   0x4130
-#define GPIO_NC_0_HV_DDI0_PAD   0x4138
-#define GPIO_NC_1_HV_DDI0_DDC_SDA   0x4120
-#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
-#define GPIO_NC_2_HV_DDI0_DDC_SCL   0x4110
-#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
-#define GPIO_NC_3_PANEL0_VDDEN  0x4140
-#define GPIO_NC_3_PANEL0_VDDEN_PAD  0x4148
-#define GPIO_NC_4_PANEL0_BLKEN  0x4150
-#define GPIO_NC_4_PANEL0_BLKEN_PAD  0x4158
-#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
-#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
-#define GPIO_NC_6_PCONF00x4180
-#define GPIO_NC_6_PAD   0x4188
-#define GPIO_NC_7_PCONF00x4190
-#define GPIO_NC_7_PAD   0x4198
-#define GPIO_NC_8_PCONF00x4170
-#define GPIO_NC_8_PAD   0x4178
-#define GPIO_NC_9_PCONF00x4100
-#define GPIO_NC_9_PAD   0x4108
-#define GPIO_NC_10_PCONF0   0x40E0
-#define GPIO_NC_10_PAD  0x40E8
-#define GPIO_NC_11_PCONF0   0x40F0
-#define GPIO_NC_11_PAD  0x40F8
+#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
+#define VLV_HV_DDI0_HPD_GPIONC_0_PAD0x4138
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD0x4128
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD0x4118
+#define VLV_PANEL0_VDDEN_GPIONC_3_PCONF00x4140
+#define VLV_PANEL0_VDDEN_GPIONC_3_PAD   0x4148
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0   0x4150
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PAD  0x4158
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0  0x4160
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
+#define VLV_HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
+#define VLV_HV_DDI1_HPD_GPIONC_6_PAD0x4188
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD0x4198
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD0x4178
+#define VLV_PANEL1_VDDEN_GPIONC_9_PCONF00x4100
+#define VLV_PANEL1_VDDEN_GPIONC_9_PAD   0x4108
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0  0x40E0
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PAD0x40F8
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF00x40C0
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD   0x40C8
+#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0

[Intel-gfx] [PATCH 2/2] drm/i915: GPIO for CHT generic MIPI

2016-02-24 Thread Deepak M

From: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>

The GPIO configuration and register offsets are different from
baytrail for cherrytrail. Port the gpio programming accordingly
for cherrytrail in this patch.

v2: Removing the duplication of parsing

v3: Moved the macro def to panel_vbt.c file

Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 123 +++--
 1 file changed, 98 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 794bd1f..6b9a1f7 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -58,6 +58,28 @@ static inline struct vbt_panel *to_vbt_panel(struct 
drm_panel *panel)
 
 #define NS_KHZ_RATIO 100
 
+#define CHV_IOSF_PORT_GPIO_N 0x13
+#define CHV_IOSF_PORT_GPIO_SE0x48
+#define CHV_IOSF_PORT_GPIO_SW0xB2
+#define CHV_IOSF_PORT_GPIO_E 0xA8
+#define CHV_MAX_GPIO_NUM_N   72
+#define CHV_MAX_GPIO_NUM_SE  99
+#define CHV_MAX_GPIO_NUM_SW  197
+#define CHV_MIN_GPIO_NUM_SE  73
+#define CHV_MIN_GPIO_NUM_SW  100
+#define CHV_MIN_GPIO_NUM_E   198
+
+#define CHV_PAD_FMLY_BASE0x4400
+#define CHV_PAD_FMLY_SIZE0x400
+#define CHV_PAD_CFG_0_1_REG_SIZE 0x8
+#define CHV_PAD_CFG_REG_SIZE 0x4
+#define CHV_VBT_MAX_PINS_PER_FMLY15
+
+#define CHV_GPIO_CFG_UNLOCK0x
+#define CHV_GPIO_CFG_HIZ   0x8100
+#define CHV_GPIO_CFG_TX_STATE_SHIFT1
+
+
 #define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
 #define VLV_HV_DDI0_HPD_GPIONC_0_PAD0x4138
 #define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
@@ -685,34 +707,13 @@ static const u8 *mipi_exec_delay(struct intel_dsi 
*intel_dsi, const u8 *data)
return data;
 }
 
-static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+void vlv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
 {
-   u8 gpio, action;
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
u16 function, pad;
u32 val;
u8 port;
-   struct drm_device *dev = intel_dsi->base.base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-
-   DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
-
-   if (dev_priv->vbt.dsi.seq_version >= 3)
-   data++;
-
-   gpio = *data++;
-
-   /* pull up/down */
-   action = *data++ & 1;
-
-   if (gpio >= ARRAY_SIZE(gtable)) {
-   DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
-   goto out;
-   }
-
-   if (!IS_VALLEYVIEW(dev_priv)) {
-   DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
-   goto out;
-   }
 
if (dev_priv->vbt.dsi.seq_version >= 3) {
if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
@@ -728,7 +729,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
port = IOSF_PORT_GPIO_SUS;
} else {
DRM_ERROR("GPIO number is not present in the table\n");
-   goto out;
+   return;
}
} else {
port = IOSF_PORT_GPIO_NC;
@@ -750,6 +751,78 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
/* pull up/down */
vlv_iosf_sb_write(dev_priv, port, pad, val);
mutex_unlock(_priv->sb_lock);
+}
+
+void chv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
+{
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   u16 function, pad;
+   u16 family_num;
+   u8 block;
+
+   if (dev_priv->vbt.dsi.seq_version >= 3) {
+   if (gpio <= CHV_MAX_GPIO_NUM_N) {
+   block = CHV_IOSF_PORT_GPIO_N;
+   DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
+   } else if (gpio <= CHV_MAX_GPIO_NUM_SE) {
+   block = CHV_IOSF_PORT_GPIO_SE;
+   gpio = gpio - CHV_MIN_GPIO_NUM_SE;
+   DRM_DEBUG_DRIVER("GPIO is in the south east Block\n");
+   } else if (gpio <= CHV_MAX_GPIO_NUM_SW) {
+   block = CHV_IOSF_PORT_GPIO_SW;
+

[Intel-gfx] [GPIO PATCH 2/2] drm/i915: GPIO for BXT generic MIPI

2016-02-22 Thread Deepak M

From: Uma Shankar <uma.shan...@intel.com>

Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.

v2 by Deepak
  - Added the GPIO table got BXT.
  - Added gpio_free

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 662 -
 1 file changed, 657 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 4849515..4fcc755 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -593,6 +594,634 @@ static struct gpio_table gtable[] = {
{ VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, 
VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
 };
 
+struct bxt_gpio_table {
+   u16 gpio_pin;
+   u16 offset;
+};
+
+#define  BXT_HV_DDI0_DDC_SDA_PIN187
+#define  BXT_HV_DDI0_DDC_SCL_PIN188
+#define  BXT_HV_DDI1_DDC_SDA_PIN189
+#define  BXT_HV_DDI1_DDC_SCL_PIN190
+#define  BXT_DBI_SDA_PIN191
+#define  BXT_DBI_SCL_PIN192
+#define  BXT_PANEL0_VDDEN_PIN   193
+#define  BXT_PANEL0_BKLTEN_PIN  194
+#define  BXT_PANEL0_BKLTCTL_PIN 195
+#define  BXT_PANEL1_VDDEN_PIN   196
+#define  BXT_PANEL1_BKLTEN_PIN  197
+#define  BXT_PANEL1_BKLTCTL_PIN 198
+#define  BXT_DBI_CSX_PIN199
+#define  BXT_DBI_RESX_PIN   200
+#define  BXT_GP_INTD_DSI_TE1_PIN201
+#define  BXT_GP_INTD_DSI_TE2_PIN202
+#define  BXT_USB_OC0_B_PIN  203
+#define  BXT_USB_OC1_B_PIN  204
+#define  BXT_MEX_WAKE0_B_PIN205
+#define  BXT_MEX_WAKE1_B_PIN206
+#define  BXT_EMMC0_CLK_PIN  156
+#define  BXT_EMMC0_D0_PIN   157
+#define  BXT_EMMC0_D1_PIN   158
+#define  BXT_EMMC0_D2_PIN   159
+#define  BXT_EMMC0_D3_PIN   160
+#define  BXT_EMMC0_D4_PIN   161
+#define  BXT_EMMC0_D5_PIN   162
+#define  BXT_EMMC0_D6_PIN   163
+#define  BXT_EMMC0_D7_PIN   164
+#define  BXT_EMMC0_CMD_PIN  165
+#define  BXT_SDIO_CLK_PIN   166
+#define  BXT_SDIO_D0_PIN167
+#define  BXT_SDIO_D1_PIN168
+#define  BXT_SDIO_D2_PIN169
+#define  BXT_SDIO_D3_PIN170
+#define  BXT_SDIO_CMD_PIN   171
+#define  BXT_SDCARD_CLK_PIN 172
+#define  BXT_SDCARD_D0_PIN  173
+#define  BXT_SDCARD_D1_PIN  174
+#define  BXT_SDCARD_D2_PIN  175
+#define  BXT_SDCARD_D3_PIN  176
+#define  BXT_SDCARD_CD_B_PIN177
+#define  BXT_SDCARD_CMD_PIN 178
+#define  BXT_SDCARD_LVL_CLK_FB_PIN  179
+#define  BXT_SDCARD_LVL_CMD_DIR_PIN 180
+#define  BXT_SDCARD_LVL_DAT_DIR_PIN 181
+#define  BXT_EMMC0_STROBE_PIN   182
+#define  BXT_SDIO_PWR_DOWN_B_PIN183
+#define  BXT_SDCARD_PWR_DOWN_B_PIN  184
+#define  BXT_SDCARD_LVL_SEL_PIN 185
+#define  BXT_SDCARD_LVL_WP_PIN  186
+#define  BXT_LPSS_I2C0_SDA_PIN  124
+#define  BXT_LPSS_I2C0_SCL_PIN  125
+#define  BXT_LPSS_I2C1_SDA_PIN  126
+#define  BXT_LPSS_I2C1_SCL_PIN  127
+#define  BXT_LPSS_I2C2_SDA_PIN  128
+#define  BXT_LPSS_I2C2_SCL_PIN  129
+#define  BXT_LPSS_I2C3_SDA_PIN  130
+#define  BXT_LPSS_I2C3_SCL_PIN  131
+#define  BXT_LPSS_I2C4_SDA_PIN  132
+#define  BXT_LPSS_I2C4_SCL_PIN  133
+#define  BXT_LPSS_I2C5_SDA_PIN  134
+#define  BXT_LPSS_I2C5_SCL_PIN  135
+#define  BXT_LPSS_I2C6_SDA_PIN  136
+#define  BXT_LPSS_I2C6_SCL_PIN  137
+#define  BXT_LPSS_I2C7_SDA_PIN  138
+#define  BXT_LPSS_I2C7_SCL_PIN  139
+#define  BXT_ISH_I2C0_SDA_PIN   140
+#define  BXT_ISH_I2C0_SCL_PIN   141
+#define  BXT_ISH_I2C1_SDA_PIN   142
+#define  BXT_ISH_I2C1_SCL_PIN   143
+#define  BXT_ISH_I2C2_SDA_PIN   144
+#define  BXT_ISH_I2C2_SCL_PIN   14

[Intel-gfx] [GPIO PATCH 1/2] drm/i915: GPIO for CHT generic MIPI

2016-02-22 Thread Deepak M

From: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>

The GPIO configuration and register offsets are different from
baytrail for cherrytrail. Port the gpio programming accordingly
for cherrytrail in this patch.

v2: Removing the duplication of parsing

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h|  20 ++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 107 ++---
 2 files changed, 102 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 606dc71..fc57477 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -615,6 +615,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   IOSF_PORT_NC 0x11
 #define   IOSF_PORT_DPIO   0x12
 #define   IOSF_PORT_GPIO_NC0x13
+#define   CHV_IOSF_PORT_GPIO_N 0x13
+#define   CHV_IOSF_PORT_GPIO_SE0x48
+#define   CHV_IOSF_PORT_GPIO_SW0xB2
+#define   CHV_IOSF_PORT_GPIO_E 0xA8
+#define   CHV_MAX_GPIO_NUM_N   72
+#define   CHV_MAX_GPIO_NUM_SE  99
+#define   CHV_MAX_GPIO_NUM_SW  197
+#define   CHV_MIN_GPIO_NUM_SE  73
+#define   CHV_MIN_GPIO_NUM_SW  100
+#define   CHV_MIN_GPIO_NUM_E   198
 #define   IOSF_PORT_CCK0x14
 #define   IOSF_PORT_DPIO_2 0x1a
 #define   IOSF_PORT_FLISDSI0x1b
@@ -630,6 +640,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define VLV_GPIO_CFG   0x2000CC00
 #define VLV_GPIO_INPUT_DIS 0x04
 
+#define CHV_PAD_FMLY_BASE  0x4400
+#define CHV_PAD_FMLY_SIZE  0x400
+#define CHV_PAD_CFG_0_1_REG_SIZE   0x8
+#define CHV_PAD_CFG_REG_SIZE   0x4
+#define CHV_VBT_MAX_PINS_PER_FMLY  15
+
+#define CHV_GPIO_CFG_UNLOCK0x
+#define CHV_GPIO_CFG_HIZ   0x8100
+#define CHV_GPIO_CFG_TX_STATE_SHIFT1
+
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC0x11
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 794bd1f..4849515 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -685,34 +685,13 @@ static const u8 *mipi_exec_delay(struct intel_dsi 
*intel_dsi, const u8 *data)
return data;
 }
 
-static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+void vlv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
 {
-   u8 gpio, action;
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
u16 function, pad;
u32 val;
u8 port;
-   struct drm_device *dev = intel_dsi->base.base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-
-   DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
-
-   if (dev_priv->vbt.dsi.seq_version >= 3)
-   data++;
-
-   gpio = *data++;
-
-   /* pull up/down */
-   action = *data++ & 1;
-
-   if (gpio >= ARRAY_SIZE(gtable)) {
-   DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
-   goto out;
-   }
-
-   if (!IS_VALLEYVIEW(dev_priv)) {
-   DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
-   goto out;
-   }
 
if (dev_priv->vbt.dsi.seq_version >= 3) {
if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
@@ -728,7 +707,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
port = IOSF_PORT_GPIO_SUS;
} else {
DRM_ERROR("GPIO number is not present in the table\n");
-   goto out;
+   return;
}
} else {
port = IOSF_PORT_GPIO_NC;
@@ -750,11 +729,89 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
/* pull up/down */
vlv_iosf_sb_write(dev_priv, port, pad, val);
mutex_unlock(_priv->sb_lock);
+}
+
+void chv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
+{
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   u16 function, pad;
+   u16 family_num;
+   u8 block;
+
+   if (dev_

Re: [Intel-gfx] [PATCH] drm/i915: Get the i2c bus number from the ACPI

2016-02-19 Thread Deepak, M



> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, February 19, 2016 7:38 PM
> To: Deepak, M <m.dee...@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Get the i2c bus number from the
> ACPI
> 
> On Fri, Feb 19, 2016 at 07:25:57PM +0530, Deepak M wrote:
> > Currently for executing the i2c MIPI sequence, we are relaying on the
> > i2c bus bunmber which is specified in the VBT.
> >
> > Signed-off-by: Deepak M <m.dee...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_dma.c   |  2 ++
> >  drivers/gpu/drm/i915/i915_drv.h   |  7 ++
> >  drivers/gpu/drm/i915/intel_acpi.c | 49
> > +++
> >  3 files changed, 58 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c
> > b/drivers/gpu/drm/i915/i915_dma.c index 1c6d227..8cd1d9d 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -387,6 +387,8 @@ static int i915_load_modeset_init(struct
> > drm_device *dev)
> >
> > intel_register_dsm_handler();
> >
> > +   intel_acpi_find_i2c(dev_priv);
> > +
> > ret = vga_switcheroo_register_client(dev->pdev,
> _switcheroo_ops, false);
> > if (ret)
> > goto cleanup_vga_client;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 6644c2e..6fe8b64 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -47,6 +47,7 @@
> >  #include 
> >  #include  /* for struct drm_dma_handle */  #include
> > 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -1880,6 +1881,11 @@ struct drm_i915_private {
> >
> > struct i915_workarounds workarounds;
> >
> > +   struct {
> > +   int i2c_bus_number;
> > +   int i2c_slave_address;
> > +   } acpi_data;
> 
> The naming is rather vague. i2c bus for what?
> 
> Also is one bus always enough? The VBT i2c stuff could use multiple i2c
> busses. Also how do we map this to the bus number that the VBT has?
> 
[Deepak, M] Most of the cases I have seen only one i2c being used, If there are 
multiple i2c busses used then need to check which i2c is used for what purpose 
and is there a protocol which is followed by BIOS team when more than one i2c 
bus is used.
> > +
> > /* Reclocking support */
> > bool render_reclock_avail;
> >
> > @@ -3426,6 +3432,7 @@ intel_opregion_notify_adapter(struct
> drm_device
> > *dev, pci_power_t state)  #ifdef CONFIG_ACPI  extern void
> > intel_register_dsm_handler(void);  extern void
> > intel_unregister_dsm_handler(void);
> > +extern acpi_status intel_acpi_find_i2c(struct drm_i915_private
> > +*dev_priv);
> >  #else
> >  static inline void intel_register_dsm_handler(void) { return; }
> > static inline void intel_unregister_dsm_handler(void) { return; } diff
> > --git a/drivers/gpu/drm/i915/intel_acpi.c
> > b/drivers/gpu/drm/i915/intel_acpi.c
> > index eb638a1..f62be5c 100644
> > --- a/drivers/gpu/drm/i915/intel_acpi.c
> > +++ b/drivers/gpu/drm/i915/intel_acpi.c
> > @@ -110,6 +110,55 @@ static void intel_dsm_platform_mux_info(void)
> > ACPI_FREE(pkg);
> >  }
> >
> > +static int i2c_acpi_get_name(struct acpi_resource *ares, void *data)
> > +{
> > +   struct drm_i915_private *dev_priv = data;
> > +   struct acpi_resource_i2c_serialbus *sb;
> > +   unsigned int val;
> > +   char *resource;
> > +   int error;
> > +
> > +   if (ares->type == ACPI_RESOURCE_TYPE_SERIAL_BUS) {
> > +   sb = >data.i2c_serial_bus;
> > +
> > +   if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) {
> > +   resource = sb->resource_source.string_ptr;
> > +   resource = strstr(resource, "I2C");
> > +   error = kstrtouint(resource+3, 0, );
> > +   if (error)
> > +   return error;
> > +   dev_priv->acpi_data.i2c_bus_number = val;
> > +   dev_priv->acpi_data.i2c_slave_address =
> > +   sb->slave_address;
> > +   }
> > +   }
> > +   return 1;
> > +}
> > +
> > +acpi_status intel_acpi_find_i2c(struct drm_i915_private *dev_priv) {
> > +   struct pci_dev *pdev = dev_priv->dev->pdev;
> > +   struct list_head r

Re: [Intel-gfx] [PATCH] drm/i915: Get the i2c bus number from the ACPI

2016-02-19 Thread Deepak, M

This patch reads the i2c bus number from the _CRS table of the display module 
of the ACPI, which will be updated by the BIOS with the i2c info which is used 
for this module.

> -Original Message-
> From: Deepak, M
> Sent: Friday, February 19, 2016 7:26 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Deepak, M <m.dee...@intel.com>
> Subject: [PATCH] drm/i915: Get the i2c bus number from the ACPI
> 
> Currently for executing the i2c MIPI sequence, we are relaying on the i2c bus
> bunmber which is specified in the VBT.
> 
> Signed-off-by: Deepak M <m.dee...@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c   |  2 ++
>  drivers/gpu/drm/i915/i915_drv.h   |  7 ++
>  drivers/gpu/drm/i915/intel_acpi.c | 49
> +++
>  3 files changed, 58 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c
> b/drivers/gpu/drm/i915/i915_dma.c index 1c6d227..8cd1d9d 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -387,6 +387,8 @@ static int i915_load_modeset_init(struct drm_device
> *dev)
> 
>   intel_register_dsm_handler();
> 
> + intel_acpi_find_i2c(dev_priv);
> +
>   ret = vga_switcheroo_register_client(dev->pdev,
> _switcheroo_ops, false);
>   if (ret)
>   goto cleanup_vga_client;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 6644c2e..6fe8b64 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -47,6 +47,7 @@
>  #include 
>  #include  /* for struct drm_dma_handle */  #include
> 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -1880,6 +1881,11 @@ struct drm_i915_private {
> 
>   struct i915_workarounds workarounds;
> 
> + struct {
> + int i2c_bus_number;
> + int i2c_slave_address;
> + } acpi_data;
> +
>   /* Reclocking support */
>   bool render_reclock_avail;
> 
> @@ -3426,6 +3432,7 @@ intel_opregion_notify_adapter(struct drm_device
> *dev, pci_power_t state)  #ifdef CONFIG_ACPI  extern void
> intel_register_dsm_handler(void);  extern void
> intel_unregister_dsm_handler(void);
> +extern acpi_status intel_acpi_find_i2c(struct drm_i915_private
> +*dev_priv);
>  #else
>  static inline void intel_register_dsm_handler(void) { return; }  static 
> inline
> void intel_unregister_dsm_handler(void) { return; } diff --git
> a/drivers/gpu/drm/i915/intel_acpi.c b/drivers/gpu/drm/i915/intel_acpi.c
> index eb638a1..f62be5c 100644
> --- a/drivers/gpu/drm/i915/intel_acpi.c
> +++ b/drivers/gpu/drm/i915/intel_acpi.c
> @@ -110,6 +110,55 @@ static void intel_dsm_platform_mux_info(void)
>   ACPI_FREE(pkg);
>  }
> 
> +static int i2c_acpi_get_name(struct acpi_resource *ares, void *data) {
> + struct drm_i915_private *dev_priv = data;
> + struct acpi_resource_i2c_serialbus *sb;
> + unsigned int val;
> + char *resource;
> + int error;
> +
> + if (ares->type == ACPI_RESOURCE_TYPE_SERIAL_BUS) {
> + sb = >data.i2c_serial_bus;
> +
> + if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) {
> + resource = sb->resource_source.string_ptr;
> + resource = strstr(resource, "I2C");
> + error = kstrtouint(resource+3, 0, );
> + if (error)
> + return error;
> + dev_priv->acpi_data.i2c_bus_number = val;
> + dev_priv->acpi_data.i2c_slave_address =
> + sb->slave_address;
> + }
> + }
> + return 1;
> +}
> +
> +acpi_status intel_acpi_find_i2c(struct drm_i915_private *dev_priv) {
> + struct pci_dev *pdev = dev_priv->dev->pdev;
> + struct list_head resource_list;
> + struct acpi_device *adev;
> + acpi_handle dhandle;
> +
> + dhandle = ACPI_HANDLE(>dev);
> + if (!dhandle)
> + return false;
> +
> + if (acpi_bus_get_device(dhandle, ))
> + return AE_OK;
> + if (acpi_bus_get_status(adev) || !adev->status.present)
> + return AE_OK;
> +
> + INIT_LIST_HEAD(_list);
> + acpi_dev_get_resources(adev, _list,
> + i2c_acpi_get_name, dev_priv);
> + acpi_dev_free_resource_list(_list);
> +
> + return AE_OK;
> +}
> +
>  static bool intel_dsm_pci_probe(struct pci_dev *pdev)  {
>   acpi_handle dhandle;
> --
> 1.9.1

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[Intel-gfx] [PATCH] drm/i915: Get the i2c bus number from the ACPI

2016-02-19 Thread Deepak M

Currently for executing the i2c MIPI sequence, we are
relaying on the i2c bus bunmber which is specified in the
VBT.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c   |  2 ++
 drivers/gpu/drm/i915/i915_drv.h   |  7 ++
 drivers/gpu/drm/i915/intel_acpi.c | 49 +++
 3 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 1c6d227..8cd1d9d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -387,6 +387,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
 
intel_register_dsm_handler();
 
+   intel_acpi_find_i2c(dev_priv);
+
ret = vga_switcheroo_register_client(dev->pdev, _switcheroo_ops, 
false);
if (ret)
goto cleanup_vga_client;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6644c2e..6fe8b64 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -47,6 +47,7 @@
 #include 
 #include  /* for struct drm_dma_handle */
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1880,6 +1881,11 @@ struct drm_i915_private {
 
struct i915_workarounds workarounds;
 
+   struct {
+   int i2c_bus_number;
+   int i2c_slave_address;
+   } acpi_data;
+
/* Reclocking support */
bool render_reclock_avail;
 
@@ -3426,6 +3432,7 @@ intel_opregion_notify_adapter(struct drm_device *dev, 
pci_power_t state)
 #ifdef CONFIG_ACPI
 extern void intel_register_dsm_handler(void);
 extern void intel_unregister_dsm_handler(void);
+extern acpi_status intel_acpi_find_i2c(struct drm_i915_private *dev_priv);
 #else
 static inline void intel_register_dsm_handler(void) { return; }
 static inline void intel_unregister_dsm_handler(void) { return; }
diff --git a/drivers/gpu/drm/i915/intel_acpi.c 
b/drivers/gpu/drm/i915/intel_acpi.c
index eb638a1..f62be5c 100644
--- a/drivers/gpu/drm/i915/intel_acpi.c
+++ b/drivers/gpu/drm/i915/intel_acpi.c
@@ -110,6 +110,55 @@ static void intel_dsm_platform_mux_info(void)
ACPI_FREE(pkg);
 }
 
+static int i2c_acpi_get_name(struct acpi_resource *ares, void *data)
+{
+   struct drm_i915_private *dev_priv = data;
+   struct acpi_resource_i2c_serialbus *sb;
+   unsigned int val;
+   char *resource;
+   int error;
+
+   if (ares->type == ACPI_RESOURCE_TYPE_SERIAL_BUS) {
+   sb = >data.i2c_serial_bus;
+
+   if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) {
+   resource = sb->resource_source.string_ptr;
+   resource = strstr(resource, "I2C");
+   error = kstrtouint(resource+3, 0, );
+   if (error)
+   return error;
+   dev_priv->acpi_data.i2c_bus_number = val;
+   dev_priv->acpi_data.i2c_slave_address =
+   sb->slave_address;
+   }
+   }
+   return 1;
+}
+
+acpi_status intel_acpi_find_i2c(struct drm_i915_private *dev_priv)
+{
+   struct pci_dev *pdev = dev_priv->dev->pdev;
+   struct list_head resource_list;
+   struct acpi_device *adev;
+   acpi_handle dhandle;
+
+   dhandle = ACPI_HANDLE(>dev);
+   if (!dhandle)
+   return false;
+
+   if (acpi_bus_get_device(dhandle, ))
+   return AE_OK;
+   if (acpi_bus_get_status(adev) || !adev->status.present)
+   return AE_OK;
+
+   INIT_LIST_HEAD(_list);
+   acpi_dev_get_resources(adev, _list,
+   i2c_acpi_get_name, dev_priv);
+   acpi_dev_free_resource_list(_list);
+
+   return AE_OK;
+}
+
 static bool intel_dsm_pci_probe(struct pci_dev *pdev)
 {
acpi_handle dhandle;
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/dsi: Added the generic gpio sequence support and gpio table

2016-02-19 Thread Deepak M

The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.

v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)

v3 by Jani
- rebase on previous patches
- don't return null on errors

v4 by Deepak
- rebase
- prefixed the VLV_ to all the GPIO macros

v5 by deepak
- readded the checks which were removed in the
  earlier patchset (Jani)

Signed-off-by: Deepak M <m.dee...@intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h|   6 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 592 ++---
 2 files changed, 555 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3774870..606dc71 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   IOSF_PORT_FLISDSI0x1b
 #define   IOSF_PORT_GPIO_SC0x48
 #define   IOSF_PORT_GPIO_SUS   0xa8
+#define   IOSF_MAX_GPIO_NUM_NC 26
+#define   IOSF_MAX_GPIO_NUM_SC 128
+#define   IOSF_MAX_GPIO_NUM172
 #define   IOSF_PORT_CCU0xa9
 #define VLV_IOSF_DATA  _MMIO(VLV_DISPLAY_BASE + 0x2104)
 #define VLV_IOSF_ADDR  _MMIO(VLV_DISPLAY_BASE + 0x2108)
 
+#define VLV_GPIO_CFG   0x2000CC00
+#define VLV_GPIO_INPUT_DIS 0x04
+
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC0x11
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 787f01c..794bd1f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -58,30 +58,356 @@ static inline struct vbt_panel *to_vbt_panel(struct 
drm_panel *panel)
 
 #define NS_KHZ_RATIO 100
 
-#define GPI0_NC_0_HV_DDI0_HPD   0x4130
-#define GPIO_NC_0_HV_DDI0_PAD   0x4138
-#define GPIO_NC_1_HV_DDI0_DDC_SDA   0x4120
-#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
-#define GPIO_NC_2_HV_DDI0_DDC_SCL   0x4110
-#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
-#define GPIO_NC_3_PANEL0_VDDEN  0x4140
-#define GPIO_NC_3_PANEL0_VDDEN_PAD  0x4148
-#define GPIO_NC_4_PANEL0_BLKEN  0x4150
-#define GPIO_NC_4_PANEL0_BLKEN_PAD  0x4158
-#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
-#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
-#define GPIO_NC_6_PCONF00x4180
-#define GPIO_NC_6_PAD   0x4188
-#define GPIO_NC_7_PCONF00x4190
-#define GPIO_NC_7_PAD   0x4198
-#define GPIO_NC_8_PCONF00x4170
-#define GPIO_NC_8_PAD   0x4178
-#define GPIO_NC_9_PCONF00x4100
-#define GPIO_NC_9_PAD   0x4108
-#define GPIO_NC_10_PCONF0   0x40E0
-#define GPIO_NC_10_PAD  0x40E8
-#define GPIO_NC_11_PCONF0   0x40F0
-#define GPIO_NC_11_PAD  0x40F8
+#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
+#define VLV_HV_DDI0_HPD_GPIONC_0_PAD0x4138
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD0x4128
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD0x4118
+#define VLV_PANEL0_VDDEN_GPIONC_3_PCONF00x4140
+#define VLV_PANEL0_VDDEN_GPIONC_3_PAD   0x4148
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0   0x4150
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PAD  0x4158
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0  0x4160
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
+#define VLV_HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
+#define VLV_HV_DDI1_HPD_GPIONC_6_PAD0x4188
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD0x4198
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD0x4178
+#define VLV_PANEL1_VDDEN_GPIONC_9_PCONF00x4100
+#define VLV_PANEL1_VDDEN_GPIONC_9_PAD   0x4108
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0  0x40E0
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PAD0x40F8
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF00x40C0
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD   0x40C8
+#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF00x41A0
+#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD   0x4

Re: [Intel-gfx] [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table

2016-02-19 Thread Deepak, M



> -Original Message-
> From: Nikula, Jani
> Sent: Friday, February 19, 2016 6:51 PM
> To: Deepak, M <m.dee...@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deepak, M <m.dee...@intel.com>
> Subject: Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio
> sequence support and gpio table
> 
> On Fri, 19 Feb 2016, Deepak M <m.dee...@intel.com> wrote:
> > The generic gpio is sequence is parsed from the VBT and the GPIO table
> > is updated with the North core, South core and SUS core elements.
> >
> > v2: Move changes in sideband.c file to new patch(Jani), rebase
> > v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
> >
> > v3 by Jani
> > - rebase on previous patches
> > - don't return null on errors
> >
> > v4 by Deepak
> > - rebase
> > - prefixed the VLV_ to all the GPIO macros
> 
> There were also versions 4, 5 and 6 by me also. v6 is at
> 
> http://patchwork.freedesktop.org/patch/msgid/f684304ca297fd3dd325c29a
> 541b8960fe468b96.1454582914.git.jani.nik...@intel.com
> 
> You should take that as the basis.
[Deepak, M] The link points me to the i2c patch not the gpio one.
> 
> Also see comments inline.
> 
> > Signed-off-by: Deepak M <m.dee...@intel.com>
> > Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h|   6 +
> >  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 606
> > ++---
> >  2 files changed, 559 insertions(+), 53 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 3774870..606dc71 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t
> reg)
> >  #define   IOSF_PORT_FLISDSI0x1b
> >  #define   IOSF_PORT_GPIO_SC0x48
> >  #define   IOSF_PORT_GPIO_SUS   0xa8
> > +#define   IOSF_MAX_GPIO_NUM_NC 26
> > +#define   IOSF_MAX_GPIO_NUM_SC 128
> > +#define   IOSF_MAX_GPIO_NUM172
> >  #define   IOSF_PORT_CCU0xa9
> >  #define VLV_IOSF_DATA
>   _MMIO(VLV_DISPLAY_BASE + 0x2104)
> >  #define VLV_IOSF_ADDR
>   _MMIO(VLV_DISPLAY_BASE + 0x2108)
> >
> > +#define VLV_GPIO_CFG   0x2000CC00
> > +#define VLV_GPIO_INPUT_DIS 0x04
> > +
> >  /* See configdb bunit SB addr map */
> >  #define BUNIT_REG_BISOC0x11
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > index 787f01c..e02e5e0 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > @@ -58,30 +58,356 @@ static inline struct vbt_panel
> > *to_vbt_panel(struct drm_panel *panel)
> >
> >  #define NS_KHZ_RATIO 100
> >
> > -#define GPI0_NC_0_HV_DDI0_HPD   0x4130
> > -#define GPIO_NC_0_HV_DDI0_PAD   0x4138
> > -#define GPIO_NC_1_HV_DDI0_DDC_SDA   0x4120
> > -#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
> > -#define GPIO_NC_2_HV_DDI0_DDC_SCL   0x4110
> > -#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
> > -#define GPIO_NC_3_PANEL0_VDDEN  0x4140
> > -#define GPIO_NC_3_PANEL0_VDDEN_PAD  0x4148
> > -#define GPIO_NC_4_PANEL0_BLKEN  0x4150
> > -#define GPIO_NC_4_PANEL0_BLKEN_PAD  0x4158
> > -#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
> > -#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
> > -#define GPIO_NC_6_PCONF00x4180
> > -#define GPIO_NC_6_PAD   0x4188
> > -#define GPIO_NC_7_PCONF00x4190
> > -#define GPIO_NC_7_PAD   0x4198
> > -#define GPIO_NC_8_PCONF00x4170
> > -#define GPIO_NC_8_PAD   0x4178
> > -#define GPIO_NC_9_PCONF00x4100
> > -#define GPIO_NC_9_PAD   0x4108
> > -#define GPIO_NC_10_PCONF0   0x40E0
> > -#define GPIO_NC_10_PAD  0x40E8
> > -#define GPIO_NC_11_PCONF0   0x40F0
> > -#define GPIO_NC_11_PAD  0x40F8
> > +#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
> > +#define VLV_HV_DDI0_HPD_GPIONC_0_PAD0x4138
> > +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
> > +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PA

[Intel-gfx] [PATCH 2/2] drm/i915: Add functions to execute the new sequences from VBT

2016-02-19 Thread Deepak M

From: Gaurav K Singh <gaurav.k.si...@intel.com>

New sequences are added in the mipi sequence block of the
VBT from version 3 onwards. The sequences are added to
make the code more generic as the panel related info
are placed in the VBT.

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.ku...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 48 ++
 1 file changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index c6e18fe..db8e210 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -1035,12 +1035,60 @@ static int vbt_panel_get_modes(struct drm_panel *panel)
return 1;
 }
 
+static int vbt_panel_power_on(struct drm_panel *panel)
+{
+   generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
+
+   return 0;
+}
+
+static int vbt_panel_power_off(struct drm_panel *panel)
+{
+   generic_exec_sequence(panel, MIPI_SEQ_POWER_OFF);
+
+   return 0;
+}
+
+static int vbt_panel_backlight_on(struct drm_panel *panel)
+{
+   generic_exec_sequence(panel, MIPI_SEQ_BACKLIGHT_ON);
+
+   return 0;
+}
+
+static int vbt_panel_backlight_off(struct drm_panel *panel)
+{
+   generic_exec_sequence(panel, MIPI_SEQ_BACKLIGHT_OFF);
+
+   return 0;
+}
+
+static int vbt_panel_get_info(struct drm_panel *panel,
+   struct drm_connector *connector)
+{
+   struct intel_connector *intel_connector =
+   to_intel_connector(connector);
+
+   if (intel_connector) {
+   connector->display_info.width_mm =
+   intel_connector->panel.fixed_mode->width_mm;
+   connector->display_info.height_mm =
+   intel_connector->panel.fixed_mode->height_mm;
+   }
+   return 0;
+}
+
 static const struct drm_panel_funcs vbt_panel_funcs = {
.disable = vbt_panel_disable,
.unprepare = vbt_panel_unprepare,
.prepare = vbt_panel_prepare,
.enable = vbt_panel_enable,
.get_modes = vbt_panel_get_modes,
+   .power_on = vbt_panel_power_on,
+   .power_off = vbt_panel_power_off,
+   .backlight_on = vbt_panel_backlight_on,
+   .backlight_off = vbt_panel_backlight_off,
+   .get_info = vbt_panel_get_info,
 };
 
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
-- 
1.9.1

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[Intel-gfx] [PATCH 1/2] drm: Add few more wrapper functions for drm panel

2016-02-19 Thread Deepak M

Currently there are few pair of functions which
are called during the panel enable/disable sequence.
To improve the granularity, adding few more wrapper
functions so that the functions are more specific
on what they are doing.

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
---
 include/drm/drm_panel.h | 47 +++
 1 file changed, 47 insertions(+)

diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 13ff44b..c729f6d 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -73,6 +73,12 @@ struct drm_panel_funcs {
int (*get_modes)(struct drm_panel *panel);
int (*get_timings)(struct drm_panel *panel, unsigned int num_timings,
   struct display_timing *timings);
+   int (*power_on)(struct drm_panel *panel);
+   int (*power_off)(struct drm_panel *panel);
+   int (*backlight_on)(struct drm_panel *panel);
+   int (*backlight_off)(struct drm_panel *panel);
+   int (*get_info)(struct drm_panel *panel,
+   struct drm_connector *connector);
 };
 
 struct drm_panel {
@@ -117,6 +123,47 @@ static inline int drm_panel_enable(struct drm_panel *panel)
return panel ? -ENOSYS : -EINVAL;
 }
 
+static inline int drm_panel_power_on(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->power_on)
+   return panel->funcs->power_on(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_power_off(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->power_off)
+   return panel->funcs->power_off(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_backlight_on(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->backlight_on)
+   return panel->funcs->backlight_on(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_backlight_off(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->backlight_off)
+   return panel->funcs->backlight_off(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_get_info(struct drm_panel *panel,
+   struct drm_connector *connector)
+{
+   if (connector && panel && panel->funcs && panel->funcs->get_info)
+   return panel->funcs->get_info(panel, connector);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
 static inline int drm_panel_get_modes(struct drm_panel *panel)
 {
if (panel && panel->funcs && panel->funcs->get_modes)
-- 
1.9.1

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[Intel-gfx] [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table

2016-02-19 Thread Deepak M

The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.

v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)

v3 by Jani
- rebase on previous patches
- don't return null on errors

v4 by Deepak
- rebase
- prefixed the VLV_ to all the GPIO macros

Signed-off-by: Deepak M <m.dee...@intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h|   6 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 606 ++---
 2 files changed, 559 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3774870..606dc71 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   IOSF_PORT_FLISDSI0x1b
 #define   IOSF_PORT_GPIO_SC0x48
 #define   IOSF_PORT_GPIO_SUS   0xa8
+#define   IOSF_MAX_GPIO_NUM_NC 26
+#define   IOSF_MAX_GPIO_NUM_SC 128
+#define   IOSF_MAX_GPIO_NUM172
 #define   IOSF_PORT_CCU0xa9
 #define VLV_IOSF_DATA  _MMIO(VLV_DISPLAY_BASE + 0x2104)
 #define VLV_IOSF_ADDR  _MMIO(VLV_DISPLAY_BASE + 0x2108)
 
+#define VLV_GPIO_CFG   0x2000CC00
+#define VLV_GPIO_INPUT_DIS 0x04
+
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC0x11
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 787f01c..e02e5e0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -58,30 +58,356 @@ static inline struct vbt_panel *to_vbt_panel(struct 
drm_panel *panel)
 
 #define NS_KHZ_RATIO 100
 
-#define GPI0_NC_0_HV_DDI0_HPD   0x4130
-#define GPIO_NC_0_HV_DDI0_PAD   0x4138
-#define GPIO_NC_1_HV_DDI0_DDC_SDA   0x4120
-#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
-#define GPIO_NC_2_HV_DDI0_DDC_SCL   0x4110
-#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
-#define GPIO_NC_3_PANEL0_VDDEN  0x4140
-#define GPIO_NC_3_PANEL0_VDDEN_PAD  0x4148
-#define GPIO_NC_4_PANEL0_BLKEN  0x4150
-#define GPIO_NC_4_PANEL0_BLKEN_PAD  0x4158
-#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
-#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
-#define GPIO_NC_6_PCONF00x4180
-#define GPIO_NC_6_PAD   0x4188
-#define GPIO_NC_7_PCONF00x4190
-#define GPIO_NC_7_PAD   0x4198
-#define GPIO_NC_8_PCONF00x4170
-#define GPIO_NC_8_PAD   0x4178
-#define GPIO_NC_9_PCONF00x4100
-#define GPIO_NC_9_PAD   0x4108
-#define GPIO_NC_10_PCONF0   0x40E0
-#define GPIO_NC_10_PAD  0x40E8
-#define GPIO_NC_11_PCONF0   0x40F0
-#define GPIO_NC_11_PAD  0x40F8
+#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
+#define VLV_HV_DDI0_HPD_GPIONC_0_PAD0x4138
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
+#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD0x4128
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
+#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD0x4118
+#define VLV_PANEL0_VDDEN_GPIONC_3_PCONF00x4140
+#define VLV_PANEL0_VDDEN_GPIONC_3_PAD   0x4148
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0   0x4150
+#define VLV_PANEL0_BKLTEN_GPIONC_4_PAD  0x4158
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0  0x4160
+#define VLV_PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
+#define VLV_HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
+#define VLV_HV_DDI1_HPD_GPIONC_6_PAD0x4188
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
+#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD0x4198
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
+#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD0x4178
+#define VLV_PANEL1_VDDEN_GPIONC_9_PCONF00x4100
+#define VLV_PANEL1_VDDEN_GPIONC_9_PAD   0x4108
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0  0x40E0
+#define VLV_PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
+#define VLV_PANEL1_BKLTCTL_GPIONC_11_PAD0x40F8
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF00x40C0
+#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD   0x40C8
+#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF00x41A0
+#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD   0x41A8
+#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF00x41B0
+#define VLV_HV_DDI2_DDC_SCL_G

[Intel-gfx] [Generic GPIO patch 3/3] drm/i915: BXT GPIO support for backlight and panel control

2016-02-19 Thread Deepak M

From: Uma Shankar 

Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.

Cc: Jani Nikula 
Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 46 ++
 1 file changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 7fd1fae..c6e18fe 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -32,6 +32,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "i915_drv.h"
 #include "intel_drv.h"
@@ -593,6 +594,16 @@ static struct gpio_table gtable[] = {
{ VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, 
VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
 };
 
+struct bxt_gpio_table {
+   u16 gpio_pin;
+   u16 offset;
+};
+
+static struct bxt_gpio_table bxt_gtable[] = {
+   {0xC1, 270},
+   {0x1B, 456}
+};
+
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 {
return port ? PORT_C : PORT_A;
@@ -812,6 +823,39 @@ out:
return 0;
 }
 
+static int bxt_program_gpio(struct intel_dsi *intel_dsi,
+   const u8 *data, const u8 **cur_data)
+{
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   u8 gpio, action;
+   u16 function;
+
+   /*
+* Skipping the first byte as it is of no
+* interest for android in new version
+*/
+   if (dev_priv->vbt.dsi.seq_version >= 3)
+   data++;
+
+   gpio = *data++;
+
+   /* pull up/down */
+   action = *data++;
+   function = (bxt_gtable[0].gpio_pin == gpio) ?
+   bxt_gtable[0].offset :
+   (bxt_gtable[1].gpio_pin == gpio) ?
+   bxt_gtable[1].offset : 0;
+   if (!function)
+   return -1;
+
+   gpio_request_one(function, GPIOF_DIR_OUT, "MIPI");
+   gpio_set_value(function, action);
+
+   *cur_data = data;
+   return 0;
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
struct drm_device *dev = intel_dsi->base.base.dev;
@@ -825,6 +869,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
ret = chv_program_gpio(intel_dsi, data, );
else if (IS_VALLEYVIEW(dev))
ret = vlv_program_gpio(intel_dsi, data, );
+   else if (IS_BROXTON(dev))
+   ret = bxt_program_gpio(intel_dsi, data, );
else
DRM_ERROR("GPIO programming missing for this platform.\n");
 
-- 
1.9.1

___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [Generic GPIO patch 2/3] drm/i915: GPIO for CHT generic MIPI

2016-02-19 Thread Deepak M

From: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>

The GPIO configuration and register offsets are different from
baytrail for cherrytrail. Port the gpio programming accordingly
for cherrytrail in this patch.

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimu...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h| 20 +++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 87 +-
 2 files changed, 106 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 606dc71..fc57477 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -615,6 +615,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   IOSF_PORT_NC 0x11
 #define   IOSF_PORT_DPIO   0x12
 #define   IOSF_PORT_GPIO_NC0x13
+#define   CHV_IOSF_PORT_GPIO_N 0x13
+#define   CHV_IOSF_PORT_GPIO_SE0x48
+#define   CHV_IOSF_PORT_GPIO_SW0xB2
+#define   CHV_IOSF_PORT_GPIO_E 0xA8
+#define   CHV_MAX_GPIO_NUM_N   72
+#define   CHV_MAX_GPIO_NUM_SE  99
+#define   CHV_MAX_GPIO_NUM_SW  197
+#define   CHV_MIN_GPIO_NUM_SE  73
+#define   CHV_MIN_GPIO_NUM_SW  100
+#define   CHV_MIN_GPIO_NUM_E   198
 #define   IOSF_PORT_CCK0x14
 #define   IOSF_PORT_DPIO_2 0x1a
 #define   IOSF_PORT_FLISDSI0x1b
@@ -630,6 +640,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define VLV_GPIO_CFG   0x2000CC00
 #define VLV_GPIO_INPUT_DIS 0x04
 
+#define CHV_PAD_FMLY_BASE  0x4400
+#define CHV_PAD_FMLY_SIZE  0x400
+#define CHV_PAD_CFG_0_1_REG_SIZE   0x8
+#define CHV_PAD_CFG_REG_SIZE   0x4
+#define CHV_VBT_MAX_PINS_PER_FMLY  15
+
+#define CHV_GPIO_CFG_UNLOCK0x
+#define CHV_GPIO_CFG_HIZ   0x8100
+#define CHV_GPIO_CFG_TX_STATE_SHIFT1
+
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC0x11
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index e02e5e0..7fd1fae 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -685,7 +685,68 @@ static const u8 *mipi_exec_delay(struct intel_dsi 
*intel_dsi, const u8 *data)
return data;
 }
 
-static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+static int chv_program_gpio(struct intel_dsi *intel_dsi,
+   const u8 *data, const u8 **cur_data)
+{
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   u8 gpio, action;
+   u16 family_num;
+   u16 function, pad;
+   u8 block;
+
+   /*
+* Skipping the first byte as it is of no
+* interest for linux kernel in new VBT version
+*/
+   if (dev_priv->vbt.dsi.seq_version >= 3)
+   data++;
+
+   gpio = *data++;
+
+   /* pull up/down */
+   action = *data++;
+
+   if (dev_priv->vbt.dsi.seq_version >= 3) {
+   if (gpio <= CHV_MAX_GPIO_NUM_N) {
+   block = CHV_IOSF_PORT_GPIO_N;
+   DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
+   } else if (gpio <= CHV_MAX_GPIO_NUM_SE) {
+   block = CHV_IOSF_PORT_GPIO_SE;
+   gpio = gpio - CHV_MIN_GPIO_NUM_SE;
+   DRM_DEBUG_DRIVER("GPIO is in the south east Block\n");
+   } else if (gpio <= CHV_MAX_GPIO_NUM_SW) {
+   block = CHV_IOSF_PORT_GPIO_SW;
+   gpio = gpio - CHV_MIN_GPIO_NUM_SW;
+   DRM_DEBUG_DRIVER("GPIO is in the south west Block\n");
+   } else {
+   block = CHV_IOSF_PORT_GPIO_E;
+   gpio = gpio - CHV_MIN_GPIO_NUM_E;
+   DRM_DEBUG_DRIVER("GPIO is in the east Block\n");
+   }
+   } else
+   block = IOSF_PORT_GPIO_NC;
+
+   family_num =  gpio / CHV_VBT_MAX_PINS_PER_FMLY;
+   gpio = gpio - (family_num * CHV_VBT_MAX_PINS_PER_FMLY);
+   pad = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) +
+   (((u16)gpio) * CHV_PAD_CFG_0_1_REG_SIZE);
+   function = pad + CHV_PAD_CFG_REG_SIZE;
+
+   mutex_lock(_priv->sb_lock);
+   vlv_iosf_sb_write(dev_priv, block, function,
+

[Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards

2016-02-15 Thread Deepak M

The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.

v2: Fixing compilation warning.
v3: Retained the old Macros (Jani)

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 96 +++-
 drivers/gpu/drm/i915/intel_dsi_pll.c | 56 ++---
 2 files changed, 89 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 144586e..4e61b06 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7663,58 +7663,62 @@ enum skl_disp_power_wells {
 #define  BXT_MIPI_DIV_SHIFT(port)  \
_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
BXT_MIPI2_DIV_SHIFT)
-/* Var clock divider to generate TX source. Result must be < 39.5 M */
-#define  BXT_MIPI1_ESCLK_VAR_DIV_MASK  (0x3F << 26)
-#define  BXT_MIPI2_ESCLK_VAR_DIV_MASK  (0x3F << 10)
-#define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
-   _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
-   BXT_MIPI2_ESCLK_VAR_DIV_MASK)
-
-#define  BXT_MIPI_ESCLK_VAR_DIV(port, val) \
-   (val << BXT_MIPI_DIV_SHIFT(port))
+
 /* TX control divider to select actual TX clock output from (8x/var) */
-#define  BXT_MIPI1_TX_ESCLK_SHIFT  21
-#define  BXT_MIPI2_TX_ESCLK_SHIFT  5
+#define  BXT_MIPI1_TX_ESCLK_SHIFT  26
+#define  BXT_MIPI2_TX_ESCLK_SHIFT  10
 #define  BXT_MIPI_TX_ESCLK_SHIFT(port) \
_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
BXT_MIPI2_TX_ESCLK_SHIFT)
-#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK(3 << 21)
-#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK(3 << 5)
+#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK(0x3F << 26)
+#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK(0x3F << 10)
 #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)   \
_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
-   BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
-#define  BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
-   (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
-   (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
-   (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-/* RX control divider to select actual RX clock output from 8x*/
-#define  BXT_MIPI1_RX_ESCLK_SHIFT  19
-#define  BXT_MIPI2_RX_ESCLK_SHIFT  3
-#define  BXT_MIPI_RX_ESCLK_SHIFT(port) \
-   _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
-   BXT_MIPI2_RX_ESCLK_SHIFT)
-#define  BXT_MIPI1_RX_ESCLK_FIXDIV_MASK(3 << 19)
-#define  BXT_MIPI2_RX_ESCLK_FIXDIV_MASK(3 << 3)
-#define  BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)   \
-   (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_RX_ESCLK_8X_BY2(port)\
-   (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_RX_ESCLK_8X_BY3(port)\
-   (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_RX_ESCLK_8X_BY4(port)\
-   (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-/* BXT-A WA: Always prog DPHY dividers to 00 */
-#define  BXT_MIPI1_DPHY_DIV_SHIFT  16
-#define  BXT_MIPI2_DPHY_DIV_SHIFT  0
-#define  BXT_MIPI_DPHY_DIV_SHIFT(port) \
-   _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
-   BXT_MIPI2_DPHY_DIV_SHIFT)
-#define  BXT_MIPI_1_DPHY_DIVIDER_MASK  (3 << 16)
-#define  BXT_MIPI_2_DPHY_DIVIDER_MASK  (3 << 0)
-#define  BXT_MIPI_DPHY_DIVIDER_MASK(port)  \
-   (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
+   BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
+#define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)  \
+   ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
+/* RX upper control divider to select actual RX clock output from 8x*/
+#define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT21
+#define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT5
+#define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)   \
+   _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
+   BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
+#define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK  (3 << 21)
+#define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK  (3 &l

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards

2016-02-04 Thread Deepak, M



> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Thursday, February 4, 2016 6:29 PM
> To: Deepak, M <m.dee...@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deepak, M <m.dee...@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider
> form B0 stepping onwards
> 
> On Wed, 03 Feb 2016, Deepak M <m.dee...@intel.com> wrote:
> > The MIPI clock calculations for the addtional clock are revised from
> > B0 stepping onwards, the bit definitions have changed compared to old
> > stepping.
> >
> > v2: Fixing compilation warning.
> 
> Why did you move and rename everything when it was not needed?
> 
> BR,
> Jani.
> 
[Deepak, M] I have deleted the old macro and added the new as per the new 
definitions. With the new bit fields nothing was matching as that of the old. 
> 
> >
> > Signed-off-by: Deepak M <m.dee...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 104 +
> --
> >  drivers/gpu/drm/i915/intel_dsi_pll.c |  64 ++---
> >  2 files changed, 95 insertions(+), 73 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index c0bd691..2568f35 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
> >
> >  /* MIPI DSI registers */
> >
> > +#define  BXT_MIPI1_RX_LOWER_SHIFT  16
> > +#define  BXT_MIPI2_RX_LOWER_SHIFT  0
> > +#define  BXT_MIPI_RX_LOWER_SHIFT(port) \
> > +   _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
> > +   BXT_MIPI2_RX_LOWER_SHIFT)
> > +#define  BXT_MIPI1_RX_LOWER_DIVIDER_MASK   (3 << 16)
> > +#define  BXT_MIPI2_RX_LOWER_DIVIDER_MASK   (3 << 0)
> > +#define  BXT_MIPI_RX_LOWER_DIVIDER_MASK(port)  \
> > +   (3 << BXT_MIPI_RX_LOWER_SHIFT(port))
> > +#define  BXT_MIPI_RX_LOWER_DIVIDER(port, val)  \
> > +   ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
> > +
> > +#define  BXT_MIPI1_8X_BY3_SHIFT19
> > +#define  BXT_MIPI2_8X_BY3_SHIFT3
> > +#define  BXT_MIPI_8X_BY3_SHIFT(port)  \
> > +   _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
> > +   BXT_MIPI2_8X_BY3_SHIFT)
> > +#define  BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
> > +#define  BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
> > +#define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)\
> > +   (3 << BXT_MIPI_8X_BY3_SHIFT(port))
> > +#define  BXT_MIPI_8X_BY3_DIVIDER(port, val)\
> > +   ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
> > +
> > +#define  BXT_MIPI1_RX_UPPER_SHIFT  21
> > +#define  BXT_MIPI2_RX_UPPER_SHIFT  5
> > +#define  BXT_MIPI_RX_UPPER_SHIFT(port) \
> > +   _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
> > +   BXT_MIPI2_RX_UPPER_SHIFT)
> > +#define  BXT_MIPI1_RX_UPPER_DIVIDER_MASK   (3 << 21)
> > +#define  BXT_MIPI2_RX_UPPER_DIVIDER_MASK   (3 << 5)
> > +#define  BXT_MIPI_RX_UPPER_DIVIDER_MASK(port)  \
> > +   (3 << BXT_MIPI_RX_UPPER_SHIFT(port))
> > +#define  BXT_MIPI_RX_UPPER_DIVIDER(port, val)  \
> > +   ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port))
> > +
> > +#define  BXT_MIPI1_TX_SHIFT26
> > +#define  BXT_MIPI2_TX_SHIFT10
> > +#define  BXT_MIPI_TX_SHIFT(port)   \
> > +   _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \
> > +   BXT_MIPI2_TX_SHIFT)
> > +#define  BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26)
> > +#define  BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10)
> > +#define  BXT_MIPI_TX_DIVIDER_MASK(port)\
> > +   (0x3F << BXT_MIPI_TX_SHIFT(port))
> > +#define  BXT_MIPI_TX_DIVIDER(port, val)\
> > +   ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port))
> > +
> > +#define RX_DIVIDER_BIT_1_2 0x3
> > +#define RX_DIVIDER_BIT_3_4 0xC
> > +
> >  #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c)   /* ports A
> and C only */
> >  #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
> >
> > @@ -7650,59 +7701,6 @@ enum skl_disp_power_wells {
&g

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards

2016-02-04 Thread Deepak, M



> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Thursday, February 4, 2016 7:28 PM
> To: Deepak, M <m.dee...@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider
> form B0 stepping onwards
> 
> On Thu, 04 Feb 2016, "Deepak, M" <m.dee...@intel.com> wrote:
> >> -Original Message-
> >> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> >> Sent: Thursday, February 4, 2016 6:29 PM
> >> To: Deepak, M <m.dee...@intel.com>; intel-gfx@lists.freedesktop.org
> >> Cc: Deepak, M <m.dee...@intel.com>
> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock
> >> divider form B0 stepping onwards
> >>
> >> On Wed, 03 Feb 2016, Deepak M <m.dee...@intel.com> wrote:
> >> > The MIPI clock calculations for the addtional clock are revised
> >> > from
> >> > B0 stepping onwards, the bit definitions have changed compared to
> >> > old stepping.
> >> >
> >> > v2: Fixing compilation warning.
> >>
> >> Why did you move and rename everything when it was not needed?
> >>
> >> BR,
> >> Jani.
> >>
> > [Deepak, M] I have deleted the old macro and added the new as per the
> new definitions. With the new bit fields nothing was matching as that of the
> old.
> 
> It's not nothing. Plenty of masks and shifts matched, but you had renamed
> the defines.
> 
> Besides, please don't move the definitions where they don't belong. We also
> have the convention of specifying the bits from highest to lowest.
> 
[Deepak, M] Okay, will fix the macro`s, are there any changes required in the 
function.
> >>
> >> >
> >> > Signed-off-by: Deepak M <m.dee...@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/i915_reg.h  | 104 +-
> ---
> >> --
> >> >  drivers/gpu/drm/i915/intel_dsi_pll.c |  64 ++---
> >> >  2 files changed, 95 insertions(+), 73 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> > b/drivers/gpu/drm/i915/i915_reg.h index c0bd691..2568f35 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
> >> >
> >> >  /* MIPI DSI registers */
> >> >
> >> > +#define  BXT_MIPI1_RX_LOWER_SHIFT   16
> >> > +#define  BXT_MIPI2_RX_LOWER_SHIFT   0
> >> > +#define  BXT_MIPI_RX_LOWER_SHIFT(port)  \
> >> > +_MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
> >> > +BXT_MIPI2_RX_LOWER_SHIFT)
> >> > +#define  BXT_MIPI1_RX_LOWER_DIVIDER_MASK(3 << 16)
> >> > +#define  BXT_MIPI2_RX_LOWER_DIVIDER_MASK(3 << 0)
> >> > +#define  BXT_MIPI_RX_LOWER_DIVIDER_MASK(port)   \
> >> > +(3 << BXT_MIPI_RX_LOWER_SHIFT(port))
> >> > +#define  BXT_MIPI_RX_LOWER_DIVIDER(port, val)   \
> >> > +((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
> >> > +
> >> > +#define  BXT_MIPI1_8X_BY3_SHIFT 19
> >> > +#define  BXT_MIPI2_8X_BY3_SHIFT 3
> >> > +#define  BXT_MIPI_8X_BY3_SHIFT(port)  \
> >> > +_MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
> >> > +BXT_MIPI2_8X_BY3_SHIFT)
> >> > +#define  BXT_MIPI1_8X_BY3_DIVIDER_MASK  (3 << 19)
> >> > +#define  BXT_MIPI2_8X_BY3_DIVIDER_MASK  (3 << 3)
> >> > +#define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
> >> > +(3 << BXT_MIPI_8X_BY3_SHIFT(port))
> >> > +#define  BXT_MIPI_8X_BY3_DIVIDER(port, val) \
> >> > +((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
> >> > +
> >> > +#define  BXT_MIPI1_RX_UPPER_SHIFT   21
> >> > +#define  BXT_MIPI2_RX_UPPER_SHIFT   5
> >> > +#define  BXT_MIPI_RX_UPPER_SHIFT(port)  \
> >> > +_MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
> >> > +BXT_MIPI2_RX_UPPER_SHIFT)
> >> > +#define  BXT_MIPI1_RX_UPPER_DIVIDER_MASK(3 << 21)
> >&

[Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards

2016-02-02 Thread Deepak M

The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.

v2: Fixing compilation warning.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 104 +--
 drivers/gpu/drm/i915/intel_dsi_pll.c |  64 ++---
 2 files changed, 95 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0bd691..2568f35 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
 
 /* MIPI DSI registers */
 
+#define  BXT_MIPI1_RX_LOWER_SHIFT  16
+#define  BXT_MIPI2_RX_LOWER_SHIFT  0
+#define  BXT_MIPI_RX_LOWER_SHIFT(port) \
+   _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
+   BXT_MIPI2_RX_LOWER_SHIFT)
+#define  BXT_MIPI1_RX_LOWER_DIVIDER_MASK   (3 << 16)
+#define  BXT_MIPI2_RX_LOWER_DIVIDER_MASK   (3 << 0)
+#define  BXT_MIPI_RX_LOWER_DIVIDER_MASK(port)  \
+   (3 << BXT_MIPI_RX_LOWER_SHIFT(port))
+#define  BXT_MIPI_RX_LOWER_DIVIDER(port, val)  \
+   ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
+
+#define  BXT_MIPI1_8X_BY3_SHIFT19
+#define  BXT_MIPI2_8X_BY3_SHIFT3
+#define  BXT_MIPI_8X_BY3_SHIFT(port)  \
+   _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
+   BXT_MIPI2_8X_BY3_SHIFT)
+#define  BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
+#define  BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
+#define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)\
+   (3 << BXT_MIPI_8X_BY3_SHIFT(port))
+#define  BXT_MIPI_8X_BY3_DIVIDER(port, val)\
+   ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
+
+#define  BXT_MIPI1_RX_UPPER_SHIFT  21
+#define  BXT_MIPI2_RX_UPPER_SHIFT  5
+#define  BXT_MIPI_RX_UPPER_SHIFT(port) \
+   _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
+   BXT_MIPI2_RX_UPPER_SHIFT)
+#define  BXT_MIPI1_RX_UPPER_DIVIDER_MASK   (3 << 21)
+#define  BXT_MIPI2_RX_UPPER_DIVIDER_MASK   (3 << 5)
+#define  BXT_MIPI_RX_UPPER_DIVIDER_MASK(port)  \
+   (3 << BXT_MIPI_RX_UPPER_SHIFT(port))
+#define  BXT_MIPI_RX_UPPER_DIVIDER(port, val)  \
+   ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port))
+
+#define  BXT_MIPI1_TX_SHIFT26
+#define  BXT_MIPI2_TX_SHIFT10
+#define  BXT_MIPI_TX_SHIFT(port)   \
+   _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \
+   BXT_MIPI2_TX_SHIFT)
+#define  BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26)
+#define  BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10)
+#define  BXT_MIPI_TX_DIVIDER_MASK(port)\
+   (0x3F << BXT_MIPI_TX_SHIFT(port))
+#define  BXT_MIPI_TX_DIVIDER(port, val)\
+   ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port))
+
+#define RX_DIVIDER_BIT_1_2 0x3
+#define RX_DIVIDER_BIT_3_4 0xC
+
 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c)   /* ports A and C only */
 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
 
@@ -7650,59 +7701,6 @@ enum skl_disp_power_wells {
 #define  BXT_MIPI_DIV_SHIFT(port)  \
_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
BXT_MIPI2_DIV_SHIFT)
-/* Var clock divider to generate TX source. Result must be < 39.5 M */
-#define  BXT_MIPI1_ESCLK_VAR_DIV_MASK  (0x3F << 26)
-#define  BXT_MIPI2_ESCLK_VAR_DIV_MASK  (0x3F << 10)
-#define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
-   _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
-   BXT_MIPI2_ESCLK_VAR_DIV_MASK)
-
-#define  BXT_MIPI_ESCLK_VAR_DIV(port, val) \
-   (val << BXT_MIPI_DIV_SHIFT(port))
-/* TX control divider to select actual TX clock output from (8x/var) */
-#define  BXT_MIPI1_TX_ESCLK_SHIFT  21
-#define  BXT_MIPI2_TX_ESCLK_SHIFT  5
-#define  BXT_MIPI_TX_ESCLK_SHIFT(port) \
-   _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
-   BXT_MIPI2_TX_ESCLK_SHIFT)
-#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK(3 << 21)
-#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK(3 << 5)
-#define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)   \
-   _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
-   BXT_MIPI2_TX_ESCLK_FIXDIV_MA

[Intel-gfx] [APL PO PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards

2016-02-02 Thread Deepak M

The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 104 +--
 drivers/gpu/drm/i915/intel_dsi_pll.c |  65 +++---
 2 files changed, 96 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0bd691..2568f35 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7638,6 +7638,57 @@ enum skl_disp_power_wells {
 
 /* MIPI DSI registers */
 
+#define  BXT_MIPI1_RX_LOWER_SHIFT  16
+#define  BXT_MIPI2_RX_LOWER_SHIFT  0
+#define  BXT_MIPI_RX_LOWER_SHIFT(port) \
+   _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \
+   BXT_MIPI2_RX_LOWER_SHIFT)
+#define  BXT_MIPI1_RX_LOWER_DIVIDER_MASK   (3 << 16)
+#define  BXT_MIPI2_RX_LOWER_DIVIDER_MASK   (3 << 0)
+#define  BXT_MIPI_RX_LOWER_DIVIDER_MASK(port)  \
+   (3 << BXT_MIPI_RX_LOWER_SHIFT(port))
+#define  BXT_MIPI_RX_LOWER_DIVIDER(port, val)  \
+   ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port))
+
+#define  BXT_MIPI1_8X_BY3_SHIFT19
+#define  BXT_MIPI2_8X_BY3_SHIFT3
+#define  BXT_MIPI_8X_BY3_SHIFT(port)  \
+   _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
+   BXT_MIPI2_8X_BY3_SHIFT)
+#define  BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
+#define  BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
+#define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)\
+   (3 << BXT_MIPI_8X_BY3_SHIFT(port))
+#define  BXT_MIPI_8X_BY3_DIVIDER(port, val)\
+   ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
+
+#define  BXT_MIPI1_RX_UPPER_SHIFT  21
+#define  BXT_MIPI2_RX_UPPER_SHIFT  5
+#define  BXT_MIPI_RX_UPPER_SHIFT(port) \
+   _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \
+   BXT_MIPI2_RX_UPPER_SHIFT)
+#define  BXT_MIPI1_RX_UPPER_DIVIDER_MASK   (3 << 21)
+#define  BXT_MIPI2_RX_UPPER_DIVIDER_MASK   (3 << 5)
+#define  BXT_MIPI_RX_UPPER_DIVIDER_MASK(port)  \
+   (3 << BXT_MIPI_RX_UPPER_SHIFT(port))
+#define  BXT_MIPI_RX_UPPER_DIVIDER(port, val)  \
+   ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port))
+
+#define  BXT_MIPI1_TX_SHIFT26
+#define  BXT_MIPI2_TX_SHIFT10
+#define  BXT_MIPI_TX_SHIFT(port)   \
+   _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \
+   BXT_MIPI2_TX_SHIFT)
+#define  BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26)
+#define  BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10)
+#define  BXT_MIPI_TX_DIVIDER_MASK(port)\
+   (0x3F << BXT_MIPI_TX_SHIFT(port))
+#define  BXT_MIPI_TX_DIVIDER(port, val)\
+   ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port))
+
+#define RX_DIVIDER_BIT_1_2 0x3
+#define RX_DIVIDER_BIT_3_4 0xC
+
 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c)   /* ports A and C only */
 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
 
@@ -7650,59 +7701,6 @@ enum skl_disp_power_wells {
 #define  BXT_MIPI_DIV_SHIFT(port)  \
_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
BXT_MIPI2_DIV_SHIFT)
-/* Var clock divider to generate TX source. Result must be < 39.5 M */
-#define  BXT_MIPI1_ESCLK_VAR_DIV_MASK  (0x3F << 26)
-#define  BXT_MIPI2_ESCLK_VAR_DIV_MASK  (0x3F << 10)
-#define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
-   _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
-   BXT_MIPI2_ESCLK_VAR_DIV_MASK)
-
-#define  BXT_MIPI_ESCLK_VAR_DIV(port, val) \
-   (val << BXT_MIPI_DIV_SHIFT(port))
-/* TX control divider to select actual TX clock output from (8x/var) */
-#define  BXT_MIPI1_TX_ESCLK_SHIFT  21
-#define  BXT_MIPI2_TX_ESCLK_SHIFT  5
-#define  BXT_MIPI_TX_ESCLK_SHIFT(port) \
-   _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
-   BXT_MIPI2_TX_ESCLK_SHIFT)
-#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK(3 << 21)
-#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK(3 << 5)
-#define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)   \
-   _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
-   BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
-#define  BXT_MIPI_TX_ES

[Intel-gfx] [PATCH] drm/i915: Parsing VBT if size of VBT exceeds 6KB

2015-12-13 Thread Deepak M

Currently the iomap for VBT works only if the size of the
VBT is less than 6KB, but if the size of the VBT exceeds
6KB than the physical address and the size of the VBT to
be iomapped is specified in the mailbox3 and is iomapped
accordingly.

v3: -Splitted the patch into small ones
-Handeled memory unmap in intel_opregion_fini
-removed the new file created for opregion macro`s
v4: Moving the vbt assignment after the opregion fields are assigned

Cc: Mika Kahola <mika.kah...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---

 drivers/gpu/drm/i915/intel_opregion.c | 47 +--
 1 file changed, 34 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index 7908a1d..5116690 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -856,6 +856,8 @@ void intel_opregion_fini(struct drm_device *dev)
}
 
/* just clear all opregion memory pointers now */
+   if (opregion->header->opregion_ver >= 2 && opregion->asle->rvda)
+   memunmap(opregion->vbt);
memunmap(opregion->header);
opregion->header = NULL;
opregion->acpi = NULL;
@@ -933,7 +935,8 @@ int intel_opregion_setup(struct drm_device *dev)
char buf[sizeof(OPREGION_SIGNATURE)];
const struct vbt_header *vbt = NULL;
int err = 0;
-   void *base;
+   void *base, *vbt_base;
+   size_t size;
 
BUILD_BUG_ON(sizeof(struct opregion_header) != 0x100);
BUILD_BUG_ON(sizeof(struct opregion_acpi) != 0x100);
@@ -963,19 +966,7 @@ int intel_opregion_setup(struct drm_device *dev)
goto err_out;
}
 
-   vbt = validate_vbt(base + OPREGION_VBT_OFFSET,
-   MAILBOX_4_SIZE, "OpRegion");
-
-   if (vbt == NULL) {
-   err = -EINVAL;
-   goto err_out;
-   }
-
-   vbt = (const struct vbt_header *)(base + OPREGION_VBT_OFFSET);
-   dev_priv->opregion.vbt_size = vbt->vbt_size;
-
opregion->header = base;
-   opregion->vbt = base + OPREGION_VBT_OFFSET;
 
opregion->lid_state = base + ACPI_CLID;
opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
@@ -998,6 +989,36 @@ int intel_opregion_setup(struct drm_device *dev)
opregion->asle->ardy = ASLE_ARDY_NOT_READY;
}
 
+   /*
+* Non-zero value in rvda field is an indication to driver that a
+* valid Raw VBT is stored in that address and driver should not refer
+* to mailbox4 for getting VBT.
+*/
+   if (opregion->header->opregion_ver >= 2 && opregion->asle->rvda) {
+   size = opregion->asle->rvds;
+   vbt_base = memremap(opregion->asle->rvda,
+   size, MEMREMAP_WB);
+   } else {
+   size = MAILBOX_4_SIZE;
+   vbt_base = base + OPREGION_VBT_OFFSET;
+   }
+
+   vbt = validate_vbt(vbt_base, size, "OpRegion");
+
+   if (vbt == NULL) {
+   err = -EINVAL;
+   goto err_out;
+   }
+
+   /* Assigning the vbt_size based on the VBT location */
+   if (opregion->header->opregion_ver >= 2 && opregion->asle->rvda)
+   dev_priv->opregion.vbt_size = opregion->asle->rvds;
+   else {
+   vbt = (const struct vbt_header *)(base + OPREGION_VBT_OFFSET);
+   dev_priv->opregion.vbt_size = vbt->vbt_size;
+   }
+
+   opregion->vbt = vbt_base;
return 0;
 
 err_out:
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915: dual link pipe selection for bxt

2015-12-09 Thread Deepak M

Pipe is assigned based on the port, but it should be
based on current crtc. Correcting the same in this patch.

v2: Use macro BXT_PIPE_SELECT(pipe) (Daniel)

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 +---
 drivers/gpu/drm/i915/intel_dsi.c | 15 +++
 2 files changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa72be9..91dbb32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8103,9 +8103,7 @@ enum skl_disp_power_wells {
 #define  RGB_FLIP_TO_BGR   (1 << 2)
 
 #define  BXT_PIPE_SELECT_MASK  (7 << 7)
-#define  BXT_PIPE_SELECT_C (2 << 7)
-#define  BXT_PIPE_SELECT_B (1 << 7)
-#define  BXT_PIPE_SELECT_A (0 << 7)
+#define  BXT_PIPE_SELECT(pipe) ((pipe) << 7)
 
 /* BXT has dual link Z inversion overlap field */
 #define  BXT_PIXEL_OVERLAP_CNT_MASK(0xf << 10)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index f5df49b..12cfcf5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder 
*intel_encoder)
I915_WRITE(MIPI_CTRL(port), tmp |
READ_REQUEST_PRIORITY_HIGH);
} else if (IS_BROXTON(dev)) {
-   /*
-* FIXME:
-* BXT can connect any PIPE to any MIPI port.
-* Select the pipe based on the MIPI port read from
-* VBT for now. Pick PIPE A for MIPI port A and C
-* for port C.
-*/
+   enum pipe pipe = intel_crtc->pipe;
+
tmp = I915_READ(MIPI_CTRL(port));
tmp &= ~BXT_PIPE_SELECT_MASK;
 
-   if (port == PORT_A)
-   tmp |= BXT_PIPE_SELECT_A;
-   else if (port == PORT_C)
-   tmp |= BXT_PIPE_SELECT_C;
-
+   tmp |= BXT_PIPE_SELECT(pipe);
I915_WRITE(MIPI_CTRL(port), tmp);
}
 
-- 
1.9.1

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Re: [Intel-gfx] [BXT MIPI PATCH 2/2] drm/i915: dual link pipe selection for bxt

2015-12-09 Thread Deepak, M



> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Wednesday, December 9, 2015 1:50 PM
> To: Deepak, M <m.dee...@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [BXT MIPI PATCH 2/2] drm/i915: dual link pipe
> selection for bxt
> 
> On Wed, Dec 09, 2015 at 05:29:58PM +0530, Deepak M wrote:
> > Pipe is assigned based on the port, but it should be based on current
> > crtc. Correcting the same in this patch.
> >
> > Signed-off-by: Deepak M <m.dee...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c | 23 ++-
> >  1 file changed, 14 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index f5df49b..0654b33 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -898,20 +898,25 @@ static void intel_dsi_prepare(struct intel_encoder
> *intel_encoder)
> > I915_WRITE(MIPI_CTRL(port), tmp |
> > READ_REQUEST_PRIORITY_HIGH);
> > } else if (IS_BROXTON(dev)) {
> > -   /*
> > -* FIXME:
> > -* BXT can connect any PIPE to any MIPI port.
> > -* Select the pipe based on the MIPI port read from
> > -* VBT for now. Pick PIPE A for MIPI port A and C
> > -* for port C.
> > -*/
> > +   enum pipe pipe = intel_crtc->pipe;
> > +
> > tmp = I915_READ(MIPI_CTRL(port));
> > tmp &= ~BXT_PIPE_SELECT_MASK;
> >
> > -   if (port == PORT_A)
> > +   switch (pipe) {
> > +   case PIPE_A:
> > tmp |= BXT_PIPE_SELECT_A;
> > -   else if (port == PORT_C)
> > +   break;
> > +   case PIPE_B:
> > +   tmp |= BXT_PIPE_SELECT_B;
> > +   break;
> > +   case PIPE_C:
> > tmp |= BXT_PIPE_SELECT_C;
> 
> Please create a BXT_PIPE_SELECT(pipe) macro like we have for all the other
> outputs that support more than 1 pipe selection bit. See e.g.
> DP_PIPE_SELECT_CHV.
> -Daniel
> 
[Deepak, M] Agreed,  Have tried to address this comment 
http://lists.freedesktop.org/archives/intel-gfx/2015-December/082431.html 
> > +   break;
> > +   default:
> > +   DRM_ERROR("Unknown pipe used\n");
> > +   return;
> > +   }
> >
> > I915_WRITE(MIPI_CTRL(port), tmp);
> > }
> > --
> > 1.9.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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[Intel-gfx] [PATCH] drm/i915: Add DPI FIFO empty status check

2015-12-08 Thread Deepak M

From: Gaurav K Singh <gaurav.k.si...@intel.com>

Before sending TURN ON packet,check the DPI
FIFO empty status.

v2: Change in commit message
Checking for FIFO empty  only during TURN ON packet.
v3: Adding a new function for DPI FIFO empty check

Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 170ae6f..eff982b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -60,6 +60,17 @@ static void wait_for_dsi_fifo_empty(struct intel_dsi 
*intel_dsi, enum port port)
DRM_ERROR("DPI FIFOs are not empty\n");
 }
 
+static void wait_for_dpi_fifo_empty(struct intel_dsi *intel_dsi, enum port 
port)
+{
+   struct drm_encoder *encoder = _dsi->base.base;
+   struct drm_device *dev = encoder->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+
+   if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & DPI_FIFO_EMPTY)
+   == DPI_FIFO_EMPTY, 50))
+   DRM_ERROR("Timeout waiting for DPI FIFO empty\n");
+}
+
 static void write_data(struct drm_i915_private *dev_priv, u32 reg,
   const u8 *data, u32 len)
 {
@@ -443,8 +454,10 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
} else {
msleep(20); /* XXX */
-   for_each_dsi_port(port, intel_dsi->ports)
+   for_each_dsi_port(port, intel_dsi->ports) {
+   wait_for_dpi_fifo_empty(intel_dsi, port);
dpi_send_cmd(intel_dsi, TURN_ON, false, port);
+   }
msleep(100);
 
drm_panel_enable(intel_dsi->panel);
-- 
1.9.1

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[Intel-gfx] [BXT MIPI PATCH 1/2] drm/i915: Set the Z inversion overlap field for BXT

2015-12-08 Thread Deepak M

For broxton dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the other platforms, hence
setting the same in this patch.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 drivers/gpu/drm/i915/intel_dsi.c | 16 +---
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 009f474..fa72be9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8107,6 +8107,10 @@ enum skl_disp_power_wells {
 #define  BXT_PIPE_SELECT_B (1 << 7)
 #define  BXT_PIPE_SELECT_A (0 << 7)
 
+/* BXT has dual link Z inversion overlap field */
+#define  BXT_PIXEL_OVERLAP_CNT_MASK(0xf << 10)
+#define  BXT_PIXEL_OVERLAP_CNT_SHIFT   10
+
 #define _MIPIA_DATA_ADDRESS(dev_priv->mipi_mmio_base + 0xb108)
 #define _MIPIC_DATA_ADDRESS(dev_priv->mipi_mmio_base + 0xb908)
 #define MIPI_DATA_ADDRESS(port)_MIPI_PORT(port, 
_MIPIA_DATA_ADDRESS, \
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index eff982b..f5df49b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -392,11 +392,21 @@ static void intel_dsi_port_enable(struct intel_encoder 
*encoder)
u32 port_ctrl;
 
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
-   temp = I915_READ(VLV_CHICKEN_3);
-   temp &= ~PIXEL_OVERLAP_CNT_MASK |
+   if (IS_BROXTON(dev)) {
+   for_each_dsi_port(port, intel_dsi->ports) {
+   temp = I915_READ(MIPI_CTRL(port));
+   temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
intel_dsi->pixel_overlap <<
+   BXT_PIXEL_OVERLAP_CNT_SHIFT;
+   I915_WRITE(MIPI_CTRL(port), temp);
+   }
+   } else {
+   temp = I915_READ(VLV_CHICKEN_3);
+   temp &= ~PIXEL_OVERLAP_CNT_MASK |
+   intel_dsi->pixel_overlap <<
PIXEL_OVERLAP_CNT_SHIFT;
-   I915_WRITE(VLV_CHICKEN_3, temp);
+   I915_WRITE(VLV_CHICKEN_3, temp);
+   }
}
 
for_each_dsi_port(port, intel_dsi->ports) {
-- 
1.9.1

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[Intel-gfx] [BXT MIPI PATCH 2/2] drm/i915: dual link pipe selection for bxt

2015-12-08 Thread Deepak M

Pipe is assigned based on the port, but it should be
based on current crtc. Correcting the same in this patch.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 23 ++-
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index f5df49b..0654b33 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -898,20 +898,25 @@ static void intel_dsi_prepare(struct intel_encoder 
*intel_encoder)
I915_WRITE(MIPI_CTRL(port), tmp |
READ_REQUEST_PRIORITY_HIGH);
} else if (IS_BROXTON(dev)) {
-   /*
-* FIXME:
-* BXT can connect any PIPE to any MIPI port.
-* Select the pipe based on the MIPI port read from
-* VBT for now. Pick PIPE A for MIPI port A and C
-* for port C.
-*/
+   enum pipe pipe = intel_crtc->pipe;
+
tmp = I915_READ(MIPI_CTRL(port));
tmp &= ~BXT_PIPE_SELECT_MASK;
 
-   if (port == PORT_A)
+   switch (pipe) {
+   case PIPE_A:
tmp |= BXT_PIPE_SELECT_A;
-   else if (port == PORT_C)
+   break;
+   case PIPE_B:
+   tmp |= BXT_PIPE_SELECT_B;
+   break;
+   case PIPE_C:
tmp |= BXT_PIPE_SELECT_C;
+   break;
+   default:
+   DRM_ERROR("Unknown pipe used\n");
+   return;
+   }
 
I915_WRITE(MIPI_CTRL(port), tmp);
}
-- 
1.9.1

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[Intel-gfx] [PATCH 3/3] drm/i915: Use the ceil value for the additional clk divider

2015-12-04 Thread Deepak M

Additional clock value divider should use the ceil
value of the calulation to get the correct divider value.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c 
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index cb3cf39..1322a71 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -454,7 +454,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, 
enum port port)
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
 
/* Max possible output of clock is 39.5 MHz, program value -1 */
-   divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
+   divider = DIV_ROUND_UP(dsi_rate, BXT_MAX_VAR_OUTPUT_KHZ) - 1;
tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
 
/*
-- 
1.9.1

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[Intel-gfx] [PATCH 1/3] drm/i915: Add DPI FIFO empty status check

2015-12-04 Thread Deepak M

From: Gaurav K Singh 

After sending SHUTDOWN or TURN ON packet,check the DPI
FIFO empty status.

Signed-off-by: Gaurav K Singh 
---
 drivers/gpu/drm/i915/intel_dsi.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 170ae6f..5c5b59a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -222,6 +222,12 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 
cmd, bool hs,
else
cmd |= DPI_LP_MODE;
 
+   mask = DPI_FIFO_EMPTY;
+
+   if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask)
+   == mask, 50))
+   DRM_ERROR("Timeout waiting for DPI FIFO empty\n");
+
/* clear bit */
I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 
-- 
1.9.1

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[Intel-gfx] [PATCH 2/3] drm/i915: Correct the Ref clock value for BXT

2015-12-04 Thread Deepak M

The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the
correct value here.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd2699..009f474 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7676,7 +7676,7 @@ enum skl_disp_power_wells {
 #define BXT_DSI_PLL_RATIO_MAX  0x7D
 #define BXT_DSI_PLL_RATIO_MIN  0x22
 #define BXT_DSI_PLL_RATIO_MASK 0xFF
-#define BXT_REF_CLOCK_KHZ  19500
+#define BXT_REF_CLOCK_KHZ  19200
 
 #define BXT_DSI_PLL_ENABLE 0x46080
 #define  BXT_DSI_PLL_DO_ENABLE (1 << 31)
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915: Add DPI FIFO empty status check

2015-12-04 Thread Deepak M

From: Gaurav K Singh <gaurav.k.si...@intel.com>

Before sending TURN ON packet,check the DPI
FIFO empty status.

v2: Change in commit message
Checking for FIFO empty  only during TURN ON packet.

Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
Got to know about the patch where they are removing this
DPI FIFO empty check while sending the SHUTDOWN packet.

http://lists.freedesktop.org/archives/intel-gfx/2014-July/048401.html

According added the check and waiting for DPI FIFIO empty
only when TURN_ON packet is sent.

 drivers/gpu/drm/i915/intel_dsi.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 170ae6f..495056f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -222,6 +222,12 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 
cmd, bool hs,
else
cmd |= DPI_LP_MODE;
 
+   mask = DPI_FIFO_EMPTY;
+
+   if ((cmd & TURN_ON) && wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) &
+   mask) == mask, 50))
+   DRM_ERROR("Timeout waiting for DPI FIFO empty\n");
+
/* clear bit */
I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add DPI FIFO empty status check

2015-12-04 Thread Deepak, M



> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, December 4, 2015 3:20 PM
> To: Deepak, M <m.dee...@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Gaurav K Singh
> <gaurav.k.si...@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add DPI FIFO empty status
> check
> 
> On Fri, Dec 04, 2015 at 07:47:37PM +0530, Deepak M wrote:
> > From: Gaurav K Singh <gaurav.k.si...@intel.com>
> >
> > After sending SHUTDOWN or TURN ON packet,check the DPI FIFO empty
> > status.
> >
> > Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c | 6 ++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 170ae6f..5c5b59a 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -222,6 +222,12 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi,
> u32 cmd, bool hs,
> > else
> > cmd |= DPI_LP_MODE;
> >
> > +   mask = DPI_FIFO_EMPTY;
> > +
> > +   if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask)
> > +   == mask, 50))
> > +   DRM_ERROR("Timeout waiting for DPI FIFO empty\n");
> > +
> 
> This checks for it _before_ sending the command, but the commit message
> says "after". Which is it supposed to be?
[Deepak, M] The check should be before, mistake in the commit message.
> 
> > /* clear bit */
> > I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
> >
> > --
> > 1.9.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use the ceil value for the additional clk divider

2015-12-04 Thread Deepak, M



> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, December 4, 2015 5:22 PM
> To: Deepak, M <m.dee...@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use the ceil value for the
> additional clk divider
> 
> On Fri, Dec 04, 2015 at 07:47:39PM +0530, Deepak M wrote:
> > Additional clock value divider should use the ceil value of the
> > calulation to get the correct divider value.
> >
> > Signed-off-by: Deepak M <m.dee...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > index cb3cf39..1322a71 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > @@ -454,7 +454,7 @@ static void bxt_dsi_program_clocks(struct
> drm_device *dev, enum port port)
> > dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
> >
> > /* Max possible output of clock is 39.5 MHz, program value -1 */
> > -   divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
> > +   divider = DIV_ROUND_UP(dsi_rate, BXT_MAX_VAR_OUTPUT_KHZ) -
> 1;
> 
> I can't find anything to support the 39.5 MHz claim above. I do know the tx
> escape clock should be <=20Mhz, so with the /2 extra divider it seems we
> should aim for <=40Mhz here. So yes, round up does make sense, but it
> seems to me that BXT_MAX_VAR_OUTPUT_KHZ should be 40 MHz.
> 
[Deepak, M] Yes, thought about it and me too feel that it should be 40 MHz.  We 
locally have tried with 2 different MIPI panels with 39.5 Mhz and didn't see 
any issue. I will confirm with SV teams and will update the patch accordingly. 
Thanks for pointing it :)

> > tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
> >
> > /*
> > --
> > 1.9.1
> >
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Correct the Ref clock value for BXT

2015-12-04 Thread Deepak, M



> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Friday, December 4, 2015 9:52 PM
> To: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Cc: Deepak, M <m.dee...@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915: Correct the Ref clock value for
> BXT
> 
> On Fri, Dec 04, 2015 at 11:55:56AM +0200, Ville Syrjälä wrote:
> > On Fri, Dec 04, 2015 at 07:47:38PM +0530, Deepak M wrote:
> > > The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the
> > > correct value here.
> > >
> > > Signed-off-by: Deepak M <m.dee...@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index 8bd2699..009f474 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7676,7 +7676,7 @@ enum skl_disp_power_wells {
> > >  #define BXT_DSI_PLL_RATIO_MAX0x7D
> > >  #define BXT_DSI_PLL_RATIO_MIN0x22
> > >  #define BXT_DSI_PLL_RATIO_MASK   0xFF
> > > -#define BXT_REF_CLOCK_KHZ19500
> > > +#define BXT_REF_CLOCK_KHZ19200
> >
> > No idea why we have this define in i915_reg.h. We don't have such
> > defines for other platforms (also my fix CHV refclk to 19.2MHz patch
> > never got reviewed by anyone either. Interedted?)
> 
> Add link and I think Deepak is volunteered ;-)
> >
[Deepak, M] Please share the link, I can go through the patch :)

> > Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> 
> Queued for -next, thanks for the patch.
> -Daniel
> >
> > >
> > >  #define BXT_DSI_PLL_ENABLE   0x46080
> > >  #define  BXT_DSI_PLL_DO_ENABLE   (1 << 31)
> > > --
> > > 1.9.1
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel OTC
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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[Intel-gfx] [MIPI SEQ PARSING v3 09/13] drm/i915: Added the generic gpio sequence support and gpio table

2015-11-30 Thread Deepak M

The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.

v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 589 +++--
 1 file changed, 553 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index bc33e3a..13f0fb7 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -59,30 +59,356 @@ static inline struct vbt_panel *to_vbt_panel(struct 
drm_panel *panel)
 
 #define NS_KHZ_RATIO 100
 
-#define GPI0_NC_0_HV_DDI0_HPD   0x4130
-#define GPIO_NC_0_HV_DDI0_PAD   0x4138
-#define GPIO_NC_1_HV_DDI0_DDC_SDA   0x4120
-#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
-#define GPIO_NC_2_HV_DDI0_DDC_SCL   0x4110
-#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
-#define GPIO_NC_3_PANEL0_VDDEN  0x4140
-#define GPIO_NC_3_PANEL0_VDDEN_PAD  0x4148
-#define GPIO_NC_4_PANEL0_BLKEN  0x4150
-#define GPIO_NC_4_PANEL0_BLKEN_PAD  0x4158
-#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
-#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
-#define GPIO_NC_6_PCONF00x4180
-#define GPIO_NC_6_PAD   0x4188
-#define GPIO_NC_7_PCONF00x4190
-#define GPIO_NC_7_PAD   0x4198
-#define GPIO_NC_8_PCONF00x4170
-#define GPIO_NC_8_PAD   0x4178
-#define GPIO_NC_9_PCONF00x4100
-#define GPIO_NC_9_PAD   0x4108
-#define GPIO_NC_10_PCONF0   0x40E0
-#define GPIO_NC_10_PAD  0x40E8
-#define GPIO_NC_11_PCONF0   0x40F0
-#define GPIO_NC_11_PAD  0x40F8
+#define HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
+#define HV_DDI0_HPD_GPIONC_0_PAD0x4138
+#define HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
+#define HV_DDI0_DDC_SDA_GPIONC_1_PAD0x4128
+#define HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
+#define HV_DDI0_DDC_SCL_GPIONC_2_PAD0x4118
+#define PANEL0_VDDEN_GPIONC_3_PCONF00x4140
+#define PANEL0_VDDEN_GPIONC_3_PAD   0x4148
+#define PANEL0_BKLTEN_GPIONC_4_PCONF0   0x4150
+#define PANEL0_BKLTEN_GPIONC_4_PAD  0x4158
+#define PANEL0_BKLTCTL_GPIONC_5_PCONF0  0x4160
+#define PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
+#define HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
+#define HV_DDI1_HPD_GPIONC_6_PAD0x4188
+#define HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
+#define HV_DDI1_DDC_SDA_GPIONC_7_PAD0x4198
+#define HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
+#define HV_DDI1_DDC_SCL_GPIONC_8_PAD0x4178
+#define PANEL1_VDDEN_GPIONC_9_PCONF00x4100
+#define PANEL1_VDDEN_GPIONC_9_PAD   0x4108
+#define PANEL1_BKLTEN_GPIONC_10_PCONF0  0x40E0
+#define PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
+#define PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
+#define PANEL1_BKLTCTL_GPIONC_11_PAD0x40F8
+#define GP_INTD_DSI_TE1_GPIONC_12_PCONF00x40C0
+#define GP_INTD_DSI_TE1_GPIONC_12_PAD   0x40C8
+#define HV_DDI2_DDC_SDA_GPIONC_13_PCONF00x41A0
+#define HV_DDI2_DDC_SDA_GPIONC_13_PAD   0x41A8
+#define HV_DDI2_DDC_SCL_GPIONC_14_PCONF00x41B0
+#define HV_DDI2_DDC_SCL_GPIONC_14_PAD   0x41B8
+#define GP_CAMERASB00_GPIONC_15_PCONF0  0x4010
+#define GP_CAMERASB00_GPIONC_15_PAD 0x4018
+#define GP_CAMERASB01_GPIONC_16_PCONF0  0x4040
+#define GP_CAMERASB01_GPIONC_16_PAD 0x4048
+#define GP_CAMERASB02_GPIONC_17_PCONF0  0x4080
+#define GP_CAMERASB02_GPIONC_17_PAD 0x4088
+#define GP_CAMERASB03_GPIONC_18_PCONF0  0x40B0
+#define GP_CAMERASB03_GPIONC_18_PAD 0x40B8
+#define GP_CAMERASB04_GPIONC_19_PCONF0  0x4000
+#define GP_CAMERASB04_GPIONC_19_PAD 0x4008
+#define GP_CAMERASB05_GPIONC_20_PCONF0  0x4030
+#define GP_CAMERASB05_GPIONC_20_PAD 0x4038
+#define GP_CAMERASB06_GPIONC_21_PCONF0  0x4060
+#define GP_CAMERASB06_GPIONC_21_PAD 0x4068
+#define GP_CAMERASB07_GPIONC_22_PCONF0  0x40A0
+#define GP_CAMERASB07_GPIONC_22_PAD 0x40A8
+#define GP_CAMERASB08_GPIONC_23_PCONF0  0x40D0
+#define GP_CAMERASB08_GPIONC_23_PAD 0x40D8
+#define GP_CAMERASB09_GPIONC_24_PCONF0  0x4020
+#define GP_CAMERASB09_GPIONC_24_PAD 0x4028
+#define GP_CAMERASB10_GPIONC_25_PCONF0  0x4050
+#define GP_CAMERASB10_GPIONC_25_PAD 0x4058
+#define GP_CAMERASB11_GPIONC_26_PCONF0  0x4090
+#define GP_CAMERASB11_G

[Intel-gfx] [MIPI SEQ PARSING v3 08/13] drm/i915: Extend gpio read/write to other cores

2015-11-30 Thread Deepak M

Adding a argument to the gpio read/write functions
which accepts the block name.

v2: rebase
v3: rebase

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h| 5 +++--
 drivers/gpu/drm/i915/i915_reg.h| 5 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 ++--
 drivers/gpu/drm/i915/intel_sideband.c  | 9 +
 4 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 59a39d1..ca865f4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3379,8 +3379,9 @@ int sandybridge_pcode_write(struct drm_i915_private 
*dev_priv, u32 mbox, u32 val
 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg);
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+   u32 reg, u32 val);
 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd2699..e29f7ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -572,6 +572,11 @@
 #define   IOSF_PORT_DPIO   0x12
 #define   IOSF_PORT_DPIO_2 0x1a
 #define   IOSF_PORT_GPIO_NC0x13
+#define   IOSF_PORT_GPIO_SC0x48
+#define   IOSF_PORT_GPIO_SUS   0xA8
+#define   MAX_GPIO_NUM_NC  26
+#define   MAX_GPIO_NUM_SC  128
+#define   MAX_GPIO_NUM 172
 #define   IOSF_PORT_CCK0x14
 #define   IOSF_PORT_CCU0xA9
 #define   IOSF_PORT_GPS_CORE   0x48
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index eb0697b..bc33e3a 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -275,14 +275,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
if (!gtable[gpio].init) {
/* program the function */
/* FIXME: remove constant below */
-   vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
+   vlv_gpio_write(dev_priv, IOSF_PORT_GPIO_NC, function, 
0x2000CC00);
gtable[gpio].init = 1;
}
 
val = 0x4 | action;
 
/* pull up/down */
-   vlv_gpio_nc_write(dev_priv, pad, val);
+   vlv_gpio_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
mutex_unlock(_priv->sb_lock);
 
return data;
diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
b/drivers/gpu/drm/i915/intel_sideband.c
index 8831fc5..3e0cbe6 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 
addr)
return val;
 }
 
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg)
 {
u32 val = 0;
-   vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+   vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
SB_CRRDDA_NP, reg, );
return val;
 }
 
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+   u32 reg, u32 val)
 {
-   vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+   vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
SB_CRWRDA_NP, reg, );
 }
 
-- 
1.9.1

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[Intel-gfx] [MIPI SEQ PARSING v3 00/13] Patches to support the version 3 of MIPI sequence in VBT.

2015-11-30 Thread Deepak M

Currently in our kernel we ioremap 8KB of memory for the
opregion and holds a maximum of 6KB sized RAW vbt data.

As per the latest opregion spec when the VBT size exceeds
6KB it cant be placed in the mailbox4 of the opregion, so
the physical address of the buffer where the Raw VBT is
stored will be mentioned in the mailbox3 with the VBT size
in the opregion version 2 and above.
A non-zero value here is an indication to driver that a
valid Raw VBT is stored here and driver should not refer
to mailbox4 for getting VBT. This is implemented in one
of the patches in this series.

link for the opregion spec : 
https://securewiki.ith.intel.com/pages/viewpage.action?pageId=48147378
(spec is under intel firewall)

In the version 3 of the MIPI sequence block, the size
field is 4 bytes so that it can support block size of
more than 64KB, but the vbt size field in the bdb header is only
2 bytes. Based on the below points this issue can be handled.
1. When the VBT is not present in the mailbox4 then VBT size
needs to be read from the mailbox3 and this VBT size field
is of 4 bytes which implies that it can be more than 64KB also.
2. If the VBT size is more than 64KB then the VBT size field
in the bdb header cant be relied. So its better to consider
the vbt size from the mailbox3 when the VBT is not present in
mailbox4.

Other patches implements the parsing of the new sequence type
which are added in the block 53.

v2: Addressed Jani`s review comments.
v3: Addressed Jani`s review comments.

Deepak M (8):
  drm/i915: Updating asle structure with new fields
  drm/i915: Add Intel opregion mailbox 5 structure
  drm/i915: Do opregion VBT validation during opregion setup
  drm/i915: Add debug entry to get the opregion VBT blob
  drm/i915: Parsing VBT if size of VBT exceeds 6KB
  drm/i915: Extend gpio read/write to other cores
  drm/i915: Added the generic gpio sequence support and gpio table
  drm: Add few more wrapper functions for drm panel

Gaurav K Singh (1):
  drm/i915: Add functions to execute the new sequences from VBT

Uma Shankar (1):
  drm/i915: BXT GPIO support for backlight and panel control

Yogesh Mohan Marimuthu (1):
  drm/i915: GPIO for CHT generic MIPI

vkorjani (2):
  drm/i915: Adding the parsing logic for the i2c element
  drm/i915: Added support the v3 mipi sequence block

 drivers/gpu/drm/i915/i915_debugfs.c|  29 +
 drivers/gpu/drm/i915/i915_drv.h|  10 +-
 drivers/gpu/drm/i915/i915_reg.h|  28 +
 drivers/gpu/drm/i915/intel_bios.c  | 175 --
 drivers/gpu/drm/i915/intel_bios.h  |  10 +-
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 887 +++--
 drivers/gpu/drm/i915/intel_opregion.c  |  72 ++-
 drivers/gpu/drm/i915/intel_sideband.c  |   9 +-
 include/drm/drm_panel.h|  47 ++
 9 files changed, 1170 insertions(+), 97 deletions(-)

-- 
1.9.1

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[Intel-gfx] [MIPI SEQ PARSING v3 05/13] drm/i915: Add debug entry to get the opregion VBT blob

2015-11-30 Thread Deepak M

Currently there is a entry to get the complete opregion
dump, this patch adds entry to get the VBT alone from
the opregion.

Adding this entry helps developer to get the VBT easily,
instead of following the old way where we get the complete
opregion dump and pick the VBT from the dump wrt to
the VBT offset.

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c   | 29 +
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/intel_bios.c |  1 +
 drivers/gpu/drm/i915/intel_opregion.c |  3 +++
 4 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d6d69f4..9b7fb00 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1865,6 +1865,34 @@ out:
return 0;
 }
 
+static int i915_opregion_vbt(struct seq_file *m, void *unused)
+{
+   struct drm_info_node *node = m->private;
+   struct drm_device *dev = node->minor->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct intel_opregion *opregion = _priv->opregion;
+   void *data = kmalloc(opregion->vbt_size, GFP_KERNEL);
+   int ret;
+
+   if (data == NULL)
+   return -ENOMEM;
+
+   ret = mutex_lock_interruptible(>struct_mutex);
+   if (ret)
+   goto out;
+
+   if (opregion->vbt) {
+   memcpy(data, opregion->vbt, opregion->vbt_size);
+   seq_write(m, data, opregion->vbt_size);
+   }
+
+   mutex_unlock(>struct_mutex);
+
+out:
+   kfree(data);
+   return 0;
+}
+
 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
 {
struct drm_info_node *node = m->private;
@@ -5383,6 +5411,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_ips_status", i915_ips_status, 0},
{"i915_sr_status", i915_sr_status, 0},
{"i915_opregion", i915_opregion, 0},
+   {"i915_opregion_vbt", i915_opregion_vbt, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
{"i915_context_status", i915_context_status, 0},
{"i915_dump_lrc", i915_dump_lrc, 0},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cf8375..59a39d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -457,6 +457,7 @@ struct intel_opregion {
u32 swsci_sbcb_sub_functions;
struct opregion_asle *asle;
void *vbt;
+   u32 vbt_size;
struct opregion_asle_ext *asle_ext;
u32 *lid_state;
struct work_struct asle_work;
diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 57a77aa..98b0e2a 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1338,6 +1338,7 @@ intel_parse_bios(struct drm_device *dev)
return -1;
}
 
+   dev_priv->opregion.vbt_size = vbt->vbt_size;
bdb = (const void *)vbt + vbt->bdb_offset;
}
 
diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index 4a78282..7908a1d 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -971,6 +971,9 @@ int intel_opregion_setup(struct drm_device *dev)
goto err_out;
}
 
+   vbt = (const struct vbt_header *)(base + OPREGION_VBT_OFFSET);
+   dev_priv->opregion.vbt_size = vbt->vbt_size;
+
opregion->header = base;
opregion->vbt = base + OPREGION_VBT_OFFSET;
 
-- 
1.9.1

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[Intel-gfx] [MIPI SEQ PARSING v3 07/13] drm/i915: Added support the v3 mipi sequence block

2015-11-30 Thread Deepak M

From: vkorjani <vikas.korj...@intel.com>

The Block 53 of the VBT, which is the MIPI sequence block
has undergone a design change because of which the parsing
logic has to be changed.

The current code will handle the parsing of v3 and other
lower versions of the MIPI sequence block.

v2: rebase
v3: minor comments fixed.

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: vkorjani <vikas.korj...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---

Addressed most of the minor comments in this version,
except the one where Jani had suggested to change the
logic in the goto_next_sequence(), Thought of handling
this as a new patch after this series.

http://lists.freedesktop.org/archives/intel-gfx/2015-September/076273.html

 drivers/gpu/drm/i915/intel_bios.c  | 125 -
 drivers/gpu/drm/i915/intel_bios.h  |   9 ++-
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   7 ++
 3 files changed, 120 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 98b0e2a..5cfb862 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -745,6 +745,72 @@ static u8 *goto_next_sequence(u8 *data, int *size)
return data;
 }
 
+
+/*
+ * Structure of single sequence in v3 version.
+ *  ___ _ __   _
+ * |   | | First|Size of |Payload ||End of |
+ * | Sequence  | Size of | Opreation|First Op|First Op||Current|
+ * | byte  | Sequence| byte |byte|byte||Seq(00)|
+ * |___|_|__||| ...|___|
+ * |  1 byte   | 4 Bytes | 1 byte   |1 bytes | Y byte ||1 byte |
+ * |   |   (X)   |  |  (Y)   |||   |
+ * |___|_|__||||___|
+ *
+ *   |<--Y--->|
+ *   |<---X--->|
+ */
+
+static u8 *goto_next_sequence_v3(u8 *data, int *size)
+{
+   int tmp = *size;
+   int op_size;
+
+   if (--tmp < 0)
+   return NULL;
+
+   /* Skip the panel id and the sequence byte */
+   data = data + 5;
+   tmp = tmp - 5;
+   while (*data != 0) {
+   u8 operation_type = *data++;
+
+   switch (operation_type) {
+   default:
+   DRM_ERROR("Unknown operation type %d\n", 
operation_type);
+   case MIPI_SEQ_ELEM_SEND_PKT:
+   case MIPI_SEQ_ELEM_DELAY:
+   case MIPI_SEQ_ELEM_GPIO:
+   case MIPI_SEQ_ELEM_I2C:
+   case MIPI_SEQ_ELEM_SPI:
+   case MIPI_SEQ_ELEM_PMIC:
+   /*
+* skip by this element payload size
+* skip elem id, command flag and data type
+*/
+   op_size = *data++;
+   tmp = tmp - (op_size + 1);
+   if (tmp < 0)
+   return NULL;
+
+   /* skip by len */
+   data += op_size;
+   break;
+   }
+   }
+
+   /* goto next sequence or end of block byte */
+   if (--tmp < 0)
+   return NULL;
+
+   /* Skip the end element marker */
+   data++;
+
+   /* update amount of data left for the sequence block to be parsed */
+   *size = tmp;
+   return data;
+}
+
 static void
 parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 {
@@ -754,8 +820,8 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct 
bdb_header *bdb)
const struct mipi_pps_data *pps;
u8 *data;
const u8 *seq_data;
-   int i, panel_id, seq_size;
-   u16 block_size;
+   int i, panel_id, panel_seq_size;
+   u32 block_size;
 
/* parse MIPI blocks only if LFP type is MIPI */
if (!dev_priv->vbt.has_mipi)
@@ -817,29 +883,40 @@ parse_mipi(struct drm_i915_private *dev_priv, const 
struct bdb_header *bdb)
 
DRM_DEBUG_DRIVER("Found MIPI sequence block\n");
 
-   block_size = get_blocksize(sequence);
-
/*
 * parse the sequence block for individual sequences
 */
dev_priv->vbt.dsi.seq_version = sequence->version;
 
seq_data = >data[0];
+   if (dev_priv->vbt.dsi.seq_version >= 3) {
+   block_size = *((unsigned int *)seq_data);
+   seq_data = seq_data + 4;
+   } else
+   block_size = get_blocksize(sequence);
 
/*
 * sequence block is variable length and hence we need to parse and
 * get the sequence data for specific panel id
 */
for (i = 0; i < MAX_MIPI_CONFIGUR

[Intel-gfx] [MIPI SEQ PARSING v3 06/13] drm/i915: Parsing VBT if size of VBT exceeds 6KB

2015-11-30 Thread Deepak M

Currently the iomap for VBT works only if the size of the
VBT is less than 6KB, but if the size of the VBT exceeds
6KB than the physical address and the size of the VBT to
be iomapped is specified in the mailbox3 and is iomapped
accordingly.

v3: -Splitted the patch into small ones
-Handeled memory unmap in intel_opregion_fini
-removed the new file created for opregion macro`s

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_opregion.c | 33 +++--
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index 7908a1d..b3a5709 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -856,6 +856,8 @@ void intel_opregion_fini(struct drm_device *dev)
}
 
/* just clear all opregion memory pointers now */
+   if (opregion->header->opregion_ver >= 2 && opregion->asle->rvda)
+   memunmap(opregion->vbt);
memunmap(opregion->header);
opregion->header = NULL;
opregion->acpi = NULL;
@@ -933,7 +935,8 @@ int intel_opregion_setup(struct drm_device *dev)
char buf[sizeof(OPREGION_SIGNATURE)];
const struct vbt_header *vbt = NULL;
int err = 0;
-   void *base;
+   void *base, *vbt_base;
+   size_t size;
 
BUILD_BUG_ON(sizeof(struct opregion_header) != 0x100);
BUILD_BUG_ON(sizeof(struct opregion_acpi) != 0x100);
@@ -963,19 +966,37 @@ int intel_opregion_setup(struct drm_device *dev)
goto err_out;
}
 
-   vbt = validate_vbt(base + OPREGION_VBT_OFFSET,
-   MAILBOX_4_SIZE, "OpRegion");
+   /*
+* Non-zero value in rvda field is an indication to driver that a
+* valid Raw VBT is stored in that address and driver should not refer
+* to mailbox4 for getting VBT.
+*/
+   if (opregion->header->opregion_ver >= 2 && opregion->asle->rvda) {
+   size = opregion->asle->rvds;
+   vbt_base = memremap(opregion->asle->rvda,
+   size, MEMREMAP_WB);
+   } else {
+   size = MAILBOX_4_SIZE;
+   vbt_base = base + OPREGION_VBT_OFFSET;
+   }
+
+   vbt = validate_vbt(vbt_base, size, "OpRegion");
 
if (vbt == NULL) {
err = -EINVAL;
goto err_out;
}
 
-   vbt = (const struct vbt_header *)(base + OPREGION_VBT_OFFSET);
-   dev_priv->opregion.vbt_size = vbt->vbt_size;
+   /* Assigning the vbt_size based on the VBT location */
+   if (opregion->header->opregion_ver >= 2 && opregion->asle->rvda)
+   dev_priv->opregion.vbt_size = opregion->asle->rvds;
+   else {
+   vbt = (const struct vbt_header *)(base + OPREGION_VBT_OFFSET);
+   dev_priv->opregion.vbt_size = vbt->vbt_size;
+   }
 
opregion->header = base;
-   opregion->vbt = base + OPREGION_VBT_OFFSET;
+   opregion->vbt = vbt_base;
 
opregion->lid_state = base + ACPI_CLID;
opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
-- 
1.9.1

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[Intel-gfx] [MIPI SEQ PARSING v3 02/13] drm/i915: Updating asle structure with new fields

2015-11-30 Thread Deepak M

v3: rebase

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_opregion.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index e362a30..64efedf 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -120,7 +120,9 @@ struct opregion_asle {
u64 fdss;
u32 fdsp;
u32 stat;
-   u8 rsvd[70];
+   u64 rvda;   /* Physical address of raw vbt data */
+   u32 rvds;   /* Size of raw vbt data */
+   u8 rsvd[58];
 } __packed;
 
 /* Driver readiness indicator */
-- 
1.9.1

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[Intel-gfx] [MIPI SEQ PARSING v3 01/13] drm/i915: Adding the parsing logic for the i2c element

2015-11-30 Thread Deepak M

From: vkorjani <vikas.korj...@intel.com>

New sequence element for i2c is been added in the
mipi sequence block of the VBT. This patch parses
and executes the i2c sequence.

v2: Add i2c_put_adapter call(Jani), rebase
v3: corrected the retry loop(Jani), rebase

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: vkorjani <vikas.korj...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c  |  6 +++
 drivers/gpu/drm/i915/intel_bios.h  |  1 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 60 ++
 3 files changed, 67 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index ce82f9c..6756a1c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -718,6 +718,12 @@ static u8 *goto_next_sequence(u8 *data, int *size)
 
data += 3;
break;
+   case MIPI_SEQ_ELEM_I2C:
+   /* skip by this element payload size */
+   data += 7;
+   len = *data;
+   data += len + 1;
+   break;
default:
DRM_ERROR("Unknown element\n");
return NULL;
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index 7ec8c9a..4ec73f5 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -954,6 +954,7 @@ enum mipi_seq_element {
MIPI_SEQ_ELEM_SEND_PKT,
MIPI_SEQ_ELEM_DELAY,
MIPI_SEQ_ELEM_GPIO,
+   MIPI_SEQ_ELEM_I2C,
MIPI_SEQ_ELEM_STATUS,
MIPI_SEQ_ELEM_MAX
 };
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index a5e99ac..92d619a 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "i915_drv.h"
@@ -104,6 +105,64 @@ static struct gpio_table gtable[] = {
{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
 };
 
+static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
+{
+   struct i2c_adapter *adapter;
+   int ret;
+   u8 reg_offset, payload_size, retries = 5;
+   struct i2c_msg msg;
+   u8 *transmit_buffer = NULL;
+   u8 flag = *data++;
+   u8 index = *data++;
+   u8 bus_number = *data++;
+   u16 slave_add = *(u16 *)(data);
+
+   data = data + 2;
+   reg_offset = *data++;
+   payload_size = *data++;
+
+   adapter = i2c_get_adapter(bus_number);
+
+   if (!adapter) {
+   DRM_ERROR("i2c_get_adapter(%u)\n", bus_number);
+   goto out;
+   }
+
+   transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
+
+   if (!transmit_buffer)
+   goto out;
+
+   transmit_buffer[0] = reg_offset;
+   memcpy(_buffer[1], data, payload_size);
+
+   msg.addr   = slave_add;
+   msg.flags  = 0;
+   msg.len= payload_size + 1;
+   msg.buf= _buffer[0];
+
+   do {
+   ret =  i2c_transfer(adapter, , 1);
+   if (ret == 1)
+   goto out;
+   else if (ret == -EAGAIN)
+   usleep_range(1000, 2500);
+   else {
+   DRM_ERROR("i2c transfer failed, error code:%d\n", ret);
+   goto out;
+   }
+   } while (retries--);
+
+   if (retries == 0)
+   DRM_ERROR("i2c transfer failed, error code:%d\n", ret);
+out:
+   kfree(transmit_buffer);
+   i2c_put_adapter(adapter);
+
+   data = data + payload_size;
+   return data;
+}
+
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 {
return port ? PORT_C : PORT_A;
@@ -236,6 +295,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
mipi_exec_send_packet,
mipi_exec_delay,
mipi_exec_gpio,
+   mipi_exec_i2c,
NULL, /* status read; later */
 };
 
-- 
1.9.1

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[Intel-gfx] [MIPI SEQ PARSING v3 04/13] drm/i915: Do opregion VBT validation during opregion setup

2015-11-30 Thread Deepak M

Calling the validate_vbt before assiging the opregion vbt blob.
Size of the VBT blob cant be more than 6KB when VBT is present
in mailbox 4.

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  3 +++
 drivers/gpu/drm/i915/intel_bios.c | 43 +++
 drivers/gpu/drm/i915/intel_opregion.c | 31 +
 3 files changed, 57 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 135d32a..8cf8375 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3324,6 +3324,9 @@ intel_opregion_notify_adapter(struct drm_device *dev, 
pci_power_t state)
 }
 #endif
 
+const struct vbt_header *validate_vbt(const void *_vbt, size_t size,
+   const char *source);
+
 /* intel_acpi.c */
 #ifdef CONFIG_ACPI
 extern void intel_register_dsm_handler(void);
diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 6756a1c..57a77aa 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1237,16 +1237,15 @@ static const struct dmi_system_id 
intel_no_opregion_vbt[] = {
{ }
 };
 
-static const struct bdb_header *validate_vbt(const void *base,
+const struct vbt_header *validate_vbt(const void *_vbt,
 size_t size,
-const void *_vbt,
 const char *source)
 {
-   size_t offset = _vbt - base;
-   const struct vbt_header *vbt = _vbt;
+   const struct vbt_header *vbt = (const struct vbt_header *)_vbt;
const struct bdb_header *bdb;
+   size_t offset;
 
-   if (offset + sizeof(struct vbt_header) > size) {
+   if (sizeof(struct vbt_header) > size) {
DRM_DEBUG_DRIVER("VBT header incomplete\n");
return NULL;
}
@@ -1256,26 +1255,26 @@ static const struct bdb_header *validate_vbt(const void 
*base,
return NULL;
}
 
-   offset += vbt->bdb_offset;
+   offset = vbt->bdb_offset;
if (offset + sizeof(struct bdb_header) > size) {
DRM_DEBUG_DRIVER("BDB header incomplete\n");
return NULL;
}
 
-   bdb = base + offset;
+   bdb = (const void *)_vbt + offset;
if (offset + bdb->bdb_size > size) {
DRM_DEBUG_DRIVER("BDB incomplete\n");
return NULL;
}
 
DRM_DEBUG_KMS("Using VBT from %s: %20s\n",
- source, vbt->signature);
-   return bdb;
+   source, vbt->signature);
+   return vbt;
 }
 
-static const struct bdb_header *find_vbt(void __iomem *bios, size_t size)
+static const struct vbt_header *find_vbt(void __iomem *bios, size_t size)
 {
-   const struct bdb_header *bdb = NULL;
+   const struct vbt_header *vbt = NULL;
size_t i;
 
/* Scour memory looking for the VBT signature. */
@@ -1289,12 +1288,12 @@ static const struct bdb_header *find_vbt(void __iomem 
*bios, size_t size)
 */
void *_bios = (void __force *) bios;
 
-   bdb = validate_vbt(_bios, size, _bios + i, "PCI ROM");
+   vbt = validate_vbt(_bios + i, size - i, "PCI ROM");
break;
}
}
 
-   return bdb;
+   return vbt;
 }
 
 /**
@@ -1311,6 +1310,7 @@ intel_parse_bios(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
struct pci_dev *pdev = dev->pdev;
+   const struct vbt_header *vbt = NULL;
const struct bdb_header *bdb = NULL;
u8 __iomem *bios = NULL;
 
@@ -1319,23 +1319,26 @@ intel_parse_bios(struct drm_device *dev)
 
init_vbt_defaults(dev_priv);
 
-   /* XXX Should this validation be moved to intel_opregion.c? */
-   if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt)
-   bdb = validate_vbt(dev_priv->opregion.header, OPREGION_SIZE,
-  dev_priv->opregion.vbt, "OpRegion");
+   if (!dmi_check_system(intel_no_opregion_vbt) &&
+   dev_priv->opregion.vbt) {
+   vbt = (const struct vbt_header *)dev_priv->opregion.vbt;
+   bdb = (const void *)dev_priv->opregion.vbt + vbt->bdb_offset;
+   }
 
-   if (bdb == NULL) {
+   if (vbt == NULL) {
size_t size;
 
bios = pci_map_rom(pdev, );
if (!bios)
return -1;
 
-   bdb = find_vbt(bios, size);
-   if (!bdb) {
+

[Intel-gfx] [MIPI SEQ PARSING v3 03/13] drm/i915: Add Intel opregion mailbox 5 structure

2015-11-30 Thread Deepak M

Mailbox 5 is BIOS to Driver Notification mailbox is intended
to support BIOS to Driver event notification or data storage
for BIOS to Driver data synchronization purpose. Mailbox 5 is
the extension of mailbox 3.

Cc: Jani Nikula <jani.nik...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   | 1 +
 drivers/gpu/drm/i915/intel_opregion.c | 9 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 71bd1dc..135d32a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -457,6 +457,7 @@ struct intel_opregion {
u32 swsci_sbcb_sub_functions;
struct opregion_asle *asle;
void *vbt;
+   struct opregion_asle_ext *asle_ext;
u32 *lid_state;
struct work_struct asle_work;
 };
diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index 64efedf..43b7c3b 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -46,6 +46,7 @@
 #define OPREGION_SWSCI_OFFSET  0x200
 #define OPREGION_ASLE_OFFSET   0x300
 #define OPREGION_VBT_OFFSET0x400
+#define OPREGION_ASLE_EXT_OFFSET   0x1C00
 
 #define OPREGION_SIGNATURE "IntelGraphicsMem"
 #define MBOX_ACPI  (1<<0)
@@ -125,6 +126,13 @@ struct opregion_asle {
u8 rsvd[58];
 } __packed;
 
+/* OpRegion mailbox #5: ASLE ext */
+struct opregion_asle_ext {
+   u32 phed;   /* Panel Header */
+   u32 bddc[64];   /* Panel EDID */
+   u32 rsvd[191];
+} __packed;
+
 /* Driver readiness indicator */
 #define ASLE_ARDY_READY(1 << 0)
 #define ASLE_ARDY_NOT_READY(0 << 0)
@@ -936,6 +944,7 @@ int intel_opregion_setup(struct drm_device *dev)
opregion->vbt = base + OPREGION_VBT_OFFSET;
 
opregion->lid_state = base + ACPI_CLID;
+   opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
 
mboxes = opregion->header->mboxes;
if (mboxes & MBOX_ACPI) {
-- 
1.9.1

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[Intel-gfx] [PATCH 1/2] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT

2015-11-26 Thread Deepak M

For dual link panel scenarios there are new fileds added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

v2: Moving the comment to intel_dsi.h(Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 10 ++
 drivers/gpu/drm/i915/intel_bios.h |  5 -
 drivers/gpu/drm/i915/intel_dsi.h  |  9 +
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index ce82f9c..2d4d7a0 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -793,6 +793,16 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct 
bdb_header *bdb)
return;
}
 
+   /*
+* These fileds are introduced from the VBT version 197 onwards,
+* so making sure that these bits are set zero in the pervious
+* versions.
+*/
+   if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+   dev_priv->vbt.dsi.config->dl_cabc_port = 0;
+   dev_priv->vbt.dsi.config->pwm_bkl_ctrl = 0;
+   }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index 7ec8c9a..9283969 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -832,7 +832,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
-   u16 rsvd3:9;
+   u16 rgb_flip:1;
+   u16 dl_cabc_port:2;
+   u16 pwm_bkl_ctrl:2;
+   u16 rsvd3:4;
 
u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e6cb252..40fd75a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -74,6 +74,15 @@ struct intel_dsi {
 
u8 escape_clk_div;
u8 dual_link;
+
+   /*
+* Below field will inform us on which port the panel blk_cntrl
+* and CABC ON/OFF commands needs to be sent in case of dual link
+* panels
+*/
+   u8 bkl_dcs_ports;
+   u8 pwm_blk_ctrl;
+
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
-- 
1.9.1

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[Intel-gfx] [PATCH 2/2] drm/i915: CABC support for backlight control

2015-11-26 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

In this design there will be no PWM signal from the SoC and DCS
commands are sent to enable and control the backlight brightness.

v2: Moving the CABC bkl functions to new file.(Jani)

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +-
 drivers/gpu/drm/i915/intel_dsi.c  |  17 +++-
 drivers/gpu/drm/i915/intel_dsi.h  |   4 +
 drivers/gpu/drm/i915/intel_dsi_cabc.c | 179 ++
 drivers/gpu/drm/i915/intel_panel.c|   4 +
 6 files changed, 205 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..2c69ed4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -82,6 +82,7 @@ i915-y += dvo_ch7017.o \
  intel_dp.o \
  intel_dsi.o \
  intel_dsi_panel_vbt.o \
+ intel_dsi_cabc.o \
  intel_dsi_pll.o \
  intel_dvo.o \
  intel_hdmi.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 71bd1dc..5febde4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3392,7 +3392,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
 enum intel_sbi_destination destination);
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-
+int intel_dsi_cabc_init_backlight_funcs(struct intel_connector 
*intel_connector);
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 170ae6f..f40b08f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1175,8 +1175,23 @@ void intel_dsi_init(struct drm_device *dev)
intel_dsi->ports = (1 << PORT_C);
}
 
-   if (dev_priv->vbt.dsi.config->dual_link)
+   if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
+   switch (dev_priv->vbt.dsi.config->dl_cabc_port) {
+   case CABC_PORT_A:
+   intel_dsi->bkl_dcs_ports = (1 << PORT_A);
+   break;
+   case CABC_PORT_C:
+   intel_dsi->bkl_dcs_ports = (1 << PORT_C);
+   break;
+   case CABC_PORT_A_AND_C:
+   intel_dsi->bkl_dcs_ports = intel_dsi->ports;
+   break;
+   default:
+   DRM_ERROR("Unknown MIPI ports for sending DCS\n");
+   }
+   } else
+   intel_dsi->bkl_dcs_ports = intel_dsi->ports;
 
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 40fd75a..0de2b4a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,10 @@
 #define DSI_DUAL_LINK_FRONT_BACK   1
 #define DSI_DUAL_LINK_PIXEL_ALT2
 
+#define CABC_PORT_A 0x00
+#define CABC_PORT_C 0x01
+#define CABC_PORT_A_AND_C   0x02
+
 struct intel_dsi_host;
 
 struct intel_dsi {
diff --git a/drivers/gpu/drm/i915/intel_dsi_cabc.c 
b/drivers/gpu/drm/i915/intel_dsi_cabc.c
new file mode 100644
index 000..d14a669
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_cabc.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright © 2006-2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in al

[Intel-gfx] [MIPI CABC 0/2] CABC patch list

2015-11-16 Thread Deepak M

CABC stands for the Content Adaptive Backlight Control.
In the normal display the backlight which we see is due to the
backlight which is being modulated by the filter, which is inturn
dependent on the image. In brief the CABC does the histogram
analysis of the image and then controls the filter and backlight.
For example in CABC to display the dark image the backlight is dimmed
and then controlls the filter to allow more light, because of
which is power consuption will be reduced.

Below are the inital set of patches which supports the CABC.
A field exits in the mipi configuration of the VBT which
when enabled indiactes the CABC is supported. Depending on
this filed the backlight control function pointer are
initalized in the intel_panel.c file.

In case of dual link panels depending on the panel
the DCS commands have to be send to either PORT A,
PORT C or both PORT A and PORT C. Again a filed is
added in the VBT to get this data from the version 197 onwards.
One of the below patches parses these fields from the
VBT.

Addressed the review comments of Jani, which were mentioned in
the below RFC patch
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075819.html

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>

Deepak M (2):
  drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT
  drm/i915: CABC support for backlight control


 drivers/gpu/drm/i915/intel_bios.c  |  13 
 drivers/gpu/drm/i915/intel_bios.h  |   5 +-
 drivers/gpu/drm/i915/intel_dsi.c   |  14 +++-
 drivers/gpu/drm/i915/intel_dsi.h   |  26 +++
 drivers/gpu/drm/i915/intel_panel.c | 145 +++--
 5 files changed, 196 insertions(+), 7 deletions(-)

-- 
1.9.1

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[Intel-gfx] [MIPI CABC 2/2] drm/i915: CABC support for backlight control

2015-11-16 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

In this design there will be no PWM signal from the SoC and DCS
commands are sent to enable and control the backlight brightness.

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
Addressed the review comments from Jani which were mentioned in
the below patch
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075819.html

Went with the name CABC because the commands which are used
here are mainly for CABC and many of the panels have the same
commands for the CABC operation. For the cases where PWM is
directly from panel PWM, DCS commands may be different and
may have to add new functions to support it.

 drivers/gpu/drm/i915/intel_dsi.c   |  14 +++-
 drivers/gpu/drm/i915/intel_dsi.h   |  24 ++
 drivers/gpu/drm/i915/intel_panel.c | 145 +++--
 3 files changed, 177 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 170ae6f..5d1ba35 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1175,8 +1175,20 @@ void intel_dsi_init(struct drm_device *dev)
intel_dsi->ports = (1 << PORT_C);
}
 
-   if (dev_priv->vbt.dsi.config->dual_link)
+   if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
+   switch (dev_priv->vbt.dsi.config->dl_cabc_port) {
+   case CABC_PORT_A:
+   intel_dsi->bkl_dcs_ports = (1 << PORT_A);
+   case CABC_PORT_C:
+   intel_dsi->bkl_dcs_ports = (1 << PORT_C);
+   case CABC_PORT_A_AND_C:
+   intel_dsi->bkl_dcs_ports = intel_dsi->ports;
+   default:
+   DRM_ERROR("Unknown MIPI ports for sending DCS\n");
+   }
+   } else
+   intel_dsi->bkl_dcs_ports = intel_dsi->ports;
 
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 4fde83b..4bcee40 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,30 @@
 #define DSI_DUAL_LINK_FRONT_BACK   1
 #define DSI_DUAL_LINK_PIXEL_ALT2
 
+#define CABC_OFF   (0 << 0)
+#define CABC_USER_INTERFACE_IMAGE  (1 << 0)
+#define CABC_STILL_PICTURE (2 << 0)
+#define CABC_VIDEO_MODE(3 << 0)
+
+#define CABC_BACKLIGHT (1 << 2)
+#define CABC_DIMMING_DISPLAY   (1 << 3)
+#define CABC_BCTRL (1 << 5)
+
+#define CABC_PORT_A0x00
+#define CABC_PORT_C0x01
+#define CABC_PORT_A_AND_C  0x02
+
+#define CABC_MAX_VALUE 0xFF
+
+#define MIPI_DCS_CABC_LEVEL_RD 0x52
+#define MIPI_DCS_CABC_MIN_BRIGHTNESS_RD0x5F
+#define MIPI_DCS_CABC_CONTROL_RD   0x56
+#define MIPI_DCS_CABC_CONTROL_BRIGHT_RD0x54
+#define MIPI_DCS_CABC_LEVEL_WR 0x51
+#define MIPI_DCS_CABC_MIN_BRIGHTNESS_WR0x5E
+#define MIPI_DCS_CABC_CONTROL_WR   0x55
+#define MIPI_DCS_CABC_CONTROL_BRIGHT_WR0x53
+
 struct intel_dsi_host;
 
 struct intel_dsi {
diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index a24df35..085d9a6 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -34,6 +34,7 @@
 #include 
 #include 
 #include "intel_drv.h"
+#include "intel_dsi.h"
 
 #define CRC_PMIC_PWM_PERIOD_NS 21333
 
@@ -533,6 +534,30 @@ static u32 vlv_get_backlight(struct intel_connector 
*connector)
return _vlv_get_backlight(dev, pipe);
 }
 
+static u32 cabc_get_backlight(struct intel_connector *connector)
+{
+   struct intel_dsi *intel_dsi = NULL;
+   struct intel_encoder *encoder = NULL;
+   struct mipi_dsi_device *dsi_device;
+   u8 data[2] = {0};
+   enum port port;
+
+   encoder = connector->encoder;
+   if (encoder->type == INTEL_OUTPUT_DSI)
+   intel_dsi = enc_to_intel_dsi(>base);
+   else {
+   DRM_ERROR("Use DSI encoder for CABC\n");
+   return -EINVAL;
+   }
+
+   for_

[Intel-gfx] [MIPI CABC 1/2] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT

2015-11-16 Thread Deepak M

For dual link panel scenarios there are new fileds added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Daniel Vetter <daniel.vet...@intel.com>
Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c | 13 +
 drivers/gpu/drm/i915/intel_bios.h |  5 -
 drivers/gpu/drm/i915/intel_dsi.h  |  2 ++
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index ce82f9c..2ef8721 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -793,6 +793,19 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct 
bdb_header *bdb)
return;
}
 
+   /*
+* These below bits will inform us on which port the panel blk_cntrl and
+* CABC ON/OFF commands needs to be sent in case of dual link panels
+*  u16 dl_cabc_port:2;
+*  u16 pwm_bkl_ctrl:2;
+* But these are introduced from the VBT version 197 onwards, so making
+* sure that these bits are zero in the pervious versions.
+*/
+   if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+   dev_priv->vbt.dsi.config->dl_cabc_port = 0;
+   dev_priv->vbt.dsi.config->pwm_bkl_ctrl = 0;
+   }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index 7ec8c9a..9283969 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -832,7 +832,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
-   u16 rsvd3:9;
+   u16 rgb_flip:1;
+   u16 dl_cabc_port:2;
+   u16 pwm_bkl_ctrl:2;
+   u16 rsvd3:4;
 
u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index e6cb252..4fde83b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -74,6 +74,8 @@ struct intel_dsi {
 
u8 escape_clk_div;
u8 dual_link;
+   u8 bkl_dcs_ports;
+   u8 pwm_blk_ctrl;
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 1/1] drm/i915: make backlight hooks connector specific

2015-09-29 Thread Deepak, M



>-Original Message-
>From: Nikula, Jani
>Sent: Tuesday, September 15, 2015 12:31 PM
>To: Daniel Vetter
>Cc: Deepak, M; Adebisi, YetundeX; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: make backlight hooks
>connector specific
>
>On Mon, 14 Sep 2015, Daniel Vetter <dan...@ffwll.ch> wrote:
>> On Mon, Sep 14, 2015 at 02:03:48PM +0300, Jani Nikula wrote:
>>> Previously we've relied on having basically one backlight and one
>>> backlight type per platform. This is already a bit quirky with PMIC
>>> PWM support on VLV/CHV platforms with MIPI DSI. In the foreseeable
>>> future we'll have at least DPCD based backlight control on eDP and
>>> DCS command based backlight control on MIPI DSI. Backlight is
>>> becoming more and more connector specific, so reflect this fact by
>>> making the backlight control hooks connector specific.
>>>
>>> This enables further work to reuse generic backlight code in
>>> intel_panel.c while adding more specific backlight code accessed via
>>> the hooks.
>>>
>>> Cc: Deepak M <m.dee...@intel.com>
>>> Cc: Yetunde Adebisi <yetundex.adeb...@intel.com>
>>> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
>>> ---
Reviewed-by: Deepak M <m.dee...@intel.com>

>>>  drivers/gpu/drm/i915/i915_drv.h  |   9 ---
>>>  drivers/gpu/drm/i915/intel_display.c |   2 -
>>>  drivers/gpu/drm/i915/intel_dp.c  |   2 +-
>>>  drivers/gpu/drm/i915/intel_drv.h |  13 +++-
>>>  drivers/gpu/drm/i915/intel_panel.c   | 116 +++-
>---
>>>  5 files changed, 74 insertions(+), 68 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h index 174f39d0bf46..813023b438b2
>>> 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -664,15 +664,6 @@ struct drm_i915_display_funcs {
>>> /* render clock increase/decrease */
>>> /* display clock increase/decrease */
>>> /* pll clock increase/decrease */
>>> -
>>> -   int (*setup_backlight)(struct intel_connector *connector, enum pipe
>pipe);
>>> -   uint32_t (*get_backlight)(struct intel_connector *connector);
>>> -   void (*set_backlight)(struct intel_connector *connector,
>>> - uint32_t level);
>>> -   void (*disable_backlight)(struct intel_connector *connector);
>>> -   void (*enable_backlight)(struct intel_connector *connector);
>>> -   uint32_t (*backlight_hz_to_pwm)(struct intel_connector *connector,
>>> -   uint32_t hz);
>>>  };
>>>
>>>  enum forcewake_domain_id {
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>> b/drivers/gpu/drm/i915/intel_display.c
>>> index fc0086748b71..15de4ccc3903 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -14520,8 +14520,6 @@ static void intel_init_display(struct
>drm_device *dev)
>>> dev_priv->display.queue_flip = intel_default_queue_flip;
>>> }
>>>
>>> -   intel_panel_init_backlight_funcs(dev);
>>> -
>>> mutex_init(_priv->pps_mutex);
>>>  }
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>>> b/drivers/gpu/drm/i915/intel_dp.c index a6872508adec..fa1a524844d5
>>> 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -5990,7 +5990,7 @@ static bool intel_edp_init_connector(struct
>intel_dp *intel_dp,
>>> }
>>>
>>> intel_panel_init(_connector->panel, fixed_mode,
>downclock_mode);
>>> -   intel_connector->panel.backlight_power =
>intel_edp_backlight_power;
>>> +   intel_connector->panel.backlight.power = intel_edp_backlight_power;
>>> intel_panel_setup_backlight(connector, pipe);
>>>
>>> return true;
>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>>> b/drivers/gpu/drm/i915/intel_drv.h
>>> index 02a755a50a96..35a65ca105b3 100644
>>> --- a/drivers/gpu/drm/i915/intel_drv.h
>>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>>> @@ -182,9 +182,17 @@ struct intel_panel {
>>> struct pwm_device *pwm;
>>>
>>> struct backlight_device *device;
>>> -   } backlight;
>>>
>>> -   void (*backlight_power)(struct intel

Re: [Intel-gfx] [PATCH] drm/i915/bios: handle MIPI Sequence Block v3+ gracefully

2015-09-23 Thread Deepak, M

Reviewed-by: Deepak M <m.dee...@intel.com>

>-Original Message-
>From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
>Vetter
>Sent: Wednesday, September 23, 2015 7:02 PM
>To: Nikula, Jani
>Cc: intel-gfx@lists.freedesktop.org; Deepak, M
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/bios: handle MIPI Sequence Block
>v3+ gracefully
>
>On Thu, Sep 17, 2015 at 04:42:07PM +0300, Jani Nikula wrote:
>> The VBT MIPI Sequence Block version 3 has forward incompatible changes:
>>
>> First, the block size in the header has been specified reserved, and
>> the actual size is a separate 32-bit value within the block. The
>> current
>> find_section() function to will only look at the size in the block
>> header, and, depending on what's in that now reserved size field,
>> continue looking for other sections in the wrong place.
>>
>> Fix this by taking the new block size field into account. This will
>> ensure that the lookups for other sections will work properly, as long
>> as the new 32-bit size does not go beyond the opregion VBT mailbox size.
>>
>> Second, the contents of the block have been completely changed.
>> Gracefully refuse parsing the yet unknown data version.
>>
>> Cc: Deepak M <m.dee...@intel.com>
>> Cc: sta...@vger.kernel.org
>> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
>
>Deepak, ping for review.
>-Daniel
>
>> ---
>>  drivers/gpu/drm/i915/intel_bios.c | 12 +++-
>>  1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index c8acc2952f82..68421c273c8c 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -42,7 +42,7 @@ find_section(const void *_bdb, int section_id)
>>  const struct bdb_header *bdb = _bdb;
>>  const u8 *base = _bdb;
>>  int index = 0;
>> -u16 total, current_size;
>> +u32 total, current_size;
>>  u8 current_id;
>>
>>  /* skip to first section */
>> @@ -57,6 +57,10 @@ find_section(const void *_bdb, int section_id)
>>  current_size = *((const u16 *)(base + index));
>>  index += 2;
>>
>> +/* The MIPI Sequence Block v3+ has a separate size field. */
>> +if (current_id == BDB_MIPI_SEQUENCE && *(base + index) >=
>3)
>> +current_size = *((const u32 *)(base + index + 1));
>> +
>>  if (index + current_size > total)
>>  return NULL;
>>
>> @@ -799,6 +803,12 @@ parse_mipi(struct drm_i915_private *dev_priv,
>const struct bdb_header *bdb)
>>  return;
>>  }
>>
>> +/* Fail gracefully for forward incompatible sequence block. */
>> +if (sequence->version >= 3) {
>> +DRM_ERROR("Unable to parse MIPI Sequence Block v3+\n");
>> +return;
>> +}
>> +
>>  DRM_DEBUG_DRIVER("Found MIPI sequence block\n");
>>
>>  block_size = get_blocksize(sequence);
>> --
>> 2.1.4
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Daniel Vetter
>Software Engineer, Intel Corporation
>http://blog.ffwll.ch
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Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 04/11] drm/i915: Using the approprite vbt size if vbt is not in mailbox4 of opregion

2015-09-22 Thread Deepak, M



>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 5:48 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 04/11] drm/i915: Using
>the approprite vbt size if vbt is not in mailbox4 of opregion
>
>On Thu, 10 Sep 2015, Deepak M <m.dee...@intel.com> wrote:
>> Currently the field in bdb header which indicates the VBT size is of 2
>> bytes, but there are some cases where VBT size exceeds 64KB in which
>> case this field may not contain the correct VBT size.
>> So its better to get the VBT size from the mailbox3 if VBT is not
>> present in the mailbox4 of opregion.
>>
>> v2: - Use opregion filed from dev_priv struct instead of creating
>>   a new field in dev_priv (Jani)
>> - Have vbt_size field vaild in all scenarios (Jani)
>> - rebase
>>
>> Signed-off-by: Deepak M <m.dee...@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h   |2 ++
>>  drivers/gpu/drm/i915/intel_bios.c |   42 +++--
>
>>  drivers/gpu/drm/i915/intel_opregion.c |6 +
>>  3 files changed, 32 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 507d57a..91ccbc6 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1777,6 +1777,8 @@ struct drm_i915_private {
>>  u32 pm_rps_events;
>>  u32 pipestat_irq_mask[I915_MAX_PIPES];
>>
>> +u32 vbt_size;
>
>No. dev_priv is not a random area to throw things into. The place you're
>looking for is dev_priv->opregion, i.e. struct intel_opregion.
>
>> +
>>  struct i915_hotplug hotplug;
>>  struct i915_fbc fbc;
>>  struct i915_drrs drrs;
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index 1932a86..34a1042 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -37,17 +37,19 @@
>>  static int panel_type;
>>
>>  static const void *
>> -find_section(const void *_bdb, int section_id)
>> +find_section(struct drm_i915_private *dev_priv,
>> +const void *_bdb, int section_id)
>>  {
>>  const struct bdb_header *bdb = _bdb;
>>  const u8 *base = _bdb;
>>  int index = 0;
>> -u16 total, current_size;
>> +u32 total, current_size;
>>  u8 current_id;
>>
>>  /* skip to first section */
>>  index += bdb->header_size;
>> -total = bdb->bdb_size;
>> +
>> +total = dev_priv->vbt_size;
>
>vbt_size != bdb_size. See below.
>
>>
>>  /* walk the sections looking for section_id */
>>  while (index + 3 < total) {
>> @@ -179,7 +181,7 @@ parse_lfp_panel_data(struct drm_i915_private
>*dev_priv,
>>  struct drm_display_mode *panel_fixed_mode;
>>  int drrs_mode;
>>
>> -lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
>> +lvds_options = find_section(dev_priv, bdb, BDB_LVDS_OPTIONS);
>>  if (!lvds_options)
>>  return;
>>
>> @@ -211,11 +213,12 @@ parse_lfp_panel_data(struct drm_i915_private
>*dev_priv,
>>  break;
>>  }
>>
>> -lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
>> +lvds_lfp_data = find_section(dev_priv, bdb, BDB_LVDS_LFP_DATA);
>>  if (!lvds_lfp_data)
>>  return;
>>
>> -lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
>> +lvds_lfp_data_ptrs = find_section(dev_priv, bdb,
>> +BDB_LVDS_LFP_DATA_PTRS);
>>  if (!lvds_lfp_data_ptrs)
>>  return;
>>
>> @@ -257,7 +260,7 @@ parse_lfp_backlight(struct drm_i915_private
>*dev_priv,
>>  const struct bdb_lfp_backlight_data *backlight_data;
>>  const struct bdb_lfp_backlight_data_entry *entry;
>>
>> -backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
>> +backlight_data = find_section(dev_priv, bdb, BDB_LVDS_BACKLIGHT);
>>  if (!backlight_data)
>>  return;
>>
>> @@ -305,14 +308,15 @@ parse_sdvo_panel_data(struct drm_i915_private
>*dev_priv,
>>  if (index == -1) {
>>  const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
>>
>> -sdvo_lvds_options = find_section(bdb,
>BDB_SDVO_LVDS_OPTIONS);
>> +sdvo_lvds_options = find_section(dev_pri

Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 05/11] drm/i915: Added support the v3 mipi sequence block

2015-09-22 Thread Deepak, M



>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 8:09 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 05/11] drm/i915: Added
>support the v3 mipi sequence block
>
>On Thu, 10 Sep 2015, Deepak M <m.dee...@intel.com> wrote:
>> From: vkorjani <vikas.korj...@intel.com>
>>
>> The Block 53 of the VBT, which is the MIPI sequence block has
>> undergone a design change because of which the parsing logic has to be
>> changed.
>>
>> The current code will handle the parsing of v3 and other lower
>> versions of the MIPI sequence block.
>>
>> v2: rebase
>>
>> Signed-off-by: vkorjani <vikas.korj...@intel.com>
>> Signed-off-by: Deepak M <m.dee...@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_bios.c  |  119
>+++-
>>  drivers/gpu/drm/i915/intel_bios.h  |8 ++
>>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |7 ++
>>  3 files changed, 114 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index 34a1042..cea641f 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -45,6 +45,7 @@ find_section(struct drm_i915_private *dev_priv,
>>  int index = 0;
>>  u32 total, current_size;
>>  u8 current_id;
>> +u8 version;
>>
>>  /* skip to first section */
>>  index += bdb->header_size;
>> @@ -56,7 +57,17 @@ find_section(struct drm_i915_private *dev_priv,
>>  current_id = *(base + index);
>>  index++;
>>
>> -current_size = *((const u16 *)(base + index));
>> +if (current_id == BDB_MIPI_SEQUENCE) {
>> +version = *(base + index + 2);
>> +if (version >= 3)
>> +current_size = *((const u32 *)(base +
>> +index + 3));
>> +else
>> +current_size = *((const u16 *)(base + index));
>> +} else {
>> +current_size = *((const u16 *)(base + index));
>> +}
>> +
>
>While reviewing I've realized the old kernels will hit this hard. I've 
>submitted a
>patch [1] to be applied to v4.3-rc and older stable kernels so that they fail
>gracefully instead of starting to parse garbage. The real parsing is too big to
>backport to upstream stable. Please review.
>
>[1] http://mid.gmane.org/1442497327-27033-1-git-send-email-
>jani.nik...@intel.com
>
>>  index += 2;
>>
>>  if (index + current_size > total)
>> @@ -745,6 +756,55 @@ static u8 *goto_next_sequence(u8 *data, int *size)
>>  return data;
>>  }
>>
>> +static u8 *goto_next_sequence_v3(u8 *data, int *size) {
>> +int tmp = *size;
>> +int op_size;
>> +
>> +if (--tmp < 0)
>> +return NULL;
>> +
>> +/* Skip the panel id and the sequence size */
>
>It's not panel id, it's the sequence byte, right?
>
>You could also store data + 1 + size of sequence, and check whether data ends
>up pointing at the same place in the end. They should.
>
>Shouldn't you also take 4 bytes of sequence size field into account in tmp?
>
>> +data = data + 5;
>> +while (*data != 0) {
>> +u8 element_type = *data++;
>> +
>> +switch (element_type) {
>
>Would be helpful to refer to operation_byte like in the spec.
>
>> +default:
>> +DRM_ERROR("Unknown element type %d\n",
>element_type);
>> +case MIPI_SEQ_ELEM_SEND_PKT:
>> +case MIPI_SEQ_ELEM_DELAY:
>> +case MIPI_SEQ_ELEM_GPIO:
>> +case MIPI_SEQ_ELEM_I2C:
>> +case MIPI_SEQ_ELEM_SPI:
>> +case MIPI_SEQ_ELEM_PMIC:
>> +/*
>> + * skip by this element payload size
>> + * skip elem id, command flag and data type
>> + */
>> +op_size = *data++;
>> +tmp = tmp - (op_size + 1);
>> +if (tmp < 0)
>> +return NULL;
>
>Isn't each operation operation byte | size of operation | payload size, i.e. 
>your
>tmp change is one byte

Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 04/11] drm/i915: Using the approprite vbt size if vbt is not in mailbox4 of opregion

2015-09-22 Thread Deepak, M



>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 7:01 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 04/11] drm/i915: Using
>the approprite vbt size if vbt is not in mailbox4 of opregion
>
>On Thu, 17 Sep 2015, Jani Nikula <jani.nik...@linux.intel.com> wrote:
>> On Thu, 10 Sep 2015, Deepak M <m.dee...@intel.com> wrote:
>>> Currently the field in bdb header which indicates the VBT size is of
>>> 2 bytes, but there are some cases where VBT size exceeds 64KB in
>>> which case this field may not contain the correct VBT size.
>>> So its better to get the VBT size from the mailbox3 if VBT is not
>>> present in the mailbox4 of opregion.
>>>
>>> v2: - Use opregion filed from dev_priv struct instead of creating
>>>   a new field in dev_priv (Jani)
>>> - Have vbt_size field vaild in all scenarios (Jani)
>>> - rebase
>>>
>>> Signed-off-by: Deepak M <m.dee...@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/i915_drv.h   |2 ++
>>>  drivers/gpu/drm/i915/intel_bios.c |   42 +++-
>-
>>>  drivers/gpu/drm/i915/intel_opregion.c |6 +
>>>  3 files changed, 32 insertions(+), 18 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h index 507d57a..91ccbc6 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1777,6 +1777,8 @@ struct drm_i915_private {
>>> u32 pm_rps_events;
>>> u32 pipestat_irq_mask[I915_MAX_PIPES];
>>>
>>> +   u32 vbt_size;
>>
>> No. dev_priv is not a random area to throw things into. The place
>> you're looking for is dev_priv->opregion, i.e. struct intel_opregion.
>>
>>> +
>>> struct i915_hotplug hotplug;
>>> struct i915_fbc fbc;
>>> struct i915_drrs drrs;
>>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>>> b/drivers/gpu/drm/i915/intel_bios.c
>>> index 1932a86..34a1042 100644
>>> --- a/drivers/gpu/drm/i915/intel_bios.c
>>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>>> @@ -37,17 +37,19 @@
>>>  static int panel_type;
>>>
>>>  static const void *
>>> -find_section(const void *_bdb, int section_id)
>>> +find_section(struct drm_i915_private *dev_priv,
>>> +   const void *_bdb, int section_id)
>>>  {
>>> const struct bdb_header *bdb = _bdb;
>>> const u8 *base = _bdb;
>>> int index = 0;
>>> -   u16 total, current_size;
>>> +   u32 total, current_size;
>>> u8 current_id;
>>>
>>> /* skip to first section */
>>> index += bdb->header_size;
>>> -   total = bdb->bdb_size;
>>> +
>>> +   total = dev_priv->vbt_size;
>>
>> vbt_size != bdb_size. See below.
>>
>>>
>>> /* walk the sections looking for section_id */
>>> while (index + 3 < total) {
>>> @@ -179,7 +181,7 @@ parse_lfp_panel_data(struct drm_i915_private
>*dev_priv,
>>> struct drm_display_mode *panel_fixed_mode;
>>> int drrs_mode;
>>>
>>> -   lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
>>> +   lvds_options = find_section(dev_priv, bdb, BDB_LVDS_OPTIONS);
>>> if (!lvds_options)
>>> return;
>>>
>>> @@ -211,11 +213,12 @@ parse_lfp_panel_data(struct drm_i915_private
>*dev_priv,
>>> break;
>>> }
>>>
>>> -   lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
>>> +   lvds_lfp_data = find_section(dev_priv, bdb, BDB_LVDS_LFP_DATA);
>>> if (!lvds_lfp_data)
>>> return;
>>>
>>> -   lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
>>> +   lvds_lfp_data_ptrs = find_section(dev_priv, bdb,
>>> +   BDB_LVDS_LFP_DATA_PTRS);
>>> if (!lvds_lfp_data_ptrs)
>>> return;
>>>
>>> @@ -257,7 +260,7 @@ parse_lfp_backlight(struct drm_i915_private
>*dev_priv,
>>> const struct bdb_lfp_backlight_data *backlight_data;
>>> const struct bdb_lfp_backlight_data_entry *entry;
>>>
>>> -   backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
>>> +   backlight_data = find_section(dev_priv, bdb, BDB_LVDS_BACKLIGH

Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 01/11] drm/i915: Adding the parsing logic for the i2c element

2015-09-22 Thread Deepak, M



>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 2:48 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 01/11] drm/i915: Adding
>the parsing logic for the i2c element
>
>On Thu, 10 Sep 2015, Deepak M <m.dee...@intel.com> wrote:
>> From: vkorjani <vikas.korj...@intel.com>
>>
>> New sequence element for i2c is been added in the mipi sequence block
>> of the VBT. This patch parses and executes the i2c sequence.
>>
>> v2: Add i2c_put_adapter call(Jani), rebase
>>
>> Signed-off-by: vkorjani <vikas.korj...@intel.com>
>> Signed-off-by: Deepak M <m.dee...@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_bios.c  |6 +++
>>  drivers/gpu/drm/i915/intel_bios.h  |1 +
>>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   61
>
>>  3 files changed, 68 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index c8acc29..0bf0942 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -714,6 +714,12 @@ static u8 *goto_next_sequence(u8 *data, int
>> *size)
>>
>>  data += 3;
>>  break;
>> +case MIPI_SEQ_ELEM_I2C:
>> +/* skip by this element payload size */
>> +data += 7;
>> +len = *data;
>> +data += len + 1;
>> +break;
>>  default:
>>  DRM_ERROR("Unknown element\n");
>>  return NULL;
>> diff --git a/drivers/gpu/drm/i915/intel_bios.h
>> b/drivers/gpu/drm/i915/intel_bios.h
>> index 1b7417e..21a7f3f 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.h
>> +++ b/drivers/gpu/drm/i915/intel_bios.h
>> @@ -956,6 +956,7 @@ enum mipi_seq_element {
>>  MIPI_SEQ_ELEM_SEND_PKT,
>>  MIPI_SEQ_ELEM_DELAY,
>>  MIPI_SEQ_ELEM_GPIO,
>> +MIPI_SEQ_ELEM_I2C,
>>  MIPI_SEQ_ELEM_STATUS,
>
>Side note, MIPI_SEQ_ELEM_STATUS doesn't seem to be in spec.
>
>
>>  MIPI_SEQ_ELEM_MAX
>>  };
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index a5e99ac..9989f61 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -31,6 +31,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include "i915_drv.h"
>> @@ -104,6 +105,65 @@ static struct gpio_table gtable[] = {
>>  { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}  };
>>
>> +static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8
>> +*data) {
>> +struct i2c_adapter *adapter;
>> +int ret;
>> +u8 reg_offset, payload_size, retries = 5;
>> +struct i2c_msg msg;
>> +u8 *transmit_buffer = NULL;
>> +    u8 flag = *data++;
>> +u8 index = *data++;
>> +u8 bus_number = *data++;
>> +u16 slave_add = *(u16 *)(data);
>> +
>> +data = data + 2;
>> +reg_offset = *data++;
>> +payload_size = *data++;
>> +
>> +adapter = i2c_get_adapter(bus_number);
>> +
>> +if (!adapter) {
>> +DRM_ERROR("i2c_get_adapter(%u) failed, index:%u flag:
>%u\n",
>> +(bus_number + 1), index, flag);
>
>Why do you log bus_number + 1 instead of what was actually tried?
[Deepak M] Will fix this.
>
>I don't see why the flag/index are useful for in the message, as they're not
>relevant to the i2c_get_adapter failing.
>
[Deepak M] Flag field is reserved and then the index is used for windows, for 
Linux these two can be skipped. Will not try to declare flag and index variable.
>> +goto out;
>> +}
>> +
>> +transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
>> +
>> +if (!transmit_buffer)
>> +goto out;
>> +
>> +transmit_buffer[0] = reg_offset;
>> +memcpy(_buffer[1], data, (size_t)payload_size);
>
>Why do you need the cast?
>
>> +
>> +msg.addr   = slave_add;
>> +msg.flags  = 0;
>> +msg.len= payload_size + 1;
>> +msg.buf= _buffer[0];
>> +
>> +do {
>> +ret =  i2c_transfer(adapter, , 1);
>>

Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 03/11] drm/i915: Parsing VBT if size of VBT exceeds 6KB

2015-09-22 Thread Deepak, M



>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Thursday, September 17, 2015 5:41 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [MIPI SEQ PARSING v2 PATCH 03/11] drm/i915: Parsing
>VBT if size of VBT exceeds 6KB
>
>On Thu, 10 Sep 2015, Deepak M <m.dee...@intel.com> wrote:
>> Currently the iomap for VBT works only if the size of the VBT is less
>> than 6KB, but if the size of the VBT exceeds 6KB than the physical
>> address and the size of the VBT to be iomapped is specified in the
>> mailbox3 and is iomapped accordingly.
>>
>> v2: - Moving the validate_vbt to opregion file (Jani)
>>     - Fix the i915_opregion() in debugfs (Jani)
>>
>> Signed-off-by: Deepak M <m.dee...@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_debugfs.c   |   24 ++-
>>  drivers/gpu/drm/i915/i915_drv.h   |4 +
>>  drivers/gpu/drm/i915/intel_bios.c |   49 +-
>>  drivers/gpu/drm/i915/intel_opregion.c |  279
>> +
>> drivers/gpu/drm/i915/intel_opregion.h |  230
>> +++
>>  5 files changed, 329 insertions(+), 257 deletions(-)  create mode
>> 100644 drivers/gpu/drm/i915/intel_opregion.h
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 41629fa..5534aa2 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -26,6 +26,8 @@
>>   *
>>   */
>>
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -39,6 +41,7 @@
>>  #include "intel_ringbuffer.h"
>>  #include 
>>  #include "i915_drv.h"
>> +#include "intel_opregion.h"
>>
>>  enum {
>>  ACTIVE_LIST,
>> @@ -1832,7 +1835,7 @@ static int i915_opregion(struct seq_file *m, void
>*unused)
>>  struct drm_device *dev = node->minor->dev;
>>  struct drm_i915_private *dev_priv = dev->dev_private;
>>  struct intel_opregion *opregion = _priv->opregion;
>> -void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
>> +void *data = kmalloc(OPREGION_VBT_OFFSET, GFP_KERNEL);
>>  int ret;
>>
>>  if (data == NULL)
>> @@ -1843,12 +1846,25 @@ static int i915_opregion(struct seq_file *m, void
>*unused)
>>  goto out;
>>
>>  if (opregion->header) {
>> -memcpy_fromio(data, opregion->header, OPREGION_SIZE);
>> -seq_write(m, data, OPREGION_SIZE);
>> +memcpy_fromio(data, opregion->header,
>OPREGION_VBT_OFFSET);
>> +seq_write(m, data, OPREGION_VBT_OFFSET);
>> +kfree(data);
>> +if (opregion->asle->rvda) {
>> +data = kmalloc(opregion->asle->rvds, GFP_KERNEL);
>> +memcpy_fromio(data,
>> +(const void __iomem *) opregion->asle->rvda,
>> +opregion->asle->rvds);
>> +seq_write(m, data, opregion->asle->rvds);
>> +} else {
>> +data = kmalloc(OPREGION_SIZE -
>OPREGION_VBT_OFFSET,
>> +GFP_KERNEL);
>> +memcpy_fromio(data, opregion->vbt,
>> +OPREGION_SIZE -
>OPREGION_VBT_OFFSET);
>> +seq_write(m, data, OPREGION_SIZE -
>OPREGION_VBT_OFFSET);
>> +    }
>
>If rvda != 0, this debugfs file no longer represents the opregion contents.
>Mailboxes #4 and #5 are dropped from the output. BTW, what is mailbox #4
>expected to contain when rvda != 0? (I still don't have access to the latest
>opregion spec version, so can't check what it actually says.)
>
>I am beginning to think we should leave "i915_opregion" debugfs file intact,
>and add a new "i915_vbt" file that contains either mailbox #4 or the data in
>rvda. This might be a cleaner approach.
>
>See my comments below, and you'll see how this would be feasible.
>
[Deepak M] I was thinking of splitting this function into 5 for dumping each 
mailbox. Which 
I felt will be cleaner.
>>  }
>>
>>  mutex_unlock(>struct_mutex);
>> -
>>  out:
>>  kfree(data);
>>  return 0;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 1287007..507d57a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/d

Re: [Intel-gfx] [PATCH] drm/i915: CABC support for backlight control

2015-09-14 Thread Deepak, M



>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Monday, September 14, 2015 5:51 PM
>To: Deepak, M; intel-gfx@lists.freedesktop.org
>Cc: Deepak, M
>Subject: Re: [Intel-gfx] [PATCH] drm/i915: CABC support for backlight control
>
>On Mon, 14 Sep 2015, Deepak M <m.dee...@intel.com> wrote:
>> In CABC (Content Adaptive Brightness Control) content grey level scale
>> can be increased while simultaneously decreasing brightness of the
>> backlight to achieve same perceived brightness.
>>
>> The CABC is not standardized and panel vendors are free to follow
>> their implementation. The CABC implementaion here assumes that the
>> panels use standard SW register for control.
>>
>> In this design there will be no PWM signal from the SoC and DCS
>> commands are sent to enable and control the backlight brightness.
>
>I think CABC is a confusing name for this. At the high level, this should be
>called, say, DCS backlight control. I think CABC is a special case of backlight
>control in the DSI panel; there are panels with brightness control via DCS
>*without* CABC.
>
>See further comments inline.
>
>>
>> v2:
>> - Created a new backlight driver for cabc, which will be registered
>>   only when it cabc is supported by panel. (Daniel Vetter)
>> v3:
>> - Use for_each_dsi_port macro for handling port C also (Gaurav)
>> - Rebase
>>
>> Signed-off-by: Deepak M <m.dee...@intel.com>
>> ---
>>  drivers/gpu/drm/i915/Makefile |1 +
>>  drivers/gpu/drm/i915/intel_dsi.c  |   18 +-
>>  drivers/gpu/drm/i915/intel_dsi_cabc.c |  310
>+
>>  drivers/gpu/drm/i915/intel_dsi_cabc.h |   46 +
>>  drivers/gpu/drm/i915/intel_panel.c|   23 ++-
>>  include/video/mipi_display.h  |8 +
>>  6 files changed, 399 insertions(+), 7 deletions(-)  create mode
>> 100644 drivers/gpu/drm/i915/intel_dsi_cabc.c
>>  create mode 100644 drivers/gpu/drm/i915/intel_dsi_cabc.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile
>> b/drivers/gpu/drm/i915/Makefile index 44d290a..d87c690 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -82,6 +82,7 @@ i915-y += dvo_ch7017.o \
>>intel_dsi.o \
>>intel_dsi_panel_vbt.o \
>>intel_dsi_pll.o \
>> +  intel_dsi_cabc.o \
>>intel_dvo.o \
>>intel_hdmi.o \
>>intel_i2c.o \
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
>> b/drivers/gpu/drm/i915/intel_dsi.c
>> index 781c267..1d98ed8 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -35,6 +35,7 @@
>>  #include "i915_drv.h"
>>  #include "intel_drv.h"
>>  #include "intel_dsi.h"
>> +#include "intel_dsi_cabc.h"
>>
>>  static const struct {
>>  u16 panel_id;
>> @@ -398,7 +399,10 @@ static void intel_dsi_enable(struct intel_encoder
>*encoder)
>>  intel_dsi_port_enable(encoder);
>>  }
>>
>> -intel_panel_enable_backlight(intel_dsi->attached_connector);
>> +if (dev_priv->vbt.dsi.config->cabc_supported)
>> +cabc_enable_backlight(intel_dsi->attached_connector);
>> +else
>> +intel_panel_enable_backlight(intel_dsi-
>>attached_connector);
>
>See my patch at [1] for how I think all of this should be handled.
>
>[1] http://mid.gmane.org/cover.1442227790.git.jani.nik...@intel.com
>
[Deepak M] Will go through that patch. 
>>  }
>>
>>  static void intel_dsi_pre_enable(struct intel_encoder *encoder) @@
>> -458,12 +462,17 @@ static void intel_dsi_enable_nop(struct
>> intel_encoder *encoder)
>>
>>  static void intel_dsi_pre_disable(struct intel_encoder *encoder)  {
>> +struct drm_device *dev = encoder->base.dev;
>> +struct drm_i915_private *dev_priv = dev->dev_private;
>>  struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>>  enum port port;
>>
>>  DRM_DEBUG_KMS("\n");
>>
>> -intel_panel_disable_backlight(intel_dsi->attached_connector);
>> +if (dev_priv->vbt.dsi.config->cabc_supported)
>> +cabc_disable_backlight(intel_dsi->attached_connector);
>> +else
>> +intel_panel_disable_backlight(intel_dsi-
>>attached_connector);
>>
>>  if (is_vid_mode(intel_dsi)) {
>>  /* Send Shutdown command to the panel in LP mode */ @@ -
>1133,7
>>

[Intel-gfx] [RFC CABC v3 PATCH 2/2] drm/i915: CABC support for backlight control

2015-09-10 Thread Deepak M

In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.

The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.

In this design there will be no PWM signal from the SoC and DCS
commands are sent to enable and control the backlight brightness.

v2:
- Created a new backlight driver for cabc, which will be registered
  only when it cabc is supported by panel. (Daniel Vetter)
v3:
- Use for_each_dsi_port macro for handling port C also (Gaurav)
- Rebase

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/Makefile  |1 +
 drivers/gpu/drm/i915/intel_dsi.c   |   18 +++---
 drivers/gpu/drm/i915/intel_panel.c |   23 +++
 include/video/mipi_display.h   |8 
 4 files changed, 43 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44d290a..d87c690 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -82,6 +82,7 @@ i915-y += dvo_ch7017.o \
  intel_dsi.o \
  intel_dsi_panel_vbt.o \
  intel_dsi_pll.o \
+ intel_dsi_cabc.o \
  intel_dvo.o \
  intel_hdmi.o \
  intel_i2c.o \
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 781c267..1d98ed8 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -35,6 +35,7 @@
 #include "i915_drv.h"
 #include "intel_drv.h"
 #include "intel_dsi.h"
+#include "intel_dsi_cabc.h"
 
 static const struct {
u16 panel_id;
@@ -398,7 +399,10 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
intel_dsi_port_enable(encoder);
}
 
-   intel_panel_enable_backlight(intel_dsi->attached_connector);
+   if (dev_priv->vbt.dsi.config->cabc_supported)
+   cabc_enable_backlight(intel_dsi->attached_connector);
+   else
+   intel_panel_enable_backlight(intel_dsi->attached_connector);
 }
 
 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
@@ -458,12 +462,17 @@ static void intel_dsi_enable_nop(struct intel_encoder 
*encoder)
 
 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 {
+   struct drm_device *dev = encoder->base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
enum port port;
 
DRM_DEBUG_KMS("\n");
 
-   intel_panel_disable_backlight(intel_dsi->attached_connector);
+   if (dev_priv->vbt.dsi.config->cabc_supported)
+   cabc_disable_backlight(intel_dsi->attached_connector);
+   else
+   intel_panel_disable_backlight(intel_dsi->attached_connector);
 
if (is_vid_mode(intel_dsi)) {
/* Send Shutdown command to the panel in LP mode */
@@ -1133,7 +1142,10 @@ void intel_dsi_init(struct drm_device *dev)
}
 
intel_panel_init(_connector->panel, fixed_mode, NULL);
-   intel_panel_setup_backlight(connector, INVALID_PIPE);
+   if (dev_priv->vbt.dsi.config->cabc_supported)
+   cabc_setup_backlight(connector, INVALID_PIPE);
+   else
+   intel_panel_setup_backlight(connector, INVALID_PIPE);
 
return;
 
diff --git a/drivers/gpu/drm/i915/intel_panel.c 
b/drivers/gpu/drm/i915/intel_panel.c
index e2ab3f6..ff2e586 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -34,6 +34,7 @@
 #include 
 #include 
 #include "intel_drv.h"
+#include "intel_dsi_cabc.h"
 
 #define CRC_PMIC_PWM_PERIOD_NS 21333
 
@@ -1586,15 +1587,29 @@ void intel_panel_fini(struct intel_panel *panel)
 void intel_backlight_register(struct drm_device *dev)
 {
struct intel_connector *connector;
+   struct drm_i915_private *dev_priv = dev->dev_private;
 
-   list_for_each_entry(connector, >mode_config.connector_list, 
base.head)
-   intel_backlight_device_register(connector);
+   list_for_each_entry(connector, >mode_config.connector_list,
+   base.head) {
+   if (connector->encoder->type == INTEL_OUTPUT_DSI &&
+   dev_priv->vbt.dsi.config->cabc_supported)
+   cabc_backlight_device_register(connector);
+   else
+   intel_backlight_device_register(connector);
+   }
 }
 
 void intel_backlight_unregister(struct drm_device *dev)
 {
struct intel_connector *connector;
+   struct drm_i915_private *dev_priv = dev->dev_private;
 
-   list_for_each_e

[Intel-gfx] [RFC CABC v3 PATCH 1/2] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT

2015-09-10 Thread Deepak M

For dual link panel scenarios there are new fileds added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.

v2: Rebase
v3: Rebase

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c |   13 +
 drivers/gpu/drm/i915/intel_bios.h |5 -
 drivers/gpu/drm/i915/intel_dsi.h  |2 ++
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index c8acc29..dacfadd 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -789,6 +789,19 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct 
bdb_header *bdb)
return;
}
 
+   /*
+* These below bits will inform us on which port the panel blk_cntrl and
+* CABC ON/OFF commands needs to be sent in case of dual link panels
+*  u16 dl_cabc_port:2;
+*  u16 pwm_bkl_ctrl:2;
+* But these are introduced from the VBT version 197 onwards, so making
+* sure that these bits are zero in the pervious versions.
+*/
+   if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+   dev_priv->vbt.dsi.config->dl_cabc_port = 0;
+   dev_priv->vbt.dsi.config->pwm_bkl_ctrl = 0;
+   }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 
diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index 1b7417e..544b51d 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -834,7 +834,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
-   u16 rsvd3:9;
+   u16 rgb_flip:1;
+   u16 dl_cabc_port:2;
+   u16 pwm_bkl_ctrl:2;
+   u16 rsvd3:4;
 
u16 rsvd4;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 42a6859..c727d7b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -74,6 +74,8 @@ struct intel_dsi {
 
u8 escape_clk_div;
u8 dual_link;
+   u8 dl_cabc_port;
+   u8 pwm_blk_ctrl;
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
-- 
1.7.9.5

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[Intel-gfx] [RFC CABC v3 PATCH 0/2] CABC patch list

2015-09-10 Thread Deepak M

CABC stands for the Content Adaptive Backlight Control.
In the normal display the backlight which we see is due to the
backlight which is being modulated by the filter, which is inturn
dependent on the image. In brief the CABC does the histogram
analysis of the image and then controls the filter and backlight.
For example in CABC to display the dark image the backlight is dimmed
and then controlls the filter to allow more light, because of
which is power consuption will be reduced.

Below are the inital set of patches which supports the CABC.
A field exits in the mipi configuration of the VBT which
when enabled indiactes the CABC is supported. Depending on
this filed the backlight control function pointer are
initalized in the intel_panel.c file.

In case of dual link panels depending on the panel
the DCS commands have to be send to either PORT A,
PORT C or both PORT A and PORT C. Again a filed is
added in the VBT to get this data from the version 197 onwards.
One of the below patches parses these fields from the
VBT.

v3:
- removed the first patch from the list as it was not necessary
- addressed Daniel and Gaurav`s comments.

Deepak M (2):
  drm/i915: Parsing the PWM cntrl and CABC ON/OFF fileds in VBT
  drm/i915: CABC support for backlight control

 drivers/gpu/drm/i915/Makefile  |1 +
 drivers/gpu/drm/i915/intel_bios.c  |   13 +
 drivers/gpu/drm/i915/intel_bios.h  |5 -
 drivers/gpu/drm/i915/intel_dsi.c   |   18 +++---
 drivers/gpu/drm/i915/intel_dsi.h   |2 ++
 drivers/gpu/drm/i915/intel_panel.c |   23 +++
 include/video/mipi_display.h   |8 
 7 files changed, 62 insertions(+), 8 deletions(-)

-- 
1.7.9.5

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[Intel-gfx] [MIPI SEQ PARSING v2 PATCH 07/11] drm/i915: Added the generic gpio sequence support and gpio table

2015-09-09 Thread Deepak M

The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.

v2: Move changes in sideband.c file to new patch(Jani), rebase

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h|5 +
 drivers/gpu/drm/i915/intel_dsi.h   |  351 
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  215 -
 3 files changed, 559 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84ed9ab..5bef50c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -568,6 +568,11 @@
 #define   IOSF_PORT_DPIO   0x12
 #define   IOSF_PORT_DPIO_2 0x1a
 #define   IOSF_PORT_GPIO_NC0x13
+#define   IOSF_PORT_GPIO_SC0x48
+#define   IOSF_PORT_GPIO_SUS   0xA8
+#define   MAX_GPIO_NUM_NC  26
+#define   MAX_GPIO_NUM_SC  128
+#define   MAX_GPIO_NUM 172
 #define   IOSF_PORT_CCK0x14
 #define   IOSF_PORT_CCU0xA9
 #define   IOSF_PORT_GPS_CORE   0x48
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 42a6859..fc89a6b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,357 @@
 #define DSI_DUAL_LINK_FRONT_BACK   1
 #define DSI_DUAL_LINK_PIXEL_ALT2
 
+#define HV_DDI0_HPD_GPIONC_0_PCONF00x4130
+#define HV_DDI0_HPD_GPIONC_0_PAD   0x4138
+#define HV_DDI0_DDC_SDA_GPIONC_1_PCONF00x4120
+#define HV_DDI0_DDC_SDA_GPIONC_1_PAD   0x4128
+#define HV_DDI0_DDC_SCL_GPIONC_2_PCONF00x4110
+#define HV_DDI0_DDC_SCL_GPIONC_2_PAD   0x4118
+#define PANEL0_VDDEN_GPIONC_3_PCONF0   0x4140
+#define PANEL0_VDDEN_GPIONC_3_PAD  0x4148
+#define PANEL0_BKLTEN_GPIONC_4_PCONF0  0x4150
+#define PANEL0_BKLTEN_GPIONC_4_PAD 0x4158
+#define PANEL0_BKLTCTL_GPIONC_5_PCONF0 0x4160
+#define PANEL0_BKLTCTL_GPIONC_5_PAD0x4168
+#define HV_DDI1_HPD_GPIONC_6_PCONF00x4180
+#define HV_DDI1_HPD_GPIONC_6_PAD   0x4188
+#define HV_DDI1_DDC_SDA_GPIONC_7_PCONF00x4190
+#define HV_DDI1_DDC_SDA_GPIONC_7_PAD   0x4198
+#define HV_DDI1_DDC_SCL_GPIONC_8_PCONF00x4170
+#define HV_DDI1_DDC_SCL_GPIONC_8_PAD   0x4178
+#define PANEL1_VDDEN_GPIONC_9_PCONF0   0x4100
+#define PANEL1_VDDEN_GPIONC_9_PAD  0x4108
+#define PANEL1_BKLTEN_GPIONC_10_PCONF0 0x40E0
+#define PANEL1_BKLTEN_GPIONC_10_PAD0x40E8
+#define PANEL1_BKLTCTL_GPIONC_11_PCONF00x40F0
+#define PANEL1_BKLTCTL_GPIONC_11_PAD   0x40F8
+#define GP_INTD_DSI_TE1_GPIONC_12_PCONF0   0x40C0
+#define GP_INTD_DSI_TE1_GPIONC_12_PAD  0x40C8
+#define HV_DDI2_DDC_SDA_GPIONC_13_PCONF0   0x41A0
+#define HV_DDI2_DDC_SDA_GPIONC_13_PAD  0x41A8
+#define HV_DDI2_DDC_SCL_GPIONC_14_PCONF0   0x41B0
+#define HV_DDI2_DDC_SCL_GPIONC_14_PAD  0x41B8
+#define GP_CAMERASB00_GPIONC_15_PCONF0 0x4010
+#define GP_CAMERASB00_GPIONC_15_PAD0x4018
+#define GP_CAMERASB01_GPIONC_16_PCONF0 0x4040
+#define GP_CAMERASB01_GPIONC_16_PAD0x4048
+#define GP_CAMERASB02_GPIONC_17_PCONF0 0x4080
+#define GP_CAMERASB02_GPIONC_17_PAD0x4088
+#define GP_CAMERASB03_GPIONC_18_PCONF0 0x40B0
+#define GP_CAMERASB03_GPIONC_18_PAD0x40B8
+#define GP_CAMERASB04_GPIONC_19_PCONF0 0x4000
+#define GP_CAMERASB04_GPIONC_19_PAD0x4008
+#define GP_CAMERASB05_GPIONC_20_PCONF0 0x4030
+#define GP_CAMERASB05_GPIONC_20_PAD0x4038
+#define GP_CAMERASB06_GPIONC_21_PCONF0 0x4060
+#define GP_CAMERASB06_GPIONC_21_PAD0x4068
+#define GP_CAMERASB07_GPIONC_22_PCONF0 0x40A0
+#define GP_CAMERASB07_GPIONC_22_PAD0x40A8
+#define GP_CAMERASB08_GPIONC_23_PCONF0 0x40D0
+#define GP_CAMERASB08_GPIONC_23_PAD0x40D8
+#define GP_CAMERASB09_GPIONC_24_PCONF0 0x4020
+#define GP_CAMERASB09_GPIONC_24_PAD0x4028
+#define GP_CAMERASB10_GPIONC_25_PCONF0 0x4050
+#define GP_CAMERASB10_GPIONC_25_PAD0x4058
+#define GP_CAMERASB11_GPIONC_26_PCONF0 0x4090
+#define GP_CAMERASB11_GPIONC_26_PAD0x4098
+
+#define SATA_GP0_GPIOC_0_PCONF00x4550
+#define SATA_GP0_GPIOC_0_PAD   0x4558
+#define SATA_GP1_GPIOC_1_PCONF00x4590
+#define SATA_GP1_GPIOC_1_PAD   0x4598
+#define SATA_LEDN_GPIOC_2_PCONF0   0x45D0
+#define SATA_LEDN_GPIOC_2_PAD  0x45D8
+#

[Intel-gfx] [MIPI SEQ PARSING v2 PATCH 09/11] drm: Add few more wrapper functions for drm panel

2015-09-09 Thread Deepak M

Currently there are few pair of functions which
are called during the panel enable/disable sequence.
To improve the granularity, adding few more wrapper
functions so that the functions are more specific
on what they are doing.

v2: rebase

Signed-off-by: Deepak M <m.dee...@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
---
 include/drm/drm_panel.h |   47 +++
 1 file changed, 47 insertions(+)

diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 13ff44b..c729f6d 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -73,6 +73,12 @@ struct drm_panel_funcs {
int (*get_modes)(struct drm_panel *panel);
int (*get_timings)(struct drm_panel *panel, unsigned int num_timings,
   struct display_timing *timings);
+   int (*power_on)(struct drm_panel *panel);
+   int (*power_off)(struct drm_panel *panel);
+   int (*backlight_on)(struct drm_panel *panel);
+   int (*backlight_off)(struct drm_panel *panel);
+   int (*get_info)(struct drm_panel *panel,
+   struct drm_connector *connector);
 };
 
 struct drm_panel {
@@ -117,6 +123,47 @@ static inline int drm_panel_enable(struct drm_panel *panel)
return panel ? -ENOSYS : -EINVAL;
 }
 
+static inline int drm_panel_power_on(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->power_on)
+   return panel->funcs->power_on(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_power_off(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->power_off)
+   return panel->funcs->power_off(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_backlight_on(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->backlight_on)
+   return panel->funcs->backlight_on(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_backlight_off(struct drm_panel *panel)
+{
+   if (panel && panel->funcs && panel->funcs->backlight_off)
+   return panel->funcs->backlight_off(panel);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_get_info(struct drm_panel *panel,
+   struct drm_connector *connector)
+{
+   if (connector && panel && panel->funcs && panel->funcs->get_info)
+   return panel->funcs->get_info(panel, connector);
+
+   return panel ? -ENOSYS : -EINVAL;
+}
+
 static inline int drm_panel_get_modes(struct drm_panel *panel)
 {
if (panel && panel->funcs && panel->funcs->get_modes)
-- 
1.7.9.5

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[Intel-gfx] [MIPI SEQ PARSING v2 PATCH 08/11] drm/i915: GPIO for CHT generic MIPI

2015-09-09 Thread Deepak M

From: Yogesh Mohan Marimuthu 

The GPIO configuration and register offsets are different from
baytrail for cherrytrail. Port the gpio programming accordingly
for cherrytrail in this patch.

v2: Rebase

Signed-off-by: Yogesh Mohan Marimuthu 
---
 drivers/gpu/drm/i915/i915_reg.h|   23 ++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  117 +++-
 2 files changed, 122 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5bef50c..c5bea41 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -568,11 +568,21 @@
 #define   IOSF_PORT_DPIO   0x12
 #define   IOSF_PORT_DPIO_2 0x1a
 #define   IOSF_PORT_GPIO_NC0x13
+#define   CHV_IOSF_PORT_GPIO_N 0x13
 #define   IOSF_PORT_GPIO_SC0x48
+#define   CHV_IOSF_PORT_GPIO_SE0x48
+#define   CHV_IOSF_PORT_GPIO_SW0xB2
 #define   IOSF_PORT_GPIO_SUS   0xA8
+#define   CHV_IOSF_PORT_GPIO_E 0xA8
 #define   MAX_GPIO_NUM_NC  26
 #define   MAX_GPIO_NUM_SC  128
 #define   MAX_GPIO_NUM 172
+#define   CHV_MAX_GPIO_NUM_N   72
+#define   CHV_MAX_GPIO_NUM_SE  99
+#define   CHV_MAX_GPIO_NUM_SW  197
+#define   CHV_MIN_GPIO_NUM_SE  73
+#define   CHV_MIN_GPIO_NUM_SW  100
+#define   CHV_MIN_GPIO_NUM_E   198
 #define   IOSF_PORT_CCK0x14
 #define   IOSF_PORT_CCU0xA9
 #define   IOSF_PORT_GPS_CORE   0x48
@@ -580,6 +590,19 @@
 #define VLV_IOSF_DATA  (VLV_DISPLAY_BASE + 0x2104)
 #define VLV_IOSF_ADDR  (VLV_DISPLAY_BASE + 0x2108)
 
+#define VLV_GPIO_CFG   0x2000CC00
+#define VLV_GPIO_INPUT_DIS 0x04
+
+#define CHV_PAD_FMLY_BASE  0x4400
+#define CHV_PAD_FMLY_SIZE  0x400
+#define CHV_PAD_CFG_0_1_REG_SIZE   0x8
+#define CHV_PAD_CFG_REG_SIZE   0x4
+#define CHV_VBT_MAX_PINS_PER_FMLY  15
+
+#define CHV_GPIO_CFG_UNLOCK0x
+#define CHV_GPIO_CFG_HiZ   0x8100
+#define CHV_GPIO_CFG_TX_STATE_SHIFT1
+
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC0x11
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 1aa5b19..b0d09f6 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -418,17 +418,75 @@ static const u8 *mipi_exec_delay(struct intel_dsi 
*intel_dsi, const u8 *data)
 
return data;
 }
-
-static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+static int chv_program_gpio(struct intel_dsi *intel_dsi,
+   const u8 *data, const u8 **cur_data)
 {
+   struct drm_device *dev = intel_dsi->base.base.dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
u8 gpio, action;
+   u16 family_num;
u16 function, pad;
-   u32 val;
u8 block;
+
+   /*
+* Skipping the first byte as it is of no
+* interest for linux kernel in new VBT version
+*/
+   if (dev_priv->vbt.dsi.seq_version >= 3)
+   data++;
+
+   gpio = *data++;
+
+   /* pull up/down */
+   action = *data++;
+
+   if (dev_priv->vbt.dsi.seq_version >= 3) {
+   if (gpio <= CHV_MAX_GPIO_NUM_N) {
+   block = CHV_IOSF_PORT_GPIO_N;
+   DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
+   } else if (gpio <= CHV_MAX_GPIO_NUM_SE) {
+   block = CHV_IOSF_PORT_GPIO_SE;
+   gpio = gpio - CHV_MIN_GPIO_NUM_SE;
+   DRM_DEBUG_DRIVER("GPIO is in the south east Block\n");
+   } else if (gpio <= CHV_MAX_GPIO_NUM_SW) {
+   block = CHV_IOSF_PORT_GPIO_SW;
+   gpio = gpio - CHV_MIN_GPIO_NUM_SW;
+   DRM_DEBUG_DRIVER("GPIO is in the south west Block\n");
+   } else {
+   block = CHV_IOSF_PORT_GPIO_E;
+   gpio = gpio - CHV_MIN_GPIO_NUM_E;
+   DRM_DEBUG_DRIVER("GPIO is in the east Block\n");
+   }
+   } else
+   block = IOSF_PORT_GPIO_NC;
+
+   family_num =  gpio / CHV_VBT_MAX_PINS_PER_FMLY;
+   gpio = gpio - (family_num * CHV_VBT_MAX_PINS_PER_FMLY);
+   pad = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) +
+   (((u16)gpio)

[Intel-gfx] [MIPI SEQ PARSING v2 PATCH 06/11] drm/i915: extending gpio read/write to other cores

2015-09-09 Thread Deepak M

Adding a argument to the gpio read/write functions
which accepts the block name.

v2: rebase

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h|5 +++--
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |4 ++--
 drivers/gpu/drm/i915/intel_sideband.c  |9 +
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91ccbc6..ed3b19b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3363,8 +3363,9 @@ int sandybridge_pcode_write(struct drm_i915_private 
*dev_priv, u32 mbox, u32 val
 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg);
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+   u32 reg, u32 val);
 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index c6a6fa1..02f1cd5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -276,14 +276,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
if (!gtable[gpio].init) {
/* program the function */
/* FIXME: remove constant below */
-   vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
+   vlv_gpio_write(dev_priv, IOSF_PORT_GPIO_NC, function, 
0x2000CC00);
gtable[gpio].init = 1;
}
 
val = 0x4 | action;
 
/* pull up/down */
-   vlv_gpio_nc_write(dev_priv, pad, val);
+   vlv_gpio_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
mutex_unlock(_priv->sb_lock);
 
return data;
diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
b/drivers/gpu/drm/i915/intel_sideband.c
index 8831fc5..3e0cbe6 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 
addr)
return val;
 }
 
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg)
 {
u32 val = 0;
-   vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+   vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
SB_CRRDDA_NP, reg, );
return val;
 }
 
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+   u32 reg, u32 val)
 {
-   vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+   vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
SB_CRWRDA_NP, reg, );
 }
 
-- 
1.7.9.5

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