[Intel-gfx] [PATCH 2/2] drm/i915/glk: Program pre_csc_gamma with unity gamma
From: Dhanya
For GLK, Pre-CSC Gamma correction get enabled/disabled based
on "Pipe CSC Enable" bit in the PLANE_COLOR_CTL.
This patch programs Unity Gamma in these registers.
Signed-off-by: Dhanya
---
drivers/gpu/drm/i915/i915_reg.h| 13 +
drivers/gpu/drm/i915/intel_color.c | 35 +++
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index be756bd..ab6684d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8512,6 +8512,19 @@ enum {
#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A,
_PAL_PREC_GC_MAX_B) + (i) * 4)
#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
+/*pipe pre-csc gamma LUTS on GEN10+*/
+#define PRE_CSC_GAMMA_AUTO_INCREMENT (1 << 10)
+#define PRE_CSC_GAMMA_LUT_SIZE 35
+#define _PRE_CSC_GAMMA_INDEX_A 0x4A484
+#define _PRE_CSC_GAMMA_INDEX_B 0x4AC84
+#define _PRE_CSC_GAMMA_INDEX_C 0x4B484
+#define _PRE_CSC_GAMMA_DATA_A 0x4A488
+#define _PRE_CSC_GAMMA_DATA_B 0x4AC88
+#define _PRE_CSC_GAMMA_DATA_C 0x4B488
+
+#define PRE_CSC_GAMMA_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMMA_INDEX_A,
_PRE_CSC_GAMMA_INDEX_B)
+#define PRE_CSC_GAMMA_DATA(pipe)_MMIO_PIPE(pipe, _PRE_CSC_GAMMA_DATA_A,
_PRE_CSC_GAMMA_DATA_B)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 8bfcdcd..05dcaa6 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -91,6 +91,32 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t
*input)
}
}
+/*Set up the Pre-CSC Gamma correction for Gen9+*/
+static void i9xx_load_pre_csc_gamma_lut(struct drm_crtc_state *crtc_state)
+{
+ struct drm_crtc *crtc = crtc_state->crtc;
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int i, pipe = intel_crtc->pipe;
+
+ I915_WRITE(PRE_CSC_GAMMA_INDEX(pipe),
+ PRE_CSC_GAMMA_AUTO_INCREMENT);
+
+ for (i = 0; i < PRE_CSC_GAMMA_LUT_SIZE; i++) {
+ uint32_t v = (i * ((1 << 16) - 1));
+
+ I915_WRITE(PRE_CSC_GAMMA_DATA(pipe), v);
+ }
+ /*
+* Reset the index, otherwise it prevents the legacy palette to be
+* written properly.
+*/
+ I915_WRITE(PRE_CSC_GAMMA_INDEX(pipe), 0);
+
+}
+
+
/* Set up the pipe CSC unit. */
static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
{
@@ -101,6 +127,15 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state
*crtc_state)
uint16_t coeffs[9] = { 0, };
struct intel_crtc_state *intel_crtc_state =
to_intel_crtc_state(crtc_state);
+ /*
+*For Gen9_LP+ Pre-CSC Gamma correction get enabled/disabled based on
+*"Pipe CSC Enable" bit in the PLANE_COLOR_CTL. We need to program 1:1
+* gamma value in these.
+*/
+
+ if (IS_GEN9_LP(dev_priv) && !IS_BROXTON(dev_priv))
+ i9xx_load_pre_csc_gamma_lut(crtc_state);
+
if (crtc_state->ctm) {
struct drm_color_ctm *ctm =
(struct drm_color_ctm *)crtc_state->ctm->data;
--
1.9.1
___
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[Intel-gfx] [PATCH 0/2] Pipe CSC and Gamma Enabling for GLK.
From: Dhanya This series contains patches for enabling CSC and Gamma for GLK. Also, it programs unity gamma to Pre-CSC Gamma lut for GLK+. Tested on GLK silicon. Dhanya (2): drm/i915/glk: Enable Pipe Level CSC & Gamma Feature. drm/i915/glk: Program pre_csc_gamma with unity gamma drivers/gpu/drm/i915/i915_reg.h | 13 + drivers/gpu/drm/i915/intel_color.c | 37 +++- drivers/gpu/drm/i915/intel_display.c | 18 +- 3 files changed, 62 insertions(+), 6 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/glk: Enable Pipe Level CSC & Gamma Feature.
From: Dhanya
For GLK, we need to program new register PLANE_COLOR_CTL
for enabling CSC and Gamma. This patch sets the pipe gamma
and pipe csc bit in the PLANE_COLOR_CTL.
Signed-off-by: Dhanya
---
drivers/gpu/drm/i915/intel_color.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 18 +-
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index f0f2d04..8bfcdcd 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -538,7 +538,7 @@ void intel_color_init(struct drm_crtc *crtc)
dev_priv->display.load_luts = haswell_load_luts;
} else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv) ||
- IS_COFFEELAKE(dev_priv)) {
+ IS_COFFEELAKE(dev_priv) || IS_GEN9_LP(dev_priv)) {
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
dev_priv->display.load_luts = broadwell_load_luts;
} else {
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 266b03f..d91a456 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3441,9 +3441,19 @@ static void skylake_update_primary_plane(struct
drm_plane *plane,
int dst_w = drm_rect_width(&plane_state->base.dst);
int dst_h = drm_rect_height(&plane_state->base.dst);
- plane_ctl = PLANE_CTL_ENABLE |
- PLANE_CTL_PIPE_GAMMA_ENABLE |
- PLANE_CTL_PIPE_CSC_ENABLE;
+ plane_ctl = PLANE_CTL_ENABLE;
+
+ if (IS_GEN9_LP(dev_priv) && !IS_BROXTON(dev_priv)) {
+ I915_WRITE(PLANE_COLOR_CTL(pipe, 0),
+ PLANE_CTL_PLANE_GAMMA_DISABLE |
+ PLANE_CTL_PIPE_GAMMA_ENABLE |
+ PLANE_CTL_PIPE_CSC_ENABLE);
+ } else {
+ plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE |
+ PLANE_CTL_PIPE_CSC_ENABLE |
+ PLANE_CTL_PLANE_GAMMA_DISABLE;
+ }
+
plane_ctl |= skl_plane_ctl_format(fb->format->format);
plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
@@ -3466,8 +3476,6 @@ static void skylake_update_primary_plane(struct drm_plane
*plane,
I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
- if (IS_GEMINILAKE(dev_priv))
- I915_WRITE(PLANE_COLOR_CTL(pipe, 0), PLANE_GAMMA_DISABLE);
if (scaler_id >= 0) {
uint32_t ps_ctrl = 0;
--
1.9.1
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[Intel-gfx] [PATCH i-g-t] tests/kms_color:Color i-g-t
From: Dhanya
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma for BDW/SKL/BXT and CHT supported.
Signed-off-by: Dhanya
---
tests/.gitignore |1 +
tests/Makefile.sources |1 +
tests/kms_color.c | 1014
3 files changed, 1016 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/.gitignore b/tests/.gitignore
index 7f20f2b..6fc4782 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -130,6 +130,7 @@ gen7_forcewake_mt
kms_3d
kms_addfb_basic
kms_atomic
+kms_color
kms_crtc_background_color
kms_cursor_crc
kms_draw_crc
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d594038..f2af648 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -68,6 +68,7 @@ TESTS_progs_M = \
gem_write_read_ring_switch \
kms_addfb_basic \
kms_atomic \
+ kms_color \
kms_cursor_crc \
kms_draw_crc \
kms_fbc_crc \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..dd3c2fb
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,1014 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ * Authors:
+ * Dhanya Pillai
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "drmtest.h"
+#include "drm.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+
+
+IGT_TEST_DESCRIPTION("Test Color Features at Pipe level");
+/*
+
+This tool tests the following color features:
+ CTM, GAMMA(8/10/12/split/legacy) and De-gamma.
+Few negative test cases are also included
+
+Tests willl enable one primary and one sprite plane and apply
+the specific color feature and do the verification by CRC checks.
+*/
+
+#define CSC_MAX_VALS9
+#define BDW_SPLITGAMMA_MAX_VALS512
+#define BDW_8BIT_GAMMA_MAX_VALS256
+#define BDW_10BIT_GAMMA_MAX_VALS 1024
+#define BDW_12BIT_GAMMA_MAX_VALS 513
+#define BDW_MAX_GAMMA ((1 << 24) - 1)
+#define BDW_MIN_GAMMA 0
+
+#define RED_FB 0
+#define GREEN_FB 1
+#define BLUE_FB 2
+
+#ifndef drm_r32g32b32
+struct drm_r32g32b32 {
+ __u32 r32;
+ __u32 g32;
+ __u32 b32;
+ __u32 reserved;
+};
+#endif
+#ifndef drm_palette
+struct drm_palette {
+ struct drm_r32g32b32 lut[0];
+};
+#endif
+#ifndef drm_ctm
+ struct drm_ctm {
+ __s64 ctm_coeff[9];
+};
+#endif
+#ifndef drm_palette_caps
+struct drm_palette_caps {
+ __u32 version;
+ __u32 reserved;
+ __u32 num_samples_before_ctm;
+ __u32 num_samples_after_ctm;
+};
+#endif
+
+enum ctm_color {
+ RED,
+ GREEN,
+ BLUE,
+ REVERSE,
+ NEGATIVE,
+ FRACTION
+};
+
+enum blob {
+ INVALID_BLOB_ID,
+ INVALID_BLOB_DATA,
+ INVALID_BLOB_LENGTH,
+ INVALID_BLOB_ID_SMALL,
+ INVALID_BLOB_NULL
+};
+
+enum color_property {
+ ctm_property,
+ legacy_gamma,
+ gamma_property_8bit,
+ gamma_property_10bit,
+ gamma_property_12bit,
+ gamma_property_split
+};
+static const float ctm_red[9] = {1, 1, 1, 0, 0, 0, 0, 0, 0};
+static const float ctm_green[9] = {0, 0, 0, 1, 1, 1, 0, 0, 0};
+static const float ctm_blue[9] = {0, 0, 0, 0, 0, 0, 1, 1, 1};
+static const float ctm_identity[9] = {1, 0, 0, 0, 1, 0, 0, 0, 1};
+static const float ctm_reverse[9] = {0, 0, 1, 0, 1, 0, 1, 0, 0};
+static const float ctm_negative[9] = {-1, -1, -1, -1, -1, -1, -1, -1, -1};
+static const float ctm_fraction[9] = {1234567.7652, 0.12334, 0.9898989,
0.45454545, 0.12121212, 0.2323
[Intel-gfx] [PATCH i-g-t] tests/kms_color:Color i-g-t
From: Dhanya
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma for SKL/BXT supported.
Signed-off-by: Dhanya
---
tests/.gitignore |1 +
tests/Makefile.sources |1 +
tests/kms_color.c | 1039
3 files changed, 1041 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/.gitignore b/tests/.gitignore
index 7f20f2b..6fc4782 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -130,6 +130,7 @@ gen7_forcewake_mt
kms_3d
kms_addfb_basic
kms_atomic
+kms_color
kms_crtc_background_color
kms_cursor_crc
kms_draw_crc
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d594038..f2af648 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -68,6 +68,7 @@ TESTS_progs_M = \
gem_write_read_ring_switch \
kms_addfb_basic \
kms_atomic \
+ kms_color \
kms_cursor_crc \
kms_draw_crc \
kms_fbc_crc \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..b1b64e7
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,1039 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Dhanya Pillai
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "drmtest.h"
+#include "drm.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+
+
+IGT_TEST_DESCRIPTION("Test Color Features at Pipe level");
+/*
+
+This tool tests the following color features:
+ CTM, GAMMA(8/10/12/split/legacy) and De-gamma.
+Few negative test cases are also included
+
+Tests willl enable one primary and one sprite plane and apply
+the specific color feature and do the verification by CRC checks.
+*/
+
+#define CSC_MAX_VALS9
+#define BDW_SPLITGAMMA_MAX_VALS512
+#define BDW_8BIT_GAMMA_MAX_VALS256
+#define BDW_10BIT_GAMMA_MAX_VALS 1024
+#define BDW_12BIT_GAMMA_MAX_VALS 513
+#define BDW_MAX_GAMMA ((1 << 24) - 1)
+#define BDW_MIN_GAMMA 0
+
+#define RED_FB 0
+#define GREEN_FB 1
+#define BLUE_FB 2
+
+#ifndef drm_r32g32b32
+struct drm_r32g32b32 {
+ __u32 r32;
+ __u32 g32;
+ __u32 b32;
+ __u32 reserved;
+};
+#endif
+#ifndef drm_palette
+struct drm_palette {
+ struct drm_r32g32b32 lut[0];
+};
+#endif
+#ifndef drm_ctm
+ struct drm_ctm {
+ __s64 ctm_coeff[9];
+};
+#endif
+#ifndef drm_palette_caps
+struct drm_palette_caps {
+ __u32 version;
+ __u32 reserved;
+ __u32 num_samples_before_ctm;
+ __u32 num_samples_after_ctm;
+};
+#endif
+
+enum ctm_color {
+ RED,
+ GREEN,
+ BLUE,
+ REVERSE,
+ NEGATIVE,
+ FRACTION
+};
+
+enum blob {
+ INVALID_BLOB_ID,
+ INVALID_BLOB_DATA,
+ INVALID_BLOB_LENGTH,
+ INVALID_BLOB_ID_SMALL,
+ INVALID_BLOB_NULL
+};
+
+enum color_property {
+ ctm_property,
+ legacy_gamma,
+ gamma_property_8bit,
+ gamma_property_10bit,
+ gamma_property_12bit,
+ gamma_property_split
+};
+static const float ctm_red[9] = {1, 1, 1, 0, 0, 0, 0, 0, 0};
+static const float ctm_green[9] = {0, 0, 0, 1, 1, 1, 0, 0, 0};
+static const float ctm_blue[9] = {0, 0, 0, 0, 0, 0, 1, 1, 1};
+static const float ctm_identity[9] = {1, 0, 0, 0, 1, 0, 0, 0, 1};
+static const float ctm_reverse[9] = {0, 0, 1, 0, 1, 0, 1, 0, 0};
+static const float ctm_negative[9] = {-1, -1, -1, -1, -1, -1, -1, -1, -1};
+static const float ctm_fraction[9] = {1234567.7652, 0.12334, 0.9898989,
0.45454545, 0.12121212, 0.232323, 3.98768,
[Intel-gfx] [PATCH i-g-t] tests/kms_color:Color i-g-t
From: Dhanya
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma for SKL/BXT supported.
Signed-off-by: Dhanya
---
tests/.gitignore |1 +
tests/Makefile.sources |1 +
tests/kms_color.c | 1037
3 files changed, 1039 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/.gitignore b/tests/.gitignore
index 7f20f2b..6fc4782 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -130,6 +130,7 @@ gen7_forcewake_mt
kms_3d
kms_addfb_basic
kms_atomic
+kms_color
kms_crtc_background_color
kms_cursor_crc
kms_draw_crc
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d594038..f2af648 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -68,6 +68,7 @@ TESTS_progs_M = \
gem_write_read_ring_switch \
kms_addfb_basic \
kms_atomic \
+ kms_color \
kms_cursor_crc \
kms_draw_crc \
kms_fbc_crc \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..16cfd44
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,1037 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "drmtest.h"
+#include "drm.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+
+
+IGT_TEST_DESCRIPTION("Test Color Features at Pipe level");
+/*
+
+This tool tests the following color features:
+ CTM, GAMMA(8/10/12/split/legacy) and De-gamma.
+Few negative test cases are also included
+
+Tests willl enable one primary and one sprite plane and apply
+the specific color feature and do the verification by CRC checks.
+*/
+
+#define CSC_MAX_VALS9
+#define BDW_SPLITGAMMA_MAX_VALS512
+#define BDW_8BIT_GAMMA_MAX_VALS256
+#define BDW_10BIT_GAMMA_MAX_VALS 1024
+#define BDW_12BIT_GAMMA_MAX_VALS 513
+#define BDW_MAX_GAMMA ((1 << 24) - 1)
+#define BDW_MIN_GAMMA 0
+
+#define RED_FB 0
+#define GREEN_FB 1
+#define BLUE_FB 2
+
+#ifndef drm_r32g32b32
+struct drm_r32g32b32 {
+ __u32 r32;
+ __u32 g32;
+ __u32 b32;
+ __u32 reserved;
+};
+#endif
+#ifndef drm_palette
+struct drm_palette {
+ struct drm_r32g32b32 lut[0];
+};
+#endif
+#ifndef drm_ctm
+ struct drm_ctm {
+ __s64 ctm_coeff[9];
+};
+#endif
+#ifndef drm_palette_caps
+struct drm_palette_caps {
+ __u32 version;
+ __u32 reserved;
+ __u32 num_samples_before_ctm;
+ __u32 num_samples_after_ctm;
+};
+#endif
+
+enum ctm_color {
+ RED,
+ GREEN,
+ BLUE,
+ REVERSE,
+ NEGATIVE,
+ FRACTION
+};
+
+enum blob {
+ INVALID_BLOB_ID,
+ INVALID_BLOB_DATA,
+ INVALID_BLOB_LENGTH,
+ INVALID_BLOB_ID_SMALL,
+ INVALID_BLOB_NULL
+};
+
+enum color_property {
+ ctm_property,
+ legacy_gamma,
+ gamma_property_8bit,
+ gamma_property_10bit,
+ gamma_property_12bit,
+ gamma_property_split
+};
+static const float ctm_red[9] = {1, 1, 1, 0, 0, 0, 0, 0, 0};
+static const float ctm_green[9] = {0, 0, 0, 1, 1, 1, 0, 0, 0};
+static const float ctm_blue[9] = {0, 0, 0, 0, 0, 0, 1, 1, 1};
+static const float ctm_identity[9] = {1, 0, 0, 0, 1, 0, 0, 0, 1};
+static const float ctm_reverse[9] = {0, 0, 1, 0, 1, 0, 1, 0, 0};
+static const float ctm_negative[9] = {-1, -1, -1, -1, -1, -1, -1, -1, -1};
+static const float ctm_fraction[9] = {1234567.7652, 0.12334, 0.9898989,
0.45454545, 0.12121212, 0.232323, 3.98768, 0.0, 1.22345};
+
+
+struct framebuffer_color {
+ int red;
+ int green;
+ int blue;
+};
+struct framebuffer_color fb_color = { 0, 0, 0};
[Intel-gfx] [PATCH i-g-t] tests/kms_color:Color i-g-t
From: Dhanya
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma for SKL/BXT supported.
Signed-off-by: Dhanya
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/kms_color.c | 997 +
3 files changed, 999 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/.gitignore b/tests/.gitignore
index 7f20f2b..6fc4782 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -130,6 +130,7 @@ gen7_forcewake_mt
kms_3d
kms_addfb_basic
kms_atomic
+kms_color
kms_crtc_background_color
kms_cursor_crc
kms_draw_crc
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d594038..f2af648 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -68,6 +68,7 @@ TESTS_progs_M = \
gem_write_read_ring_switch \
kms_addfb_basic \
kms_atomic \
+ kms_color \
kms_cursor_crc \
kms_draw_crc \
kms_fbc_crc \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..4f95239
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,997 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "drmtest.h"
+#include "drm.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+
+
+IGT_TEST_DESCRIPTION("Test Color Features at Pipe level");
+/*
+
+This tool tests the following color features:
+ CTM, GAMMA(8/10/12/split/legacy) and De-gamma.
+Few negative test cases are also included
+
+Tests willl enable one primary and one sprite plane and apply
+the specific color feature and do the verification by CRC checks.
+*/
+
+#define CSC_MAX_VALS9
+#define BDW_SPLITGAMMA_MAX_VALS512
+#define BDW_8BIT_GAMMA_MAX_VALS256
+#define BDW_10BIT_GAMMA_MAX_VALS 1024
+#define BDW_12BIT_GAMMA_MAX_VALS 513
+#define BDW_MAX_GAMMA ((1 << 24) - 1)
+#define BDW_MIN_GAMMA 0
+
+#define RED_FB 0
+#define GREEN_FB 1
+#define BLUE_FB 2
+
+#ifndef drm_r32g32b32
+struct drm_r32g32b32 {
+ __u32 r32;
+ __u32 g32;
+ __u32 b32;
+ __u32 reserved;
+};
+#endif
+#ifndef drm_palette
+struct drm_palette {
+ struct drm_r32g32b32 lut[0];
+};
+#endif
+#ifndef drm_ctm
+ struct drm_ctm {
+ __s64 ctm_coeff[9];
+};
+#endif
+enum ctm_color {
+ RED,
+ GREEN,
+ BLUE,
+ REVERSE,
+ NEGATIVE,
+ FRACTION
+};
+
+enum blob {
+ INVALID_BLOB_ID,
+ INVALID_BLOB_DATA,
+ INVALID_BLOB_LENGTH,
+ INVALID_BLOB_ID_SMALL,
+ INVALID_BLOB_NULL
+};
+
+enum color_property {
+ ctm_property,
+ legacy_gamma,
+ gamma_property_8bit,
+ gamma_property_10bit,
+ gamma_property_12bit,
+ gamma_property_split
+};
+static const float ctm_red[9] = {1, 1, 1, 0, 0, 0, 0, 0, 0};
+static const float ctm_green[9] = {0, 0, 0, 1, 1, 1, 0, 0, 0};
+static const float ctm_blue[9] = {0, 0, 0, 0, 0, 0, 1, 1, 1};
+static const float ctm_identity[9] = {1, 0, 0, 0, 1, 0, 0, 0, 1};
+static const float ctm_reverse[9] = {0, 0, 1, 0, 1, 0, 1, 0, 0};
+static const float ctm_negative[9] = {-1, -1, -1, -1, -1, -1, -1, -1, -1};
+static const float ctm_fraction[9] = {1234567.7652, 0.12334, 0.9898989,
0.45454545, 0.12121212, 0.232323, 3.98768, 0.0, 1.22345};
+
+
+struct framebuffer_color {
+ int red;
+ int green;
+ int blue;
+};
+struct framebuffer_color fb_color = { 0, 0, 0};
+
+
+struct data_t {
+ int fb_initial;
+ int drm_fd;
+ int gen;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb1;
[Intel-gfx] [PATCH i-g-t] tests/kms_color:Color i-g-t
From: Dhanya
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma for SKL/BXT supported.
Signed-off-by: Dhanya
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/kms_color.c | 999 +
3 files changed, 1001 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/.gitignore b/tests/.gitignore
index 7f20f2b..6fc4782 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -130,6 +130,7 @@ gen7_forcewake_mt
kms_3d
kms_addfb_basic
kms_atomic
+kms_color
kms_crtc_background_color
kms_cursor_crc
kms_draw_crc
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d594038..f2af648 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -68,6 +68,7 @@ TESTS_progs_M = \
gem_write_read_ring_switch \
kms_addfb_basic \
kms_atomic \
+ kms_color \
kms_cursor_crc \
kms_draw_crc \
kms_fbc_crc \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..d951a09
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,999 @@
+/*
+ * Copyright ?? 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "drmtest.h"
+#include "drm.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+
+
+IGT_TEST_DESCRIPTION("Test Color Features at Pipe level");
+/*
+
+This tool tests the following color features:
+ CTM, GAMMA(8/10/12/split/legacy) and De-gamma.
+Few negative test cases are also included
+
+Tests willl enable one primary and one sprite plane and apply
+the specific color feature and do the verification by CRC checks.
+*/
+
+#define CSC_MAX_VALS9
+#define BDW_SPLITGAMMA_MAX_VALS512
+#define BDW_8BIT_GAMMA_MAX_VALS256
+#define BDW_10BIT_GAMMA_MAX_VALS 1024
+#define BDW_12BIT_GAMMA_MAX_VALS 513
+#define BDW_MAX_GAMMA ((1 << 24) - 1)
+#define BDW_MIN_GAMMA 0
+
+#define RED_FB 0
+#define GREEN_FB 1
+#define BLUE_FB 2
+
+#ifndef drm_r32g32b32
+struct drm_r32g32b32 {
+ __u32 r32;
+ __u32 g32;
+ __u32 b32;
+ __u32 reserved;
+};
+#endif
+#ifndef drm_palette
+struct drm_palette {
+ struct drm_r32g32b32 lut[0];
+};
+#endif
+#ifndef drm_ctm
+ struct drm_ctm {
+ __s64 ctm_coeff[9];
+};
+#endif
+enum ctm_color {
+ RED,
+ GREEN,
+ BLUE,
+ REVERSE,
+ NEGATIVE,
+ FRACTION
+};
+
+enum blob {
+ INVALID_BLOB_ID,
+ INVALID_BLOB_DATA,
+ INVALID_BLOB_LENGTH,
+ INVALID_BLOB_ID_SMALL,
+ INVALID_BLOB_NULL
+};
+
+enum color_property {
+ ctm_property,
+ legacy_gamma,
+ gamma_property_8bit,
+ gamma_property_10bit,
+ gamma_property_12bit,
+ gamma_property_split
+};
+static const float ctm_red[9] = {1, 1, 1, 0, 0, 0, 0, 0, 0};
+static const float ctm_green[9] = {0, 0, 0, 1, 1, 1, 0, 0, 0};
+static const float ctm_blue[9] = {0, 0, 0, 0, 0, 0, 1, 1, 1};
+static const float ctm_identity[9] = {1, 0, 0, 0, 1, 0, 0, 0, 1};
+static const float ctm_reverse[9] = {0, 0, 1, 0, 1, 0, 1, 0, 0};
+static const float ctm_negative[9] = {-1, -1, -1, -1, -1, -1, -1, -1, -1};
+static const float ctm_fraction[9] = {1234567.7652, 0.12334, 0.9898989,
0.45454545, 0.12121212, 0.232323, 3.98768, 0.0, 1.22345};
+
+
+struct framebuffer_color {
+ int red;
+ int green;
+ int blue;
+};
+struct framebuffer_color fb_color = { 0, 0, 0};
+
+
+struct data_t {
+ int fb_initial;
+ int drm_fd;
+ int gen;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb
[Intel-gfx] [PATCH] tests/kms_color:Color IGT
From: Dhanya
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma for SKL/BXT supported.
Signed-off-by: Dhanya
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/kms_color.c | 684 +
3 files changed, 686 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/.gitignore b/tests/.gitignore
index 80af9a7..58c79e2 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -127,6 +127,7 @@ gen7_forcewake_mt
kms_3d
kms_addfb_basic
kms_atomic
+kms_color
kms_crtc_background_color
kms_cursor_crc
kms_draw_crc
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 8fb2de8..906c14f 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -64,6 +64,7 @@ TESTS_progs_M = \
gem_write_read_ring_switch \
kms_addfb_basic \
kms_atomic \
+ kms_color \
kms_cursor_crc \
kms_draw_crc \
kms_fbc_crc \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..b5d199b
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,684 @@
+/*
+ * Copyright ?? 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include "drmtest.h"
+#include "drm.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+#include
+#include
+#include
+#include
+
+
+IGT_TEST_DESCRIPTION("Test Color Features at Pipe level");
+/*
+This tool tests the following color features:
+ 1.csc-red
+ 2.csc-green
+ 3.csc-blue
+ 4.gamma-legacy
+ 5.gamma-8bit
+ 6.gamma-10bit
+ 7.gamma-12bit
+ 8.gamma-split
+
+Verification is done by CRC checks.
+
+*/
+
+#define CSC_MAX_VALS9
+#define GEN9_SPLITGAMMA_MAX_VALS512
+#define GEN9_8BIT_GAMMA_MAX_VALS256
+#define GEN9_10BIT_GAMMA_MAX_VALS 1024
+#define GEN9_12BIT_GAMMA_MAX_VALS 513
+#define GEN9_MAX_GAMMA ((1 << 24) - 1)
+#define GEN9_MIN_GAMMA 0
+#define RED_CSC 0
+#define GREEN_CSC 1
+#define BLUE_CSC 2
+#define RED_FB 0
+#define GREEN_FB 1
+#define BLUE_FB 2
+
+struct _drm_r32g32b32 {
+ __u32 r32;
+ __u32 g32;
+ __u32 b32;
+ __u32 reserved;
+};
+
+struct _drm_palette {
+ struct _drm_r32g32b32 lut[0];
+};
+
+struct _drm_ctm {
+ __s64 ctm_coeff[9];
+};
+
+float ctm_red[9] = {1, 1, 1, 0, 0, 0, 0, 0, 0};
+float ctm_green[9] = {0, 0, 0, 1, 1, 1, 0, 0, 0};
+float ctm_blue[9] = {0, 0, 0, 0, 0, 0, 1, 1, 1};
+float ctm_unity[9] = {1, 0, 0, 0, 1, 0, 0, 0, 1};
+
+struct framebuffer_color {
+ int red;
+ int green;
+ int blue;
+};
+struct framebuffer_color fb_color = {0,0,0};
+
+igt_crc_t crc_reference, crc_reference_black, crc_reference_white;
+igt_crc_t crc_black, crc_white, crc_current;
+
+struct data_t {
+ int fb_initial;
+ int drm_fd;
+ int gen;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb1;
+igt_pipe_crc_t *pipe_crc;
+ enum pipe pipe;
+
+};
+
+
+static int create_blob(int fd, uint64_t *data, int length)
+{
+ struct drm_mode_create_blob blob;
+ int ret = -1;
+
+ blob.data = (uint64_t)data;
+ blob.length = length;
+ blob.blob_id = -1;
+ ret = ioctl(fd, DRM_IOCTL_MODE_CREATEPROPBLOB, &blob);
+ if (!ret)
+ return blob.blob_id;
+ igt_fail(IGT_EXIT_FAILURE);
+ return ret;
+}
+
+static void prepare_crtc(struct data_t *data, igt_output_t *output,
+enum pipe pipe1, igt_plane_t *plane, drmModeModeInfo
*mode,
+enum igt_commit_style s)
+{
+ igt_display_t *display = &data->display;
+
+ igt_output
[Intel-gfx] [PATCH] tests/kms_color:Color IGT
From: Dhanya
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma verifications are supported.
Signed-off-by: Dhanya
---
tests/Makefile.sources |1 +
tests/kms_color.c | 1070
2 files changed, 1071 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 8fb2de8..906c14f 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -64,6 +64,7 @@ TESTS_progs_M = \
gem_write_read_ring_switch \
kms_addfb_basic \
kms_atomic \
+ kms_color \
kms_cursor_crc \
kms_draw_crc \
kms_fbc_crc \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..c261c3f
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,1070 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include "drmtest.h"
+#include "drm.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+#include
+#include
+#include
+#include
+
+
+IGT_TEST_DESCRIPTION("Test Color Features at Pipe level");
+typedef unsigned char u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
+#define CSC_MAX_VALS9
+
+#define GEN9_SPLITGAMMA_MAX_VALS512
+#define GEN9_8BIT_GAMMA_MAX_VALS256
+#define GEN9_10BIT_GAMMA_MAX_VALS 1024
+#define GEN9_12BIT_GAMMA_MAX_VALS 513
+#define BDW_MAX_GAMMA ((1 << 24) - 1)
+
+
+#define CSC_COEFF_MAX 0x3FE00
+#define CSC_COEFF_MIN 0xFFFC
+
+#define VAR_LEN 100
+/*OFFSETS*/
+
+#define _PIPE_A_CSC_COEFF 0x49010
+#define _PIPE_B_CSC_COEFF 0x49110
+#define GAMMA_8BIT_PIPEA 0x4A000
+#define GAMMA_8BIT_PIPEB 0x4A800
+#define GAMMA_8BIT_PIPEC 0x4B000
+
+#define GAMMA_10BIT_PIPEA 0x4A404
+#define GAMMA_10BIT_PIPEB 0x4AC04
+#define GAMMA_10BIT_PIPEC 0x4B404
+
+#define CSC_TEST 0
+#define GAMMA_TEST 1
+#define DEGAMMA_TEST 2
+#define ENABLE 0
+#define DISABLE 1
+#define RED 0
+#define GREEN 1
+#define BLUE 2
+#define UNITY 3
+#define GAMMA_1 0
+#define GAMMA_2 1
+#define GAMMA_2_2 2
+#define PRIMARY 0
+#define SECONDARY 1
+
+#define CSC_COEFF_UNITY 0x1
+
+#define GET_BIT_MASK(n) ((1 << n) - 1)
+#define GET_BITS(x, start, nbits) ((x >> start) & GET_BIT_MASK(nbits))
+#define GET_BITS_ROUNDOFF(x, start, nbits) \
+ ((GET_BITS(x, start, (nbits + 1)) + 1) >> 1)
+
+/*Structure defination will be removed once intergrated in libdrm */
+struct drm_r32g32b32 {
+ __u32 r32;
+ __u32 g32;
+ __u32 b32;
+ __u32 reserved;
+};
+
+struct drm_palette {
+ struct drm_r32g32b32 lut[0];
+};
+
+struct drm_ctm {
+ __s64 ctm_coeff[9];
+};
+
+float ctm_red[9] = {1, 1, 1, 0, 0, 0, 0, 0, 0};
+float ctm_green[9] = {0, 0, 0, 1, 1, 1, 0, 0, 0};
+float ctm_blue[9] = {0, 0, 0, 0, 0, 0, 1, 1, 1};
+float ctm_unity[9] = {1, 0, 0, 0, 1, 0, 0, 0, 1};
+
+struct data_t {
+ int fb_initial;
+ int drm_fd;
+ int gen;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb1;
+};
+
+
+static int create_blob(int fd, uint64_t *data, int length)
+{
+ struct drm_mode_create_blob blob;
+ int ret = -1;
+
+ blob.data = (uint64_t)data;
+ blob.length = length;
+ blob.blob_id = -1;
+ ret = ioctl(fd, DRM_IOCTL_MODE_CREATEPROPBLOB, &blob);
+ if (!ret)
+ return blob.blob_id;
+ igt_info("Blob creation ioctl failed");
+ return ret;
+}
+
+static void prepare_crtc(struct data_t *data, igt_output_t *output,
+ enum pipe pipe, igt_plane_t *plane, drmModeModeInfo *mode,
+ enum igt_commit_style s)
+{
+ igt_display_t *display = &data->d
[Intel-gfx] [PATCH] tests/kms_color:Color IGT
From: Dhanya
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma supported.
Signed-off-by: Dhanya
---
tests/Makefile.sources | 3 +
tests/kms_color.c | 639 +
2 files changed, 642 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 994c31b..f49c396 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -77,9 +77,12 @@ TESTS_progs_M = \
kms_setmode \
kms_universal_plane \
kms_vblank \
+ kms_color \
+ color-correction\
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_render_compression \
pm_lpsp \
pm_rpm \
pm_rps \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..48fad7a
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,639 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+#include
+#include
+IGT_TEST_DESCRIPTION("Test Color Features at Plane/Pipe level");
+
+
+#define CHV_CSC_VALS9
+#define I915_PIPE_CSC (1<<0)
+#define I915_PLANE_CSC (1<<1)
+
+#define CSC_MANTISSA_MAX_BITS1
+#define CSC_MANTISSA_MAX_VALUE ((1 << CSC_MANTISSA_MAX_BITS) - 1)
+#define CSC_FRACTION_MAX_BITS10
+#define GAMMA_RED_SHIFT16
+#define GAMMA_GREEN_SHIFT 8
+#define STANDARD_GAMMA 2.2
+#define I915_GAMMA_FLAG_DEGAMMA(1<<0)
+#define I915_PIPE_GAMMA(1<<0)
+#define I915_PLANE_GAMMA (1<<1)
+#define I915_GAMMA_PRECISION_UNKNOWN 0
+#define I915_GAMMA_PRECISION_CURRENT 0x
+#define I915_GAMMA_PRECISION_LEGACY(1<<0)
+#define I915_GAMMA_PRECISION_10BIT (1<<1)
+#define I915_GAMMA_PRECISION_12BIT (1<<2)
+#define I915_GAMMA_PRECISION_14BIT (1<<3)
+#define I915_GAMMA_PRECISION_16BIT (1<<4)
+#define CHV_DEGAMMA_MAX_INDEX 64
+#define CHV_DEGAMMA_VALS 65
+#define CHV_8BIT_GAMMA_MAX_INDEX 256
+#define CHV_8BIT_GAMMA_MAX_VALSCHV_8BIT_GAMMA_MAX_INDEX
+#define CHV_10BIT_GAMMA_MAX_INDEX 256
+#define CHV_10BIT_GAMMA_MAX_VALS (CHV_10BIT_GAMMA_MAX_INDEX + 1)
+#define DEFAULT 0
+#define RANDOM 1
+#define DRM_IOCTL_MODE_CREATEPROPBLOB \
+ DRM_IOWR(0xBD, struct drm_mode_create_blob)
+
+struct drm_intel_csc {
+ uint32_t version;
+ int csc_matrix[9];
+
+};
+
+struct CURVE_SLIDER_VALUES {
+ int32_t brightness;
+ int32_t contrast;
+ float gamma;
+};
+
+struct rgb_pixel {
+ uint32_t red;
+ uint32_t green;
+ uint32_t blue;
+};
+
+struct drm_intel_gamma {
+ uint32_t version;
+ uint32_t num_samples;
+ struct rgb_pixel gamma_values[257];
+};
+struct drm_intel_degamma {
+ uint32_t version;
+ uint32_t num_samples;
+ struct rgb_pixel degamma_values[65];
+};
+
+static struct drm_mode_create_blob {
+ uint64_t data;
+ uint32_t length;
+ uint32_t blob_id;
+};
+
+
+struct data_t {
+ int fb_initial;
+ int drm_fd;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb1;
+};
+
+ static void
+paint_color(struct data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+int create_blob(int fd, uint64_t *data, int length)
+{
+ struct drm_mode_create_blob blob;
+ int ret = -1;
+
+ blob.data = (uint64_t)data;
+ blob.length = length;
+ blob.blob_id = -1;
+ ret = ioctl(fd, DRM_
[Intel-gfx] [PATCH] tests/kms_color:Color IGT
From: Dhanya
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma supported.
Signed-off-by: Dhanya
---
tests/Makefile.sources | 3 +
tests/kms_color.c | 639 +
2 files changed, 642 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 994c31b..f49c396 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -77,9 +77,12 @@ TESTS_progs_M = \
kms_setmode \
kms_universal_plane \
kms_vblank \
+ kms_color \
+ color-correction\
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_render_compression \
pm_lpsp \
pm_rpm \
pm_rps \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..4f6e157
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,639 @@
+/*
+ * Copyeight © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+#include
+#include
+IGT_TEST_DESCRIPTION("Test Color Features at Plane/Pipe level");
+
+
+#define CHV_CSC_VALS9
+#define I915_PIPE_CSC (1<<0)
+#define I915_PLANE_CSC (1<<1)
+
+#define CSC_MANTISSA_MAX_BITS1
+#define CSC_MANTISSA_MAX_VALUE ((1 << CSC_MANTISSA_MAX_BITS) - 1)
+#define CSC_FRACTION_MAX_BITS10
+#define GAMMA_RED_SHIFT16
+#define GAMMA_GREEN_SHIFT 8
+#define STANDARD_GAMMA 2.2
+#define I915_GAMMA_FLAG_DEGAMMA(1<<0)
+#define I915_PIPE_GAMMA(1<<0)
+#define I915_PLANE_GAMMA (1<<1)
+#define I915_GAMMA_PRECISION_UNKNOWN 0
+#define I915_GAMMA_PRECISION_CURRENT 0x
+#define I915_GAMMA_PRECISION_LEGACY(1<<0)
+#define I915_GAMMA_PRECISION_10BIT (1<<1)
+#define I915_GAMMA_PRECISION_12BIT (1<<2)
+#define I915_GAMMA_PRECISION_14BIT (1<<3)
+#define I915_GAMMA_PRECISION_16BIT (1<<4)
+#define CHV_DEGAMMA_MAX_INDEX 64
+#define CHV_DEGAMMA_VALS 65
+#define CHV_8BIT_GAMMA_MAX_INDEX 256
+#define CHV_8BIT_GAMMA_MAX_VALSCHV_8BIT_GAMMA_MAX_INDEX
+#define CHV_10BIT_GAMMA_MAX_INDEX 256
+#define CHV_10BIT_GAMMA_MAX_VALS (CHV_10BIT_GAMMA_MAX_INDEX + 1)
+#define DEFAULT 0
+#define RANDOM 1
+#define DRM_IOCTL_MODE_CREATEPROPBLOB \
+ DRM_IOWR(0xBD, struct drm_mode_create_blob)
+
+struct drm_intel_csc {
+ uint32_t version;
+ int csc_matrix[9];
+
+};
+
+struct CURVE_SLIDER_VALUES {
+ int32_t brightness;
+ int32_t contrast;
+ float gamma;
+};
+
+struct rgb_pixel {
+ uint32_t red;
+ uint32_t green;
+ uint32_t blue;
+};
+
+struct drm_intel_gamma {
+ uint32_t version;
+ uint32_t num_samples;
+ struct rgb_pixel gamma_values[257];
+};
+struct drm_intel_degamma {
+ uint32_t version;
+ uint32_t num_samples;
+ struct rgb_pixel degamma_values[65];
+};
+
+static struct drm_mode_create_blob {
+ uint64_t data;
+ uint32_t length;
+ uint32_t blob_id;
+};
+
+
+struct data_t {
+ int fb_initial;
+ int drm_fd;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb1;
+};
+
+ static void
+paint_color(struct data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+int create_blob(int fd, uint64_t *data, int length)
+{
+ struct drm_mode_create_blob blob;
+ int ret = -1;
+
+ blob.data = (uint64_t)data;
+ blob.length = length;
+ blob.blob_id = -1;
+ ret = ioctl(fd,
[Intel-gfx] [PATCH] tests/kms_color.c :Color IGT Patch
From: dhanyapr
This patch will verify color correction capability of a display driver.
Currently Pipe level CSC and Pipe level Gamma are supported.
Signed-off-by: dhanyapr
---
tests/Makefile.sources |1 +
tests/kms_color.c | 508
2 files changed, 509 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 994c31b..6211898 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -80,6 +80,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_color \
pm_lpsp \
pm_rpm \
pm_rps \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..df4ac06
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,508 @@
+/*
+ * Copyeight © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+#include
+#include
+IGT_TEST_DESCRIPTION("Test Gamma at Plane/Pipe level");
+
+
+#define CHV_CSC_VALS9
+#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct
drm_mode_create_blob)
+#define I915_PIPE_CSC (1<<0)
+#define I915_PLANE_CSC (1<<1)
+#define I915_CSC_COEFF_FORMAT_UNKNOWN 0
+#define I915_CSC_COEFF_FORMAT_CURRENT 0x
+#define I915_CSC_COEFF_FORMAT_S1_30 (1<<0)
+#define I915_CSC_COEFF_FORMAT_S2_29 (1<<1)
+
+#define CSC_MANTISSA_MAX_BITS1
+#define CSC_MANTISSA_MAX_VALUE ((1 << CSC_MANTISSA_MAX_BITS) - 1)
+#define CSC_FRACTION_MAX_BITS10
+#define GAMMA_RED_SHIFT16
+#define GAMMA_GREEN_SHIFT 8
+#define STANDARD_GAMMA 2.2
+#define I915_GAMMA_FLAG_DEGAMMA(1<<0)
+#define I915_PIPE_GAMMA(1<<0)
+#define I915_PLANE_GAMMA (1<<1)
+#define I915_GAMMA_PRECISION_UNKNOWN 0
+#define I915_GAMMA_PRECISION_CURRENT 0x
+#define I915_GAMMA_PRECISION_LEGACY(1<<0)
+#define I915_GAMMA_PRECISION_10BIT (1<<1)
+#define I915_GAMMA_PRECISION_12BIT (1<<2)
+#define I915_GAMMA_PRECISION_14BIT (1<<3)
+#define I915_GAMMA_PRECISION_16BIT (1<<4)
+#define CHV_DEGAMMA_MAX_INDEX 64
+#define CHV_DEGAMMA_VALS 65
+#define CHV_8BIT_GAMMA_MAX_INDEX 256
+#define CHV_8BIT_GAMMA_MAX_VALSCHV_8BIT_GAMMA_MAX_INDEX
+#define CHV_10BIT_GAMMA_MAX_INDEX 256
+#define CHV_10BIT_GAMMA_MAX_VALS (CHV_10BIT_GAMMA_MAX_INDEX + 1)
+
+#define CHV_SPRITE_GAMMA_MAX_VALS 6
+#define DEFAULT 0
+#define RANDOM 1
+#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct
drm_mode_create_blob)
+
+struct drm_intel_csc{
+ uint32_t csc_level;
+ uint32_t csc_format;
+ uint32_t reserved;
+ uint64_t csc_matrix[9];
+
+};
+
+
+
+typedef struct{
+ int32_t brightness;
+ int32_t contrast;
+ float gamma;
+} CURVE_SLIDER_VALUES;
+
+typedef struct r16g16b16_pixel {
+ uint16_t red;
+ uint16_t green;
+ uint16_t blue;
+} rgb_pixel;
+
+struct drm_intel_gamma{
+ uint32_t flags;
+ uint32_t gamma_level;
+ uint32_t gamma_precision;
+ uint32_t num_samples;
+ uint32_t reserved;
+ rgb_pixel gamma_values[257];
+};
+
+static struct drm_mode_create_blob {
+ uint64_t data;
+ uint32_t length;
+ uint32_t blob_id;
+};
+
+
+typedef struct {
+ int fb_initial;
+ int drm_fd;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb1;
+} data_t;
+
+ static void
+paint_color(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+
[Intel-gfx] [PATCH] tests/kms_color.c :Color IGT Patch
From: dhanyapr
This patch will verify color correction capability of a display driver.
Currently Pipe level CSC and Pipe level Gamma are supported.
Signed-off-by: dhanyapr
---
tests/Makefile.sources |1 +
tests/kms_color.c | 508
2 files changed, 509 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 994c31b..6211898 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -80,6 +80,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_color \
pm_lpsp \
pm_rpm \
pm_rps \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..df4ac06
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,508 @@
+/*
+ * Copyeight © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+#include
+#include
+IGT_TEST_DESCRIPTION("Test Gamma at Plane/Pipe level");
+
+
+#define CHV_CSC_VALS9
+#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct
drm_mode_create_blob)
+#define I915_PIPE_CSC (1<<0)
+#define I915_PLANE_CSC (1<<1)
+#define I915_CSC_COEFF_FORMAT_UNKNOWN 0
+#define I915_CSC_COEFF_FORMAT_CURRENT 0x
+#define I915_CSC_COEFF_FORMAT_S1_30 (1<<0)
+#define I915_CSC_COEFF_FORMAT_S2_29 (1<<1)
+
+#define CSC_MANTISSA_MAX_BITS1
+#define CSC_MANTISSA_MAX_VALUE ((1 << CSC_MANTISSA_MAX_BITS) - 1)
+#define CSC_FRACTION_MAX_BITS10
+#define GAMMA_RED_SHIFT16
+#define GAMMA_GREEN_SHIFT 8
+#define STANDARD_GAMMA 2.2
+#define I915_GAMMA_FLAG_DEGAMMA(1<<0)
+#define I915_PIPE_GAMMA(1<<0)
+#define I915_PLANE_GAMMA (1<<1)
+#define I915_GAMMA_PRECISION_UNKNOWN 0
+#define I915_GAMMA_PRECISION_CURRENT 0x
+#define I915_GAMMA_PRECISION_LEGACY(1<<0)
+#define I915_GAMMA_PRECISION_10BIT (1<<1)
+#define I915_GAMMA_PRECISION_12BIT (1<<2)
+#define I915_GAMMA_PRECISION_14BIT (1<<3)
+#define I915_GAMMA_PRECISION_16BIT (1<<4)
+#define CHV_DEGAMMA_MAX_INDEX 64
+#define CHV_DEGAMMA_VALS 65
+#define CHV_8BIT_GAMMA_MAX_INDEX 256
+#define CHV_8BIT_GAMMA_MAX_VALSCHV_8BIT_GAMMA_MAX_INDEX
+#define CHV_10BIT_GAMMA_MAX_INDEX 256
+#define CHV_10BIT_GAMMA_MAX_VALS (CHV_10BIT_GAMMA_MAX_INDEX + 1)
+
+#define CHV_SPRITE_GAMMA_MAX_VALS 6
+#define DEFAULT 0
+#define RANDOM 1
+#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct
drm_mode_create_blob)
+
+struct drm_intel_csc{
+ uint32_t csc_level;
+ uint32_t csc_format;
+ uint32_t reserved;
+ uint64_t csc_matrix[9];
+
+};
+
+
+
+typedef struct{
+ int32_t brightness;
+ int32_t contrast;
+ float gamma;
+} CURVE_SLIDER_VALUES;
+
+typedef struct r16g16b16_pixel {
+ uint16_t red;
+ uint16_t green;
+ uint16_t blue;
+} rgb_pixel;
+
+struct drm_intel_gamma{
+ uint32_t flags;
+ uint32_t gamma_level;
+ uint32_t gamma_precision;
+ uint32_t num_samples;
+ uint32_t reserved;
+ rgb_pixel gamma_values[257];
+};
+
+static struct drm_mode_create_blob {
+ uint64_t data;
+ uint32_t length;
+ uint32_t blob_id;
+};
+
+
+typedef struct {
+ int fb_initial;
+ int drm_fd;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb1;
+} data_t;
+
+ static void
+paint_color(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+
[Intel-gfx] [PATCH] tests/kms_color.c :Color IGT Patch This patch will verify color correction capability of a display driver. Currently Pipe level CSC and Pipe level Gamma are supported.
From: dhanyapr
Signed-off-by: dhanyapr
---
tests/Makefile.sources | 1 +
tests/kms_color.c | 508 +
2 files changed, 509 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 994c31b..6211898 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -80,6 +80,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_color \
pm_lpsp \
pm_rpm \
pm_rps \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..df4ac06
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,508 @@
+/*
+ * Copyeight ?? 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+#include
+#include
+IGT_TEST_DESCRIPTION("Test Gamma at Plane/Pipe level");
+
+
+#define CHV_CSC_VALS9
+#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct
drm_mode_create_blob)
+#define I915_PIPE_CSC (1<<0)
+#define I915_PLANE_CSC (1<<1)
+#define I915_CSC_COEFF_FORMAT_UNKNOWN 0
+#define I915_CSC_COEFF_FORMAT_CURRENT 0x
+#define I915_CSC_COEFF_FORMAT_S1_30 (1<<0)
+#define I915_CSC_COEFF_FORMAT_S2_29 (1<<1)
+
+#define CSC_MANTISSA_MAX_BITS1
+#define CSC_MANTISSA_MAX_VALUE ((1 << CSC_MANTISSA_MAX_BITS) - 1)
+#define CSC_FRACTION_MAX_BITS10
+#define GAMMA_RED_SHIFT16
+#define GAMMA_GREEN_SHIFT 8
+#define STANDARD_GAMMA 2.2
+#define I915_GAMMA_FLAG_DEGAMMA(1<<0)
+#define I915_PIPE_GAMMA(1<<0)
+#define I915_PLANE_GAMMA (1<<1)
+#define I915_GAMMA_PRECISION_UNKNOWN 0
+#define I915_GAMMA_PRECISION_CURRENT 0x
+#define I915_GAMMA_PRECISION_LEGACY(1<<0)
+#define I915_GAMMA_PRECISION_10BIT (1<<1)
+#define I915_GAMMA_PRECISION_12BIT (1<<2)
+#define I915_GAMMA_PRECISION_14BIT (1<<3)
+#define I915_GAMMA_PRECISION_16BIT (1<<4)
+#define CHV_DEGAMMA_MAX_INDEX 64
+#define CHV_DEGAMMA_VALS 65
+#define CHV_8BIT_GAMMA_MAX_INDEX 256
+#define CHV_8BIT_GAMMA_MAX_VALSCHV_8BIT_GAMMA_MAX_INDEX
+#define CHV_10BIT_GAMMA_MAX_INDEX 256
+#define CHV_10BIT_GAMMA_MAX_VALS (CHV_10BIT_GAMMA_MAX_INDEX + 1)
+
+#define CHV_SPRITE_GAMMA_MAX_VALS 6
+#define DEFAULT 0
+#define RANDOM 1
+#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct
drm_mode_create_blob)
+
+struct drm_intel_csc{
+ uint32_t csc_level;
+ uint32_t csc_format;
+ uint32_t reserved;
+ uint64_t csc_matrix[9];
+
+};
+
+
+
+typedef struct{
+ int32_t brightness;
+ int32_t contrast;
+ float gamma;
+} CURVE_SLIDER_VALUES;
+
+typedef struct r16g16b16_pixel {
+ uint16_t red;
+ uint16_t green;
+ uint16_t blue;
+} rgb_pixel;
+
+struct drm_intel_gamma{
+ uint32_t flags;
+ uint32_t gamma_level;
+ uint32_t gamma_precision;
+ uint32_t num_samples;
+ uint32_t reserved;
+ rgb_pixel gamma_values[257];
+};
+
+static struct drm_mode_create_blob {
+ uint64_t data;
+ uint32_t length;
+ uint32_t blob_id;
+};
+
+
+typedef struct {
+ int fb_initial;
+ int drm_fd;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb1;
+} data_t;
+
+ static void
+paint_color(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+int create_blob(int fd, uint64_t *data, int length)
+{
+ struct drm_mode_create_blob blob;
+ int ret = -1;
+ bl
[Intel-gfx] [PATCH] tests/kms_color.c :Color IGT Patch This patch will verify color correction capability of a display driver. Currently Pipe level CSC and Pipe level Gamma are supported.
From: root
Signed-off-by: dhanyapr
---
tests/Makefile.sources | 1 +
tests/kms_color.c | 508 +
2 files changed, 509 insertions(+)
create mode 100644 tests/kms_color.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 994c31b..6211898 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -80,6 +80,7 @@ TESTS_progs_M = \
kms_crtc_background_color \
kms_plane_scaling \
kms_panel_fitting \
+ kms_color \
pm_lpsp \
pm_rpm \
pm_rps \
diff --git a/tests/kms_color.c b/tests/kms_color.c
new file mode 100644
index 000..df4ac06
--- /dev/null
+++ b/tests/kms_color.c
@@ -0,0 +1,508 @@
+/*
+ * Copyeight © 2013,2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "igt_core.h"
+#include "intel_chipset.h"
+#include "igt_aux.h"
+#include
+#include
+IGT_TEST_DESCRIPTION("Test Gamma at Plane/Pipe level");
+
+
+#define CHV_CSC_VALS9
+#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct
drm_mode_create_blob)
+#define I915_PIPE_CSC (1<<0)
+#define I915_PLANE_CSC (1<<1)
+#define I915_CSC_COEFF_FORMAT_UNKNOWN 0
+#define I915_CSC_COEFF_FORMAT_CURRENT 0x
+#define I915_CSC_COEFF_FORMAT_S1_30 (1<<0)
+#define I915_CSC_COEFF_FORMAT_S2_29 (1<<1)
+
+#define CSC_MANTISSA_MAX_BITS1
+#define CSC_MANTISSA_MAX_VALUE ((1 << CSC_MANTISSA_MAX_BITS) - 1)
+#define CSC_FRACTION_MAX_BITS10
+#define GAMMA_RED_SHIFT16
+#define GAMMA_GREEN_SHIFT 8
+#define STANDARD_GAMMA 2.2
+#define I915_GAMMA_FLAG_DEGAMMA(1<<0)
+#define I915_PIPE_GAMMA(1<<0)
+#define I915_PLANE_GAMMA (1<<1)
+#define I915_GAMMA_PRECISION_UNKNOWN 0
+#define I915_GAMMA_PRECISION_CURRENT 0x
+#define I915_GAMMA_PRECISION_LEGACY(1<<0)
+#define I915_GAMMA_PRECISION_10BIT (1<<1)
+#define I915_GAMMA_PRECISION_12BIT (1<<2)
+#define I915_GAMMA_PRECISION_14BIT (1<<3)
+#define I915_GAMMA_PRECISION_16BIT (1<<4)
+#define CHV_DEGAMMA_MAX_INDEX 64
+#define CHV_DEGAMMA_VALS 65
+#define CHV_8BIT_GAMMA_MAX_INDEX 256
+#define CHV_8BIT_GAMMA_MAX_VALSCHV_8BIT_GAMMA_MAX_INDEX
+#define CHV_10BIT_GAMMA_MAX_INDEX 256
+#define CHV_10BIT_GAMMA_MAX_VALS (CHV_10BIT_GAMMA_MAX_INDEX + 1)
+
+#define CHV_SPRITE_GAMMA_MAX_VALS 6
+#define DEFAULT 0
+#define RANDOM 1
+#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct
drm_mode_create_blob)
+
+struct drm_intel_csc{
+ uint32_t csc_level;
+ uint32_t csc_format;
+ uint32_t reserved;
+ uint64_t csc_matrix[9];
+
+};
+
+
+
+typedef struct{
+ int32_t brightness;
+ int32_t contrast;
+ float gamma;
+} CURVE_SLIDER_VALUES;
+
+typedef struct r16g16b16_pixel {
+ uint16_t red;
+ uint16_t green;
+ uint16_t blue;
+} rgb_pixel;
+
+struct drm_intel_gamma{
+ uint32_t flags;
+ uint32_t gamma_level;
+ uint32_t gamma_precision;
+ uint32_t num_samples;
+ uint32_t reserved;
+ rgb_pixel gamma_values[257];
+};
+
+static struct drm_mode_create_blob {
+ uint64_t data;
+ uint32_t length;
+ uint32_t blob_id;
+};
+
+
+typedef struct {
+ int fb_initial;
+ int drm_fd;
+ int w, h;
+ igt_display_t display;
+ struct igt_fb fb_prep;
+ struct igt_fb fb, fb1;
+} data_t;
+
+ static void
+paint_color(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
+{
+ cairo_t *cr;
+ cr = igt_get_cairo_ctx(d->drm_fd, fb);
+ igt_paint_test_pattern(cr, w, h);
+ cairo_destroy(cr);
+}
+
+int create_blob(int fd, uint64_t *data, int length)
+{
+ struct drm_mode_create_blob blob;
+ int ret = -1;
+ blob.da
