[PATCH v1 2/3] drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+

2024-01-08 Thread Haridhar Kalvala 
From: Harish Chegondi 

Xe_LPG+ (IP version 12.74) should take the same general code
paths as Xe_LPG (versions 12.70 and 12.71).

Xe_LPG+'s workaround list will be handled by the next patch.

Signed-off-by: Harish Chegondi 
Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++-
 drivers/gpu/drm/i915/gt/intel_mocs.c  | 2 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c   | 2 +-
 drivers/gpu/drm/i915/i915_debugfs.c   | 2 +-
 4 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 40687806d22a..1ade568ffbfa 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1190,7 +1190,8 @@ static int intel_engine_init_tlb_invalidation(struct 
intel_engine_cs *engine)
num = ARRAY_SIZE(xelpmp_regs);
}
} else {
-   if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
+   if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||
+   GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c 
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 353f93baaca0..25c1023eb5f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(struct 
drm_i915_private *i915,
memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
table->unused_entries_index = I915_MOCS_PTE;
-   if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
+   if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {
table->size = ARRAY_SIZE(mtl_mocs_table);
table->table = mtl_mocs_table;
table->n_entries = MTL_NUM_MOCS_ENTRIES;
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 7090e4be29cb..8f4b3c8af09c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
 * temporary wa and should be removed after fixing real cause
 * of forcewake timeouts.
 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
pg_enable =
GEN9_MEDIA_PG_ENABLE |
GEN11_MEDIA_SAMPLER_PG_ENABLE;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index db99c2ef66db..990eaa029d9c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -147,7 +147,7 @@ static const char *i915_cache_level_str(struct 
drm_i915_gem_object *obj)
 {
struct drm_i915_private *i915 = obj_to_i915(obj);
 
-   if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
+   if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {
switch (obj->pat_index) {
case 0: return " WB";
case 1: return " WT";
-- 
2.25.1

[PATCH v1 3/3] drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74

2024-01-08 Thread Haridhar Kalvala 
From: Matt Roper 

Some of our existing Xe_LPG workarounds and tuning are also applicable
to the version 12.74 variant.  Extend the condition bounds accordingly.
Also fix the comment on Wa_14018575942 while we're at it.

v2: Extend some more workarounds (Harish)

Signed-off-by: Matt Roper 
Signed-off-by: Harish Chegondi 
Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c|  4 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +
 drivers/gpu/drm/i915/i915_perf.c|  2 +-
 3 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 86a04afff64b..e1bf13e3d307 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -226,7 +226,7 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs 
*engine, u32 *cs)
 static int mtl_dummy_pipe_control(struct i915_request *rq)
 {
/* Wa_14016712196 */
-   if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 71)) 
||
+   if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) 
||
IS_DG2(rq->i915)) {
u32 *cs;
 
@@ -822,7 +822,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request 
*rq, u32 *cs)
flags |= PIPE_CONTROL_FLUSH_L3;
 
/* Wa_14016712196 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
IS_DG2(i915))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || 
IS_DG2(i915))
/* dummy PIPE_CONTROL + depth flush */
cs = gen12_emit_pipe_control(cs, 0,
 PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3eacbc50caf8..72dac27d9332 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -789,8 +789,13 @@ static void xelpg_ctx_gt_tuning_init(struct 
intel_engine_cs *engine,
 
dg2_ctx_gt_tuning_init(engine, wal);
 
-   if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
-   IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
+   /*
+* Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in
+* gen12_emit_indirect_ctx_rcs() rather than here on some early
+* steppings.
+*/
+   if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)))
wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
@@ -908,7 +913,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (engine->class != RENDER_CLASS)
goto done;
 
-   if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_ctx_workarounds_init(engine, wal);
else if (IS_PONTEVECCHIO(i915))
; /* noop; none at this time */
@@ -1643,7 +1648,7 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
 static void
 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-   /* Wa_14018778641 / Wa_18018781329 */
+   /* Wa_14018575942 / Wa_18018781329 */
wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
 
/* Wa_22016670082 */
@@ -1710,7 +1715,7 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
  */
 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {
wa_mcr_write_or(wal, XEHP_L3SCQREG7, 
BLEND_FILL_CACHING_OPT_DIS);
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
}
@@ -1743,7 +1748,7 @@ gt_init_workarounds(struct intel_gt *gt, struct 
i915_wa_list *wal)
return;
}
 
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_gt_workarounds_init(gt, wal);
else if (IS_PONTEVECCHIO(i915))
pvc_gt_workarounds_init(gt, wal);
@@ -2216,7 +2221,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs 
*engine)
 
if (engine->gt->type == GT_MEDIA)
; /* none yet */
-   else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+   else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_whitelist_build(engine);
else if (IS_PONTEVECCHIO(i915))
pvc_whitelist_build(engine);
@@ -2828,7 +2833,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
 {

[PATCH v1 1/3] drm/i915: Add additional ARL PCI IDs

2024-01-08 Thread Haridhar Kalvala 
From: Matt Roper 

Our existing MTL driver handling is also sufficient to handle ARL, so
these IDs are simply added to the MTL ID list.

Bspec: 55420
Signed-off-by: Matt Roper 
---
 include/drm/i915_pciids.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index fcf1849aa47c..07779a11758e 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -751,10 +751,13 @@
 /* MTL */
 #define INTEL_MTL_IDS(info) \
INTEL_VGA_DEVICE(0x7D40, info), \
+   INTEL_VGA_DEVICE(0x7D41, info), \
INTEL_VGA_DEVICE(0x7D45, info), \
+   INTEL_VGA_DEVICE(0x7D51, info), \
INTEL_VGA_DEVICE(0x7D55, info), \
INTEL_VGA_DEVICE(0x7D60, info), \
INTEL_VGA_DEVICE(0x7D67, info), \
+   INTEL_VGA_DEVICE(0x7DD1, info), \
INTEL_VGA_DEVICE(0x7DD5, info)
 
 #endif /* _I915_PCIIDS_H */
-- 
2.25.1

[PATCH v1 0/3] Extend ARL support

2024-01-08 Thread Haridhar Kalvala 
Some SKUs of Arrow Lake use a slightly newer Xe_LPG+ graphics
IP (version 12.74).  Add some additional PCI IDs and extend the
code to support this newer IP version.  The general code flow
should continue to match existing MTL and Xe_LPG code paths.

Harish Chegondi (1):
  drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+

Matt Roper (2):
  drm/i915: Add additional ARL PCI IDs
  drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74

 drivers/gpu/drm/i915/gt/gen8_engine_cs.c|  4 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c   |  3 ++-
 drivers/gpu/drm/i915/gt/intel_mocs.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/i915_perf.c|  2 +-
 include/drm/i915_pciids.h   |  3 +++
 8 files changed, 26 insertions(+), 16 deletions(-)

-- 
2.25.1

[PATCH v1 3/3] drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74

2023-12-21 Thread Haridhar Kalvala 
From: Matt Roper 

Some of our existing Xe_LPG workarounds and tuning are also applicable
to the version 12.74 variant.  Extend the condition bounds accordingly.
Also fix the comment on Wa_14018575942 while we're at it.

v2: Extend some more workarounds (Harish)

Signed-off-by: Matt Roper 
Signed-off-by: Harish Chegondi 
Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c|  4 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +
 drivers/gpu/drm/i915/i915_perf.c|  2 +-
 3 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 86a04afff64b..e1bf13e3d307 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -226,7 +226,7 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs 
*engine, u32 *cs)
 static int mtl_dummy_pipe_control(struct i915_request *rq)
 {
/* Wa_14016712196 */
-   if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 71)) 
||
+   if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) 
||
IS_DG2(rq->i915)) {
u32 *cs;
 
@@ -822,7 +822,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request 
*rq, u32 *cs)
flags |= PIPE_CONTROL_FLUSH_L3;
 
/* Wa_14016712196 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
IS_DG2(i915))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || 
IS_DG2(i915))
/* dummy PIPE_CONTROL + depth flush */
cs = gen12_emit_pipe_control(cs, 0,
 PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3eacbc50caf8..72dac27d9332 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -789,8 +789,13 @@ static void xelpg_ctx_gt_tuning_init(struct 
intel_engine_cs *engine,
 
dg2_ctx_gt_tuning_init(engine, wal);
 
-   if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
-   IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
+   /*
+* Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in
+* gen12_emit_indirect_ctx_rcs() rather than here on some early
+* steppings.
+*/
+   if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)))
wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
@@ -908,7 +913,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (engine->class != RENDER_CLASS)
goto done;
 
-   if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_ctx_workarounds_init(engine, wal);
else if (IS_PONTEVECCHIO(i915))
; /* noop; none at this time */
@@ -1643,7 +1648,7 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
 static void
 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-   /* Wa_14018778641 / Wa_18018781329 */
+   /* Wa_14018575942 / Wa_18018781329 */
wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
 
/* Wa_22016670082 */
@@ -1710,7 +1715,7 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
  */
 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {
wa_mcr_write_or(wal, XEHP_L3SCQREG7, 
BLEND_FILL_CACHING_OPT_DIS);
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
}
@@ -1743,7 +1748,7 @@ gt_init_workarounds(struct intel_gt *gt, struct 
i915_wa_list *wal)
return;
}
 
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_gt_workarounds_init(gt, wal);
else if (IS_PONTEVECCHIO(i915))
pvc_gt_workarounds_init(gt, wal);
@@ -2216,7 +2221,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs 
*engine)
 
if (engine->gt->type == GT_MEDIA)
; /* none yet */
-   else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+   else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_whitelist_build(engine);
else if (IS_PONTEVECCHIO(i915))
pvc_whitelist_build(engine);
@@ -2828,7 +2833,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
 {

[PATCH v1 2/3] drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+

2023-12-21 Thread Haridhar Kalvala 
From: Harish Chegondi 

Xe_LPG+ (IP version 12.74) should take the same general code
paths as Xe_LPG (versions 12.70 and 12.71).

Xe_LPG+'s workaround list will be handled by the next patch.

Signed-off-by: Harish Chegondi 
Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++-
 drivers/gpu/drm/i915/gt/intel_mocs.c  | 2 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c   | 2 +-
 drivers/gpu/drm/i915/i915_debugfs.c   | 2 +-
 4 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 40687806d22a..1ade568ffbfa 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1190,7 +1190,8 @@ static int intel_engine_init_tlb_invalidation(struct 
intel_engine_cs *engine)
num = ARRAY_SIZE(xelpmp_regs);
}
} else {
-   if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
+   if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||
+   GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c 
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 353f93baaca0..25c1023eb5f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(struct 
drm_i915_private *i915,
memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
table->unused_entries_index = I915_MOCS_PTE;
-   if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
+   if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {
table->size = ARRAY_SIZE(mtl_mocs_table);
table->table = mtl_mocs_table;
table->n_entries = MTL_NUM_MOCS_ENTRIES;
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 7090e4be29cb..8f4b3c8af09c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
 * temporary wa and should be removed after fixing real cause
 * of forcewake timeouts.
 */
-   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+   if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
pg_enable =
GEN9_MEDIA_PG_ENABLE |
GEN11_MEDIA_SAMPLER_PG_ENABLE;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index db99c2ef66db..990eaa029d9c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -147,7 +147,7 @@ static const char *i915_cache_level_str(struct 
drm_i915_gem_object *obj)
 {
struct drm_i915_private *i915 = obj_to_i915(obj);
 
-   if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
+   if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {
switch (obj->pat_index) {
case 0: return " WB";
case 1: return " WT";
-- 
2.25.1

[PATCH v1 1/3] drm/i915: Add additional ARL PCI IDs

2023-12-21 Thread Haridhar Kalvala 
From: Matt Roper 

Our existing MTL driver handling is also sufficient to handle ARL, so
these IDs are simply added to the MTL ID list.

Bspec: 55420
Signed-off-by: Matt Roper 
---
 include/drm/i915_pciids.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index fcf1849aa47c..07779a11758e 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -751,10 +751,13 @@
 /* MTL */
 #define INTEL_MTL_IDS(info) \
INTEL_VGA_DEVICE(0x7D40, info), \
+   INTEL_VGA_DEVICE(0x7D41, info), \
INTEL_VGA_DEVICE(0x7D45, info), \
+   INTEL_VGA_DEVICE(0x7D51, info), \
INTEL_VGA_DEVICE(0x7D55, info), \
INTEL_VGA_DEVICE(0x7D60, info), \
INTEL_VGA_DEVICE(0x7D67, info), \
+   INTEL_VGA_DEVICE(0x7DD1, info), \
INTEL_VGA_DEVICE(0x7DD5, info)
 
 #endif /* _I915_PCIIDS_H */
-- 
2.25.1

[PATCH v1 0/3] Extend ARL support

2023-12-21 Thread Haridhar Kalvala 
Some SKUs of Arrow Lake use a slightly newer Xe_LPG+ graphics
IP (version 12.74).  Add some additional PCI IDs and extend the
code to support this newer IP version.  The general code flow
should continue to match existing MTL and Xe_LPG code paths.

Harish Chegondi (1):
  drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+

Matt Roper (2):
  drm/i915: Add additional ARL PCI IDs
  drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74

 drivers/gpu/drm/i915/gt/gen8_engine_cs.c|  4 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c   |  3 ++-
 drivers/gpu/drm/i915/gt/intel_mocs.c|  2 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +
 drivers/gpu/drm/i915/i915_debugfs.c |  2 +-
 drivers/gpu/drm/i915/i915_perf.c|  2 +-
 include/drm/i915_pciids.h   |  3 +++
 8 files changed, 26 insertions(+), 16 deletions(-)

-- 
2.25.1

[PATCH v2] drm/i915/mtl: Add fake PCH for Meteor Lake

2023-12-19 Thread Haridhar Kalvala 
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.

On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC die in this case), unlike many past
platforms where the SDE was on a separate PCH die. The code is (badly)
structured today in a way that assumes the SDE is always on the PCH for
modern platforms, so on platforms where we don't actually need to identify
the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as
MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows
us to avoid restructuring a bunch of the code.we've been assigning a
"fake PCH" as a quick hack that allows us to avoid restructuring a bunch
of the code.

Removed unused macros of LNL amd MTL as well.

v2: Reorder PCH_MTL conditional check (Matt Roper)
Reverting to PCH_MTL for PICA interrupt(Matt Roper)

Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/display/intel_backlight.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_bios.c|  3 +--
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_display_irq.c |  2 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c   |  5 +
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c |  6 ++
 drivers/gpu/drm/i915/display/intel_pps.c |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c | 16 
 drivers/gpu/drm/i915/soc/intel_pch.h |  6 +-
 9 files changed, 19 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c 
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 612d4cd9dacb..696ae59874a9 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct 
drm_i915_private *i915, int
 
if (controller == 1 &&
INTEL_PCH_TYPE(i915) >= PCH_ICP &&
-   INTEL_PCH_TYPE(i915) < PCH_MTP)
+   INTEL_PCH_TYPE(i915) <= PCH_ADP)
return intel_de_read(i915, SOUTH_CHICKEN1) & 
ICP_SECOND_PPS_IO_SELECT;
 
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index aa169b0055e9..0e61e424802e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2204,8 +2204,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 
vbt_pin)
if (IS_DGFX(i915))
return vbt_pin;
 
-   if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
-   IS_ALDERLAKE_P(i915)) {
+   if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c985ebb6831a..b251a71092dd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3467,15 +3467,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 {
u32 freq;
 
-   if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
-   freq = dg1_rawclk(dev_priv);
-   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
+   if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
/*
 * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
 * "RAWCLK_FREQ defaults to the values for 38.4 and does
 * not need to be programmed."
 */
freq = 38400;
+   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+   freq = dg1_rawclk(dev_priv);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a7d8f3fc98de..6964f4b95865 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -986,7 +986,7 @@ static void gen8_read_and_ack_pch_irqs(struct 
drm_i915_private *i915, u32 *pch_i
 * their flags both in the PICA and SDE IIR.
 */
if (*pch_iir & SDE_PICAINTERRUPT) {
-   drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTP);
+   drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTL);
 
pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0);
*pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c 
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 40d7b6f3f489..854566ba5414 100644
--- a/drivers/gpu/drm/i915/d

[PATCH] drm/i915/mtl: Add fake PCH for Meteor Lake

2023-12-19 Thread Haridhar Kalvala 
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.

On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC die in this case), unlike many past
platforms where the SDE was on a separate PCH die. The code is (badly)
structured today in a way that assumes the SDE is always on the PCH for
modern platforms, so on platforms where we don't actually need to identify
the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as
MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows
us to avoid restructuring a bunch of the code.we've been assigning a
"fake PCH" as a quick hack that allows us to avoid restructuring a bunch
of the code.

Removed unused macros of LNL amd MTL as well.

Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/display/intel_backlight.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_bios.c|  3 +--
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_display_irq.c |  2 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c   |  5 +
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c |  6 ++
 drivers/gpu/drm/i915/display/intel_pps.c |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c | 16 
 drivers/gpu/drm/i915/soc/intel_pch.h |  6 +-
 9 files changed, 17 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c 
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 612d4cd9dacb..696ae59874a9 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct 
drm_i915_private *i915, int
 
if (controller == 1 &&
INTEL_PCH_TYPE(i915) >= PCH_ICP &&
-   INTEL_PCH_TYPE(i915) < PCH_MTP)
+   INTEL_PCH_TYPE(i915) <= PCH_ADP)
return intel_de_read(i915, SOUTH_CHICKEN1) & 
ICP_SECOND_PPS_IO_SELECT;
 
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index aa169b0055e9..0e61e424802e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2204,8 +2204,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 
vbt_pin)
if (IS_DGFX(i915))
return vbt_pin;
 
-   if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
-   IS_ALDERLAKE_P(i915)) {
+   if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c985ebb6831a..2e6e55d3e885 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3469,7 +3469,7 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
freq = dg1_rawclk(dev_priv);
-   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
+   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
/*
 * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
 * "RAWCLK_FREQ defaults to the values for 38.4 and does
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a7d8f3fc98de..e318e24d1efd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -986,7 +986,7 @@ static void gen8_read_and_ack_pch_irqs(struct 
drm_i915_private *i915, u32 *pch_i
 * their flags both in the PICA and SDE IIR.
 */
if (*pch_iir & SDE_PICAINTERRUPT) {
-   drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTP);
+   drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) <= PCH_ADP);
 
pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0);
*pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c 
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 40d7b6f3f489..854566ba5414 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -155,7 +155,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct 
drm_i915_private *i915,
const struct gmbus_pin *pins;
size_t size;
 
-   if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
+   if (INTEL_PCH_TYPE(i915) >= PCH_MTL) {
pins = gmbus_pins_mtp;
size = ARRAY_SIZE(gmbus_pins_mtp);
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2)

[PATCH] drm/i915/xelpg: Add fake PCH for xelpg

2023-12-18 Thread Haridhar Kalvala 
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.

On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC die in this case), unlike many past
platforms where the SDE was on a separate PCH die. The code is (badly)
structured today in a way that assumes the SDE is always on the PCH for
modern platforms, so on platforms where we don't actually need to identify
the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as
MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows
us to avoid restructuring a bunch of the code.we've been assigning a
"fake PCH" as a quick hack that allows us to avoid restructuring a bunch
of the code.

Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/display/intel_backlight.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_display_irq.c |  2 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c   |  6 ++
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c |  7 +++
 drivers/gpu/drm/i915/display/intel_pps.c |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c | 12 +++-
 drivers/gpu/drm/i915/soc/intel_pch.h |  4 ++--
 8 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c 
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 612d4cd9dacb..696ae59874a9 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct 
drm_i915_private *i915, int
 
if (controller == 1 &&
INTEL_PCH_TYPE(i915) >= PCH_ICP &&
-   INTEL_PCH_TYPE(i915) < PCH_MTP)
+   INTEL_PCH_TYPE(i915) <= PCH_ADP)
return intel_de_read(i915, SOUTH_CHICKEN1) & 
ICP_SECOND_PPS_IO_SELECT;
 
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c985ebb6831a..2e6e55d3e885 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3469,7 +3469,7 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
freq = dg1_rawclk(dev_priv);
-   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
+   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
/*
 * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
 * "RAWCLK_FREQ defaults to the values for 38.4 and does
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a7d8f3fc98de..e318e24d1efd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -986,7 +986,7 @@ static void gen8_read_and_ack_pch_irqs(struct 
drm_i915_private *i915, u32 *pch_i
 * their flags both in the PICA and SDE IIR.
 */
if (*pch_iir & SDE_PICAINTERRUPT) {
-   drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTP);
+   drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) <= PCH_ADP);
 
pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0);
*pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c 
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 40d7b6f3f489..2d9c740ba17e 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -155,7 +155,8 @@ static const struct gmbus_pin *get_gmbus_pin(struct 
drm_i915_private *i915,
const struct gmbus_pin *pins;
size_t size;
 
-   if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
+   if ((INTEL_PCH_TYPE(i915) >= PCH_LNL) ||
+   (INTEL_PCH_TYPE(i915) >= PCH_MTL)) {
pins = gmbus_pins_mtp;
size = ARRAY_SIZE(gmbus_pins_mtp);
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
@@ -164,9 +165,6 @@ static const struct gmbus_pin *get_gmbus_pin(struct 
drm_i915_private *i915,
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
pins = gmbus_pins_dg1;
size = ARRAY_SIZE(gmbus_pins_dg1);
-   } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
-   pins = gmbus_pins_mtp;
-   size = ARRAY_SIZE(gmbus_pins_mtp);
} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
pins = gmbus_pins_icp;
size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c 
b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 04f62f27ad74..63f697383bf3 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/dr

[PATCH] drm/i915: Add Wa_14019877138

2023-12-12 Thread Haridhar Kalvala 
Enable Force Dispatch Ends Collection for DG2.

BSpec: 46001

Signed-off-by: Haridhar Kalvala 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 9de41703fae5..50962cfd1353 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -469,6 +469,9 @@
 #define XEHP_PSS_MODE2 MCR_REG(0x703c)
 #define   SCOREBOARD_STALL_FLUSH_CONTROL   REG_BIT(5)
 
+#define XEHP_PSS_CHICKEN   MCR_REG(0x7044)
+#define   FD_END_COLLECT   REG_BIT(5)
+
 #define GEN7_SC_INSTDONE   _MMIO(0x7100)
 #define GEN12_SC_INSTDONE_EXTRA_MMIO(0x7104)
 #define GEN12_SC_INSTDONE_EXTRA2   _MMIO(0x7108)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4cbf9e512645..3eacbc50caf8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -777,6 +777,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs 
*engine,
 
/* Wa_18019271663:dg2 */
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
+
+   /* Wa_14019877138:dg2 */
+   wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);
 }
 
 static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
-- 
2.25.1

[Intel-gfx] [PATCH] drm/i915: Add Wa_14019877138

2023-12-05 Thread Haridhar Kalvala 
Enable Force Dispatch Ends Collection for DG2.

BSpec: 46001

Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 9de41703fae5..85ba62639807 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -469,6 +469,9 @@
 #define XEHP_PSS_MODE2 MCR_REG(0x703c)
 #define   SCOREBOARD_STALL_FLUSH_CONTROL   REG_BIT(5)
 
+#defineXEHP_PSS_CHICKENMCR_REG(0x7044)
+#define  FD_END_COLLECTREG_BIT(5)
+
 #define GEN7_SC_INSTDONE   _MMIO(0x7100)
 #define GEN12_SC_INSTDONE_EXTRA_MMIO(0x7104)
 #define GEN12_SC_INSTDONE_EXTRA2   _MMIO(0x7108)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4cbf9e512645..3eacbc50caf8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -777,6 +777,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs 
*engine,
 
/* Wa_18019271663:dg2 */
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
+
+   /* Wa_14019877138:dg2 */
+   wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);
 }
 
 static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
-- 
2.25.1

[Intel-gfx] [PATCH] drm/i915: ATS-M device ID update

2023-11-20 Thread Haridhar Kalvala 
ATS-M device ID update.

BSpec: 44477

Signed-off-by: Haridhar Kalvala 
---
 include/drm/i915_pciids.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 1c9ea6ab3eb9..fcf1849aa47c 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -738,7 +738,8 @@
INTEL_DG2_G12_IDS(info)
 
 #define INTEL_ATS_M150_IDS(info) \
-   INTEL_VGA_DEVICE(0x56C0, info)
+   INTEL_VGA_DEVICE(0x56C0, info), \
+   INTEL_VGA_DEVICE(0x56C2, info)
 
 #define INTEL_ATS_M75_IDS(info) \
INTEL_VGA_DEVICE(0x56C1, info)
-- 
2.25.1

[Intel-gfx] [PATCH] drm/i915/mtl: Add Wa_14017856879

2023-04-04 Thread Haridhar Kalvala 
Wa_14017856879 implementation for mtl.

Bspec: 46046

Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 35a4cfac2d20..492b3de6678d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1177,7 +1177,9 @@
 #define   THREAD_EX_ARB_MODE_RR_AFTER_DEP  
REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
+#define GEN9_ROW_CHICKEN3  MCR_REG(0xe49c)
 #define   HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE   (1 << 6)
+#define   MTL_DISABLE_FIX_FOR_EOT_FLUSHREG_BIT(9)
 
 #define GEN8_ROW_CHICKEN   MCR_REG(0xe4f0)
 #define   FLOW_CONTROL_ENABLE  REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1c8e0e91a2fe..6ea453ddd011 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2971,6 +2971,11 @@ general_render_compute_wa_init(struct intel_engine_cs 
*engine, struct i915_wa_li
 
add_render_compute_tuning_settings(i915, wal);
 
+   if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+   IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+   /* Wa_14017856879 */
+   wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, 
MTL_DISABLE_FIX_FOR_EOT_FLUSH);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
/*
-- 
2.25.1

[Intel-gfx] [PATCH dii-client] drm/i915/mtl: Add Wa_14017856879 for mtl

2023-04-04 Thread Haridhar Kalvala 
Wa_14017856879 implementation for mtl.

Bspec: 46046

Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 35a4cfac2d20..492b3de6678d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1177,7 +1177,9 @@
 #define   THREAD_EX_ARB_MODE_RR_AFTER_DEP  
REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
+#define GEN9_ROW_CHICKEN3  MCR_REG(0xe49c)
 #define   HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE   (1 << 6)
+#define   MTL_DISABLE_FIX_FOR_EOT_FLUSHREG_BIT(9)
 
 #define GEN8_ROW_CHICKEN   MCR_REG(0xe4f0)
 #define   FLOW_CONTROL_ENABLE  REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1c8e0e91a2fe..6ea453ddd011 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2971,6 +2971,11 @@ general_render_compute_wa_init(struct intel_engine_cs 
*engine, struct i915_wa_li
 
add_render_compute_tuning_settings(i915, wal);
 
+   if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+   IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+   /* Wa_14017856879 */
+   wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, 
MTL_DISABLE_FIX_FOR_EOT_FLUSH);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
/*
-- 
2.25.1