[Intel-gfx] [PATCH 8/8] drm/i915/mtl: Hook up interrupts for standalone media
Top-level handling of standalone media interrupts will be processed as
part of the primary GT's interrupt handler (since primary and media GTs
share an MMIO space, unlike remote tile setups). When we get down to
the point of handling engine interrupts, we need to take care to lookup
VCS and VECS engines in the media GT rather than the primary.
There are also a couple of additional "other" instance bits that
correspond to the media GT's GuC and media GT's power management
interrupts; we need to direct those to the media GT instance as well.
Bspec: 45605
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 19 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_sa_media.c | 7 +++
drivers/gpu/drm/i915/i915_drv.h | 3 +++
4 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 0dfd0c42d00d..f26882fdc24c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -59,11 +59,17 @@ static void
gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
const u16 iir)
{
+ struct intel_gt *media_gt = gt->i915->media_gt;
+
if (instance == OTHER_GUC_INSTANCE)
return guc_irq_handler(>->uc.guc, iir);
+ if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt)
+ return guc_irq_handler(&media_gt->uc.guc, iir);
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt)
+ return gen11_rps_irq_handler(&media_gt->rps, iir);
if (instance == OTHER_KCR_INSTANCE)
return intel_pxp_irq_handler(>->pxp, iir);
@@ -81,6 +87,18 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
{
struct intel_engine_cs *engine;
+ /*
+* Platforms with standalone media have their media engines in another
+* GT.
+*/
+ if (MEDIA_VER(gt->i915) >= 13 &&
+ (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
+ if (!gt->i915->media_gt)
+ goto err;
+
+ gt = gt->i915->media_gt;
+ }
+
if (instance <= MAX_ENGINE_INSTANCE)
engine = gt->engine_class[class][instance];
else
@@ -89,6 +107,7 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
if (likely(engine))
return intel_engine_cs_irq(engine, iir);
+err:
WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
class, instance);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 05a40ef33258..21c7a225157f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1552,6 +1552,8 @@
#define OTHER_GTPM_INSTANCE 1
#define OTHER_KCR_INSTANCE 4
#define OTHER_GSC_INSTANCE 6
+#define OTHER_MEDIA_GUC_INSTANCE 16
+#define OTHER_MEDIA_GTPM_INSTANCE17
#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c
b/drivers/gpu/drm/i915/gt/intel_sa_media.c
index cf3053710bbf..41c270f103cf 100644
--- a/drivers/gpu/drm/i915/gt/intel_sa_media.c
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -36,5 +36,12 @@ int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t
phys_addr,
gt->uncore = uncore;
gt->phys_addr = phys_addr;
+ /*
+* For current platforms we can assume there's only a single
+* media GT and cache it for quick lookup.
+*/
+ drm_WARN_ON(&i915->drm, i915->media_gt);
+ i915->media_gt = gt;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d45dca70bfa6..917958d42805 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -497,6 +497,9 @@ struct drm_i915_private {
struct kobject *sysfs_gt;
+ /* Quick lookup of media GT (current platforms only have one) */
+ struct intel_gt *media_gt;
+
struct {
struct i915_gem_contexts {
spinlock_t lock; /* locks list */
--
2.37.2
[Intel-gfx] [PATCH 6/8] drm/i915/xelpmp: Expose media as another GT
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +
drivers/gpu/drm/i915/gt/intel_sa_media.c | 39
drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +
drivers/gpu/drm/i915/i915_pci.c | 15 +
drivers/gpu/drm/i915/intel_device_info.h | 5 ++-
drivers/gpu/drm/i915/intel_uncore.c | 16 --
drivers/gpu/drm/i915/intel_uncore.h | 20 ++--
9 files changed, 123 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..e83e4cd46968 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -123,6 +123,7 @@ gt-y += \
gt/intel_ring.o \
gt/intel_ring_submission.o \
gt/intel_rps.o \
+ gt/intel_sa_media.o \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index d21ec11346a5..2a29502289cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -776,10 +776,15 @@ void intel_gt_driver_late_release_all(struct
drm_i915_private *i915)
}
}
-static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
+static int intel_gt_tile_setup(struct intel_gt *gt,
+ phys_addr_t phys_addr,
+ u32 gsi_offset)
{
int ret;
+ /* GSI offset is only applicable for media GTs */
+ drm_WARN_ON(>->i915->drm, gsi_offset);
+
if (!gt_is_root(gt)) {
struct intel_uncore *uncore;
@@ -832,7 +837,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
- ret = intel_gt_tile_setup(gt, phys_addr);
+ ret = intel_gt_tile_setup(gt, phys_addr, 0);
if (ret)
return ret;
@@ -862,7 +867,8 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
goto err;
}
- ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base,
+ gtdef->gsi_offset);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 94f9ddcfb3a5..05a40ef33258 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1576,4 +1576,12 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
+/*
+ * Standalone Media's non-engine GT registers are located at their regular GT
+ * offsets plus 0x38. This extra offset is stored inside the intel_uncore
+ * structure so that the existing code can be used for both GTs without
+ * modification.
+ */
+#define MTL_MEDIA_GSI_BASE 0x38
+
#endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c
b/drivers/gpu/drm/i915/gt/intel_sa_media.c
new file mode 100644
index ..8c5c519457cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include
+
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_sa_media.h"
+
+int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
+ u32 gsi_offset)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore;
+
+ uncore = drmm_kzalloc(&i915->drm, sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ uncore->gsi_offset = gsi_offset;
+
+ intel_gt_common_init_early(gt);
+ intel_uncore_init_early(uncore, gt);
+
+ /*
+* Standalone media shares the general MMIO space with the primary
+* GT. We'll re-use the primary GT's mapping.
+*/
+ uncore->regs = i915->uncore.regs;
+ if (drm_WARN_ON(&i915->drm, uncore->regs == NULL))
+ return -EIO;
+
+ gt->uncore = uncore;
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_m
[Intel-gfx] [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume}
Moving the locking for MMIO debug (and the final check for unclaimed
accesses when resuming debug after a userspace-initiated forcewake) will
make it simpler to completely skip MMIO debug handling on uncores that
don't support it in future patches.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_uncore.c | 41 +++--
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 9b81b2543ce2..e717ea55484a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -50,23 +50,33 @@ intel_uncore_mmio_debug_init_early(struct
intel_uncore_mmio_debug *mmio_debug)
mmio_debug->unclaimed_mmio_check = 1;
}
-static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug)
+static void mmio_debug_suspend(struct intel_uncore *uncore)
{
- lockdep_assert_held(&mmio_debug->lock);
+ spin_lock(&uncore->debug->lock);
/* Save and disable mmio debugging for the user bypass */
- if (!mmio_debug->suspend_count++) {
- mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check;
- mmio_debug->unclaimed_mmio_check = 0;
+ if (!uncore->debug->suspend_count++) {
+ uncore->debug->saved_mmio_check =
uncore->debug->unclaimed_mmio_check;
+ uncore->debug->unclaimed_mmio_check = 0;
}
+
+ spin_unlock(&uncore->debug->lock);
}
-static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
+static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);
+
+static void mmio_debug_resume(struct intel_uncore *uncore)
{
- lockdep_assert_held(&mmio_debug->lock);
+ spin_lock(&uncore->debug->lock);
+
+ if (!--uncore->debug->suspend_count)
+ uncore->debug->unclaimed_mmio_check =
uncore->debug->saved_mmio_check;
- if (!--mmio_debug->suspend_count)
- mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check;
+ if (check_for_unclaimed_mmio(uncore))
+ drm_info(&uncore->i915->drm,
+"Invalid mmio detected during user access\n");
+
+ spin_unlock(&uncore->debug->lock);
}
static const char * const forcewake_domain_names[] = {
@@ -677,9 +687,7 @@ void intel_uncore_forcewake_user_get(struct intel_uncore
*uncore)
spin_lock_irq(&uncore->lock);
if (!uncore->user_forcewake_count++) {
intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
- spin_lock(&uncore->debug->lock);
- mmio_debug_suspend(uncore->debug);
- spin_unlock(&uncore->debug->lock);
+ mmio_debug_suspend(uncore);
}
spin_unlock_irq(&uncore->lock);
}
@@ -695,14 +703,7 @@ void intel_uncore_forcewake_user_put(struct intel_uncore
*uncore)
{
spin_lock_irq(&uncore->lock);
if (!--uncore->user_forcewake_count) {
- spin_lock(&uncore->debug->lock);
- mmio_debug_resume(uncore->debug);
-
- if (check_for_unclaimed_mmio(uncore))
- drm_info(&uncore->i915->drm,
-"Invalid mmio detected during user access\n");
- spin_unlock(&uncore->debug->lock);
-
+ mmio_debug_resume(uncore);
intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
}
spin_unlock_irq(&uncore->lock);
--
2.37.2
[Intel-gfx] [PATCH 5/8] drm/i915: Rename and expose common GT early init routine
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 7c0525e96155..d21ec11346a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -35,7 +35,7 @@
#include "intel_uncore.h"
#include "shmem_utils.h"
-static void __intel_gt_init_early(struct intel_gt *gt)
+void intel_gt_common_init_early(struct intel_gt *gt)
{
spin_lock_init(>->irq_lock);
@@ -65,7 +65,7 @@ void intel_root_gt_init_early(struct drm_i915_private *i915)
gt->i915 = i915;
gt->uncore = &i915->uncore;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -789,7 +789,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
phys_addr_t phys_addr)
gt->uncore = uncore;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
intel_uncore_init_early(gt->uncore, gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 4d8779529cc2..c9a359f35d0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -44,6 +44,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc
*gsc)
return container_of(gsc, struct intel_gt, gsc);
}
+void intel_gt_common_init_early(struct intel_gt *gt);
void intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
--
2.37.2
[Intel-gfx] [PATCH 2/8] drm/i915: Only hook up uncore->debug for primary uncore
The original intent of intel_uncore_mmio_debug as described in commit
0a9b26306d6a ("drm/i915: split out uncore_mmio_debug") was to be a
singleton structure that could be shared between multiple GTs' uncore
objects in a multi-tile system. Somehow we went off track and
started allocating separate instances of this structure for each GT,
which defeats that original goal.
But in reality, there isn't even a need to share the mmio_debug between
multiple GTs; on all modern platforms (i.e., everything after gen7)
unclaimed register accesses are something that can only be detected for
display registers. There's no point in grabbing the debug spinlock and
checking for unclaimed accesses on an uncore used by an xehpsdv or pvc
remote tile GT, or the uncore used by a mtl standalone media GT since
all of the display accesses go through the primary intel_uncore.
The simplest solution is to simply leave uncore->debug NULL on all
intel_uncore instances except for the primary one. This will allow us
to avoid the pointless debug spinlock acquisition we've been doing on
MMIO accesses coming in through these intel_uncores.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 9 -
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 23 ++-
drivers/gpu/drm/i915/intel_uncore.h | 3 +--
4 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index e4bac2431e41..a82b5e2e0d83 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -781,21 +781,13 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
phys_addr_t phys_addr)
int ret;
if (!gt_is_root(gt)) {
- struct intel_uncore_mmio_debug *mmio_debug;
struct intel_uncore *uncore;
uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
if (!uncore)
return -ENOMEM;
- mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
- if (!mmio_debug) {
- kfree(uncore);
- return -ENOMEM;
- }
-
gt->uncore = uncore;
- gt->uncore->debug = mmio_debug;
__intel_gt_init_early(gt);
}
@@ -817,7 +809,6 @@ intel_gt_tile_cleanup(struct intel_gt *gt)
intel_uncore_cleanup_mmio(gt->uncore);
if (!gt_is_root(gt)) {
- kfree(gt->uncore->debug);
kfree(gt->uncore);
kfree(gt);
}
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 053a7dab5506..de9020771836 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -326,7 +326,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
intel_device_info_subplatform_init(dev_priv);
intel_step_init(dev_priv);
- intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
+ intel_uncore_mmio_debug_init_early(dev_priv);
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index e717ea55484a..6841f76533f9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -44,14 +44,19 @@ fw_domains_get(struct intel_uncore *uncore, enum
forcewake_domains fw_domains)
}
void
-intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
+intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
{
- spin_lock_init(&mmio_debug->lock);
- mmio_debug->unclaimed_mmio_check = 1;
+ spin_lock_init(&i915->mmio_debug.lock);
+ i915->mmio_debug.unclaimed_mmio_check = 1;
+
+ i915->uncore.debug = &i915->mmio_debug;
}
static void mmio_debug_suspend(struct intel_uncore *uncore)
{
+ if (!uncore->debug)
+ return;
+
spin_lock(&uncore->debug->lock);
/* Save and disable mmio debugging for the user bypass */
@@ -67,6 +72,9 @@ static bool check_for_unclaimed_mmio(struct intel_uncore
*uncore);
static void mmio_debug_resume(struct intel_uncore *uncore)
{
+ if (!uncore->debug)
+ return;
+
spin_lock(&uncore->debug->lock);
if (!--uncore->debug->suspend_count)
@@ -1705,7 +1713,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
const bool read,
const bool before)
{
- if (likely(!uncore->i915->params.mmio_debug))
+ if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug)
return;
/* interrupts are disabled and re-enabled around uncore->lock usage
[Intel-gfx] [PATCH 4/8] drm/i915: Prepare more multi-GT initialization
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
immediate MTL media enabling, this same framework will also be used
farther down the road when we enable remote tiles on xehpsdv and pvc.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 48 +--
drivers/gpu/drm/i915/gt/intel_gt.h| 1 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 16 +++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
7 files changed, 67 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..41acc285e8bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index cf7aab7adb30..7c0525e96155 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -807,17 +807,16 @@ static void
intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
-
- if (!gt_is_root(gt))
- kfree(gt);
}
int intel_gt_probe_all(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_gt *gt = &i915->gt0;
+ const struct intel_gt_definition *gtdef;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
@@ -828,14 +827,55 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
* and it has been already initialized early during probe
* in i915_driver_probe()
*/
+ gt->i915 = i915;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
i915->gt[0] = gt;
- /* TODO: add more tiles */
+ for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
+gtdef->setup != NULL;
+i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
+ gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ gt->i915 = i915;
+ gt->name = gtdef->name;
+ gt->type = gtdef->type;
+ gt->info.engine_mask = gtdef->engine_mask;
+ gt->info.id = i;
+
+ drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
+ if (GEM_WARN_ON(range_overflows_t(resource_size_t,
+ gtdef->mapping_base,
+ SZ_16M,
+ pci_resource_len(pdev,
mmio_bar {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ if (ret)
+ goto err;
+
+ i915->gt[i] = gt;
+ }
+
return 0;
+
+err:
+ i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name,
ret);
+ intel_gt_release_all(i915);
+
+ return ret;
}
int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 40b06adf509a..4d8779529cc2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
-
void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int intel_gt_wait_for_idle(struct intel_gt *gt, l
[Intel-gfx] [PATCH 3/8] drm/i915: Use managed allocations for extra uncore objects
We're slowly transitioning the init-time kzalloc's of the driver over to
DRM-managed allocations; let's make sure the uncore objects allocated
for non-root GTs are thus allocated.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a82b5e2e0d83..cf7aab7adb30 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -783,7 +783,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
phys_addr_t phys_addr)
if (!gt_is_root(gt)) {
struct intel_uncore *uncore;
- uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
+ uncore = drmm_kzalloc(>->i915->drm, sizeof(*uncore),
GFP_KERNEL);
if (!uncore)
return -ENOMEM;
@@ -808,10 +808,8 @@ intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
- if (!gt_is_root(gt)) {
- kfree(gt->uncore);
+ if (!gt_is_root(gt))
kfree(gt);
- }
}
int intel_gt_probe_all(struct drm_i915_private *i915)
--
2.37.2
[Intel-gfx] [PATCH 0/8] i915: Add "standalone media" support for MTL
Starting with MTL, media functionality has moved into a new, second GT
at the hardware level. This new GT, referred to as "standalone media"
in the spec, has its own GuC, power management/forcewake, etc. The
general non-engine GT registers for standalone media start at 0x38,
but otherwise use the same MMIO offsets as the primary GT.
Standalone media has a lot of similarity to the remote tiles
present on platforms like xehpsdv and pvc, and our i915 implementation
can share much of the general "multi GT" infrastructure between the two
types of platforms. However there are a few notable differences
we must deal with:
- The 0x38 offset only applies to the non-engine GT registers
(which the specs refer to as "GSI" registers). The engine registers
remain at their usual locations (e.g., 0x1C for VCS0).
- Unlike platforms with remote tiles, all interrupt handling for
standalone media still happens via the primary GT.
Matt Roper (8):
drm/i915: Move locking and unclaimed check into
mmio_debug_{suspend,resume}
drm/i915: Only hook up uncore->debug for primary uncore
drm/i915: Use managed allocations for extra uncore objects
drm/i915: Prepare more multi-GT initialization
drm/i915: Rename and expose common GT early init routine
drm/i915/xelpmp: Expose media as another GT
drm/i915/mtl: Use primary GT's irq lock for media GT
drm/i915/mtl: Hook up interrupts for standalone media
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 +--
drivers/gpu/drm/i915/gt/intel_gt.c| 88 ++-
drivers/gpu/drm/i915/gt/intel_gt.h| 4 +-
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 35 ++--
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 8 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 10 +++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 26 +++---
drivers/gpu/drm/i915/gt/intel_sa_media.c | 47 ++
drivers/gpu/drm/i915/gt/intel_sa_media.h | 15
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 24 ++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_driver.c| 6 +-
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_pci.c | 15
drivers/gpu/drm/i915/intel_device_info.h | 19
drivers/gpu/drm/i915/intel_uncore.c | 80 +++--
drivers/gpu/drm/i915/intel_uncore.h | 23 -
drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +-
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 14 +--
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 4 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
25 files changed, 340 insertions(+), 116 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
--
2.37.2
Re: [Intel-gfx] [PATCH v2 15/21] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox
On Thu, Aug 18, 2022 at 04:41:56PM -0700, Radhakrishna Sripada wrote:
> From Meteorlake, Latency Level, SAGV bloack time are read from
> LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type
> and QGV information are also to be read from Mem SS registers.
>
> v2:
> - Simplify MTL_MEM_SS_INFO_QGV_POINT macro(MattR)
> - Nit: Rearrange the bit def's from higher to lower(MattR)
> - Restore platform definition for ADL-P(MattR)
> - Move back intel_qgv_point def to intel_bw.c(Jani)
> Bspec: 64636, 64608
>
> Cc: Matt Roper
> Cc: Jani Nikula
> Original Author: Caz Yokoyama
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 42 ++---
> drivers/gpu/drm/i915/i915_reg.h | 16 ++
> drivers/gpu/drm/i915/intel_dram.c | 41 +++-
> drivers/gpu/drm/i915/intel_pm.c | 8 -
> 4 files changed, 100 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 79269d2c476b..46b63afd536a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -137,6 +137,42 @@ int icl_pcode_restrict_qgv_points(struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> +static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
> +struct intel_qgv_point *sp, int point)
> +{
> + u32 val, val2;
> + u16 dclk;
> +
> + val = intel_uncore_read(&dev_priv->uncore,
> + MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
> + val2 = intel_uncore_read(&dev_priv->uncore,
> + MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
> + dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
> + sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
> + sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
> + sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
> +
> + sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
> + sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
> +
> + sp->t_rc = sp->t_rp + sp->t_ras;
> +
> + return 0;
> +}
> +
> +static int
> +intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
> + struct intel_qgv_point *sp,
> + int point)
> +{
> + if (DISPLAY_VER(dev_priv) >= 14)
> + return mtl_read_qgv_point_info(dev_priv, sp, point);
> + else if (IS_DG1(dev_priv))
> + return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
> + else
> + return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
> +}
> +
> static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_info *qi,
> bool is_y_tile)
> @@ -193,11 +229,7 @@ static int icl_get_qgv_points(struct drm_i915_private
> *dev_priv,
> for (i = 0; i < qi->num_points; i++) {
> struct intel_qgv_point *sp = &qi->points[i];
>
> - if (IS_DG1(dev_priv))
> - ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
> - else
> - ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
> -
> + ret = intel_read_qgv_point_info(dev_priv, sp, i);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b2d5e1230c25..5245af8d0ea8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8397,4 +8397,20 @@ enum skl_power_gate {
> #define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0)
> #define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16)
>
> +#define MTL_LATENCY_SAGV _MMIO(0x4578c)
> +#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
Minor nitpick: we usually have two additional spaces (for a total of
three) between the 'define' and the field name.
> +
> +#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
> +#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
> +#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
> +#define MTL_N_OF_ENABLED_QGV_POINTS_MASKREG_GENMASK(11, 8)
Another nitpick: we usually order fields from low to high (which is
also usually how the spec orders them).
> +
> +#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2)
> +#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 +
> (point) * 2)
> +#def
[Intel-gfx] [PATCH] drm/i915/ats-m: Add thread execution tuning setting
On client DG2 platforms, optimal performance is achieved with the
hardware's default "age based" thread execution setting. However on
ATS-M, switching this to "round robin after dependencies" provides
better performance. We'll add a new "tuning" feature flag to the ATS-M
device info to enable/disable this setting.
Bspec: 68331
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h| 1 +
4 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 94f9ddcfb3a5..d414785003cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1110,6 +1110,8 @@
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
#define GEN11_DIS_PICK_2ND_EUREG_BIT(7)
#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
+#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
+#define THREAD_EX_ARB_MODE_RR_AFTER_DEP
REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3cdb8294e13f..ff8c3735abc9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2700,6 +2700,15 @@ add_render_compute_tuning_settings(struct
drm_i915_private *i915,
0 /* write-only, so skip validation */,
true);
}
+
+ /*
+* This tuning setting proves beneficial only on ATS-M designs; the
+* default "age based" setting is optimal on regular DG2 and other
+* platforms.
+*/
+ if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
+ wa_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
+ THREAD_EX_ARB_MODE_RR_AFTER_DEP);
}
/*
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 857e8bb6865c..26b25d9434d6 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1080,6 +1080,7 @@ static const struct intel_device_info ats_m_info = {
DG2_FEATURES,
.display = { 0 },
.require_force_probe = 1,
+ .tuning_thread_rr_after_dep = 1,
};
#define XE_HPC_FEATURES \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0ccde94b225f..6904ad03ca19 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -171,6 +171,7 @@ enum intel_ppgtt_type {
func(has_runtime_pm); \
func(has_snoop); \
func(has_coherent_ggtt); \
+ func(tuning_thread_rr_after_dep); \
func(unfenced_needs_alignment); \
func(hws_needs_physical);
--
2.37.2
[Intel-gfx] [PATCH] Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"
This reverts commit ca6920811aa5428270dd78af0a7a36b10119065a.
The intent of Wa_14015141709 was to inform us that userspace can no
longer control object-level preemption as it has on past platforms
(i.e., by twiddling register bit CS_CHICKEN1[0]). The description of
the workaround in the spec wasn't terribly well-written, and when we
requested clarification from the hardware teams we were told that on the
kernel side we should also probably stop setting
FF_SLICE_CS_CHICKEN1[14], which is the register bit that directs the
hardware to honor the settings in per-context register CS_CHICKEN1. It
turns out that this guidance about FF_SLICE_CS_CHICKEN1[14] was a
mistake; even though CS_CHICKEN1[0] is non-operational and useless to
userspace, there are other bits in the register that do still work and
might need to be adjusted by userspace in the future (e.g., to implement
other workarounds that show up). If we don't set
FF_SLICE_CS_CHICKEN1[14] in i915, then those future workarounds would
not take effect.
This miscommunication came to light because another workaround
(Wa_16013994831) has now shown up that requires userspace to adjust the
value of CS_CHICKEN[10] in certain circumstances. To ensure userspace's
updates to this chicken bit are handled properly by the hardware, we
need to make sure that FF_SLICE_CS_CHICKEN1[14] is once again set by the
kernel.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 ---
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3cdb8294e13f..69a0c6a74474 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2389,7 +2389,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
FF_DOP_CLOCK_GATE_DISABLE);
}
- if (HAS_PERCTX_PREEMPT_CTRL(i915)) {
+ if (IS_GRAPHICS_VER(i915, 9, 12)) {
/*
FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
wa_masked_en(wal,
GEN7_FF_SLICE_CS_CHICKEN1,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b00ef3626db..d6a1ab6f65de 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1352,9 +1352,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GUC_DEPRIVILEGE(dev_priv) \
(INTEL_INFO(dev_priv)->has_guc_deprivilege)
-#define HAS_PERCTX_PREEMPT_CTRL(i915) \
- ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
-
#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
IS_ALDERLAKE_S(dev_priv))
--
2.37.2
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning
i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614 > [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 > [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 > [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 > [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 > [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939 > [i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941 > [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 > [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 > [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598 > [i915#6637]: https://gitlab.freedesktop.org/drm/intel/issues/6637 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > > > Build changes > - > > * Linux: CI_DRM_12017 -> Patchwork_107638v1 > > CI-20190529: 20190529 > CI_DRM_12017: d09b6a64bd55b1c8c7baada7537621015f0cfd71 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_6634: e01fe99f00692864b709253638c809231d1fb333 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_107638v1: d09b6a64bd55b1c8c7baada7537621015f0cfd71 @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add Wa_1509727124
On Wed, Aug 24, 2022 at 02:26:38PM +0300, Joonas Lahtinen wrote: > Quoting Matt Roper (2022-08-02 18:09:16) > > On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote: > > > Bspec: 46052 > > > Reviewed-by: Matt Roper > > > Signed-off-by: Harish Chegondi > > > > Applied to drm-intel-gt-next. Thanks for the patch. > > This patch is completely lacking the commit message. > > That is unacceptable, please make sure there is a proper commit message > for any merged patches going forward. > > Please do explain the patch rationale in this mail thread so it at least > becomes available from the Link: that gets added by DIM when this was > committed. > > Regards, Joonas There isn't really too much to say on this one. For the record, the justification is that we're implementing Wa_1509727124 from the workaround database which simply tells us that we need to program 0xE18C[9] to 1; this patch is just following that guidance from the spec. There's no further information available beyond that. Going forward we'll make sure we put some kind of statement in the commit message body to make it clear that the workaround number and register/bit setting are the only information we have and that this isn't an oversight. Thanks. Matt -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
[Intel-gfx] [PATCH v2 2/2] drm/i915/dg2: Add additional tuning settings
Some additional MMIO tuning settings have appeared in the bspec's
performance tuning guide section.
One of the tuning settings here is also documented as formal workaround
Wa_22012654132 for some steppings of DG2. However the tuning setting
applies to all DG2 variants and steppings, making it a superset of the
workaround.
v2:
- Move DRAW_WATERMARK to engine workaround section. It only moves into
the engine context on future platforms. (Lucas)
- CHICKEN_RASTER_2 needs to be handled as a masked register. (Lucas)
Bspec: 68331
Cc: Lucas De Marchi
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++---
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index b3b49f6d6d1c..f64fafe28f72 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -259,6 +259,9 @@
#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
#define GEN9_PREEMPT_GPGPU_LEVEL_MASK
GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
+#define DRAW_WATERMARK _MMIO(0x26c0)
+#define VERT_WM_VAL REG_GENMASK(9, 0)
+
#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /*
Global MOCS regs */
#define RENDER_HWS_PGA_GEN7_MMIO(0x4080)
@@ -374,6 +377,9 @@
#define CHICKEN_RASTER_1 _MMIO(0x6204)
#define DIS_SF_ROUND_NEAREST_EVENREG_BIT(8)
+#define CHICKEN_RASTER_2 _MMIO(0x6208)
+#define TBIMR_FAST_CLIP REG_BIT(5)
+
#define VFLSKPD_MMIO(0x62a8)
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
@@ -1124,6 +1130,8 @@
#define RT_CTRL_MMIO(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)
+#define STACKID_CTRL REG_GENMASK(6, 5)
+#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL,
0x2)
#define EU_PERF_CNTL1 _MMIO(0xe558)
#define EU_PERF_CNTL5 _MMIO(0xe55c)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a68d279b01f0..31e129329fb0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -568,6 +568,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs
*engine,
static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
wa_add(wal,
@@ -2195,15 +2196,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
}
- if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) ||
- IS_DG2_G11(i915)) {
- /* Wa_22012654132:dg2 */
- wa_add(wal, GEN10_CACHE_MODE_SS, 0,
- _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
- 0 /* write-only, so skip validation */,
- true);
- }
-
/* Wa_14013202645:dg2 */
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0))
@@ -2692,6 +2684,23 @@ add_render_compute_tuning_settings(struct
drm_i915_private *i915,
if (IS_DG2(i915)) {
wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+ wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
+ wa_write_clr_set(wal, DRAW_WATERMARK, VERT_WM_VAL,
+REG_FIELD_PREP(VERT_WM_VAL, 0x3FF));
+
+ /*
+* This is also listed as Wa_22012654132 for certain DG2
+* steppings, but the tuning setting programming is a superset
+* since it applies to all DG2 variants and steppings.
+*
+* Note that register 0xE420 is write-only and cannot be read
+* back for verification on DG2 (due to Wa_14012342262), so
+* we need to explicitly skip the readback.
+*/
+ wa_add(wal, GEN10_CACHE_MODE_SS, 0,
+ _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
+ 0 /* write-only, so skip validation */,
+ true);
}
}
--
2.37.1
[Intel-gfx] [PATCH] drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning
Although register tuning settings are generally implemented via the
workaround infrastructure, it turns out that the DRAW_WATERMARK register
is not properly saved/restored by hardware around power events (i.e.,
RC6 entry) so updates to the value cannot be applied in the usual
manner. New workaround Wa_16014892111 informs us that any tuning
updates to this register must instead be applied via an INDIRECT_CTX
batch buffer. This will ensure that the necessary value is re-applied
when a context begins running, even if an RC6 entry had wiped the
register back to hardware defaults since the last context ran.
Fixes: 6dc85721df74 ("drm/i915/dg2: Add additional tuning settings")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6642
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 --
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index eec73c66406c..070cec4ff8a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1242,6 +1242,23 @@ dg2_emit_rcs_hang_wabb(const struct intel_context *ce,
u32 *cs)
return cs;
}
+/*
+ * The bspec's tuning guide asks us to program a vertical watermark value of
+ * 0x3FF. However this register is not saved/restored properly by the
+ * hardware, so we're required to apply the desired value via INDIRECT_CTX
+ * batch buffer to ensure the value takes effect properly. All other bits
+ * in this register should remain at 0 (the hardware default).
+ */
+static u32 *
+dg2_emit_draw_watermark_setting(u32 *cs)
+{
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(DRAW_WATERMARK);
+ *cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF);
+
+ return cs;
+}
+
static u32 *
gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
{
@@ -1263,6 +1280,10 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
*ce, u32 *cs)
if (!HAS_FLAT_CCS(ce->engine->i915))
cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV);
+ /* Wa_16014892111 */
+ if (IS_DG2(ce->engine->i915))
+ cs = dg2_emit_draw_watermark_setting(cs);
+
return cs;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 31e129329fb0..3cdb8294e13f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2685,8 +2685,6 @@ add_render_compute_tuning_settings(struct
drm_i915_private *i915,
if (IS_DG2(i915)) {
wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
- wa_write_clr_set(wal, DRAW_WATERMARK, VERT_WM_VAL,
-REG_FIELD_PREP(VERT_WM_VAL, 0x3FF));
/*
* This is also listed as Wa_22012654132 for certain DG2
--
2.37.2
Re: [Intel-gfx] [PATCH v2 21/21] drm/i915/mtl: Do not update GV point, mask value
On Thu, Aug 18, 2022 at 04:42:02PM -0700, Radhakrishna Sripada wrote:
> No need to update mask value/restrict because
> "Pcode only wants to use GV bandwidth value, not the mask value."
> for Display version greater than 14.
While the code changes might be correct, I can't decipher what the
commit message here is trying to tell us. I'm not sure what the source
or context of the quote is, but the description in the commit message
should be more focused on why it's correct for our driver to skip these
operations. I assume it has something to do with the new pm_demand
interfaces we'll be using to program this information into the hardware
in a future series? If so, maybe this patch (with a modified commit
message) is better suited for inclusion in that future series where the
context makes more sense.
>
> Bspec: 646365
This page number seems to be incorrect too.
Matt
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/intel_pm.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d09e9e5f4481..47869fe964ba 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3924,6 +3924,14 @@ void intel_sagv_pre_plane_update(struct
> intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>
> + /*
> + * No need to update mask value/restrict because
> + * "Pcode only wants to use GV bandwidth value, not the mask value."
> + * for DISPLAY_VER() >= 14.
> + */
> + if (DISPLAY_VER(i915) >= 14)
> + return;
> +
> /*
>* Just return if we can't control SAGV or don't have it.
>* This is different from situation when we have SAGV but just can't
> @@ -3944,6 +3952,16 @@ void intel_sagv_post_plane_update(struct
> intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
>
> + /*
> + * No need to update mask value/restrict because
> + * "Pcode only wants to use GV bandwidth value, not the mask value."
> + * for DISPLAY_VER() >= 14.
> + *
> + * GV bandwidth will be set by intel_pmdemand_post_plane_update()
> + */
> + if (DISPLAY_VER(i915) >= 14)
> + return;
> +
> /*
>* Just return if we can't control SAGV or don't have it.
>* This is different from situation when we have SAGV but just can't
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2 14/21] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM
On Thu, Aug 18, 2022 at 04:41:55PM -0700, Radhakrishna Sripada wrote:
> Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
> instead of GT driver mailbox.
>
> v2: Use the extracted wm latency adjustment function(Matt)
>
> Bspec: 64608
>
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++
> drivers/gpu/drm/i915/intel_pm.c | 21 ++---
> 2 files changed, 25 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 04a269fa8717..b2d5e1230c25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8390,4 +8390,11 @@ enum skl_power_gate {
> #define GEN12_STATE_ACK_DEBUG_MMIO(0x20BC)
>
> #define MTL_MEDIA_GSI_BASE 0x38
> +
> +#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
> +#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
> +#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
> +#define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0)
> +#define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16)
You might consider "_{EVEN,ODD}_LEVEL_MASK" naming here, just in case
future IP versions add additional levels beyond LP5.
Otherwise,
Reviewed-by: Matt Roper
> +
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 898e56d2eaf7..fac565d23d57 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2908,13 +2908,28 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> u16 wm[])
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> + int max_level = ilk_wm_max_level(dev_priv);
>
> - if (DISPLAY_VER(dev_priv) >= 9) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + u32 val;
> +
> + val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1);
> + wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
> + wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
> + val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3);
> + wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
> + wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
> + val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5);
> + wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
> + wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
> +
> + adjust_wm_latency(wm, max_level, 6,
> + dev_priv->dram_info.wm_lv_0_adjust_needed);
> + } else if (DISPLAY_VER(dev_priv) >= 9) {
> int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
> + int mult = IS_DG2(dev_priv) ? 2 : 1;
> u32 val;
> int ret;
> - int max_level = ilk_wm_max_level(dev_priv);
> - int mult = IS_DG2(dev_priv) ? 2 : 1;
>
> /* read the first set of memory latencies[0:3] */
> val = 0; /* data0 to be programmed to 0 for first set */
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2 13/21] drm/i915: Extract wm latency adjustment to its own function
On Thu, Aug 18, 2022 at 04:41:54PM -0700, Radhakrishna Sripada wrote:
> Watermark latency is adjusted in cases when latency is 0us for level
> greater than 1, the subsequent levels are disabled. Extract this logic
> into its own function.
>
> Suggested-by: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/intel_pm.c | 88 ++---
> 1 file changed, 48 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ef7553b494ea..898e56d2eaf7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2861,15 +2861,59 @@ static void ilk_compute_wm_level(const struct
> drm_i915_private *dev_priv,
> result->enable = true;
> }
>
> +static void
> +adjust_wm_latency(u16 wm[], int max_level, int read_latency,
> + bool wm_lv_0_adjust_needed)
> +{
> + int i, level;
> +
> + /*
> + * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
> + * need to be disabled. We make sure to sanitize the values out
> + * of the punit to satisfy this requirement.
> + */
> + for (level = 1; level <= max_level; level++) {
> + if (wm[level] == 0) {
> + for (i = level + 1; i <= max_level; i++)
> + wm[i] = 0;
> +
> + max_level = level - 1;
> + break;
> + }
> + }
> +
> + /*
> + * WaWmMemoryReadLatency
> + *
> + * punit doesn't take into account the read latency so we need
> + * to add proper adjustement to each valid level we retrieve
> + * from the punit when level 0 response data is 0us.
> + */
> + if (wm[0] == 0) {
> + for (level = 0; level <= max_level; level++)
> + wm[level] += read_latency;
> + }
> +
> + /*
> + * WA Level-0 adjustment for 16GB DIMMs: SKL+
> + * If we could not get dimm info enable this WA to prevent from
> + * any underrun. If not able to get Dimm info assume 16GB dimm
> + * to avoid any underrun.
> + */
> + if (wm_lv_0_adjust_needed)
> + wm[0] += 1;
> +}
> +
> static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
> u16 wm[])
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
>
> if (DISPLAY_VER(dev_priv) >= 9) {
> + int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
> u32 val;
> - int ret, i;
> - int level, max_level = ilk_wm_max_level(dev_priv);
> + int ret;
> + int max_level = ilk_wm_max_level(dev_priv);
> int mult = IS_DG2(dev_priv) ? 2 : 1;
>
> /* read the first set of memory latencies[0:3] */
> @@ -2909,44 +2953,8 @@ static void intel_read_wm_latency(struct
> drm_i915_private *dev_priv,
> wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
> GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
>
> - /*
> - * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
> - * need to be disabled. We make sure to sanitize the values out
> - * of the punit to satisfy this requirement.
> - */
> - for (level = 1; level <= max_level; level++) {
> - if (wm[level] == 0) {
> - for (i = level + 1; i <= max_level; i++)
> - wm[i] = 0;
> -
> - max_level = level - 1;
> -
> - break;
> - }
> - }
> -
> - /*
> - * WaWmMemoryReadLatency
> - *
> - * punit doesn't take into account the read latency so we need
> - * to add proper adjustement to each valid level we retrieve
> - * from the punit when level 0 response data is 0us.
> - */
> - if (wm[0] == 0) {
> - u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
> -
> - for (level = 0; level <= max_level; level++)
> - wm[level] += adjust;
> - }
> -
> - /*
> - * WA Level-0 adjustment for 16GB DIMMs: SKL+
> - * If we could not get dimm info enable this WA to prevent from
> - * any underrun. If not able to get Dimm info assume 16GB dimm
> - * to
Re: [Intel-gfx] [PATCH v2 07/21] drm/i915/mtl: Add gmbus and gpio support
On Thu, Aug 18, 2022 at 04:41:48PM -0700, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-14] are mapped to TC ports.
>
> BSpec: 49306
>
> Original Author: Brian J Lovin
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 17 +
> drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index a6ba7fb72339..542b8b2654be 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -116,6 +116,20 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
> [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> };
>
> +static const struct gmbus_pin gmbus_pins_mtp[] = {
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> + [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> + [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> + [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
> + [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
There's no GPIO_CTL registers for pin 13 or pin 14 on on MTP so these
last two entries shouldn't be here (and the commit message should be
fixed too).
Matt
> +};
> +
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>unsigned int pin)
> {
> @@ -128,6 +142,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct
> drm_i915_private *i915,
> } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> pins = gmbus_pins_dg1;
> size = ARRAY_SIZE(gmbus_pins_dg1);
> + } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
> + pins = gmbus_pins_mtp;
> + size = ARRAY_SIZE(gmbus_pins_mtp);
> } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
> pins = gmbus_pins_icp;
> size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h
> b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8edc2e99cf53..20f704bd4e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -24,6 +24,7 @@ struct i2c_adapter;
> #define GMBUS_PIN_2_BXT 2
> #define GMBUS_PIN_3_BXT 3
> #define GMBUS_PIN_4_CNP 4
> +#define GMBUS_PIN_5_MTP 5
> #define GMBUS_PIN_9_TC1_ICP 9
> #define GMBUS_PIN_10_TC2_ICP 10
> #define GMBUS_PIN_11_TC3_ICP 11
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2 01/21] drm/i915: Read graphics/media/display arch version from hw
On Thu, Aug 18, 2022 at 04:41:42PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper
>
> Going forward, the hardware teams no longer consider new platforms to
> have a "generation" in the way we've defined it for past platforms.
> Instead, each IP block (graphics, media, display) will have their own
> architecture major.minor versions and stepping ID's which should be read
> directly from a register in the MMIO space. New hardware programming
> styles, features, and workarounds should be conditional solely on the
> architecture version, and should no longer be derived from the PCI
> device ID, revision ID, or platform-specific feature flags.
>
> v1.1: Fix build error
As Jani noted on the previous version, this patch needs to be split into
three patches (and/or be based on top of the other series that Jani has
in flight). Also the giant macro is no longer necessary on current
drm-tip now that we the version values stored consistently in
structures; we can just use a regular function and pass pointers to the
structures.
Bala also had feedback on the previous version that hasn't been
incorporated here yet either.
Matt
>
> Bspec: 63361, 64111
>
> Signed-off-by: Matt Roper
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +
> drivers/gpu/drm/i915/i915_driver.c| 80 ++-
> drivers/gpu/drm/i915/i915_drv.h | 16 ++--
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> drivers/gpu/drm/i915/intel_device_info.c | 32
> drivers/gpu/drm/i915/intel_device_info.h | 14
> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
> 8 files changed, 128 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 94f9ddcfb3a5..a053493dae24 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -39,6 +39,8 @@
> #define FORCEWAKE_ACK_RENDER_GEN9_MMIO(0xd84)
> #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
>
> +#define GMD_ID_GRAPHICS _MMIO(0xd8c)
> +
> #define MCFG_MCR_SELECTOR_MMIO(0xfd0)
> #define SF_MCR_SELECTOR _MMIO(0xfd8)
> #define GEN8_MCR_SELECTOR_MMIO(0xfdc)
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index deb8a8b76965..33566f6e9546 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -70,6 +70,7 @@
> #include "gem/i915_gem_pm.h"
> #include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> +#include "gt/intel_gt_regs.h"
> #include "gt/intel_rc6.h"
>
> #include "pxp/intel_pxp_pm.h"
> @@ -306,15 +307,83 @@ static void sanitize_gpu(struct drm_i915_private *i915)
> __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> }
>
> +#define IP_VER_READ(offset, ri_prefix) \
> + addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); \
> + if (drm_WARN_ON(&i915->drm, !addr)) { \
> + /* Fall back to whatever was in the device info */ \
> + RUNTIME_INFO(i915)->ri_prefix.ver =
> INTEL_INFO(i915)->ri_prefix.ver; \
> + RUNTIME_INFO(i915)->ri_prefix.rel =
> INTEL_INFO(i915)->ri_prefix.rel; \
> + goto ri_prefix##done; \
> + } \
> + \
> + ver = ioread32(addr); \
> + pci_iounmap(pdev, addr); \
> + \
> + RUNTIME_INFO(i915)->ri_prefix.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK,
> ver); \
> + RUNTIME_INFO(i915)->ri_prefix.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK,
> ver); \
> + RUNTIME_INFO(i915)->ri_prefix.step = REG_FIELD_GET(GMD_ID_STEP, ver); \
> + \
> + /* Sanity check against expected versions from device info */ \
> + if (RUNTIME_INFO(i915)->ri_prefix.ver !=
> INTEL_INFO(i915)->ri_prefix.ver || \
> + RUNTIME_INFO(i915)->ri_prefix.rel >
> INTEL_INFO(i915)->ri_prefix.rel) \
> + drm_dbg(&i915->drm, \
> + "Hardware reports " #ri_prefix " IP version %u.%u but
> minimum expected is %u.%u\n", \
> + RUNTIME_INFO(i915)->ri_prefix.ver, \
> + RUNTIME_INFO(i915)->ri_prefix.rel, \
> + INTEL_INFO(i915)->ri_prefix.ver, \
> + INTEL_INFO(i915)->ri_prefix.rel); \
> +ri_prefix##done:
> +
> +/**
> + * intel_ip
Re: [Intel-gfx] [PATCH] drm/i915: Skip Bit12 fw domain reset for gen12+
On Wed, Aug 17, 2022 at 03:43:04PM -0700, Radhakrishna Sripada wrote: > Bit12 of the Forcewake request register should not be cleared post > gen12. Do not touch this bit while clearing during fw domain reset. > > Bspec: 52542 > > Signed-off-by: Sushma Venkatesh Reddy > Signed-off-by: Radhakrishna Sripada > --- > drivers/gpu/drm/i915/intel_uncore.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c > b/drivers/gpu/drm/i915/intel_uncore.c > index a852c471d1b3..c85e2b686c95 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -113,7 +113,10 @@ fw_domain_reset(const struct > intel_uncore_forcewake_domain *d) >* off in ICL+), so no waiting for acks >*/ > /* WaRsClearFWBitsAtReset:bdw,skl */ While we're at it, let's remove the "bdw,skl" from this comment since it's misleading and doesn't match the code. We do still apply this workaround on other pre-gen12 platforms than just those two. Aside from the comment tweak, Reviewed-by: Matt Roper > - fw_clear(d, 0x); > + if (GRAPHICS_VER(d->uncore->i915) >= 12) > + fw_clear(d, 0xefff); > + else > + fw_clear(d, 0x); > } > > static inline void > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/gt: Add dedicated function for non-ctx register tuning settings
b.freedesktop.org/drm/intel/issues/5289 > [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 > [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 > [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 > [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 > [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723 > [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 > [i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011 > [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 > [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 > [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 > [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334 > [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 > [i915#6458]: https://gitlab.freedesktop.org/drm/intel/issues/6458 > [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463 > [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493 > [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > > > Build changes > - > > * Linux: CI_DRM_11990 -> Patchwork_107342v1 > > CI-20190529: 20190529 > CI_DRM_11990: 6590d43d39b99e1cd8693801b2ea8adeb97d9a04 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_6629: d24e986fb3b2ab6d755498d27828bc85931d12ff @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_107342v1: 6590d43d39b99e1cd8693801b2ea8adeb97d9a04 @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107342v1/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
[Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Add dedicated function for non-ctx register tuning settings
The bspec performance tuning section gives recommended settings that the
driver should program for various MMIO registers. Although these
settings aren't "workarounds" we use the workaround infrastructure to do
this programming to make sure it is handled at the appropriate places
and doesn't conflict with any real workarounds.
Since more of these are starting to show up on recent platforms, it's a
good time to create a dedicated function to hold them so that there's
less ambiguity about how/where to implement new ones.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 42 ++---
1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 59cf28baa472..a68d279b01f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2102,13 +2102,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
/* Wa_1509235366:dg2 */
wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
INVALIDATION_BROADCAST_MODE_DIS |
GLOBAL_INVALIDATION_MODE);
-
- /*
-* The following are not actually "workarounds" but rather
-* recommended tuning settings documented in the bspec's
-* performance guide section.
-*/
- wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
}
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
@@ -2676,6 +2669,32 @@ ccs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
}
}
+/*
+ * The bspec performance guide has recommended MMIO tuning settings. These
+ * aren't truly "workarounds" but we want to program them with the same
+ * workaround infrastructure to ensure that they're automatically added to
+ * the GuC save/restore lists, re-applied at the right times, and checked for
+ * any conflicting programming requested by real workarounds.
+ *
+ * Programming settings should be added here only if their registers are not
+ * part of an engine's register state context. If a register is part of a
+ * context, then any tuning settings should be programmed in an appropriate
+ * function invoked by __intel_engine_init_ctx_wa().
+ */
+static void
+add_render_compute_tuning_settings(struct drm_i915_private *i915,
+ struct i915_wa_list *wal)
+{
+ if (IS_PONTEVECCHIO(i915)) {
+ wa_write(wal, XEHPC_L3SCRUB,
+SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+ }
+
+ if (IS_DG2(i915)) {
+ wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+ }
+}
+
/*
* The workarounds in this function apply to shared registers in
* the general render reset domain that aren't tied to a
@@ -2690,14 +2709,9 @@ general_render_compute_wa_init(struct intel_engine_cs
*engine, struct i915_wa_li
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_PONTEVECCHIO(i915)) {
- /*
-* The following is not actually a "workaround" but rather
-* a recommended tuning setting documented in the bspec's
-* performance guide section.
-*/
- wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED |
SCRUB_RATE_4B_PER_CLK);
+ add_render_compute_tuning_settings(i915, wal);
+ if (IS_PONTEVECCHIO(i915)) {
/* Wa_16016694945 */
wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
}
--
2.37.1
[Intel-gfx] [PATCH v2 2/2] drm/i915/dg2: Add additional tuning settings
Some additional MMIO tuning settings have appeared in the bspec's
performance tuning guide section.
One of the tuning settings here is also documented as formal workaround
Wa_22012654132 for some steppings of DG2. However the tuning setting
applies to all DG2 variants and steppings, making it a superset of the
workaround.
v2:
- Move DRAW_WATERMARK to engine workaround section. It only moves into
the engine context on future platforms. (Lucas)
- CHICKEN_RASTER_2 needs to be handled as a masked register. (Lucas)
Bspec: 68331
Cc: Lucas De Marchi
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++---
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index b3b49f6d6d1c..f64fafe28f72 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -259,6 +259,9 @@
#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
#define GEN9_PREEMPT_GPGPU_LEVEL_MASK
GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
+#define DRAW_WATERMARK _MMIO(0x26c0)
+#define VERT_WM_VAL REG_GENMASK(9, 0)
+
#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /*
Global MOCS regs */
#define RENDER_HWS_PGA_GEN7_MMIO(0x4080)
@@ -374,6 +377,9 @@
#define CHICKEN_RASTER_1 _MMIO(0x6204)
#define DIS_SF_ROUND_NEAREST_EVENREG_BIT(8)
+#define CHICKEN_RASTER_2 _MMIO(0x6208)
+#define TBIMR_FAST_CLIP REG_BIT(5)
+
#define VFLSKPD_MMIO(0x62a8)
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
@@ -1124,6 +1130,8 @@
#define RT_CTRL_MMIO(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)
+#define STACKID_CTRL REG_GENMASK(6, 5)
+#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL,
0x2)
#define EU_PERF_CNTL1 _MMIO(0xe558)
#define EU_PERF_CNTL5 _MMIO(0xe55c)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a68d279b01f0..31e129329fb0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -568,6 +568,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs
*engine,
static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
wa_add(wal,
@@ -2195,15 +2196,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
}
- if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) ||
- IS_DG2_G11(i915)) {
- /* Wa_22012654132:dg2 */
- wa_add(wal, GEN10_CACHE_MODE_SS, 0,
- _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
- 0 /* write-only, so skip validation */,
- true);
- }
-
/* Wa_14013202645:dg2 */
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0))
@@ -2692,6 +2684,23 @@ add_render_compute_tuning_settings(struct
drm_i915_private *i915,
if (IS_DG2(i915)) {
wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+ wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
+ wa_write_clr_set(wal, DRAW_WATERMARK, VERT_WM_VAL,
+REG_FIELD_PREP(VERT_WM_VAL, 0x3FF));
+
+ /*
+* This is also listed as Wa_22012654132 for certain DG2
+* steppings, but the tuning setting programming is a superset
+* since it applies to all DG2 variants and steppings.
+*
+* Note that register 0xE420 is write-only and cannot be read
+* back for verification on DG2 (due to Wa_14012342262), so
+* we need to explicitly skip the readback.
+*/
+ wa_add(wal, GEN10_CACHE_MODE_SS, 0,
+ _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
+ 0 /* write-only, so skip validation */,
+ true);
}
}
--
2.37.1
[Intel-gfx] [PATCH 2/2] drm/i915/dg2: Add additional tuning settings
Some additional MMIO tuning settings have appeared in the bspec's
performance tuning guide section.
One of the tuning settings here is also documented as formal workaround
Wa_22012654132 for some steppings of DG2. However the tuning setting
applies to all DG2 variants and steppings, making it a superset of the
workaround.
Bspec: 68331
Cc: Lucas De Marchi
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++---
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index b3b49f6d6d1c..f64fafe28f72 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -259,6 +259,9 @@
#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
#define GEN9_PREEMPT_GPGPU_LEVEL_MASK
GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
+#define DRAW_WATERMARK _MMIO(0x26c0)
+#define VERT_WM_VAL REG_GENMASK(9, 0)
+
#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /*
Global MOCS regs */
#define RENDER_HWS_PGA_GEN7_MMIO(0x4080)
@@ -374,6 +377,9 @@
#define CHICKEN_RASTER_1 _MMIO(0x6204)
#define DIS_SF_ROUND_NEAREST_EVENREG_BIT(8)
+#define CHICKEN_RASTER_2 _MMIO(0x6208)
+#define TBIMR_FAST_CLIP REG_BIT(5)
+
#define VFLSKPD_MMIO(0x62a8)
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
@@ -1124,6 +1130,8 @@
#define RT_CTRL_MMIO(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)
+#define STACKID_CTRL REG_GENMASK(6, 5)
+#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL,
0x2)
#define EU_PERF_CNTL1 _MMIO(0xe558)
#define EU_PERF_CNTL5 _MMIO(0xe55c)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a68d279b01f0..2db7f7dc3c8c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -568,6 +568,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs
*engine,
static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ wa_write_or(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
+ wa_write_clr_set(wal, DRAW_WATERMARK, VERT_WM_VAL,
+REG_FIELD_PREP(VERT_WM_VAL, 0x3FF));
wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
wa_add(wal,
@@ -2195,15 +2198,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
}
- if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) ||
- IS_DG2_G11(i915)) {
- /* Wa_22012654132:dg2 */
- wa_add(wal, GEN10_CACHE_MODE_SS, 0,
- _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
- 0 /* write-only, so skip validation */,
- true);
- }
-
/* Wa_14013202645:dg2 */
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0))
@@ -2692,6 +2686,21 @@ add_render_compute_tuning_settings(struct
drm_i915_private *i915,
if (IS_DG2(i915)) {
wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+ wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
+
+ /*
+* This is also listed as Wa_22012654132 for certain DG2
+* steppings, but the tuning setting programming is a superset
+* since it applies to all DG2 variants and steppings.
+*
+* Note that register 0xE420 is write-only and cannot be read
+* back for verification on DG2 (due to Wa_14012342262), so
+* we need to explicitly skip the readback.
+*/
+ wa_add(wal, GEN10_CACHE_MODE_SS, 0,
+ _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
+ 0 /* write-only, so skip validation */,
+ true);
}
}
--
2.37.1
[Intel-gfx] [PATCH 1/2] drm/i915/gt: Add dedicated function for non-ctx register tuning settings
The bspec performance tuning section gives recommended settings that the
driver should program for various MMIO registers. Although these
settings aren't "workarounds" we use the workaround infrastructure to do
this programming to make sure it is handled at the appropriate places
and doesn't conflict with any real workarounds.
Since more of these are starting to show up on recent platforms, it's a
good time to create a dedicated function to hold them so that there's
less ambiguity about how/where to implement new ones.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 42 ++---
1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 59cf28baa472..a68d279b01f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2102,13 +2102,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
/* Wa_1509235366:dg2 */
wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
INVALIDATION_BROADCAST_MODE_DIS |
GLOBAL_INVALIDATION_MODE);
-
- /*
-* The following are not actually "workarounds" but rather
-* recommended tuning settings documented in the bspec's
-* performance guide section.
-*/
- wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
}
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
@@ -2676,6 +2669,32 @@ ccs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
}
}
+/*
+ * The bspec performance guide has recommended MMIO tuning settings. These
+ * aren't truly "workarounds" but we want to program them with the same
+ * workaround infrastructure to ensure that they're automatically added to
+ * the GuC save/restore lists, re-applied at the right times, and checked for
+ * any conflicting programming requested by real workarounds.
+ *
+ * Programming settings should be added here only if their registers are not
+ * part of an engine's register state context. If a register is part of a
+ * context, then any tuning settings should be programmed in an appropriate
+ * function invoked by __intel_engine_init_ctx_wa().
+ */
+static void
+add_render_compute_tuning_settings(struct drm_i915_private *i915,
+ struct i915_wa_list *wal)
+{
+ if (IS_PONTEVECCHIO(i915)) {
+ wa_write(wal, XEHPC_L3SCRUB,
+SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+ }
+
+ if (IS_DG2(i915)) {
+ wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+ }
+}
+
/*
* The workarounds in this function apply to shared registers in
* the general render reset domain that aren't tied to a
@@ -2690,14 +2709,9 @@ general_render_compute_wa_init(struct intel_engine_cs
*engine, struct i915_wa_li
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_PONTEVECCHIO(i915)) {
- /*
-* The following is not actually a "workaround" but rather
-* a recommended tuning setting documented in the bspec's
-* performance guide section.
-*/
- wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED |
SCRUB_RATE_4B_PER_CLK);
+ add_render_compute_tuning_settings(i915, wal);
+ if (IS_PONTEVECCHIO(i915)) {
/* Wa_16016694945 */
wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
}
--
2.37.1
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Sanitycheck PCI BARs (rev2)
RN][15] ([i915#2867]) -> [PASS][16]
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106927v2/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
>
> * igt@i915_selftest@live@slpc:
> - {bat-rpls-1}: [DMESG-FAIL][17] ([i915#6367]) -> [PASS][18]
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-rpls-1/igt@i915_selftest@l...@slpc.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106927v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html
>
>
> Warnings
>
> * igt@i915_selftest@live@hangcheck:
> - bat-dg1-5: [DMESG-FAIL][19] ([i915#4957]) -> [DMESG-FAIL][20]
> ([i915#4494] / [i915#4957])
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106927v2/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
> - bat-dg1-6: [DMESG-FAIL][21] ([i915#4494] / [i915#4957]) ->
> [DMESG-FAIL][22] ([i915#4957])
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
>[22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106927v2/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
> [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
> [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
> [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
> [i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
> [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
> [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
>
>
> Build changes
> -
>
> * Linux: CI_DRM_11971 -> Patchwork_106927v2
>
> CI-20190529: 20190529
> CI_DRM_11971: 2bdae66c9988dd0f07633629c0a85383cfc05940 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6614: fbb4a4058b8f4119a079b2fda5c94aaacd850a78 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_106927v2: 2bdae66c9988dd0f07633629c0a85383cfc05940 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> 4e46a15b7ddf drm/i915: Sanitycheck PCI BARs
> 79faae70c394 drm/i915: Use of BARs names instead of numbers
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106927v2/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 21/23] drm/i915/dmc: MTL DMC debugfs entries
On Wed, Jul 27, 2022 at 06:34:18PM -0700, Radhakrishna Sripada wrote:
> From: Anusha Srivatsa
>
> MTL needs both Pipe A and Pipe B DMC to be loaded
> along with Main DMC. Patch also adds
That's true, but it's unrelated to this patch. intel_dmc_load_program()
always loads all of the pipe firmwares (including pipe C and pipe D)
assuming it found them in the firmware file.
> DMC debug register for MTL.
>
> BSpec: 49788
> Cc: Matt Roper
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 9c4f442fa407..2fabb2760474 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1005,7 +1005,7 @@ static int intel_dmc_debugfs_status_show(struct
> seq_file *m, void *unused)
> seq_printf(m, "Pipe A fw loaded: %s\n",
> str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload));
> seq_printf(m, "Pipe B fw support: %s\n",
> -str_yes_no(IS_ALDERLAKE_P(i915)));
> +str_yes_no(DISPLAY_VER(i915) >= 13));
What is this debugfs trying to tell us? Pipe DMC fw for all four pipes
has been supported since TGL. So the output here is misleading (and
incomplete since it doesn't include C/D).
The thing that changed in DG2 was that we were required to upload the
pipe A firmware along with the main firmware (other pipes optional).
The thing that further changed in ADL-P was that we were required to
upload *both* pipe A and pipe B along with the main firmware (other two
pipes still optional).
Even if the output here was trying to indicate which pipe firmware(s)
need to be uploaded at the same time as the main firmware (rather than
being uploaded later), the change here wouldn't be correct since as
noted above, DG2 (which has display version 13) only required pipe A and
not B.
I think we probably need to decide what the purpose of this debugfs is
supposed to be and then rework it accordingly.
Matt
> seq_printf(m, "Pipe B fw loaded: %s\n",
> str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload));
>
> @@ -1029,9 +1029,9 @@ static int intel_dmc_debugfs_status_show(struct
> seq_file *m, void *unused)
>* reg for DC3CO debugging and validation,
>* but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
>*/
> - seq_printf(m, "DC3CO count: %d\n",
> -intel_de_read(i915, IS_DGFX(i915) ?
> - DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
> + seq_printf(m, "DC3CO count: %d\n", intel_de_read(i915,
> +(IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) ?
> + DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
> } else {
> dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :
> SKL_DMC_DC3_DC5_COUNT;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 20/23] drm/i915/dmc: Load DMC on MTL
On Wed, Jul 27, 2022 at 06:34:17PM -0700, Radhakrishna Sripada wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> Adding support to load DMC v2.08 on MTL.
>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep
>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index fa9ef591b885..9c4f442fa407 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -52,6 +52,11 @@
>
> #define DISPLAY_VER12_DMC_MAX_FW_SIZEICL_DMC_MAX_FW_SIZE
>
> +#define MTL_DMC_PATH DMC_PATH(mtl, 2, 08)
> +#define MTL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8)
> +#define MTL_DMC_MAX_FW_SIZE 0x1
Is it correct that Xe_LPD+ has a smaller payload than Xe_LPD platforms?
Actually, looking closer I'm wondering if the
DISPLAY_VER13_DMC_MAX_FW_SIZE we were using on Xe_LPD was correct. I
think the value here is supposed to be a per-payload maximum (i.e.,
checked separately for the main DMC and the pipe DMC), right? And the
MMIO ranges the payloads can be loaded into both appear to be sized
0x1, so it's not clear to me whether we needed the 0x2 value on
ADL-P and DG2.
Matt
> +MODULE_FIRMWARE(MTL_DMC_PATH);
> +
> #define DG2_DMC_PATH DMC_PATH(dg2, 2, 06)
> #define DG2_DMC_VERSION_REQUIRED DMC_VERSION(2, 06)
> MODULE_FIRMWARE(DG2_DMC_PATH);
> @@ -827,7 +832,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
> *dev_priv)
>*/
> intel_dmc_runtime_pm_get(dev_priv);
>
> - if (IS_DG2(dev_priv)) {
> + if (IS_METEORLAKE(dev_priv)) {
> + dmc->fw_path = MTL_DMC_PATH;
> + dmc->required_version = MTL_DMC_VERSION_REQUIRED;
> + dmc->max_fw_size = MTL_DMC_MAX_FW_SIZE;
> + } else if (IS_DG2(dev_priv)) {
> dmc->fw_path = DG2_DMC_PATH;
> dmc->required_version = DG2_DMC_VERSION_REQUIRED;
> dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 19/23] drm/i915/display/mtl: Extend MBUS programming
On Wed, Jul 27, 2022 at 06:34:16PM -0700, Radhakrishna Sripada wrote: > From: José Roberto de Souza > > Display version 14 also supports MBUS joining just like ADL-P > and also it don't need MBUS initialization, so extending ADL-P s/don't/doesn't/ Otherwise, Reviewed-by: Matt Roper > code paths to display version 14 and higher. > > Bspec: 49213 > > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h| 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > b/drivers/gpu/drm/i915/display/intel_display_power.c > index ccc3f78b1607..c0bc5c30cef3 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -1101,7 +1101,7 @@ static void icl_mbus_init(struct drm_i915_private > *dev_priv) > unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask; > u32 mask, val, i; > > - if (IS_ALDERLAKE_P(dev_priv)) > + if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) > return; > > mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 5767bbba2260..6a876cd53228 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1360,7 +1360,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ > IS_ALDERLAKE_S(dev_priv)) > > -#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915)) > +#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= > 14) > > #define HAS_3D_PIPELINE(i915)(INTEL_INFO(i915)->has_3d_pipeline) > > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH 18/23] drm/i915/mtl: DBUF handling is same as adlp
On Wed, Jul 27, 2022 at 06:34:15PM -0700, Radhakrishna Sripada wrote: > Meteorlake uses a similar DBUF programming as ADL-P. > Reuse the call flow for meteorlake. Although the patch below is correct, the commit message and subject line here are extremely misleading. MTL uses _very_ different handling/programming of DBUF (via the new PM demand mechanism). The only thing that's actually the same is the computation of which dbufs will be enabled (which is all this patch deals with). > > Bspec: 49255 > > Cc: Matt Roper > Original Author: Caz Yokoyama > Signed-off-by: Radhakrishna Sripada > --- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 58a3c72418a7..d73be4bbaaa3 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4934,7 +4934,7 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc > *crtc, u8 active_pipes, bool > > if (IS_DG2(dev_priv)) > return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus); > - else if (IS_ALDERLAKE_P(dev_priv)) > + else if (DISPLAY_VER(dev_priv) >= 14 || IS_ALDERLAKE_P(dev_priv)) An alternative would be to just do else if (DISPLAY_VER(dev_priv) >= 13) here since DG2 is already broken out into its own case above. But either way, Reviewed-by: Matt Roper with an updated commit message/subject change. > return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus); > else if (DISPLAY_VER(dev_priv) == 12) > return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus); > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH 17/23] drm/i915/mtl: Update MBUS_DBOX credits
On Wed, Jul 27, 2022 at 06:34:14PM -0700, Radhakrishna Sripada wrote:
> Display version 14 platforms has different credits values compared to ADL-P.
s/has/have/
> Update the credits based on pipe usage.
>
> Bspec: 49213
>
> Cc: Jose Roberto de Souza
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++
> drivers/gpu/drm/i915/intel_pm.c | 47 ++---
> 2 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d37607109398..2f9cbdd068e8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1125,8 +1125,12 @@
> #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
> #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
> #define MBUS_DBOX_BW_CREDIT(x)
> REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
> +#define MBUS_DBOX_BW_4CREDITS_MTL0x2
> +#define MBUS_DBOX_BW_8CREDITS_MTL0x3
It might be better to move the REG_FIELD_PREP into the definition here
#define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK,
0x2)
#define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK,
0x3)
and then...
> #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
> #define MBUS_DBOX_B_CREDIT(x)
> REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
> +#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
> +#define MBUS_DBOX_I_CREDIT(x)
> REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
> #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
> #define MBUS_DBOX_A_CREDIT(x)
> REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f71b3b8b590c..58a3c72418a7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8443,6 +8443,27 @@ void intel_dbuf_post_plane_update(struct
> intel_atomic_state *state)
> new_dbuf_state->enabled_slices);
> }
>
> +static bool xelpdp_is_one_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
> +{
> + switch (pipe) {
> + case PIPE_A:
> + case PIPE_D:
> + if (is_power_of_2(active_pipes & (BIT(PIPE_A) | BIT(PIPE_D
> + return true;
> + break;
> + case PIPE_B:
> + case PIPE_C:
> + if (is_power_of_2(active_pipes & (BIT(PIPE_B) | BIT(PIPE_C
> + return true;
> + break;
> + default: /* to suppress compiler warning */
> + MISSING_CASE(pipe);
> + break;
> + }
> +
> + return false;
> +}
> +
> void intel_mbus_dbox_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> @@ -8462,20 +8483,28 @@ void intel_mbus_dbox_update(struct intel_atomic_state
> *state)
>new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
> return;
>
> + if (DISPLAY_VER(i915) >= 14)
> + val |= MBUS_DBOX_I_CREDIT(2);
> +
> if (DISPLAY_VER(i915) >= 12) {
> val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> }
>
> - /* Wa_22010947358:adl-p */
> - if (IS_ALDERLAKE_P(i915))
> + if (DISPLAY_VER(i915) >= 14)
> + val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
> + MBUS_DBOX_A_CREDIT(8);
> + else if (IS_ALDERLAKE_P(i915))
> + /* Wa_22010947358:adl-p */
> val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
>MBUS_DBOX_A_CREDIT(4);
> else
> val |= MBUS_DBOX_A_CREDIT(2);
>
> - if (IS_ALDERLAKE_P(i915)) {
> + if (DISPLAY_VER(i915) >= 14) {
> + val |= MBUS_DBOX_B_CREDIT(0xA);
> + } else if (IS_ALDERLAKE_P(i915)) {
> val |= MBUS_DBOX_BW_CREDIT(2);
> val |= MBUS_DBOX_B_CREDIT(8);
> } else if (DISPLAY_VER(i915) >= 12) {
> @@ -8487,10 +8516,20 @@ void intel_mbus_dbox_update(struct intel_atomic_state
> *state)
> }
>
> for_each_new_intel_crtc_in_state(state, crtc
Re: [Intel-gfx] [PATCH 16/23] drm/i915/mtl: Update memory bandwidth parameters
On Wed, Jul 27, 2022 at 06:34:13PM -0700, Radhakrishna Sripada wrote:
> Like ADL_P, Meteorlake has different memory characteristics from
> past platforms. Update the values used by our memory bandwidth
> calculations accordingly.
>
> Bspec: 64631
>
> Cc: Matt Roper
> Cc: Caz Yokoyama
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 42 ++---
> 1 file changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 8bbf47da1716..447a15f2c18a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -178,7 +178,32 @@ static int icl_get_qgv_points(struct drm_i915_private
> *dev_priv,
> qi->num_points = dram_info->num_qgv_points;
> qi->num_psf_points = dram_info->num_psf_gv_points;
>
> - if (DISPLAY_VER(dev_priv) >= 12)
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + switch (dram_info->type) {
> + case INTEL_DRAM_DDR4:
> + qi->t_bl = 4;
> + qi->max_numchannels = 2;
> + qi->channel_width = 64;
> + qi->deinterleave = 2;
> + break;
> + case INTEL_DRAM_DDR5:
> + qi->t_bl = 8;
> + qi->max_numchannels = 4;
> + qi->channel_width = 32;
> + qi->deinterleave = 2;
> + break;
> + case INTEL_DRAM_LPDDR4:
> + case INTEL_DRAM_LPDDR5:
> + qi->t_bl = 16;
> + qi->max_numchannels = 8;
> + qi->channel_width = 16;
> + qi->deinterleave = 4;
> + break;
> + default:
> + MISSING_CASE(dram_info->type);
> + return -EINVAL;
> + }
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> switch (dram_info->type) {
> case INTEL_DRAM_DDR4:
> qi->t_bl = is_y_tile ? 8 : 4;
> @@ -212,7 +237,7 @@ static int icl_get_qgv_points(struct drm_i915_private
> *dev_priv,
> qi->max_numchannels = 1;
> break;
> }
> - else if (DISPLAY_VER(dev_priv) == 11) {
> + } else if (DISPLAY_VER(dev_priv) == 11) {
> qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
> qi->max_numchannels = 1;
> }
> @@ -311,6 +336,13 @@ static const struct intel_sa_info adlp_sa_info = {
> .derating = 20,
> };
>
> +static const struct intel_sa_info mtl_sa_info = {
> + .deburst = 32,
> + .deprogbwlimit = 38, /* GB/s */
> + .displayrtids = 256,
> + .derating = 20,
> +};
> +
> static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
> intel_sa_info *sa)
> {
> struct intel_qgv_info qi = {};
> @@ -585,9 +617,11 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (IS_DG2(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 14)
> + tgl_get_bw_info(dev_priv, &mtl_sa_info);
> + else if (IS_DG2(dev_priv))
> dg2_get_bw_info(dev_priv);
> - else if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_P(dev_priv))
> + else if (IS_ALDERLAKE_P(dev_priv))
Here you're undoing the change from the previous patch. If you drop the
unwanted change from the previous patch and rebase the real changes here
accordingly,
Reviewed-by: Matt Roper
> tgl_get_bw_info(dev_priv, &adlp_sa_info);
> else if (IS_ALDERLAKE_S(dev_priv))
> tgl_get_bw_info(dev_priv, &adls_sa_info);
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 15/23] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox
On Wed, Jul 27, 2022 at 06:34:12PM -0700, Radhakrishna Sripada wrote:
> From Meteorlake, Latency Level, SAGV bloack time are read from
> LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type
> and QGV information are also tob read from Mem SS registers.
There seems to be a typo here. I'm not sure what it's trying to say.
>
> Bspec: 49324, 64636
49324 doesn't look correct. Did you mean 64608?
>
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 49 +++--
> drivers/gpu/drm/i915/display/intel_bw.h | 9 +
> drivers/gpu/drm/i915/i915_reg.h | 16
> drivers/gpu/drm/i915/intel_dram.c | 41 -
> drivers/gpu/drm/i915/intel_pm.c | 8 +++-
> 5 files changed, 110 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 79269d2c476b..8bbf47da1716 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -15,11 +15,6 @@
> #include "intel_pcode.h"
> #include "intel_pm.h"
>
> -/* Parameters for Qclk Geyserville (QGV) */
> -struct intel_qgv_point {
> - u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
> -};
> -
> struct intel_psf_gv_point {
> u8 clk; /* clock in multiples of 16. MHz */
> };
> @@ -137,6 +132,42 @@ int icl_pcode_restrict_qgv_points(struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> +static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
> +struct intel_qgv_point *sp, int point)
> +{
> + u32 val, val2;
> + u16 dclk;
> +
> + val = intel_uncore_read(&dev_priv->uncore,
> + MTL_MEM_SS_INFO_QGV_POINT(point, 0));
> + val2 = intel_uncore_read(&dev_priv->uncore,
> + MTL_MEM_SS_INFO_QGV_POINT(point, 1));
> + dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
> + sp->dclk = DIV_ROUND_UP((16667 * dclk) + 500, 1000);
What is the "+ 500" for here? You're already doing a DIV_ROUND_UP, so
this doesn't seem right.
> + sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
> + sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
> +
> + sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
> + sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
> +
> + sp->t_rc = sp->t_rp + sp->t_ras;
> +
> + return 0;
> +}
> +
> +int
> +intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
> + struct intel_qgv_point *sp,
> + int point)
> +{
> + if (DISPLAY_VER(dev_priv) >= 14)
> + return mtl_read_qgv_point_info(dev_priv, sp, point);
> + else if (IS_DG1(dev_priv))
> + return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
> + else
> + return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
> +}
> +
> static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_info *qi,
> bool is_y_tile)
> @@ -193,11 +224,7 @@ static int icl_get_qgv_points(struct drm_i915_private
> *dev_priv,
> for (i = 0; i < qi->num_points; i++) {
> struct intel_qgv_point *sp = &qi->points[i];
>
> - if (IS_DG1(dev_priv))
> - ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
> - else
> - ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
> -
> + ret = intel_read_qgv_point_info(dev_priv, sp, i);
> if (ret)
> return ret;
>
> @@ -560,7 +587,7 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>
> if (IS_DG2(dev_priv))
> dg2_get_bw_info(dev_priv);
> - else if (IS_ALDERLAKE_P(dev_priv))
> + else if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_P(dev_priv))
ADL-P is display version 13, so it's already covered by the first half
of the condition here.
But this doesn't look right in general. At the very least MTL has a
deburst value of 32, so we don't want to re-use ADL-P's 16. I didn't
check all the others, but there may or may not be other differences.
> tgl_get_bw_info(dev_priv, &adlp_sa_info);
> else if (IS_ALDERLAKE_S(dev_priv))
> tgl_get_bw_info(dev_priv, &adls_sa_info);
> diff --git a/drivers/gpu/drm/i9
Re: [Intel-gfx] [PATCH 13/23] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM
On Wed, Jul 27, 2022 at 06:34:10PM -0700, Radhakrishna Sripada wrote:
> Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers
> instead of GT driver mailbox.
>
> Bspec: 64608
>
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++
> drivers/gpu/drm/i915/intel_pm.c | 105 +++-
> 2 files changed, 71 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6087d40eed70..23b50d671550 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8754,4 +8754,11 @@ enum skl_power_gate {
> #define GEN12_STATE_ACK_DEBUG_MMIO(0x20BC)
>
> #define MTL_MEDIA_GSI_BASE 0x38
> +
> +#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
> +#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
> +#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
> +#define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0)
> +#define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16)
> +
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ef7553b494ea..fac565d23d57 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2861,16 +2861,75 @@ static void ilk_compute_wm_level(const struct
> drm_i915_private *dev_priv,
> result->enable = true;
> }
>
> +static void
> +adjust_wm_latency(u16 wm[], int max_level, int read_latency,
> + bool wm_lv_0_adjust_needed)
The refactoring to separate the adjustment from the readout should
probably be a separate patch before you add the MTL-specific changes on
top.
Matt
> +{
> + int i, level;
> +
> + /*
> + * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
> + * need to be disabled. We make sure to sanitize the values out
> + * of the punit to satisfy this requirement.
> + */
> + for (level = 1; level <= max_level; level++) {
> + if (wm[level] == 0) {
> + for (i = level + 1; i <= max_level; i++)
> + wm[i] = 0;
> +
> + max_level = level - 1;
> + break;
> + }
> + }
> +
> + /*
> + * WaWmMemoryReadLatency
> + *
> + * punit doesn't take into account the read latency so we need
> + * to add proper adjustement to each valid level we retrieve
> + * from the punit when level 0 response data is 0us.
> + */
> + if (wm[0] == 0) {
> + for (level = 0; level <= max_level; level++)
> + wm[level] += read_latency;
> + }
> +
> + /*
> + * WA Level-0 adjustment for 16GB DIMMs: SKL+
> + * If we could not get dimm info enable this WA to prevent from
> + * any underrun. If not able to get Dimm info assume 16GB dimm
> + * to avoid any underrun.
> + */
> + if (wm_lv_0_adjust_needed)
> + wm[0] += 1;
> +}
> +
> static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
> u16 wm[])
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> + int max_level = ilk_wm_max_level(dev_priv);
>
> - if (DISPLAY_VER(dev_priv) >= 9) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> u32 val;
> - int ret, i;
> - int level, max_level = ilk_wm_max_level(dev_priv);
> +
> + val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1);
> + wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
> + wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
> + val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3);
> + wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
> + wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
> + val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5);
> + wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val);
> + wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val);
> +
> + adjust_wm_latency(wm, max_level, 6,
> + dev_priv->dram_info.wm_lv_0_adjust_needed);
> + } else if (DISPLAY_VER(dev_priv) >= 9) {
> + int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
> int mult = IS_DG2(dev_priv) ? 2 : 1;
> + u32 val;
> + int ret;
>
> /* read the first set of memory latencies[0:3] */
>
Re: [Intel-gfx] [PATCH 11/23] drm/i915/mtl: Add DP AUX support on TypeC ports
On Wed, Jul 27, 2022 at 06:34:08PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak
>
> On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
> changed wrt. previous platforms, adjust the code accordingly.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 45 -
> 1 file changed, 44 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 40c4bdd9cb26..10616e18dc18 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -637,6 +637,46 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp
> *intel_dp, int index)
> }
> }
>
> +static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + return XELPDP_DP_AUX_CH_CTL(aux_ch);
> + default:
> + MISSING_CASE(aux_ch);
> + return XELPDP_DP_AUX_CH_CTL(AUX_CH_A);
> + }
> +}
> +
> +static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + return XELPDP_DP_AUX_CH_DATA(aux_ch, index);
The definition of XELPDP_DP_AUX_CH_DATA was in the previous patch but
wasn't actually used there; it should probably be moved to this one.
Matt
> + default:
> + MISSING_CASE(aux_ch);
> + return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index);
> + }
> +}
> +
> void intel_dp_aux_fini(struct intel_dp *intel_dp)
> {
> if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
> @@ -652,7 +692,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
> struct intel_encoder *encoder = &dig_port->base;
> enum aux_ch aux_ch = dig_port->aux_ch;
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
> + intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
> intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
> } else if (DISPLAY_VER(dev_priv) >= 9) {
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 10/23] drm/i915/mtl: Add display power wells
On Mon, Aug 01, 2022 at 06:23:39PM -0700, Matt Roper wrote:
> On Wed, Jul 27, 2022 at 06:34:07PM -0700, Radhakrishna Sripada wrote:
> > From: Imre Deak
> >
> > Add support for display power wells on MTL. The differences from D13:
Also, this should be "...from Xe_LPD"
Matt
> > - The AUX HW block is moved to the PICA block, where the registers are on
> > an always-on power well and the functionality needs to be powered on/off
> > via the AUX_CH_CTL register: [1], [2]
> > - The DDI IO power on/off programming sequence is moved to the PHY PLL
> > enable/disable sequence. [3], [4], [5]
> >
> > Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
> >
> > Signed-off-by: Imre Deak
> > ---
> > .../i915/display/intel_display_power_map.c| 115 +-
> > .../i915/display/intel_display_power_well.c | 43 +++
> > .../i915/display/intel_display_power_well.h | 4 +
> > drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++
> > drivers/gpu/drm/i915/i915_reg.h | 30 +
> > 5 files changed, 199 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 97b367f39f35..cd28976f8076 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list
> > xelpd_power_wells[] = {
> > I915_PW_DESCRIPTORS(xelpd_power_wells_main),
> > };
> >
> > +/*
> > + * MTL is based on XELPD power domains with the exception of power gating
> > for:
> > + * - DDI_IO (moved to PLL logic)
> > + * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA
> > always-on)
> > + */
> > +#define XELPDP_PW_2_POWER_DOMAINS \
> > + XELPD_PW_B_POWER_DOMAINS, \
> > + XELPD_PW_C_POWER_DOMAINS, \
> > + XELPD_PW_D_POWER_DOMAINS, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC4
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
> > + XELPDP_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
> > + XELPDP_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_AUDIO_MMIO,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
> > + POWER_DOMAIN_AUX_USBC1,
> > + POWER_DOMAIN_AUX_TBT1);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
> > + POWER_DOMAIN_AUX_USBC2,
> > + POWER_DOMAIN_AUX_TBT2);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
> > + POWER_DOMAIN_AUX_USBC3,
> > + POWER_DOMAIN_AUX_TBT3);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
> > + POWER_DOMAIN_AUX_USBC4,
> > + POWER_DOMAIN_AUX_TBT4);
> > +
> > +static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
> > + {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("DC_off", &xelpdp_pwdoms_dc_off,
> > + .id = SKL_DISP_DC_OFF),
> > + ),
> > + .ops = &gen9_dc_off_power_well_ops,
> > + }, {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("PW_2", &xelpdp_pwdoms_pw_2,
> > + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> > + .id = SKL_DISP_PW_2),
> > + ),
> > + .ops = &hsw_power_well_ops,
> > + .has_vga = true,
> > + .has_fuses = true,
> > + }, {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("PW_A", &xelpd_pwdoms_pw_a,
> > + .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
> > + ),
> > + .ops = &hsw_power_well_ops,
> > + .irq_pipe_mask = BIT(PIPE_A),
> > + .has_fuses = true,
> > + }, {
> > + .instances = &I915_PW_INSTANCES(
> > + I915_PW("PW_B", &xelpd_pwdoms_pw_b,
> > + .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
> &
Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add Wa_1509727124
On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote:
> Bspec: 46052
> Reviewed-by: Matt Roper
> Signed-off-by: Harish Chegondi
Applied to drm-intel-gt-next. Thanks for the patch.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 60d6eb5f245b..b3b49f6d6d1c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1078,6 +1078,7 @@
>
> #define GEN10_SAMPLER_MODE _MMIO(0xe18c)
> #define ENABLE_SMALLPL REG_BIT(15)
> +#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>
> #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e8111fce56d0..59cf28baa472 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2119,6 +2119,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> }
>
> + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> + IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> + /* Wa_1509727124:dg2 */
> + wa_masked_en(wal, GEN10_SAMPLER_MODE,
> + SC_DISABLE_POWER_OPTIMIZATION_EBB);
> + }
> +
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> /* Wa_14012419201:dg2 */
> --
> 2.37.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 12/23] drm/i915/mtl: Fix rawclk for Meteorlake PCH
On Wed, Jul 27, 2022 at 06:34:09PM -0700, Radhakrishna Sripada wrote: > From: Clint Taylor > > MTL has a fixed rawclk of 38400Mhz. Register does not need to be > reprogrammed. > > Bspec: 49304 > > Signed-off-by: Clint Taylor > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 86a22c3766e5..390a198b0011 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -3036,6 +3036,13 @@ u32 intel_read_rawclk(struct drm_i915_private > *dev_priv) > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) > freq = dg1_rawclk(dev_priv); > + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) > + /* > + * MTL always uses a 38.4 MHz rawclk. The bspec tells us Indentation isn't quite right here. Patch is also missing your s-o-b. With those fixed, Reviewed-by: Matt Roper > + * "RAWCLK_FREQ defaults to the values for 38.4 and does > + * not need to be programmed." > + */ > + freq = 38400; > else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) > freq = cnp_rawclk(dev_priv); > else if (HAS_PCH_SPLIT(dev_priv)) > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH 00/23] Initial Meteorlake Support
On Wed, Jul 27, 2022 at 06:33:57PM -0700, Radhakrishna Sripada wrote: > The PCI Id's and platform definition are posted earlier. > This series adds handful of early enablement patches including > support for display power wells, VBT and AUX Channel mapping, > PCH and gmbus support, dbus, mbus, sagv and memory bandwidth support. > > This series also add the support for a new way to read Graphics, > Media and Display versions. One general note on the series --- most of the patches that weren't authored by you appear to be missing your s-o-b line. Make sure you add that when you resend and/or push the patches. Matt > > Anusha Srivatsa (2): > drm/i915/mtl: Add CDCLK Support > drm/i915/dmc: MTL DMC debugfs entries > > Clint Taylor (1): > drm/i915/mtl: Fix rawclk for Meteorlake PCH > > Imre Deak (3): > drm/i915/mtl: Add VBT port and AUX_CH mapping > drm/i915/mtl: Add display power wells > drm/i915/mtl: Add DP AUX support on TypeC ports > > José Roberto de Souza (2): > drm/i915: Parse and set stepping for platforms with GMD > drm/i915/display/mtl: Extend MBUS programming > > Madhumitha Tolakanahalli Pradeep (2): > drm/i915/dmc: Load DMC on MTL > drm/i915/mtl: Update CHICKEN_TRANS* register addresses > > Matt Roper (4): > drm/i915: Read graphics/media/display arch version from hw > drm/i915/mtl: MMIO range is now 4MB > drm/i915/mtl: Don't mask off CCS according to DSS fusing > drm/i915/mtl: Define engine context layouts > > Radhakrishna Sripada (9): > drm/i915/mtl: Add PCH support > drm/i915/mtl: Add gmbus and gpio support > drm/i915/mtl: Add support for MTL in Display Init sequences > drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM > drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox > drm/i915/mtl: Update memory bandwidth parameters > drm/i915/mtl: Update MBUS_DBOX credits > drm/i915/mtl: DBUF handling is same as adlp > drm/i915/mtl: Do not update GV point, mask value > > drivers/gpu/drm/i915/display/intel_bios.c | 14 +- > drivers/gpu/drm/i915/display/intel_bw.c | 87 - > drivers/gpu/drm/i915/display/intel_bw.h | 9 + > drivers/gpu/drm/i915/display/intel_cdclk.c| 351 -- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- > drivers/gpu/drm/i915/display/intel_display.c | 7 +- > .../drm/i915/display/intel_display_power.c| 5 +- > .../i915/display/intel_display_power_map.c| 115 +- > .../i915/display/intel_display_power_well.c | 43 +++ > .../i915/display/intel_display_power_well.h | 4 + > drivers/gpu/drm/i915/display/intel_dmc.c | 19 +- > drivers/gpu/drm/i915/display/intel_dp_aux.c | 53 ++- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- > drivers/gpu/drm/i915/display/intel_gmbus.c| 17 + > drivers/gpu/drm/i915/display/intel_gmbus.h| 1 + > drivers/gpu/drm/i915/display/intel_psr.c | 6 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 + > drivers/gpu/drm/i915/gt/intel_lrc.c | 47 ++- > drivers/gpu/drm/i915/i915_driver.c| 85 - > drivers/gpu/drm/i915/i915_drv.h | 18 +- > drivers/gpu/drm/i915/i915_pci.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 91 - > drivers/gpu/drm/i915/intel_device_info.c | 32 +- > drivers/gpu/drm/i915/intel_device_info.h | 14 + > drivers/gpu/drm/i915/intel_dram.c | 41 +- > drivers/gpu/drm/i915/intel_pch.c | 9 +- > drivers/gpu/drm/i915/intel_pch.h | 4 + > drivers/gpu/drm/i915/intel_pm.c | 180 ++--- > drivers/gpu/drm/i915/intel_step.c | 60 +++ > drivers/gpu/drm/i915/intel_uncore.c | 11 +- > .../gpu/drm/i915/selftests/mock_gem_device.c | 1 + > 32 files changed, 1178 insertions(+), 155 deletions(-) > > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH 10/23] drm/i915/mtl: Add display power wells
@ -1910,3 +1946,10 @@ const struct i915_power_well_ops tgl_tc_cold_off_ops =
> {
> .disable = tgl_tc_cold_off_power_well_disable,
> .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
> };
> +
> +const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
> + .sync_hw = xelpdp_aux_power_well_sync_hw,
> + .enable = xelpdp_aux_power_well_enable,
> + .disable = xelpdp_aux_power_well_disable,
> + .is_enabled = xelpdp_aux_power_well_enabled,
> +};
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index d0624642dcb6..03d11576327d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -80,6 +80,9 @@ struct i915_power_well_instance {
>*/
> u8 idx;
> } hsw;
> + struct {
> + u8 aux_ch;
> + } xelpdp;
> };
> };
>
> @@ -169,5 +172,6 @@ extern const struct i915_power_well_ops
> vlv_dpio_power_well_ops;
> extern const struct i915_power_well_ops icl_aux_power_well_ops;
> extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> +extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 2bc119374555..40c4bdd9cb26 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -150,6 +150,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> u32 unused)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> u32 ret;
>
> /*
> @@ -170,6 +171,13 @@ static u32 skl_get_aux_send_ctl(struct intel_dp
> *intel_dp,
> if (intel_tc_port_in_tbt_alt_mode(dig_port))
> ret |= DP_AUX_CH_CTL_TBT_IO;
>
> + /*
> + * Power request bit is already set during aux power well enable.
> + * Preserve the bit across aux transactions.
> + */
> + if (DISPLAY_VER(i915) >= 14)
> + ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST;
> +
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index baf747adf1db..6087d40eed70 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3619,6 +3619,34 @@
> #define DP_AUX_CH_CTL(aux_ch)_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL,
> _DPB_AUX_CH_CTL)
> #define DP_AUX_CH_DATA(aux_ch, i)_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1,
> _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>
> +#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
> +#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
> +#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
> +#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
> +
> +#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
> +#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
> +#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
> +#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
> +
> +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
> +_DPA_AUX_CH_CTL, \
> +_DPB_AUX_CH_CTL, \
> +0, /* port/aux_ch C is
> non-existent */ \
> +
> _XELPDP_USBC1_AUX_CH_CTL, \
> +
> _XELPDP_USBC2_AUX_CH_CTL, \
> +
> _XELPDP_USBC3_AUX_CH_CTL, \
> +
> _XELPDP_USBC4_AUX_CH_CTL))
> +
> +#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
> +_DPA_AUX_CH_DATA1, \
> +_DPB_AUX_CH_DATA1, \
> +0, /* port/aux_ch C is
> non-existent */ \
> +
> _XELPDP_USBC1_AUX_CH_DATA1, \
> +
> _XELPDP_USBC2_AUX_CH_DATA1, \
> +
> _XELPDP_USBC3_AUX_CH_DATA1, \
> +
> _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> +
> #define DP_AUX_CH_CTL_SEND_BUSY(1 << 31)
> #define DP_AUX_CH_CTL_DONE (1 << 30)
> #define DP_AUX_CH_CTL_INTERRUPT(1 << 29)
> @@ -3631,6 +3659,8 @@
> #define DP_AUX_CH_CTL_RECEIVE_ERROR(1 << 25)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK(0x1f << 20)
> #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
> +#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST (1 << 19)
> +#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS (1 << 18)
We should probably start using REG_BIT() for the new bits at least.
Matt
> #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
> #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
> #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 09/23] drm/i915/mtl: Add support for MTL in Display Init sequences
On Wed, Jul 27, 2022 at 06:34:06PM -0700, Radhakrishna Sripada wrote: > The initialization sequence for Meteorlake reuses the sequence for > icelake for most parts. Some changes viz. reset PICA handshake > are added. > > Bspec: 49189 > > Cc: Matt Roper > Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ > drivers/gpu/drm/i915/i915_reg.h| 3 ++- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > b/drivers/gpu/drm/i915/display/intel_display_power.c > index 589af257edeb..ccc3f78b1607 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -1381,6 +1381,9 @@ static void intel_pch_reset_handshake(struct > drm_i915_private *dev_priv, > reset_bits = RESET_PCH_HANDSHAKE_ENABLE; > } > > + if (DISPLAY_VER(dev_priv) >= 14) > + reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; > + > val = intel_de_read(dev_priv, reg); > > if (enable) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 50ddc5ba72b9..baf747adf1db 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5926,7 +5926,8 @@ >_BW_BUDDY1_PAGE_MASK)) > > #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) > -#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) > +#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) > +#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) > > #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) > #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH 08/23] drm/i915/mtl: Add VBT port and AUX_CH mapping
On Wed, Jul 27, 2022 at 06:34:05PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak
>
> Add the proper VBT port,AUX_CH -> i915 port,AUX_CH mapping which just
> follows the ADL_P one.
>
> Signed-off-by: Imre Deak
This doesn't seem to be documented in the bspec in the usual places
(e.g., page 20124), but in general we should always assume the next
platform inherits the behavior of the previous platform unless there's
information to suggest different behavior, so
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 51dde5bfd956..2971505bcf2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2418,7 +2418,7 @@ static enum port dvo_port_to_port(struct
> drm_i915_private *i915,
> [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
> };
>
> - if (DISPLAY_VER(i915) == 13)
> + if (DISPLAY_VER(i915) >= 13)
> return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping),
> ARRAY_SIZE(xelpd_port_mapping[0]),
> xelpd_port_mapping,
> @@ -3576,7 +3576,7 @@ enum aux_ch intel_bios_port_aux_ch(struct
> drm_i915_private *i915,
> aux_ch = AUX_CH_C;
> break;
> case DP_AUX_D:
> - if (DISPLAY_VER(i915) == 13)
> + if (DISPLAY_VER(i915) >= 13)
> aux_ch = AUX_CH_D_XELPD;
> else if (IS_ALDERLAKE_S(i915))
> aux_ch = AUX_CH_USBC3;
> @@ -3586,7 +3586,7 @@ enum aux_ch intel_bios_port_aux_ch(struct
> drm_i915_private *i915,
> aux_ch = AUX_CH_D;
> break;
> case DP_AUX_E:
> - if (DISPLAY_VER(i915) == 13)
> + if (DISPLAY_VER(i915) >= 13)
> aux_ch = AUX_CH_E_XELPD;
> else if (IS_ALDERLAKE_S(i915))
> aux_ch = AUX_CH_USBC4;
> @@ -3594,25 +3594,25 @@ enum aux_ch intel_bios_port_aux_ch(struct
> drm_i915_private *i915,
> aux_ch = AUX_CH_E;
> break;
> case DP_AUX_F:
> - if (DISPLAY_VER(i915) == 13)
> + if (DISPLAY_VER(i915) >= 13)
> aux_ch = AUX_CH_USBC1;
> else
> aux_ch = AUX_CH_F;
> break;
> case DP_AUX_G:
> - if (DISPLAY_VER(i915) == 13)
> + if (DISPLAY_VER(i915) >= 13)
> aux_ch = AUX_CH_USBC2;
> else
> aux_ch = AUX_CH_G;
> break;
> case DP_AUX_H:
> - if (DISPLAY_VER(i915) == 13)
> + if (DISPLAY_VER(i915) >= 13)
> aux_ch = AUX_CH_USBC3;
> else
> aux_ch = AUX_CH_H;
> break;
> case DP_AUX_I:
> - if (DISPLAY_VER(i915) == 13)
> + if (DISPLAY_VER(i915) >= 13)
> aux_ch = AUX_CH_USBC4;
> else
> aux_ch = AUX_CH_I;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 07/23] drm/i915/mtl: Add gmbus and gpio support
On Wed, Jul 27, 2022 at 06:34:04PM -0700, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to combo phys and
This description is misleading since MTL doesn't have "combo phys."
I think the key point to note here is that compared to ICP/TGP/ADP, we
now have two additional GPIO pins (4 and 5).
Matt
> GPIO_CTL[9-14] are mapped to TC ports.
>
> BSpec: 49306
>
> Original Author: Brian J Lovin
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 17 +
> drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index a6ba7fb72339..542b8b2654be 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -116,6 +116,20 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
> [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> };
>
> +static const struct gmbus_pin gmbus_pins_mtp[] = {
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> + [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> + [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> + [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
> + [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
> +};
> +
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>unsigned int pin)
> {
> @@ -128,6 +142,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct
> drm_i915_private *i915,
> } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> pins = gmbus_pins_dg1;
> size = ARRAY_SIZE(gmbus_pins_dg1);
> + } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
> + pins = gmbus_pins_mtp;
> + size = ARRAY_SIZE(gmbus_pins_mtp);
> } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
> pins = gmbus_pins_icp;
> size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h
> b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8edc2e99cf53..20f704bd4e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -24,6 +24,7 @@ struct i2c_adapter;
> #define GMBUS_PIN_2_BXT 2
> #define GMBUS_PIN_3_BXT 3
> #define GMBUS_PIN_4_CNP 4
> +#define GMBUS_PIN_5_MTP 5
> #define GMBUS_PIN_9_TC1_ICP 9
> #define GMBUS_PIN_10_TC2_ICP 10
> #define GMBUS_PIN_11_TC3_ICP 11
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_1509727124
On Thu, Jul 28, 2022 at 11:49:07AM -0700, Harish Chegondi wrote:
> Bspec: 46052
> Cc: Matt Roper
> Signed-off-by: Harish Chegondi
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 60d6eb5f245b..b3b49f6d6d1c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1078,6 +1078,7 @@
>
> #define GEN10_SAMPLER_MODE _MMIO(0xe18c)
> #define ENABLE_SMALLPL REG_BIT(15)
> +#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>
> #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e8111fce56d0..434d85aec72b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2119,6 +2119,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> }
>
> + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> + IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_FOREVER) ||
a0..forever covers all steppins and can be simplified to just
IS_DG2_G11().
With that changed,
Reviewed-by: Matt Roper
> + IS_DG2_G12(i915)) {
> + /* Wa_1509727124:dg2 */
> + wa_masked_en(wal, GEN10_SAMPLER_MODE,
> + SC_DISABLE_POWER_OPTIMIZATION_EBB);
> + }
> +
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> /* Wa_14012419201:dg2 */
> --
> 2.37.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct instead of gt for gen11_gu_misc_irq_handler/ack()
On Tue, Jul 26, 2022 at 09:44:38AM -0700, Srivatsa, Anusha wrote:
> Thanks Tvrtko :)
> @Roper, Matthew D Did you have any other feedback on this patch?
Nope, looks fine to me. Thanks.
Reviewed-by: Matt Roper
>
> Anusha
>
> > -Original Message-
> > From: Tvrtko Ursulin
> > Sent: Tuesday, July 26, 2022 1:59 AM
> > To: Srivatsa, Anusha ; intel-
> > g...@lists.freedesktop.org; Ursulin, Tvrtko
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct
> > instead of gt for gen11_gu_misc_irq_handler/ack()
> >
> >
> > On 25/07/2022 19:38, Srivatsa, Anusha wrote:
> > > @Ursulin, Tvrtko Is this wat you had in mind?
> >
> > Two functions aligned in prototype yes - but I left to you guys which
> > prototype is correct. AFAICT Matt looked and concluded i915 is correct so
> > that's good for me.
> >
> > Regards,
> >
> > Tvrtko
> >
> > >> -Original Message-
> > >> From: Srivatsa, Anusha
> > >> Sent: Thursday, July 21, 2022 3:51 PM
> > >> To: intel-gfx@lists.freedesktop.org
> > >> Cc: Srivatsa, Anusha ; Ursulin, Tvrtko
> > >> ; Roper, Matthew D
> > >>
> > >> Subject: [PATCH] drm/i915: Pass drm_i915_private struct instead of gt
> > >> for
> > >> gen11_gu_misc_irq_handler/ack()
> > >>
> > >> gen11_gu_misc_irq_handler() and gen11_gu_misc_ack() do nothing tile
> > >> specific.
> > >>
> > >> v2: gen11_gu_misc_irq_ack() tile agnostic like
> > >> gen11_gu_misc_irq_handler()
> > >> (Tvrtko)
> > >>
> > >> Cc: Tvrtko Ursulin
> > >> Cc: Matt Roper
> > >> Signed-off-by: Anusha Srivatsa
> > >> ---
> > >> drivers/gpu/drm/i915/i915_irq.c | 16
> > >> 1 file changed, 8 insertions(+), 8 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > >> b/drivers/gpu/drm/i915/i915_irq.c index 73cebc6aa650..eb37b6bacaac
> > >> 100644
> > >> --- a/drivers/gpu/drm/i915/i915_irq.c
> > >> +++ b/drivers/gpu/drm/i915/i915_irq.c
> > >> @@ -2653,9 +2653,9 @@ static irqreturn_t gen8_irq_handler(int irq,
> > >> void
> > >> *arg) }
> > >>
> > >> static u32
> > >> -gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
> > >> +gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32
> > >> +master_ctl)
> > >> {
> > >> -void __iomem * const regs = gt->uncore->regs;
> > >> +void __iomem * const regs = i915->uncore.regs;
> > >> u32 iir;
> > >>
> > >> if (!(master_ctl & GEN11_GU_MISC_IRQ)) @@ -2669,10 +2669,10
> > @@
> > >> gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl) }
> > >>
> > >> static void
> > >> -gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
> > >> +gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32
> > >> +iir)
> > >> {
> > >> if (iir & GEN11_GU_MISC_GSE)
> > >> -intel_opregion_asle_intr(gt->i915);
> > >> +intel_opregion_asle_intr(i915);
> > >> }
> > >>
> > >> static inline u32 gen11_master_intr_disable(void __iomem * const
> > >> regs) @@
> > >> -2736,11 +2736,11 @@ static irqreturn_t gen11_irq_handler(int irq,
> > >> void
> > >> *arg)
> > >> if (master_ctl & GEN11_DISPLAY_IRQ)
> > >> gen11_display_irq_handler(i915);
> > >>
> > >> -gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> > >> +gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
> > >>
> > >> gen11_master_intr_enable(regs);
> > >>
> > >> -gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> > >> +gen11_gu_misc_irq_handler(i915, gu_misc_iir);
> > >>
> > >> pmu_irq_stats(i915, IRQ_HANDLED);
> > >>
> > >> @@ -2801,11 +2801,11 @@ static irqreturn_t dg1_irq_handler(int irq,
> > >> void
> > >> *arg)
> > >> if (master_ctl & GEN11_DISPLAY_IRQ)
> > >> gen11_display_irq_handler(i915);
> > >>
> > >> -gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> > >> +gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
> > >>
> > >> dg1_master_intr_enable(regs);
> > >>
> > >> -gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> > >> +gen11_gu_misc_irq_handler(i915, gu_misc_iir);
> > >>
> > >> pmu_irq_stats(i915, IRQ_HANDLED);
> > >>
> > >> --
> > >> 2.25.1
> > >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v3] drm/i915/dg2: Add performance workaround 18019455067
I think you may have missed Lucas' reply to your v3:
https://lists.freedesktop.org/archives/intel-gfx/2022-June/300712.html
Also, here's the reply to v2 that he's referring to:
https://lists.freedesktop.org/archives/intel-gfx/2022-June/300646.html
I.e., he wants this to be called from a new 'tuning_init' function that
is itself called from general_render_compute_wa_init, since we expect
more of these things to show up in the future so it makes sense to have
a dedicated place for them.
Matt
On Wed, Jul 20, 2022 at 11:19:18AM +0300, Lionel Landwerlin wrote:
> Ping?
>
> On 11/07/2022 14:30, Lionel Landwerlin wrote:
> > Ping?
> >
> > On 30/06/2022 11:35, Lionel Landwerlin wrote:
> > > The recommended number of stackIDs for Ray Tracing subsystem is 512
> > > rather than 2048 (default HW programming).
> > >
> > > v2: Move the programming to dg2_ctx_gt_tuning_init() (Lucas)
> > >
> > > v3: Move programming to general_render_compute_wa_init() (Matt)
> > >
> > > Signed-off-by: Lionel Landwerlin
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
> > > 2 files changed, 13 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > index 07ef111947b8c..12fc87b957425 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > @@ -1112,6 +1112,10 @@
> > > #define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
> > > #define RT_CTRL _MMIO(0xe530)
> > > +#define RT_CTRL_NUMBER_OF_STACKIDS_MASK REG_GENMASK(6, 5)
> > > +#define NUMBER_OF_STACKIDS_512 2
> > > +#define NUMBER_OF_STACKIDS_1024 1
> > > +#define NUMBER_OF_STACKIDS_2048 0
> > > #define DIS_NULL_QUERY REG_BIT(10)
> > > #define EU_PERF_CNTL1 _MMIO(0xe558)
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 3213c593a55f4..ea674e456cd76 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -2737,6 +2737,15 @@ general_render_compute_wa_init(struct
> > > intel_engine_cs *engine, struct i915_wa_li
> > > wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> > > wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> > > }
> > > +
> > > + if (IS_DG2(i915)) {
> > > + /* Performance tuning for Ray-tracing */
> > > + wa_write_clr_set(wal,
> > > + RT_CTRL,
> > > + RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> > > + REG_FIELD_PREP(RT_CTRL_NUMBER_OF_STACKIDS_MASK,
> > > + NUMBER_OF_STACKIDS_512));
> > > + }
> > > }
> > > static void
> >
> >
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915/display: Cleanup intel_phy_is_combo()
On Mon, Jul 25, 2022 at 09:45:57AM -0700, Srivatsa, Anusha wrote:
>
>
> > -Original Message-
> > From: Roper, Matthew D
> > Sent: Thursday, July 21, 2022 1:50 PM
> > To: Srivatsa, Anusha
> > Cc: intel-gfx@lists.freedesktop.org; Murthy, Arun R
> >
> > Subject: Re: [PATCH] drm/i915/display: Cleanup intel_phy_is_combo()
> >
> > On Thu, Jul 21, 2022 at 01:17:54PM -0700, Anusha Srivatsa wrote:
> > > No functional change. Cleanup the intel_phy_is_combo
> >
> > But there actually is a functional change here --- display version 14 will
> > now
> > (properly) fall through to the 'else' branch instead of being picked up by
> > the
> > 11/12/adl branch. I believe that was your original motivation for this
> > patch,
> > so you may want to mention that in the commit message (and drop the "no
> > functional change" statement).
> >
> > The code change itself looks fine to me since it seems like the traditional
> > combo PHYs may be a thing of the past and we don't want to keep assuming
> > future platforms will have any.
> >
> With the change in commit message can I add your reviewed-by laong with
> Arun's?
Yeah, with an updated commit message,
Reviewed-by: Matt Roper
>
> Anusha
> > Matt
> >
> > > to accommodate for cases where combo phy is not available.
> > >
> > > v2: retain comment that explains DG2 returning false from
> > > intel_phy_is_combo() (Arun)
> > >
> > > Cc: Arun R Murthy
> > > Cc: Matt Roper
> > > Signed-off-by: Anusha Srivatsa
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 14 ++
> > > 1 file changed, 6 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index a0f84cbe974f..b9d0be7753a8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -2082,22 +2082,20 @@ bool intel_phy_is_combo(struct
> > > drm_i915_private *dev_priv, enum phy phy) {
> > > if (phy == PHY_NONE)
> > > return false;
> > > - else if (IS_DG2(dev_priv))
> > > - /*
> > > - * DG2 outputs labelled as "combo PHY" in the bspec use
> > > - * SNPS PHYs with completely different programming,
> > > - * hence we always return false here.
> > > - */
> > > - return false;
> > > else if (IS_ALDERLAKE_S(dev_priv))
> > > return phy <= PHY_E;
> > > else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> > > return phy <= PHY_D;
> > > else if (IS_JSL_EHL(dev_priv))
> > > return phy <= PHY_C;
> > > - else if (DISPLAY_VER(dev_priv) >= 11)
> > > + else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11,
> > > +12))
> > > return phy <= PHY_B;
> > > else
> > > + /*
> > > + * DG2 outputs labelled as "combo PHY" in the bspec use
> > > + * SNPS PHYs with completely different programming,
> > > + * hence we always return false here.
> > > + */
> > > return false;
> > > }
> > >
> > > --
> > > 2.25.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915/display: Cleanup intel_phy_is_combo()
On Thu, Jul 21, 2022 at 01:17:54PM -0700, Anusha Srivatsa wrote:
> No functional change. Cleanup the intel_phy_is_combo
But there actually is a functional change here --- display version 14
will now (properly) fall through to the 'else' branch instead of being
picked up by the 11/12/adl branch. I believe that was your original
motivation for this patch, so you may want to mention that in the commit
message (and drop the "no functional change" statement).
The code change itself looks fine to me since it seems like the
traditional combo PHYs may be a thing of the past and we don't want to
keep assuming future platforms will have any.
Matt
> to accommodate for cases where combo phy is not available.
>
> v2: retain comment that explains DG2 returning false from
> intel_phy_is_combo() (Arun)
>
> Cc: Arun R Murthy
> Cc: Matt Roper
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 ++
> 1 file changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a0f84cbe974f..b9d0be7753a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2082,22 +2082,20 @@ bool intel_phy_is_combo(struct drm_i915_private
> *dev_priv, enum phy phy)
> {
> if (phy == PHY_NONE)
> return false;
> - else if (IS_DG2(dev_priv))
> - /*
> - * DG2 outputs labelled as "combo PHY" in the bspec use
> - * SNPS PHYs with completely different programming,
> - * hence we always return false here.
> - */
> - return false;
> else if (IS_ALDERLAKE_S(dev_priv))
> return phy <= PHY_E;
> else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> return phy <= PHY_D;
> else if (IS_JSL_EHL(dev_priv))
> return phy <= PHY_C;
> - else if (DISPLAY_VER(dev_priv) >= 11)
> + else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
> return phy <= PHY_B;
> else
> + /*
> + * DG2 outputs labelled as "combo PHY" in the bspec use
> + * SNPS PHYs with completely different programming,
> + * hence we always return false here.
> + */
> return false;
> }
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct instead of gt for gen11_gu_misc_irq_handler()
On Wed, Jul 20, 2022 at 10:03:42AM -0700, Srivatsa, Anusha wrote:
>
>
> > -Original Message-
> > From: Tvrtko Ursulin
> > Sent: Wednesday, July 20, 2022 2:38 AM
> > To: Roper, Matthew D ; Srivatsa, Anusha
> >
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct
> > instead of gt for gen11_gu_misc_irq_handler()
> >
> >
> > On 18/07/2022 19:54, Matt Roper wrote:
> > > On Mon, Jul 18, 2022 at 11:34:24AM -0700, Anusha Srivatsa wrote:
> > >> gen11_gu_misc_irq_handler() does not do anything tile specific.
> > >>
> > >> Cc: Matt Roper
> > >> Signed-off-by: Anusha Srivatsa
> > >
> > > Reviewed-by: Matt Roper
> > >
> > >> ---
> > >> drivers/gpu/drm/i915/i915_irq.c | 8
> > >> 1 file changed, 4 insertions(+), 4 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > >> b/drivers/gpu/drm/i915/i915_irq.c index 73cebc6aa650..c304af777d58
> > >> 100644
> > >> --- a/drivers/gpu/drm/i915/i915_irq.c
> > >> +++ b/drivers/gpu/drm/i915/i915_irq.c
> > >> @@ -2669,10 +2669,10 @@ gen11_gu_misc_irq_ack(struct intel_gt *gt,
> > const u32 master_ctl)
> > >> }
> > >>
> > >> static void
> > >> -gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
> > >> +gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32
> > >> +iir)
> > >> {
> > >>if (iir & GEN11_GU_MISC_GSE)
> > >> - intel_opregion_asle_intr(gt->i915);
> > >> + intel_opregion_asle_intr(i915);
> > >> }
> > >>
> > >> static inline u32 gen11_master_intr_disable(void __iomem * const
> > >> regs) @@ -2740,7 +2740,7 @@ static irqreturn_t gen11_irq_handler(int
> > >> irq, void *arg)
> > >>
> >
> > Maybe this is correct but it leaves this, round about here:
> >
> > gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> >
> > So _if_ these registers are truly not per GT, or don't live in the GT block,
> > change this one as well?
> Tvrtko,
> gen11_gu_misc_irq_ack() does not fall in the same category. We do
> operations where we grab register per gt and do some writes that are
> not gt agnostic.
I don't understand what you're saying here. The ack and the handler
functions go hand in hand; they should either both be GT-centric or both
be device centric.
Since the MMIO space is duplicated for each tile, it's always _possible_
to read and process an interrupt register for each tile. The question
is whether this is a type of interrupt where it can only be delivered on
tile0 (similar to display, if we had a multi-tile platform that
supported display) or can each tile raise its own interrupt
independently, requiring that we both ack and handle those interrupts in
a per-tile manner?
Right now the only kind of interrupt we handle on GU_MISC is the "GSE"
bit which is apparently related to panel backlight (display), so it
wouldn't make sense to handle that in a per-GT manner (and we really
shouldn't be receiving the interrupt at all on any of our multi-tile
platforms right now). So it sounds to me like our ack routine should
also be switched over to drm_i915_private.
Matt
>
> Anusha
> > Regards,
> >
> > Tvrtko
> >
> > >>gen11_master_intr_enable(regs);
> > >>
> > >> - gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> > >> + gen11_gu_misc_irq_handler(i915, gu_misc_iir);
> > >>
> > >>pmu_irq_stats(i915, IRQ_HANDLED);
> > >>
> > >> @@ -2805,7 +2805,7 @@ static irqreturn_t dg1_irq_handler(int irq,
> > >> void *arg)
> > >>
> > >>dg1_master_intr_enable(regs);
> > >>
> > >> - gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> > >> + gen11_gu_misc_irq_handler(i915, gu_misc_iir);
> > >>
> > >>pmu_irq_stats(i915, IRQ_HANDLED);
> > >>
> > >> --
> > >> 2.25.1
> > >>
> > >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct instead of gt for gen11_gu_misc_irq_handler()
On Mon, Jul 18, 2022 at 11:34:24AM -0700, Anusha Srivatsa wrote:
> gen11_gu_misc_irq_handler() does not do anything tile specific.
>
> Cc: Matt Roper
> Signed-off-by: Anusha Srivatsa
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_irq.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 73cebc6aa650..c304af777d58 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2669,10 +2669,10 @@ gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32
> master_ctl)
> }
>
> static void
> -gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
> +gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)
> {
> if (iir & GEN11_GU_MISC_GSE)
> - intel_opregion_asle_intr(gt->i915);
> + intel_opregion_asle_intr(i915);
> }
>
> static inline u32 gen11_master_intr_disable(void __iomem * const regs)
> @@ -2740,7 +2740,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
>
> gen11_master_intr_enable(regs);
>
> - gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> + gen11_gu_misc_irq_handler(i915, gu_misc_iir);
>
> pmu_irq_stats(i915, IRQ_HANDLED);
>
> @@ -2805,7 +2805,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>
> dg1_master_intr_enable(regs);
>
> - gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> + gen11_gu_misc_irq_handler(i915, gu_misc_iir);
>
> pmu_irq_stats(i915, IRQ_HANDLED);
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms
On Wed, Jul 13, 2022 at 03:50:35AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms
> URL : https://patchwork.freedesktop.org/series/106269/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11877_full -> Patchwork_106269v1_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_106269v1_full absolutely need
> to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_106269v1_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (13 -> 13)
> --
>
> No changes in participating hosts
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_106269v1_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_selftest@live@hangcheck:
> - shard-skl: NOTRUN -> [INCOMPLETE][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-skl9/igt@i915_selftest@l...@hangcheck.html
Random incomplete (logs cut off abruptly with no errors reported). Does
not appear to be related to this patch.
Patch applied to drm-intel-gt-next. Thanks Lucas for the review.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@drm_buddy@all:
> - {shard-dg1}:NOTRUN -> [SKIP][2] +4 similar issues
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-dg1-15/igt@drm_bu...@all.html
>
> * igt@kms_setmode@clone-exclusive-crtc:
> - {shard-dg1}:NOTRUN -> [INCOMPLETE][3]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-dg1-16/igt@kms_setm...@clone-exclusive-crtc.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_106269v1_full that come from known
> issues:
>
> ### CI changes ###
>
> Issues hit
>
> * boot:
> - shard-skl: ([PASS][4], [PASS][5], [PASS][6], [PASS][7],
> [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13],
> [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19],
> [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) -> ([PASS][25],
> [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31],
> [PASS][32], [PASS][33], [PASS][34], [FAIL][35], [PASS][36], [PASS][37],
> [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43],
> [PASS][44]) ([i915#5032])
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl9/boot.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl9/boot.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl7/boot.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl7/boot.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl6/boot.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl6/boot.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl5/boot.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl5/boot.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl4/boot.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl3/boot.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl3/boot.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl2/boot.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl2/boot.html
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl1/boot.html
>[22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl10/boot.html
>[23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl10/boot.html
>[24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11877/shard-skl10/boot.html
>[25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-skl9/boot.html
>[26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-skl9/boot.html
>[27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106269v1/shard-sk
[Intel-gfx] [PATCH] drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms
Accidental use of a "SLICE" macro where a "SUBSLICE" macro was intended
causes the group ID for steering to be calculated incorrectly on
pre-Xe_HP platforms.
Fixes: 9a92732f040a ("drm/i915/gt: Add general DSS steering iterator to
intel_gt_mcr")
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index f8c64ab9d3ca..e79405a45312 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -515,7 +515,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt,
unsigned int dss,
*group = dss / GEN_DSS_PER_GSLICE;
*instance = dss % GEN_DSS_PER_GSLICE;
} else {
- *group = dss / GEN_MAX_HSW_SLICES;
+ *group = dss / GEN_MAX_SS_PER_HSW_SLICE;
*instance = dss % GEN_MAX_SS_PER_HSW_SLICE;
return;
}
--
2.36.1
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/dg2: Add Wa_15010599737
On Sat, Jul 09, 2022 at 07:41:45AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/dg2: Add Wa_15010599737
> URL : https://patchwork.freedesktop.org/series/106130/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11862_full -> Patchwork_106130v1_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_106130v1_full absolutely need
> to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_106130v1_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (10 -> 13)
> --
>
> Additional (3): shard-rkl shard-dg1 shard-tglu
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_106130v1_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt:
> - shard-tglb: [PASS][1] -> [FAIL][2] +2 similar issues
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11862/shard-tglb7/igt@kms_frontbuffer_track...@fbcpsr-1p-indfb-fliptrack-mmap-gtt.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-tglb3/igt@kms_frontbuffer_track...@fbcpsr-1p-indfb-fliptrack-mmap-gtt.html
This is an expected regression in functionality due to the new
restrictions imposed by the workaround: the test now fails because
FBC is turned off whenever PSR1 is active. However that's exactly
what the workaround asks us to do (in order to avoid incorrect hardware
behavior).
>
> * igt@kms_invalid_mode@clock-too-high@edp-1-pipe-d:
> - shard-tglb: NOTRUN -> [SKIP][3] +3 similar issues
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-tglb1/igt@kms_invalid_mode@clock-too-h...@edp-1-pipe-d.html
https://gitlab.freedesktop.org/drm/intel/-/issues/6403
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
> - {shard-rkl}:NOTRUN -> [FAIL][4] +7 similar issues
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-rkl-6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
>
> * igt@kms_invalid_mode@zero-vdisplay@hdmi-a-1-pipe-a:
> - {shard-dg1}:NOTRUN -> [WARN][5]
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-dg1-19/igt@kms_invalid_mode@zero-vdisp...@hdmi-a-1-pipe-a.html
>
> * {igt@kms_rmfb@rmfb-ioctl@pipe-d-hdmi-a-1}:
> - {shard-dg1}:NOTRUN -> [FAIL][6] +3 similar issues
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-dg1-19/igt@kms_rmfb@rmfb-io...@pipe-d-hdmi-a-1.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_106130v1_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_create@create-massive:
> - shard-apl: NOTRUN -> [DMESG-WARN][7] ([i915#4991])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-apl3/igt@gem_cre...@create-massive.html
>
> * igt@gem_ctx_persistence@engines-hostile-preempt:
> - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +1
> similar issue
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-snb4/igt@gem_ctx_persiste...@engines-hostile-preempt.html
>
> * igt@gem_ctx_persistence@hostile:
> - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2410])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-tglb1/igt@gem_ctx_persiste...@hostile.html
>
> * igt@gem_exec_balancer@parallel-balancer:
> - shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +26 similar
> issues
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-snb4/igt@gem_exec_balan...@parallel-balancer.html
>
> * igt@gem_exec_fair@basic-none-share@rcs0:
> - shard-glk: NOTRUN -> [FAIL][11] ([i915#2842])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-glk6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
>
> * igt@gem_exec_fair@basic-none@vecs0:
> - shard-apl: [PASS][12] -> [FAIL][13] ([i915#2842])
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11862/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106130v1/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html
>
> * igt@gem_exec_fair@basic-pace@bcs0:
> - shard-iclb:
[Intel-gfx] [PATCH 2/2] drm/i915: Add Wa_14016291713
We already disable FBC when PSR2 is enabled on display version 12 and
above; this new workaround now requires that we do the same with PSR1 on
display versions 12 and 13.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 16537830ccf0..7436b35f7ea0 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1098,6 +1098,12 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
return 0;
}
+ /* Wa_14016291713 */
+ if (IS_DISPLAY_VER(i915, 12, 13) && crtc_state->has_psr) {
+ plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
+ return 0;
+ }
+
if (!pixel_format_is_valid(plane_state)) {
plane_state->no_fbc_reason = "pixel format not supported";
return 0;
--
2.36.1
[Intel-gfx] [PATCH 1/2] drm/i915/dg2: Add Wa_15010599737
This workaround may need to be extended to other platforms soon, but for now it's marked as DG2-specific. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index e6bb24dc7b99..60d6eb5f245b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -371,6 +371,9 @@ #define GEN9_WM_CHICKEN3 _MMIO(0x5588) #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) +#define CHICKEN_RASTER_1 _MMIO(0x6204) +#define DIS_SF_ROUND_NEAREST_EVENREG_BIT(8) + #define VFLSKPD_MMIO(0x62a8) #define DIS_OVER_FETCH_CACHE REG_BIT(1) #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index dcc1ee392c0d..e8111fce56d0 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -689,6 +689,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); + + /* Wa_15010599737:dg2 */ + wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); } static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, -- 2.36.1
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Introduce Meteorlake
On Fri, Jul 08, 2022 at 04:38:48PM +, Patchwork wrote:
> == Series Details ==
>
> Series: i915: Introduce Meteorlake
> URL : https://patchwork.freedesktop.org/series/106075/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11859_full -> Patchwork_106075v1_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_106075v1_full absolutely need
> to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_106075v1_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (13 -> 13)
> --
>
> No changes in participating hosts
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_106075v1_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@gem_exec_schedule@wide@vcs1:
> - shard-kbl: [PASS][1] -> [INCOMPLETE][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-kbl4/igt@gem_exec_schedule@w...@vcs1.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106075v1/shard-kbl1/igt@gem_exec_schedule@w...@vcs1.html
Test actually finished executing, but then there were some NVME errors,
followed by
<2>[ 334.527621] softdog: Initiating panic
<0>[ 334.529807] Kernel panic - not syncing: Software Watchdog Timer expired
This looks like general system instability, likely not related to
graphics at all.
Series applied to drm-intel-gt-next (as suggested by Rodrigo, since this
will allow the IS_METEORLAKE definitions to be cross-pollinated across
both drm-intel branches most easily).
Thanks for the patches.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
> - {shard-rkl}:NOTRUN -> [WARN][3]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106075v1/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
>
> * igt@kms_cursor_legacy@cursor-vs-flip@atomic:
> - {shard-dg1}:[PASS][4] -> [FAIL][5] +4 similar issues
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-dg1-12/igt@kms_cursor_legacy@cursor-vs-f...@atomic.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106075v1/shard-dg1-15/igt@kms_cursor_legacy@cursor-vs-f...@atomic.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_106075v1_full that come from known
> issues:
>
> ### CI changes ###
>
> Possible fixes
>
> * boot:
> - shard-skl: ([PASS][6], [PASS][7], [PASS][8], [PASS][9],
> [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15],
> [PASS][16], [FAIL][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21],
> [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27],
> [PASS][28], [PASS][29], [PASS][30]) ([i915#5032]) -> ([PASS][31], [PASS][32],
> [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38],
> [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44],
> [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50],
> [PASS][51], [PASS][52])
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl10/boot.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl10/boot.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl10/boot.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl1/boot.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl1/boot.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl3/boot.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl3/boot.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl3/boot.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl4/boot.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl4/boot.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl4/boot.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl5/boot.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl5/boot.html
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl5/boot.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl6/boot.html
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11859/shard-skl6/boot.html
>[22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr (rev2)
On Sat, Jul 02, 2022 at 06:25:09PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr (rev2)
> URL : https://patchwork.freedesktop.org/series/105883/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11842_full -> Patchwork_105883v2_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_105883v2_full absolutely need
> to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_105883v2_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (10 -> 13)
> --
>
> Additional (3): shard-rkl shard-dg1 shard-tglu
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_105883v2_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> *
> igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
> - shard-iclb: NOTRUN -> [SKIP][1] +3 similar issues
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105883v2/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscal...@pipe-a-valid-mode.html
Seems to be new tests that match
https://gitlab.freedesktop.org/drm/intel/-/issues/2672 .
New tests were likely introduced by
commit 01f75333df0d27768ef987653ab49c3a1223ce3d
Author: Swati Sharma
AuthorDate: Thu Jun 30 13:15:11 2022 +0300
Commit: Juha-Pekka Heikkila
CommitDate: Fri Jul 1 12:41:09 2022 +0300
tests/i915/kms_flip_scaled_crc: Add new tests covering modifiers and
pixel-formats
>
> * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-b-hdmi-a-2:
> - shard-glk: [PASS][2] -> [FAIL][3]
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11842/shard-glk7/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-b-hdmi-a-2.html
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105883v2/shard-glk1/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-b-hdmi-a-2.html
CRC mismatch. Display CRCs would not be impacted by this patch which
just adds a new GT loop interface
Patch applied to drm-intel-gt-next. Thanks Matt Atwood for the review.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_exec_capture@pi@rcs0:
> - {shard-dg1}:NOTRUN -> [INCOMPLETE][4]
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105883v2/shard-dg1-15/igt@gem_exec_capture@p...@rcs0.html
>
> *
> igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
> - {shard-tglu}: NOTRUN -> [SKIP][5] +14 similar issues
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105883v2/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscal...@pipe-a-valid-mode.html
>
> *
> igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
> - {shard-dg1}:NOTRUN -> [SKIP][6] +13 similar issues
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105883v2/shard-dg1-12/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscal...@pipe-a-valid-mode.html
>
> * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
> - {shard-rkl}:NOTRUN -> [SKIP][7] +31 similar issues
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105883v2/shard-rkl-5/igt@kms_flip_scaled_...@flip-64bpp-linear-to-16bpp-linear-downscaling.html
>
> *
> {igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode}:
> - shard-iclb: NOTRUN -> [SKIP][8] +2 similar issues
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105883v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscal...@pipe-a-default-mode.html
>
>
>
> ### Piglit changes ###
>
> Possible regressions
>
> * spec@arb_gpu_shader5@texturegatheroffsets@fs-rgba-0-unorm-2d:
> - pig-glk-j5005: NOTRUN -> [INCOMPLETE][9]
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105883v2/pig-glk-j5005/spec@arb_gpu_shader5@texturegatheroffs...@fs-rgba-0-unorm-2d.html
>
> * spec@ext_framebuffer_multisample@sample-coverage 4 non-inverted:
> - pig-skl-6260u: NOTRUN -> [CRASH][10]
>[10]: None
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_105883v2_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_persistence@legacy-engines-hostile:
> - shard-snb: NOTRU
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] i915/perf: Replace DRM_DEBUG with driver specific drm_dbg call
On Fri, Jul 08, 2022 at 01:44:00PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] i915/perf: Replace DRM_DEBUG with driver
> specific drm_dbg call
> URL : https://patchwork.freedesktop.org/series/106062/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11857_full -> Patchwork_106062v1_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_106062v1_full absolutely need
> to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_106062v1_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (13 -> 13)
> --
>
> No changes in participating hosts
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_106062v1_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
> - shard-apl: [PASS][1] -> [WARN][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-apl2/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106062v1/shard-apl2/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
Seems to be the same warning seen in
https://gitlab.freedesktop.org/drm/intel/-/issues/2684
https://gitlab.freedesktop.org/drm/intel/-/issues/2681
https://gitlab.freedesktop.org/drm/intel/-/issues/1804
but on a different platform. Not caused by these patches.
>
> * igt@i915_selftest@live@slpc:
> - shard-skl: [PASS][3] -> [INCOMPLETE][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-skl7/igt@i915_selftest@l...@slpc.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106062v1/shard-skl6/igt@i915_selftest@l...@slpc.html
Log cuts off in middle. Likely a sporadic system/network crash; not
caused by the changes here.
>
> * igt@kms_async_flips@test-time-stamp@pipe-a-edp-1:
> - shard-tglb: [PASS][5] -> [INCOMPLETE][6]
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-tglb1/igt@kms_async_flips@test-time-st...@pipe-a-edp-1.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106062v1/shard-tglb8/igt@kms_async_flips@test-time-st...@pipe-a-edp-1.html
Another unexpected incomplete. Not caused by these patches.
Series applied to drm-intel-gt-next (with a minor tweak to the author
line to make the formatting match the s-o-b line). Thanks for the
patches and reviews.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_busy@close-race:
> - {shard-tglu}: [PASS][7] -> [INCOMPLETE][8]
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-tglu-2/igt@gem_b...@close-race.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106062v1/shard-tglu-4/igt@gem_b...@close-race.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_106062v1_full that come from known
> issues:
>
> ### CI changes ###
>
> Possible fixes
>
> * boot:
> - shard-snb: ([PASS][9], [PASS][10], [PASS][11], [PASS][12],
> [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
> [PASS][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
> [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30],
> [PASS][31], [PASS][32], [PASS][33]) ([i915#4338]) -> ([PASS][34], [PASS][35],
> [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41],
> [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47],
> [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53],
> [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-snb7/boot.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-snb7/boot.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-snb7/boot.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-snb7/boot.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-snb6/boot.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-snb6/boot.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-snb6/boot.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-snb6/boot.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11857/shard-snb6/boot.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/mtl: Add MeteorLake PCI IDs
On Thu, Jul 07, 2022 at 05:03:35PM -0700, Radhakrishna Sripada wrote:
> Add Meteorlake PCI IDs. Split into M, and P subplatforms.
>
> v2: Update PCI id's
> v3: Move id 7d60 under MTL_M(MattR)
>
> Bspec: 55420
>
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Matt Roper
Since our hardware starts reporting IP version / platform identity
through MMIO registers starting with MTL, we'll likely start migrating
away from PCI ID as the primary means of platform identification in the
future. But this looks good for getting the platform started in the
short term.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 14 ++
> drivers/gpu/drm/i915/intel_device_info.h | 4
> include/drm/i915_pciids.h| 13 +
> 5 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 00998a78a2ba..1744036bab10 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1019,6 +1019,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_ADLP_RPLP(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
> +#define IS_METEORLAKE_M(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> +#define IS_METEORLAKE_P(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 859d43c7d0a3..aacc10f2e73f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1214,6 +1214,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_RPLP_IDS(&adl_p_info),
> INTEL_DG2_IDS(&dg2_info),
> INTEL_ATS_M_IDS(&ats_m_info),
> + INTEL_MTL_IDS(&mtl_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 27c343316afa..d98fbbd589aa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -202,6 +202,14 @@ static const u16 subplatform_g12_ids[] = {
> INTEL_DG2_G12_IDS(0),
> };
>
> +static const u16 subplatform_m_ids[] = {
> + INTEL_MTL_M_IDS(0),
> +};
> +
> +static const u16 subplatform_p_ids[] = {
> + INTEL_MTL_P_IDS(0),
> +};
> +
> static bool find_devid(u16 id, const u16 *p, unsigned int num)
> {
> for (; num; num--, p++) {
> @@ -256,6 +264,12 @@ void intel_device_info_subplatform_init(struct
> drm_i915_private *i915)
> } else if (find_devid(devid, subplatform_g12_ids,
> ARRAY_SIZE(subplatform_g12_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_G12);
> + } else if (find_devid(devid, subplatform_m_ids,
> + ARRAY_SIZE(subplatform_m_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_M);
> + } else if (find_devid(devid, subplatform_p_ids,
> + ARRAY_SIZE(subplatform_p_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_P);
> }
>
> GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 7ba9663213f4..23bf230aa104 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -127,6 +127,10 @@ enum intel_platform {
> */
> #define INTEL_SUBPLATFORM_N1
>
> +/* MTL */
> +#define INTEL_SUBPLATFORM_M 0
> +#define INTEL_SUBPLATFORM_P 1
> +
> enum intel_ppgtt_type {
> INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
> INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 1bd0420a213d..278031aa2e84 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -733,5 +733,18 @@
> #define INTEL_ATS_M_IDS(info) \
> INTEL_ATS_M150_IDS(info), \
> INTEL_ATS_M75_IDS(info)
> +/* MTL */
> +#define INTEL_MTL_M_IDS(info) \
> + INTEL_VGA_DEVICE(0x7D40, info), \
> + INTEL_VGA_DEVICE(0x7D60, info)
> +
> +#define INTEL_MTL_P_IDS(info) \
> + INTEL_VGA_DEVICE(0x7D45, info), \
> + INTEL_VGA_DEVICE(0x7D55, info), \
> + INTEL_VGA_DEVICE(0x7DD5, info)
> +
> +#define INTEL_MTL_IDS(info) \
> + INTEL_MTL_M_IDS(info), \
> + INTEL_MTL_P_IDS(info)
>
> #endif /* _I915_PCIIDS_H */
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/mtl: Add MeteorLake platform info
On Thu, Jul 07, 2022 at 05:03:34PM -0700, Radhakrishna Sripada wrote:
> MTL has Xe_LPD+ display IP (version = 14), MTL graphics IP
> (version = 12.70), and Xe_LPM+ media IP (version = 13).
>
> Bspec: 55413
> Bspec: 55416
> Bspec: 55417
> Bspec: 55418
> Bspec: 55726
> Bspec: 45544
> Bspec: 65380
>
> v2: rearrange the fields in pci_info(MattR)
>
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 25
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 4 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c22f29c3faa0..00998a78a2ba 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1018,6 +1018,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> #define IS_ADLP_RPLP(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> +#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
I didn't notice it before, but this definition is kind of in an odd
place, mixed into the middle of the subplatform definitions. We should
probably move up to the platform definition section and place it under
IS_PONTEVECCHIO(). That's a trivial change that we can do while
applying the patch though. No need to send another version for that.
Aside from that,
Reviewed-by: Matt Roper
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 0cdd6513fbb7..859d43c7d0a3 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1107,6 +1107,31 @@ static const struct intel_device_info pvc_info = {
> .require_force_probe = 1,
> };
>
> +#define XE_LPDP_FEATURES \
> + XE_LPD_FEATURES,\
> + .display.ver = 14, \
> + .display.has_cdclk_crawl = 1
> +
> +__maybe_unused
> +static const struct intel_device_info mtl_info = {
> + XE_HP_FEATURES,
> + XE_LPDP_FEATURES,
> + /*
> + * Real graphics IP version will be obtained from hardware GMD_ID
> + * register. Value provided here is just for sanity checking.
> + */
> + .graphics.ver = 12,
> + .graphics.rel = 70,
> + .media.ver = 13,
> + PLATFORM(INTEL_METEORLAKE),
> + .display.has_modular_fia = 1,
> + .has_flat_ccs = 0,
> + .has_snoop = 1,
> + .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
> + .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
> + .require_force_probe = 1,
> +};
> +
> #undef PLATFORM
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index f0bf23726ed8..27c343316afa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -73,6 +73,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(XEHPSDV),
> PLATFORM_NAME(DG2),
> PLATFORM_NAME(PONTEVECCHIO),
> + PLATFORM_NAME(METEORLAKE),
> };
> #undef PLATFORM_NAME
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 1c150cd7dceb..7ba9663213f4 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -89,6 +89,7 @@ enum intel_platform {
> INTEL_XEHPSDV,
> INTEL_DG2,
> INTEL_PONTEVECCHIO,
> + INTEL_METEORLAKE,
> INTEL_MAX_PLATFORMS
> };
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/mtl: Add MeteorLake platform info
On Thu, Jul 07, 2022 at 01:26:09PM -0700, Radhakrishna Sripada wrote:
> MTL has Xe_LPD+ display IP (version = 14), MTL graphics IP
> (version = 12.70), and Xe_LPM+ media IP (version = 13).
>
> Bspec: 55413
> Bspec: 55416
> Bspec: 55417
> Bspec: 55418
> Bspec: 55726
> Bspec: 45544
> Bspec: 65380
>
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 25
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 4 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c22f29c3faa0..00998a78a2ba 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1018,6 +1018,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> #define IS_ADLP_RPLP(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> +#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 0cdd6513fbb7..82895ecb25ba 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1107,6 +1107,31 @@ static const struct intel_device_info pvc_info = {
> .require_force_probe = 1,
> };
>
> +#define XE_LPDP_FEATURES \
> + XE_LPD_FEATURES,\
> + .display.ver = 14, \
> + .display.has_cdclk_crawl = 1
> +
> +__maybe_unused
> +static const struct intel_device_info mtl_info = {
> + XE_HP_FEATURES,
> + XE_LPDP_FEATURES,
> + /*
> + * Real graphics IP version will be obtained from hardware GMD_ID
> + * register. Value provided here is just for sanity checking.
> + */
> + .graphics.ver = 12,
> + .graphics.rel = 70,
> + .media.ver = 13,
> + .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
> + PLATFORM(INTEL_METEORLAKE),
> + .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
> + .require_force_probe = 1,
> + .has_flat_ccs = 0,
> + .has_snoop = 1,
> + .display.has_modular_fia = 1,
Not a huge deal, but the ordering here is a bit non-standard. On other
platforms we tend to order things as:
*_FEATURES
IP version values
PLATFORM(FOO)
everything else, sorted alphabetically
Matt
> +};
> +
> #undef PLATFORM
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index f0bf23726ed8..27c343316afa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -73,6 +73,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(XEHPSDV),
> PLATFORM_NAME(DG2),
> PLATFORM_NAME(PONTEVECCHIO),
> + PLATFORM_NAME(METEORLAKE),
> };
> #undef PLATFORM_NAME
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 1c150cd7dceb..7ba9663213f4 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -89,6 +89,7 @@ enum intel_platform {
> INTEL_XEHPSDV,
> INTEL_DG2,
> INTEL_PONTEVECCHIO,
> + INTEL_METEORLAKE,
> INTEL_MAX_PLATFORMS
> };
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/mtl: Add MeteorLake PCI IDs
On Thu, Jul 07, 2022 at 01:26:10PM -0700, Radhakrishna Sripada wrote:
> Add Meteorlake PCI IDs. Split into M, and P subplatforms.
>
> v2: Update PCI id's
>
> Bspec: 55420
>
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 14 ++
> drivers/gpu/drm/i915/intel_device_info.h | 4
> include/drm/i915_pciids.h| 13 +
> 5 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 00998a78a2ba..1744036bab10 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1019,6 +1019,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_ADLP_RPLP(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
> +#define IS_METEORLAKE_M(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> +#define IS_METEORLAKE_P(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 82895ecb25ba..afe88d979cdc 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1214,6 +1214,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_RPLP_IDS(&adl_p_info),
> INTEL_DG2_IDS(&dg2_info),
> INTEL_ATS_M_IDS(&ats_m_info),
> + INTEL_MTL_IDS(&mtl_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 27c343316afa..d98fbbd589aa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -202,6 +202,14 @@ static const u16 subplatform_g12_ids[] = {
> INTEL_DG2_G12_IDS(0),
> };
>
> +static const u16 subplatform_m_ids[] = {
> + INTEL_MTL_M_IDS(0),
> +};
> +
> +static const u16 subplatform_p_ids[] = {
> + INTEL_MTL_P_IDS(0),
> +};
> +
> static bool find_devid(u16 id, const u16 *p, unsigned int num)
> {
> for (; num; num--, p++) {
> @@ -256,6 +264,12 @@ void intel_device_info_subplatform_init(struct
> drm_i915_private *i915)
> } else if (find_devid(devid, subplatform_g12_ids,
> ARRAY_SIZE(subplatform_g12_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_G12);
> + } else if (find_devid(devid, subplatform_m_ids,
> + ARRAY_SIZE(subplatform_m_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_M);
> + } else if (find_devid(devid, subplatform_p_ids,
> + ARRAY_SIZE(subplatform_p_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_P);
> }
>
> GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 7ba9663213f4..23bf230aa104 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -127,6 +127,10 @@ enum intel_platform {
> */
> #define INTEL_SUBPLATFORM_N1
>
> +/* MTL */
> +#define INTEL_SUBPLATFORM_M 0
> +#define INTEL_SUBPLATFORM_P 1
> +
> enum intel_ppgtt_type {
> INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
> INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 1bd0420a213d..6dfeb52f7c6f 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -733,5 +733,18 @@
> #define INTEL_ATS_M_IDS(info) \
> INTEL_ATS_M150_IDS(info), \
> INTEL_ATS_M75_IDS(info)
> +/* MTL */
> +#define INTEL_MTL_M_IDS(info) \
> + INTEL_VGA_DEVICE(0x7D40, info)
> +
> +#define INTEL_MTL_P_IDS(info) \
> + INTEL_VGA_DEVICE(0x7D45, info), \
> + INTEL_VGA_DEVICE(0x7D55, info), \
> + INTEL_VGA_DEVICE(0x7D60, info), \
It looks like this one is supposed to be in the MTL_M list rather than
the MTL_P list.
Matt
> + INTEL_VGA_DEVICE(0x7DD5, info)
> +
> +#define INTEL_MTL_IDS(info) \
> + INTEL_MTL_M_IDS(info), \
> + INTEL_MTL_P_IDS(info)
>
> #endif /* _I915_PCIIDS_H */
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] i915/perf: Disable OA sseu config param for non-gen11 platforms
On Thu, Jul 07, 2022 at 11:27:38AM -0700, Nerlige Ramappa, Umesh wrote:
> The global sseu config is applicable only to gen11 platforms where
> concurrent media, render and OA use cases may cause some subslices to be
> turned off and hence lose NOA configuration. Return ENODEV for non-gen11
> platforms.
>
> v2: gfx12 is already shipped with this, disable for gfx12.5+ (Lionel)
The commit message doesn't really match reality anymore with v2; you
might want to update the commit message a bit.
Also, minor nitpick: although we write IP version numbers as
"arc.release" in shorthand, we shouldn't make the mistake of treating
those as fractional numbers since ".5" != ".50" the way they get handled
in the driver. So this should say "12.50+" rather than "12.5+."
>
> Signed-off-by: Umesh Nerlige Ramappa
> ---
> drivers/gpu/drm/i915/i915_perf.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 1577ab6754db..0ba98f73f217 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -3706,6 +3706,12 @@ static int read_properties_unlocked(struct i915_perf
> *perf,
> case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
> struct drm_i915_gem_context_param_sseu user_sseu;
>
> + if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
> + DRM_DEBUG("SSEU config not supported on gfx
> %x\n",
> + GRAPHICS_VER_FULL(perf->i915));
This should probably be using the device-specific drm_dbg() call.
Actually the perf code in general needs some updates to eliminate
DRM_DEBUG throughout...not only do we want to avoid using the old
non-device-aware interface in newer code, that's also the wrong old
interface to call (DRM_DEBUG categorizes messages as DRM_UT_CORE,
whereas DRM_DEBUG_DRIVER is the one that treats them as driver messages
with DRM_UT_DRIVER).
Matt
> + return -ENODEV;
> + }
> +
> if (copy_from_user(&user_sseu,
> u64_to_user_ptr(value),
> sizeof(user_sseu))) {
> --
> 2.35.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915/display: clean up comments
On Fri, Jul 01, 2022 at 04:32:36PM -0400, Tom Rix wrote:
> spelling changes
> resoluition -> resolution
> dont-> don't
> commmit -> commit
> Invalidade -> Invalidate
>
> Signed-off-by: Tom Rix
Reviewed-by: Matt Roper
and applied to drm-intel-next. Thanks for the patch.
Matt
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7d61c55184e5..e6a870641cd2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -555,7 +555,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> /*
>* TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
>* values from BSpec. In order to setting an optimal power
> - * consumption, lower than 4k resoluition mode needs to decrese
> + * consumption, lower than 4k resolution mode needs to decrease
>* IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
>* mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
>*/
> @@ -959,7 +959,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> int psr_setup_time;
>
> /*
> - * Current PSR panels dont work reliably with VRR enabled
> + * Current PSR panels don't work reliably with VRR enabled
>* So if VRR is enabled, do not enable PSR.
>*/
> if (crtc_state->vrr.enable)
> @@ -1664,7 +1664,7 @@ static void intel_psr2_sel_fetch_pipe_alignment(const
> struct intel_crtc_state *c
> *
> * Plane scaling and rotation is not supported by selective fetch and both
> * properties can change without a modeset, so need to be check at every
> - * atomic commmit.
> + * atomic commit.
> */
> static bool psr2_sel_fetch_plane_state_supported(const struct
> intel_plane_state *plane_state)
> {
> @@ -2203,7 +2203,7 @@ static void _psr_invalidate_handle(struct intel_dp
> *intel_dp)
> }
>
> /**
> - * intel_psr_invalidate - Invalidade PSR
> + * intel_psr_invalidate - Invalidate PSR
> * @dev_priv: i915 device
> * @frontbuffer_bits: frontbuffer plane tracking bits
> * @origin: which operation caused the invalidate
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v8 0/3] drm/doc/rfc: i915 VM_BIND feature design + uapi
On Thu, Jun 30, 2022 at 05:31:07PM -0700, Niranjana Vishwanathapura wrote: > This is the i915 driver VM_BIND feature design RFC patch series along > with the required uapi definition and description of intended use cases. > > v2: Reduce the scope to simple Mesa use case. > Remove all compute related uapi, vm_bind/unbind queue support and > only support a timeline out fence instead of an in/out timeline > fence array. > v3: Expand documentation on dma-resv usage, TLB flushing, execbuf3 and > VM_UNBIND. Add FENCE_VALID and TLB_FLUSH flags. > v4: Remove I915_GEM_VM_BIND_TLB_FLUSH flag and add additional > uapi documentation for vm_bind/unbind. > v5: Update TLB flushing documentation. > Add version support to stage implementation. > v6: Define and use drm_i915_gem_timeline_fence structure for > execbuf3 and vm_bind/unbind timeline fences. > v7: Rename I915_PARAM_HAS_VM_BIND to I915_PARAM_VM_BIND_VERSION. > Update documentation on async vm_bind/unbind and versioning. > Remove redundant vm_bind/unbind FENCE_VALID flag, execbuf3 > batch_count field and I915_EXEC3_SECURE flag. > v8: Remove I915_GEM_VM_BIND_READONLY and minor documentation > updates. > > Signed-off-by: Niranjana Vishwanathapura > Reviewed-by: Daniel Vetter > Acked-by: Paulo Zanoni Series applied to drm-intel-gt-next. Thanks for the patches and reviews. Matt > > Niranjana Vishwanathapura (3): > drm/doc/rfc: VM_BIND feature design document > drm/i915: Update i915 uapi documentation > drm/doc/rfc: VM_BIND uapi definition > > Documentation/gpu/rfc/i915_vm_bind.h | 291 + > Documentation/gpu/rfc/i915_vm_bind.rst | 245 + > Documentation/gpu/rfc/index.rst| 4 + > include/uapi/drm/i915_drm.h| 205 + > 4 files changed, 700 insertions(+), 45 deletions(-) > create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h > create mode 100644 Documentation/gpu/rfc/i915_vm_bind.rst > > -- > 2.21.0.rc0.32.g243a4c7e27 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH 2/2] drm/i915: DG2 and ATS-M device ID updates
On Fri, Jul 01, 2022 at 09:59:50AM -0700, Lucas De Marchi wrote: > On Fri, Jul 01, 2022 at 08:22:31AM -0700, Matt Roper wrote: > > Small BAR support has now landed, which allows us to add the PCI IDs > > that correspond to add-in card designs of DG2 and ATS-M. There's also > > one additional MB-down PCI ID that recently appeared (0x5698) so we add > > it too. > > > > Cc: Lucas De Marchi > > Signed-off-by: Matt Roper > > > Reviewed-by: Lucas De Marchi Thanks. Applied to drm-intel-gt-next (since that's the branch that has the small BAR patches that were a pre-req to adding these IDs) and dropped the equivalent patch from topic/core-from-CI. Matt > > Lucas De Marchi -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
[Intel-gfx] [PATCH] drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr
Although all DSS belong to a single pool on Xe_HP platforms (i.e.,
they're not organized into slices from a topology point of view), we do
still need to pass 'group' and 'instance' targets when steering register
accesses to a specific instance of a per-DSS multicast register. The
rules for how to determine group and instance IDs (which previously used
legacy terms "slice" and "subslice") varies by platform. Some platforms
determine steering by gslice membership, some platforms by cslice
membership, and future platforms may have other rules.
Since looping over each DSS and performing steered unicast register
accesses is a relatively common pattern, let's add a dedicated iteration
macro to handle this (and replace the platform-specific "instdone" loop
we were using previously. This will avoid the calling code needing to
figure out the details about how to obtain steering IDs for a specific
DSS.
Most of the places where we use this new loop are in the GPU errorstate
code at the moment, but we do have some additional features coming in
the future that will also need to loop over each DSS and steer some
register accesses accordingly.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 34 ++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 22
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 25 ++
drivers/gpu/drm/i915/gt/intel_gt_mcr.h| 24 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 13 ---
drivers/gpu/drm/i915/i915_gpu_error.c | 32 ++---
6 files changed, 75 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 283870c65991..37fa813af766 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1517,7 +1517,6 @@ void intel_engine_get_instdone(const struct
intel_engine_cs *engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *i915 = engine->i915;
- const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -1542,32 +1541,19 @@ void intel_engine_get_instdone(const struct
intel_engine_cs *engine,
intel_uncore_read(uncore,
GEN12_SC_INSTDONE_EXTRA2);
}
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
- for_each_instdone_gslice_dss_xehp(i915, sseu, iter,
slice, subslice) {
- instdone->sampler[slice][subslice] =
- intel_gt_mcr_read(engine->gt,
- GEN7_SAMPLER_INSTDONE,
- slice, subslice);
- instdone->row[slice][subslice] =
- intel_gt_mcr_read(engine->gt,
- GEN7_ROW_INSTDONE,
- slice, subslice);
- }
- } else {
- for_each_instdone_slice_subslice(i915, sseu, slice,
subslice) {
- instdone->sampler[slice][subslice] =
- intel_gt_mcr_read(engine->gt,
- GEN7_SAMPLER_INSTDONE,
- slice, subslice);
- instdone->row[slice][subslice] =
- intel_gt_mcr_read(engine->gt,
- GEN7_ROW_INSTDONE,
- slice, subslice);
- }
+ for_each_ss_steering(iter, engine->gt, slice, subslice) {
+ instdone->sampler[slice][subslice] =
+ intel_gt_mcr_read(engine->gt,
+ GEN7_SAMPLER_INSTDONE,
+ slice, subslice);
+ instdone->row[slice][subslice] =
+ intel_gt_mcr_read(engine->gt,
+ GEN7_ROW_INSTDONE,
+ slice, subslice);
}
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
- for_each_instdone_gslice_dss_xehp(i915, sseu, iter,
slice, subslice)
+ for_each_ss_steering(iter, engine->gt, slice, subslice)
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pvc: Implement w/a 16016694945
On Fri, Jul 01, 2022 at 12:52:21PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pvc: Implement w/a 16016694945
> URL : https://patchwork.freedesktop.org/series/105837/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11835_full -> Patchwork_105837v1_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_105837v1_full absolutely need
> to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_105837v1_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (13 -> 13)
> --
>
> No changes in participating hosts
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_105837v1_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_create@create-ext-cpu-access-big:
> - {shard-rkl}:NOTRUN -> [SKIP][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/shard-rkl-5/igt@gem_cre...@create-ext-cpu-access-big.html
>
> * igt@i915_query@query-regions-unallocated:
> - {shard-dg1}:NOTRUN -> [SKIP][2] +2 similar issues
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/shard-dg1-16/igt@i915_qu...@query-regions-unallocated.html
These both look like new tests that were just added to exercise small
BAR support; I believe the skips were expected until the corresponding
kernel changes from Matt Auld landed (which just happened this morning,
probably after this series was tested). Not related to Gustavo's patch
here.
>
>
> ### Piglit changes ###
>
> Possible regressions
>
> * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-3-unorm-2drect-const:
> - pig-glk-j5005: NOTRUN -> [CRASH][3] +1 similar issue
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/pig-glk-j5005/spec@arb_gpu_shader5@texturegatheroff...@vs-rgba-3-unorm-2drect-const.html
>
> * spec@ext_texture_snorm@fbo-colormask-formats:
> - pig-skl-6260u: NOTRUN -> [INCOMPLETE][4]
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/pig-skl-6260u/spec@ext_texture_sn...@fbo-colormask-formats.html
The PVC workaround wouldn't have impacted execution on old gen9
platforms like GLK and SKL. Not related to Gustavo's patch.
Applied to drm-intel-gt-next. Thanks for the patch.
Matt
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_105837v1_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_persistence@hang:
> - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271]) +116 similar
> issues
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/shard-skl6/igt@gem_ctx_persiste...@hang.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#5784])
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11835/shard-tglb7/igt@gem_...@unwedge-stress.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/shard-tglb5/igt@gem_...@unwedge-stress.html
>
> * igt@gem_exec_balancer@parallel-bb-first:
> - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +1 similar
> issue
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11835/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/shard-iclb3/igt@gem_exec_balan...@parallel-bb-first.html
>
> * igt@gem_exec_fair@basic-none@vcs0:
> - shard-apl: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar
> issue
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11835/shard-apl8/igt@gem_exec_fair@basic-n...@vcs0.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/shard-apl7/igt@gem_exec_fair@basic-n...@vcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs0:
> - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842])
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11835/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842])
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105837v1/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html
>
> * igt@gem_exec_fair@basic-throttle@rcs0:
> - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2849]
[Intel-gfx] [PATCH 1/2] Revert "topic/core-for-CI: Add remaining DG2 and ATS-M device IDs"
This reverts commit f7d7dddaab81eeae4508197b5f38f0b974d97b8c.
In reality we'll just rebase this patch out of the topic/core-for-CI
branch after landing the "real" copy in drm-intel. But to prevent
pre-merge CI from getting confused, we send it as an explicit revert on
the mailing list.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 --
include/drm/i915_pciids.h| 25 +++-
3 files changed, 4 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0cdd6513fbb7..5edc8fbf1dff 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1075,6 +1075,7 @@ static const struct intel_device_info dg2_info = {
.require_force_probe = 1,
};
+__maybe_unused
static const struct intel_device_info ats_m_info = {
DG2_FEATURES,
.display = { 0 },
@@ -1188,7 +1189,6 @@ static const struct pci_device_id pciidlist[] = {
INTEL_RPLS_IDS(&adl_s_info),
INTEL_RPLP_IDS(&adl_p_info),
INTEL_DG2_IDS(&dg2_info),
- INTEL_ATS_M_IDS(&ats_m_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index f0bf23726ed8..7eb893666595 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -189,12 +189,10 @@ static const u16 subplatform_rpl_ids[] = {
static const u16 subplatform_g10_ids[] = {
INTEL_DG2_G10_IDS(0),
- INTEL_ATS_M150_IDS(0),
};
static const u16 subplatform_g11_ids[] = {
INTEL_DG2_G11_IDS(0),
- INTEL_ATS_M75_IDS(0),
};
static const u16 subplatform_g12_ids[] = {
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4585fed4e41e..283dadfbb4db 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -696,41 +696,22 @@
#define INTEL_DG2_G10_IDS(info) \
INTEL_VGA_DEVICE(0x5690, info), \
INTEL_VGA_DEVICE(0x5691, info), \
- INTEL_VGA_DEVICE(0x5692, info), \
- INTEL_VGA_DEVICE(0x56A0, info), \
- INTEL_VGA_DEVICE(0x56A1, info), \
- INTEL_VGA_DEVICE(0x56A2, info)
+ INTEL_VGA_DEVICE(0x5692, info)
#define INTEL_DG2_G11_IDS(info) \
INTEL_VGA_DEVICE(0x5693, info), \
INTEL_VGA_DEVICE(0x5694, info), \
INTEL_VGA_DEVICE(0x5695, info), \
- INTEL_VGA_DEVICE(0x56A5, info), \
- INTEL_VGA_DEVICE(0x56A6, info), \
- INTEL_VGA_DEVICE(0x56B0, info), \
- INTEL_VGA_DEVICE(0x56B1, info)
+ INTEL_VGA_DEVICE(0x56B0, info)
#define INTEL_DG2_G12_IDS(info) \
INTEL_VGA_DEVICE(0x5696, info), \
INTEL_VGA_DEVICE(0x5697, info), \
- INTEL_VGA_DEVICE(0x56A3, info), \
- INTEL_VGA_DEVICE(0x56A4, info), \
- INTEL_VGA_DEVICE(0x56B2, info), \
- INTEL_VGA_DEVICE(0x56B3, info)
+ INTEL_VGA_DEVICE(0x56B2, info)
#define INTEL_DG2_IDS(info) \
INTEL_DG2_G10_IDS(info), \
INTEL_DG2_G11_IDS(info), \
INTEL_DG2_G12_IDS(info)
-#define INTEL_ATS_M150_IDS(info) \
- INTEL_VGA_DEVICE(0x56C0, info)
-
-#define INTEL_ATS_M75_IDS(info) \
- INTEL_VGA_DEVICE(0x56C1, info)
-
-#define INTEL_ATS_M_IDS(info) \
- INTEL_ATS_M150_IDS(info), \
- INTEL_ATS_M75_IDS(info)
-
#endif /* _I915_PCIIDS_H */
--
2.36.1
[Intel-gfx] [PATCH 2/2] drm/i915: DG2 and ATS-M device ID updates
Small BAR support has now landed, which allows us to add the PCI IDs
that correspond to add-in card designs of DG2 and ATS-M. There's also
one additional MB-down PCI ID that recently appeared (0x5698) so we add
it too.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 ++
include/drm/i915_pciids.h| 26 +---
3 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5edc8fbf1dff..0cdd6513fbb7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1075,7 +1075,6 @@ static const struct intel_device_info dg2_info = {
.require_force_probe = 1,
};
-__maybe_unused
static const struct intel_device_info ats_m_info = {
DG2_FEATURES,
.display = { 0 },
@@ -1189,6 +1188,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_RPLS_IDS(&adl_s_info),
INTEL_RPLP_IDS(&adl_p_info),
INTEL_DG2_IDS(&dg2_info),
+ INTEL_ATS_M_IDS(&ats_m_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 7eb893666595..f0bf23726ed8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -189,10 +189,12 @@ static const u16 subplatform_rpl_ids[] = {
static const u16 subplatform_g10_ids[] = {
INTEL_DG2_G10_IDS(0),
+ INTEL_ATS_M150_IDS(0),
};
static const u16 subplatform_g11_ids[] = {
INTEL_DG2_G11_IDS(0),
+ INTEL_ATS_M75_IDS(0),
};
static const u16 subplatform_g12_ids[] = {
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 283dadfbb4db..1bd0420a213d 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -696,22 +696,42 @@
#define INTEL_DG2_G10_IDS(info) \
INTEL_VGA_DEVICE(0x5690, info), \
INTEL_VGA_DEVICE(0x5691, info), \
- INTEL_VGA_DEVICE(0x5692, info)
+ INTEL_VGA_DEVICE(0x5692, info), \
+ INTEL_VGA_DEVICE(0x56A0, info), \
+ INTEL_VGA_DEVICE(0x56A1, info), \
+ INTEL_VGA_DEVICE(0x56A2, info)
#define INTEL_DG2_G11_IDS(info) \
INTEL_VGA_DEVICE(0x5693, info), \
INTEL_VGA_DEVICE(0x5694, info), \
INTEL_VGA_DEVICE(0x5695, info), \
- INTEL_VGA_DEVICE(0x56B0, info)
+ INTEL_VGA_DEVICE(0x5698, info), \
+ INTEL_VGA_DEVICE(0x56A5, info), \
+ INTEL_VGA_DEVICE(0x56A6, info), \
+ INTEL_VGA_DEVICE(0x56B0, info), \
+ INTEL_VGA_DEVICE(0x56B1, info)
#define INTEL_DG2_G12_IDS(info) \
INTEL_VGA_DEVICE(0x5696, info), \
INTEL_VGA_DEVICE(0x5697, info), \
- INTEL_VGA_DEVICE(0x56B2, info)
+ INTEL_VGA_DEVICE(0x56A3, info), \
+ INTEL_VGA_DEVICE(0x56A4, info), \
+ INTEL_VGA_DEVICE(0x56B2, info), \
+ INTEL_VGA_DEVICE(0x56B3, info)
#define INTEL_DG2_IDS(info) \
INTEL_DG2_G10_IDS(info), \
INTEL_DG2_G11_IDS(info), \
INTEL_DG2_G12_IDS(info)
+#define INTEL_ATS_M150_IDS(info) \
+ INTEL_VGA_DEVICE(0x56C0, info)
+
+#define INTEL_ATS_M75_IDS(info) \
+ INTEL_VGA_DEVICE(0x56C1, info)
+
+#define INTEL_ATS_M_IDS(info) \
+ INTEL_ATS_M150_IDS(info), \
+ INTEL_ATS_M75_IDS(info)
+
#endif /* _I915_PCIIDS_H */
--
2.36.1
Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add performance workaround 18019455067
On Mon, Jun 27, 2022 at 03:59:28PM +0300, Lionel Landwerlin wrote: > The recommended number of stackIDs for Ray Tracing subsystem is 512 > rather than 2048 (default HW programming). > > v2: Move the programming to dg2_ctx_gt_tuning_init() (Lucas) I'm not sure this is actually the correct move. As far as I can see on bspec 46261, RT_CTRL isn't part of the engine's context, so we need to make sure it gets added to engine->wa_list instead of engine->ctx_wa_list, otherwise it won't be properly re-applied after engine resets and such. Most of our other tuning values are part of the context image, so this one is a bit unusual. To get it onto the engine->wa_list, the workaround needs to either be defined via rcs_engine_wa_init() or general_render_compute_wa_init(). The latter is the new, preferred location for registers that are part of the render/compute reset domain, but that don't live in the RCS engine's 0x2xxx MMIO range (since all RCS and CCS engines get reset together, the items in general_render_compute_wa_init() will make sure it's dealt with as part of the handling for the first RCS/CCS engine, so that we won't miss out on applying it if the platform doesn't have an RCS). At the moment we don't have too many "tuning" values that we need to set that aren't part of an engine's context, so we don't yet have a dedicated "tuning" function for engine-style workarounds like we do with ctx-style workarounds. Matt > > Signed-off-by: Lionel Landwerlin > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 07ef111947b8c..12fc87b957425 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1112,6 +1112,10 @@ > #define GEN12_PUSH_CONST_DEREF_HOLD_DISREG_BIT(8) > > #define RT_CTRL _MMIO(0xe530) > +#define RT_CTRL_NUMBER_OF_STACKIDS_MASKREG_GENMASK(6, 5) > +#define NUMBER_OF_STACKIDS_512 2 > +#define NUMBER_OF_STACKIDS_10241 > +#define NUMBER_OF_STACKIDS_20480 > #define DIS_NULL_QUERY REG_BIT(10) > > #define EU_PERF_CNTL1_MMIO(0xe558) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 3213c593a55f4..4d80716b957d4 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -575,6 +575,11 @@ static void dg2_ctx_gt_tuning_init(struct > intel_engine_cs *engine, > FF_MODE2_TDS_TIMER_MASK, > FF_MODE2_TDS_TIMER_128, > 0, false); > + wa_write_clr_set(wal, > + RT_CTRL, > + RT_CTRL_NUMBER_OF_STACKIDS_MASK, > + REG_FIELD_PREP(RT_CTRL_NUMBER_OF_STACKIDS_MASK, > + NUMBER_OF_STACKIDS_512)); > } > > /* > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
[Intel-gfx] [PATCH 2/2] drm/i915: Prefer "XEHP_" prefix for registers
We've been introducing new registers with a mix of "XEHP_"
(architecture) and "XEHPSDV_" (platform) prefixes. For consistency,
let's settle on "XEHP_" as the preferred form.
XEHPSDV_RP_STATE_CAP stays with its current name since that's truly a
platform-specific register and not something that applies to the Xe_HP
architecture as a whole.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 8
drivers/gpu/drm/i915/i915_reg.h | 6 +++---
5 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index e63de9c06596..166d0a4b9e8c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -836,8 +836,8 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915,
u16 type,
} else {
resource_size_t lmem_range;
- lmem_range = intel_gt_mcr_read_any(&i915->gt0,
XEHPSDV_TILE0_ADDR_RANGE) & 0x;
- lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
+ lmem_range = intel_gt_mcr_read_any(&i915->gt0,
XEHP_TILE0_ADDR_RANGE) & 0x;
+ lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
lmem_size *= SZ_1G;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 61815b6e87de..37c1095d8603 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -324,11 +324,11 @@
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
-#define XEHPSDV_TILE0_ADDR_RANGE _MMIO(0x4900)
-#define XEHPSDV_TILE_LMEM_RANGE_SHIFT8
+#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
+#define XEHP_TILE_LMEM_RANGE_SHIFT 8
-#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
-#define XEHPSDV_CCS_BASE_SHIFT 8
+#define XEHP_FLAT_CCS_BASE_ADDR_MMIO(0x4910)
+#define XEHP_CCS_BASE_SHIFT 8
#define GAMTARBMODE_MMIO(0x4a08)
#define ARB_MODE_BWGTLB_DISABLE (1 << 9)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index ae8a8f725f01..73a8b46e0234 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -679,7 +679,7 @@ static ssize_t media_RP0_freq_mhz_show(struct device *dev,
u32 val;
int err;
- err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
+ err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
PCODE_MBOX_FC_SC_READ_FUSED_P0,
PCODE_MBOX_DOMAIN_MEDIAFF, &val);
@@ -700,7 +700,7 @@ static ssize_t media_RPn_freq_mhz_show(struct device *dev,
u32 val;
int err;
- err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
+ err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
PCODE_MBOX_FC_SC_READ_FUSED_PN,
PCODE_MBOX_DOMAIN_MEDIAFF, &val);
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 2ff448047020..d09b996a9759 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -105,12 +105,12 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
resource_size_t lmem_range;
u64 tile_stolen, flat_ccs_base;
- lmem_range = intel_gt_mcr_read_any(&i915->gt0,
XEHPSDV_TILE0_ADDR_RANGE) & 0x;
- lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
+ lmem_range = intel_gt_mcr_read_any(&i915->gt0,
XEHP_TILE0_ADDR_RANGE) & 0x;
+ lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
lmem_size *= SZ_1G;
- flat_ccs_base = intel_gt_mcr_read_any(gt,
XEHPSDV_FLAT_CCS_BASE_ADDR);
- flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) *
SZ_64K;
+ flat_ccs_base = intel_gt_mcr_read_any(gt,
XEHP_FLAT_CCS_BASE_ADDR);
+ flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT) * SZ_64K;
/* FIXME: Remove this when we have small-bar enabled */
if (pci_resource_len(pdev, 2) < lmem_size) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cf5e16abf6c7..643d7f020a4a 100644
--- a/
[Intel-gfx] [PATCH 1/2] drm/i915: Correct duplicated/misplaced GT register definitions
XEHPSDV_FLAT_CCS_BASE_ADDR, GEN8_L3_LRA_1_GPGPU, and MMCD_MISC_CTRL were
duplicated between i915_reg.h and intel_gt_regs.h. These are all GT
registers, so we should drop the copy from i915_reg.h.
XEHPSDV_TILE0_ADDR_RANGE was defined in i915_reg.h, but really belongs
in intel_gt_regs.h. Move it.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h| 3 +++
drivers/gpu/drm/i915/i915_reg.h| 17 -
3 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index fa54823d1219..e63de9c06596 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -14,6 +14,7 @@
#include "gem/i915_gem_region.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_mcr.h"
+#include "gt/intel_gt_regs.h"
#include "gt/intel_region_lmem.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 07ef111947b8..61815b6e87de 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -324,6 +324,9 @@
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
+#define XEHPSDV_TILE0_ADDR_RANGE _MMIO(0x4900)
+#define XEHPSDV_TILE_LMEM_RANGE_SHIFT8
+
#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
#define XEHPSDV_CCS_BASE_SHIFT 8
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 932bd6aa4a0a..cf5e16abf6c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8345,23 +8345,6 @@ enum skl_power_gate {
#define SGGI_DIS REG_BIT(15)
#define SGR_DIS REG_BIT(13)
-#define XEHPSDV_TILE0_ADDR_RANGE _MMIO(0x4900)
-#define XEHPSDV_TILE_LMEM_RANGE_SHIFT 8
-
-#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
-#define XEHPSDV_CCS_BASE_SHIFT 8
-
-/* gamt regs */
-#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
-#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for
LRA1/2 */
-#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for
LRA1/2 */
-#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /*"" */
-#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /*"" */
-
-#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
-#define MMCD_PCLA (1 << 31)
-#define MMCD_HOTSPOT_EN (1 << 27)
-
#define _ICL_PHY_MISC_A0x64C00
#define _ICL_PHY_MISC_B0x64C04
#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F"
*/
--
2.36.1
Re: [Intel-gfx] [PATCH] drm/i915: Call i915_gem_suspend() only after display is turned off
On Thu, Jun 23, 2022 at 07:48:32AM -0700, Souza, Jose wrote: > On Wed, 2022-06-22 at 15:19 -0700, Matt Roper wrote: > > On Tue, Jun 21, 2022 at 10:03:04AM -0700, Souza, Jose wrote: > > > On Fri, 2022-06-17 at 12:28 -0700, Matt Roper wrote: > > > > On Fri, Jun 17, 2022 at 12:06:29PM -0700, José Roberto de Souza wrote: > > > > > Gem buffers could still be in use by display after i915_gem_suspend() > > > > > is executed so there is chances that i915_gem_flush_free_objects() > > > > > will be being executed at the same time that > > > > > intel_runtime_pm_driver_release() is executed printing warnings about > > > > > wakerefs will being held. > > > > > > > > By the same logic do we need to adjust i915_driver_remove() too? > > > > > > Nope, all display buffers are freed in i915_driver_unregister() call > > > chain: > > > > > > > > > i915_driver_remove() > > > i915_driver_unregister() > > > intel_display_driver_unregister() > > > drm_atomic_helper_shutdown() > > > i915_gem_suspend() > > > i915_gem_drain_freed_objects() > > > > > > > > > Only FBC compressed framebuffer is freed after that but that will not > > > cause any warnings as it is allocated from stolen memory. > > > > Okay sounds good; thanks for checking. > > > > I'm still having a bit of trouble understanding your description of the > > issue in the commit message though: > > > > "...so there is chances that i915_gem_flush_free_objects() will > > be being executed at the same time that > > intel_runtime_pm_driver_release()..." > > > > I'm not super familiar with the driver teardown paths, or the memory > > management cleanup details. Intuitively it makes sense that we should > > clean up memory management (GEM) only after we've torn down display so > > that all objects that were used by framebuffers are out of circulation. > > But from a cursory view, it looks like i915_gem_suspend() is mostly > > concerned with quiescing the GT and cleaning up PPGTT (which doesn't > > impact display since all of its buffers are in the GGTT). > > > > Is the problem arising from i915->mm.free_work still doing asynchronous > > work to actually release the unused objects at the same time we're > > tearing down runtime PM later? If so does swapping the order of the > > gem_suspend and display disable here actually prevent that from > > happening or does it just make the race less likely by helping some > > objects free up earlier? > > So when the last reference of a gem object is removed it is added to the > mm.free_list list and mm.free_work is queued to actually free the object. > i915_gem_drain_freed_objects() flushes the mm.free_work. > > If any other gem object has its last reference removed after > i915_gem_suspend()/i915_gem_drain_freed_objects() the warning in > intel_runtime_pm_driver_release() can happen as the mm.free_work could be > running at the same time. > > But when pci_driver.remove() is called, probably all file descriptors > attached to this device have been closed and the functions called after > i915_gem_suspend() will not free any gem object, so I don't believe we will > have any more warnings. Okay, thanks for explaining, makes sense. You might want to add some of this extra explanation to the commit message too for future reference, but either way, Reviewed-by: Matt Roper > > > > > > > Matt > > > > > > > > > > > > > > > > > Matt > > > > > > > > > > > > > > So here only calling i915_gem_suspend() and by consequence > > > > > i915_gem_drain_freed_objects() only after display is down making > > > > > sure all buffers are freed. > > > > > > > > > > Signed-off-by: José Roberto de Souza > > > > > --- > > > > > drivers/gpu/drm/i915/i915_driver.c | 4 ++-- > > > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_driver.c > > > > > b/drivers/gpu/drm/i915/i915_driver.c > > > > > index d26dcca7e654a..4227675dd1cfe 100644 > > > > > --- a/drivers/gpu/drm/i915/i915_driver.c > > > > > +++ b/drivers/gpu/drm/i915/i915_driver.c > > > > > @@ -1067,8 +1067,6 @@ void i915
Re: [Intel-gfx] [PATCH] drm/i915: Call i915_gem_suspend() only after display is turned off
On Tue, Jun 21, 2022 at 10:03:04AM -0700, Souza, Jose wrote:
> On Fri, 2022-06-17 at 12:28 -0700, Matt Roper wrote:
> > On Fri, Jun 17, 2022 at 12:06:29PM -0700, José Roberto de Souza wrote:
> > > Gem buffers could still be in use by display after i915_gem_suspend()
> > > is executed so there is chances that i915_gem_flush_free_objects()
> > > will be being executed at the same time that
> > > intel_runtime_pm_driver_release() is executed printing warnings about
> > > wakerefs will being held.
> >
> > By the same logic do we need to adjust i915_driver_remove() too?
>
> Nope, all display buffers are freed in i915_driver_unregister() call chain:
>
>
> i915_driver_remove()
> i915_driver_unregister()
> intel_display_driver_unregister()
> drm_atomic_helper_shutdown()
> i915_gem_suspend()
> i915_gem_drain_freed_objects()
>
>
> Only FBC compressed framebuffer is freed after that but that will not cause
> any warnings as it is allocated from stolen memory.
Okay sounds good; thanks for checking.
I'm still having a bit of trouble understanding your description of the
issue in the commit message though:
"...so there is chances that i915_gem_flush_free_objects() will
be being executed at the same time that
intel_runtime_pm_driver_release()..."
I'm not super familiar with the driver teardown paths, or the memory
management cleanup details. Intuitively it makes sense that we should
clean up memory management (GEM) only after we've torn down display so
that all objects that were used by framebuffers are out of circulation.
But from a cursory view, it looks like i915_gem_suspend() is mostly
concerned with quiescing the GT and cleaning up PPGTT (which doesn't
impact display since all of its buffers are in the GGTT).
Is the problem arising from i915->mm.free_work still doing asynchronous
work to actually release the unused objects at the same time we're
tearing down runtime PM later? If so does swapping the order of the
gem_suspend and display disable here actually prevent that from
happening or does it just make the race less likely by helping some
objects free up earlier?
Matt
>
> >
> >
> > Matt
> >
> > >
> > > So here only calling i915_gem_suspend() and by consequence
> > > i915_gem_drain_freed_objects() only after display is down making
> > > sure all buffers are freed.
> > >
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > > b/drivers/gpu/drm/i915/i915_driver.c
> > > index d26dcca7e654a..4227675dd1cfe 100644
> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > @@ -1067,8 +1067,6 @@ void i915_driver_shutdown(struct drm_i915_private
> > > *i915)
> > > intel_runtime_pm_disable(&i915->runtime_pm);
> > > intel_power_domains_disable(i915);
> > >
> > > - i915_gem_suspend(i915);
> > > -
> > > if (HAS_DISPLAY(i915)) {
> > > drm_kms_helper_poll_disable(&i915->drm);
> > >
> > > @@ -1085,6 +1083,8 @@ void i915_driver_shutdown(struct drm_i915_private
> > > *i915)
> > >
> > > intel_dmc_ucode_suspend(i915);
> > >
> > > + i915_gem_suspend(i915);
> > > +
> > > /*
> > >* The only requirement is to reboot with display DC states disabled,
> > >* for now leaving all display power wells in the INIT power domain
> > > --
> > > 2.36.1
> > >
> >
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add performance workaround 18019455067
On Wed, Jun 22, 2022 at 09:38:36PM +0300, Lionel Landwerlin wrote:
> This is the recommended value for optimal performance.
>
> Signed-off-by: Lionel Landwerlin
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 07ef111947b8c..a50b5790e434e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1112,6 +1112,9 @@
> #define GEN12_PUSH_CONST_DEREF_HOLD_DISREG_BIT(8)
>
> #define RT_CTRL _MMIO(0xe530)
> +#define NUMBER_OF_STACKIDS_512 (2 << 5)
> +#define NUMBER_OF_STACKIDS_1024(1 << 5)
> +#define NUMBER_OF_STACKIDS_2048(0 << 5)
Preferred notation these days would be to use REG_* macros. I.e.,
#define NUMBER_OF_STACKIDSREG_GENMASK(6, 5)
#define NUMBER_OF_STACKIDS_512REG_FIELD_PREP(NUMBER_OF_STACKIDS, 0x2)
It's also probably not worth defining the other values that we're not
using. If we wind up needing one of them on a future platform, we'll
want to double check at that point anyway to make sure the meaning
hasn't changed.
> #define DIS_NULL_QUERY REG_BIT(10)
>
> #define EU_PERF_CNTL1_MMIO(0xe558)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3213c593a55f4..a8a389d36986c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2106,6 +2106,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
>* performance guide section.
>*/
> wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> +
> +/* Wa_18019455067:dg2 / BSpec 68331/54402 */
Generally we just stick the bspec page numbers in the commit message
above the Signed-off-by line and don't put them in the code itself.
> +wa_write_or(wal, RT_CTRL, NUMBER_OF_STACKIDS_512);
This will bit-wise OR the STACKIDS_512 into register's existing value.
Since the hardware default for the field is 0 that would probably work
out okay in this case, but in general when we need to change the value
of a multi-bit field we want to define the workaround in a way that will
clear all bits of the field before OR'ing in the new value so that you
don't wind up with any leftover garbage. You can do that with
wa_write_clr_set(wal, RT_CTRL, NUMBER_OF_STACKIDS,
NUMBER_OF_STACKIDS_512);
Looks like there might be some whitespace issues here too (spaces
where we should have tabs according to the kernel coding style).
Matt
> }
>
> if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> --
> 2.32.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915/guc: ADL-N should use the same GuC FW as ADL-S
On Tue, Jun 21, 2022 at 04:30:05PM -0700, Daniele Ceraolo Spurio wrote:
> The only difference between the ADL S and P GuC FWs is the HWConfig
> support. ADL-N does not support HWConfig, so we should use the same
> binary as ADL-S, otherwise the GuC might attempt to fetch a config
> table that does not exist. ADL-N is internally identified as an ADL-P,
> so we need to special-case it in the FW selection code.
>
> Fixes: 7e28d0b26759 ("drm/i915/adl-n: Enable ADL-N platform")
> Cc: John Harrison
> Cc: Tejas Upadhyay
> Cc: Anusha Srivatsa
> Cc: Jani Nikula
> Signed-off-by: Daniele Ceraolo Spurio
Would the config table still get used somehow even though we return
false for ADL-N in has_table()?
Even if it couldn't be used, this change makes the behavior more clear
and explicit.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index d2c5c9367cc4..ef2d10184ee2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -162,6 +162,15 @@ __uc_fw_auto_select(struct drm_i915_private *i915,
> struct intel_uc_fw *uc_fw)
> u8 rev = INTEL_REVID(i915);
> int i;
>
> + /*
> + * The only difference between the ADL GuC FWs is the HWConfig support.
> + * ADL-N does not support HWConfig, so we should use the same binary as
> + * ADL-S, otherwise the GuC might attempt to fetch a config table that
> + * does not exist.
> + */
> + if (IS_ADLP_N(i915))
> + p = INTEL_ALDERLAKE_S;
> +
> GEM_BUG_ON(uc_fw->type >= ARRAY_SIZE(blobs_all));
> fw_blobs = blobs_all[uc_fw->type].blobs;
> fw_count = blobs_all[uc_fw->type].count;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915: Call i915_gem_suspend() only after display is turned off
On Fri, Jun 17, 2022 at 12:06:29PM -0700, José Roberto de Souza wrote:
> Gem buffers could still be in use by display after i915_gem_suspend()
> is executed so there is chances that i915_gem_flush_free_objects()
> will be being executed at the same time that
> intel_runtime_pm_driver_release() is executed printing warnings about
> wakerefs will being held.
By the same logic do we need to adjust i915_driver_remove() too?
Matt
>
> So here only calling i915_gem_suspend() and by consequence
> i915_gem_drain_freed_objects() only after display is down making
> sure all buffers are freed.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_driver.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index d26dcca7e654a..4227675dd1cfe 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1067,8 +1067,6 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
> intel_runtime_pm_disable(&i915->runtime_pm);
> intel_power_domains_disable(i915);
>
> - i915_gem_suspend(i915);
> -
> if (HAS_DISPLAY(i915)) {
> drm_kms_helper_poll_disable(&i915->drm);
>
> @@ -1085,6 +1083,8 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
>
> intel_dmc_ucode_suspend(i915);
>
> + i915_gem_suspend(i915);
> +
> /*
>* The only requirement is to reboot with display DC states disabled,
>* for now leaving all display power wells in the INIT power domain
> --
> 2.36.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Re-do the intel-gtt split
snb_pte_encode;
> +
> + ggtt->vm.vma_ops.bind_vma= intel_ggtt_bind_vma;
> + ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma;
> +
> + return ggtt_probe_common(ggtt, size);
> +}
> +
> static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -576,12 +1104,12 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt,
> struct intel_gt *gt)
> ggtt->vm.dma = i915->drm.dev;
> dma_resv_init(&ggtt->vm._resv);
>
> - if (GRAPHICS_VER(i915) <= 5)
> - ret = intel_gt_gmch_gen5_probe(ggtt);
> + if (GRAPHICS_VER(i915) < 6)
> + ret = intel_ggtt_gmch_probe(ggtt);
> else if (GRAPHICS_VER(i915) < 8)
> - ret = intel_gt_gmch_gen6_probe(ggtt);
> + ret = gen6_gmch_probe(ggtt);
> else
> - ret = intel_gt_gmch_gen8_probe(ggtt);
> + ret = gen8_gmch_probe(ggtt);
We could also take the opportunity to reverse the if/else ladder here
and put it in the i915-preferred "newest at top" order.
> if (ret) {
> dma_resv_fini(&ggtt->vm._resv);
> return ret;
> @@ -635,7 +1163,10 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
>
> int i915_ggtt_enable_hw(struct drm_i915_private *i915)
> {
> - return intel_gt_gmch_gen5_enable_hw(i915);
> + if (GRAPHICS_VER(i915) < 6)
> + return intel_ggtt_gmch_enable_hw(i915);
> +
> + return 0;
> }
>
> void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
> new file mode 100644
> index ..1c15825d4bd3
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
> @@ -0,0 +1,132 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include "intel_ggtt_gmch.h"
> +
> +#include
> +#include
> +
> +#include
> +
> +#include "i915_drv.h"
> +#include "i915_utils.h"
> +#include "intel_gtt.h"
> +#include "intel_gt_regs.h"
> +#include "intel_gt.h"
> +
> +static void gen5_ggtt_insert_page(struct i915_address_space *vm,
All the "gen5_" prefixes in this file seem a bit misleading if they wind
up getting used on earlier platforms too; most of the driver uses the
prefix to indicate the first platform/architecture that the function was
used on. Maybe we should also rename these with a "gmch_" prefix as
well to indicate that they're intended for the platforms where the GMCH
was an independent chip and not integrated into the CPU?
Anyway, all of my review comments are just bikeshedding so feel free to
use or ignore them as you see fit. Either way, this series should fix
the issue and restore GGTT handling for non-x86.
Reviewed-by: Matt Roper
> + dma_addr_t addr,
> + u64 offset,
> + enum i915_cache_level cache_level,
> + u32 unused)
> +{
> + unsigned int flags = (cache_level == I915_CACHE_NONE) ?
> + AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
> +
> + intel_gmch_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
> +}
> +
> +static void gen5_ggtt_insert_entries(struct i915_address_space *vm,
> + struct i915_vma_resource *vma_res,
> + enum i915_cache_level cache_level,
> + u32 unused)
> +{
> + unsigned int flags = (cache_level == I915_CACHE_NONE) ?
> + AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
> +
> + intel_gmch_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >>
> PAGE_SHIFT,
> + flags);
> +}
> +
> +static void gen5_ggtt_invalidate(struct i915_ggtt *ggtt)
> +{
> + intel_gmch_gtt_flush();
> +}
> +
> +static void gen5_ggtt_clear_range(struct i915_address_space *vm,
> + u64 start, u64 length)
> +{
> + intel_gmch_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
> +}
> +
> +static void gen5_ggtt_remove(struct i915_address_space *vm)
> +{
> + intel_gmch_remove();
> +}
> +
> +/*
> + * Certain Gen5 chipsets require idling the GPU before unmapping anything
> from
> + * the GTT when VT-d is enabled.
> + */
> +static bool needs_idle_maps(struct drm_i915_private *i915)
> +{
> + /*
> + * Query intel_iommu to see if we need the workaround. Presumably that
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Cleanup interface for MCR operations
On Fri, Jun 17, 2022 at 06:57:20AM -0700, Harish Chegondi wrote:
> On Tue, Jun 14, 2022 at 05:10:19PM -0700, Matt Roper wrote:
> > Let's replace the assortment of intel_gt_* and intel_uncore_* functions
> > that operate on MCR registers with a cleaner set of interfaces:
> >
> > * intel_gt_mcr_read -- unicast read from specific instance
> > * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated
> > instance
> > * intel_gt_mcr_unicast_write -- unicast write to specific instance
> > * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
> >
> > We'll also replace the historic "slice" and "subslice" terminology with
> > "group" and "instance" to match the documentation for more recent
> > platforms; these days MCR steering applies to more types of replication
> > than just slice/subslice.
> >
> > v2:
> > - Reference the new kerneldoc from i915.rst. (Jani)
> > - Tweak the wording of the documentation for a couple functions to
> >clarify the difference between "_fw" and non-"_fw" forms.
> >
> > Signed-off-by: Matt Roper
> > Acked-by: Jani Nikula
> > ---
> > Documentation/gpu/i915.rst | 12 +
> > drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ++-
> > drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 239
> > drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 43 ++--
> > drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 +-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +-
> > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
> > 9 files changed, 200 insertions(+), 145 deletions(-)
> >
> > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> > index 54060cd6c419..4e59db1cfb00 100644
> > --- a/Documentation/gpu/i915.rst
> > +++ b/Documentation/gpu/i915.rst
> > @@ -246,6 +246,18 @@ Display State Buffer
> > .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
> > :internal:
> >
> > +GT Programming
> > +==
> > +
> > +Multicast/Replicated (MCR) Registers
> > +
> > +
> > +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > + :doc: GT Multicast/Replicated (MCR) Register Support
> > +
> > +.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > + :internal:
> > +
> > Memory Management and Command Submission
> >
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > index da30503d3ca2..fa54823d1219 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> > @@ -835,7 +835,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private
> > *i915, u16 type,
> > } else {
> > resource_size_t lmem_range;
> >
> > - lmem_range = intel_gt_read_register(&i915->gt0,
> > XEHPSDV_TILE0_ADDR_RANGE) & 0x;
> > + lmem_range = intel_gt_mcr_read_any(&i915->gt0,
> > XEHPSDV_TILE0_ADDR_RANGE) & 0x;
> > lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
> > lmem_size *= SZ_1G;
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 244af1bdb7db..136cc44c3deb 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1428,14 +1428,6 @@ void intel_engine_cancel_stop_cs(struct
> > intel_engine_cs *engine)
> > ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
> > }
> >
> > -static u32
> > -read_subslice_reg(const struct intel_engine_cs *engine,
> > - int slice, int subslice, i915_reg_t reg)
> > -{
> > - return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
> > - slice, subslice);
> > -}
> > -
> > /* NB: please notice the memset */
> > void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> >struct intel_instdone *instdone)
> > @@ -1469,28 +1461,33 @@ void intel_engine_get_instdone(const struct
> > intel_engine_cs *engine,
> >
Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform
On Thu, Jun 16, 2022 at 05:31:00PM +0530, Anshuman Gupta wrote:
> DG2 NB SKU need to distinguish between MBD and AIC to probe
> the VRAM Self Refresh feature support. Adding those sub platform
> accordingly.
>
> Cc: Matt Roper
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/intel_device_info.c | 21 +
> drivers/gpu/drm/i915/intel_device_info.h | 11 +++
> include/drm/i915_pciids.h| 23 ---
> 4 files changed, 47 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a5bc6a774c5a..f1f8699eedfd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
>
> #define IS_DG2_G10(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
> IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
> #define IS_DG2_G11(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
> IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
> #define IS_DG2_G12(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
> IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
> #define IS_ADLS_RPLS(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index f0bf23726ed8..93da555adc4e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
> INTEL_RPLP_IDS(0),
> };
>
> +static const u16 subplatform_g10_mb_mbd_ids[] = {
> + INTEL_DG2_G10_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g11_mb_mbd_ids[] = {
> + INTEL_DG2_G11_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g12_mb_mbd_ids[] = {
> + INTEL_DG2_G12_NB_MBD_IDS(0),
> +};
We only need a single MBD subplatform, not three new subplatforms.
Unless I'm forgetting something, a single device ID can be assigned two
two independent subplatforms at the same time. So the decision about
whether to set the G10, G11, or G12 bit is one decision. The decision
about whether to set the MBD bit is a completely separate decision that
doesn't care about the G10/G11/G12 stuff.
> +
> static const u16 subplatform_g10_ids[] = {
> INTEL_DG2_G10_IDS(0),
> INTEL_ATS_M150_IDS(0),
> @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct
> drm_i915_private *i915)
> } else if (find_devid(devid, subplatform_rpl_ids,
> ARRAY_SIZE(subplatform_rpl_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_RPL);
> + } else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
> + ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
> + } else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
> + ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
> + } else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
> + ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
Assuming you consolidate MBD back down to just a single extra
subplatform, the lookup and bit setting should happen in a separate 'if'
statement (not an 'else' block).
if (find_devid(devid, subplatform_mbd_ids,
ARRAY_SIZE(subplatform_mbd_ids)))
mask |= BIT(INTEL_SUBPLATFORM_MBD);
Matt
> } else if (find_devid(devid, subplatform_g10_ids,
> ARRAY_SIZE(subplatform_g10_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_G10);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 08341174ee0a..c929e2d7e59c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -97,7 +97,7 @@ enum intel_platform {
> * it is fine for the same bit to be used on multiple parent platforms.
> */
>
> -#define INTEL_SUBPLATFORM_BITS (3)
> +#define INTEL_SUBPLATFORM_BITS (6)
> #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
>
> /* HSW/BDW/SKL/KBL/CFL */
> @@ -111,9 +111,12 @@ enum
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Extract, polish, and document multicast handling
issues/4171 > [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 > [i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278 > [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 > [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 > [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369 > [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 > [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 > [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 > [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893 > [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939 > [i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099 > [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51 > [i915#5161]: https://gitlab.freedesktop.org/drm/intel/issues/5161 > [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 > [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 > [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 > [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 > [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 > [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 > [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 > [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 > [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 > [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 > [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 > [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 > [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591 > [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939 > [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > > > Build changes > - > > * Linux: CI_DRM_11758 -> Patchwork_105134v1 > > CI-20190529: 20190529 > CI_DRM_11758: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_6526: 02888400228efbb29437726aa04114575ea939c3 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_105134v1: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Extract, polish, and document multicast handling
el/issues/5356 > [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594 > [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763 > [i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885 > [i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011 > [i915#6105]: https://gitlab.freedesktop.org/drm/intel/issues/6105 > [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227 > > > Build changes > - > > * Linux: CI_DRM_11758 -> Patchwork_105134v1 > > CI-20190529: 20190529 > CI_DRM_11758: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_6526: 02888400228efbb29437726aa04114575ea939c3 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_105134v1: a2644b16f1f05a1a6eff99d7076bfa0e770bdeb6 @ > git://anongit.freedesktop.org/gfx-ci/linux > > > ### Linux commits > > aa8c692ba084 drm/i915/gt: Cleanup interface for MCR operations > 6be8d7758465 drm/i915/gt: Move multicast register handling to a dedicated file > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105134v1/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915: Implement w/a 22010492432 for adl-s
On Mon, Jun 13, 2022 at 11:14:39PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> adl-s needs the combo PLL DCO fraction w/a as well.
> Get us slightly more accurate clock out of the PLL.
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 64708e874b13..982e5b945680 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2459,7 +2459,7 @@ static void icl_wrpll_params_populate(struct
> skl_wrpll_params *params,
> }
>
> /*
> - * Display WA #22010492432: ehl, tgl, adl-p
> + * Display WA #22010492432: ehl, tgl, adl-s, adl-p
> * Program half of the nominal DCO divider fraction value.
> */
> static bool
> @@ -2467,7 +2467,7 @@ ehl_combo_pll_div_frac_wa_needed(struct
> drm_i915_private *i915)
> {
> return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
>IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
> - IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
> + IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) ||
> IS_ALDERLAKE_P(i915)) &&
>i915->dpll.ref_clks.nssc == 38400;
> }
>
> --
> 2.35.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pvc: Add recommended MMIO setting
m/intel/issues/1982 > [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 > [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 > [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 > [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 > [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 > [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 > [i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852 > [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 > [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 > [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 > [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 > [i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070 > [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 > [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 > [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 > [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 > [i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376 > [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 > [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 > [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 > [i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614 > [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 > [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 > [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701 > [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 > [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825 > [i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828 > [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 > [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 > [i915#3963]: https://gitlab.freedesktop.org/drm/intel/issues/3963 > [i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032 > [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 > [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 > [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 > [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 > [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 > [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 > [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 > [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 > [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#4613]: https://gitlab.freedesktop
[Intel-gfx] [PATCH v2 0/2] i915: Extract, polish, and document multicast handling
Multicast/replicated (MCR) registers on Intel hardware are a purely GT-specific concept. Rather than leaving MCR register handling spread across several places throughout the driver (intel_uncore.c, intel_gt.c, etc.) with confusing combinations of handler functions living in different namespaces, let's consolidate it all into a single place (intel_gt_mcr.c) and provide a more consistent and clearly-documented interface for the rest of the driver to access such registers: * intel_gt_mcr_read -- unicast read from specific instance * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated instance * intel_gt_mcr_unicast_write -- unicast write to specific instance * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances v2: - Reference the new kerneldoc from i915.rst. (Jani) - Tweak the wording of the documentation for a couple functions to clarify the difference between "_fw" and non-"_fw" forms. Matt Roper (2): drm/i915/gt: Move multicast register handling to a dedicated file drm/i915/gt: Cleanup interface for MCR operations Documentation/gpu/i915.rst | 12 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 36 +- drivers/gpu/drm/i915/gt/intel_gt.c | 297 +--- drivers/gpu/drm/i915/gt/intel_gt.h | 15 - drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 497 drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 34 ++ drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 2 - drivers/gpu/drm/i915/intel_uncore.c | 112 - drivers/gpu/drm/i915/intel_uncore.h | 8 - 15 files changed, 577 insertions(+), 460 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.h -- 2.35.3
[Intel-gfx] [PATCH v2 2/2] drm/i915/gt: Cleanup interface for MCR operations
Let's replace the assortment of intel_gt_* and intel_uncore_* functions
that operate on MCR registers with a cleaner set of interfaces:
* intel_gt_mcr_read -- unicast read from specific instance
* intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated
instance
* intel_gt_mcr_unicast_write -- unicast write to specific instance
* intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
We'll also replace the historic "slice" and "subslice" terminology with
"group" and "instance" to match the documentation for more recent
platforms; these days MCR steering applies to more types of replication
than just slice/subslice.
v2:
- Reference the new kerneldoc from i915.rst. (Jani)
- Tweak the wording of the documentation for a couple functions to
clarify the difference between "_fw" and non-"_fw" forms.
Signed-off-by: Matt Roper
Acked-by: Jani Nikula
---
Documentation/gpu/i915.rst | 12 +
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ++-
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 239
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 43 ++--
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
9 files changed, 200 insertions(+), 145 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 54060cd6c419..4e59db1cfb00 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -246,6 +246,18 @@ Display State Buffer
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
:internal:
+GT Programming
+==
+
+Multicast/Replicated (MCR) Registers
+
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+ :doc: GT Multicast/Replicated (MCR) Register Support
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+ :internal:
+
Memory Management and Command Submission
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index da30503d3ca2..fa54823d1219 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -835,7 +835,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915,
u16 type,
} else {
resource_size_t lmem_range;
- lmem_range = intel_gt_read_register(&i915->gt0,
XEHPSDV_TILE0_ADDR_RANGE) & 0x;
+ lmem_range = intel_gt_mcr_read_any(&i915->gt0,
XEHPSDV_TILE0_ADDR_RANGE) & 0x;
lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
lmem_size *= SZ_1G;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 244af1bdb7db..136cc44c3deb 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1428,14 +1428,6 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs
*engine)
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
}
-static u32
-read_subslice_reg(const struct intel_engine_cs *engine,
- int slice, int subslice, i915_reg_t reg)
-{
- return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
- slice, subslice);
-}
-
/* NB: please notice the memset */
void intel_engine_get_instdone(const struct intel_engine_cs *engine,
struct intel_instdone *instdone)
@@ -1469,28 +1461,33 @@ void intel_engine_get_instdone(const struct
intel_engine_cs *engine,
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
for_each_instdone_gslice_dss_xehp(i915, sseu, iter,
slice, subslice) {
instdone->sampler[slice][subslice] =
- read_subslice_reg(engine, slice,
subslice,
-
GEN7_SAMPLER_INSTDONE);
+ intel_gt_mcr_read(engine->gt,
+ GEN7_SAMPLER_INSTDONE,
+ slice, subslice);
instdone->row[slice][subslice] =
- read_subslice_reg(engine, slice,
subslice,
- GEN7_ROW_INSTDONE);
+ intel_gt_mcr_read(engine->gt,
+ GEN7_ROW_INSTDONE,
+ slice, subslice);
[Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Move multicast register handling to a dedicated file
Handling of multicast/replicated registers is spread across intel_gt.c
and intel_uncore.c today. As multicast handling and the related
steering logic gets more complicated with the addition of new platforms
and new rules it makes sense to centralize it all in one place.
For now the existing functions have been moved to the new .c/.h as-is.
Function renames and updates to operate in a more consistent manner will
be done in subsequent patches.
Signed-off-by: Matt Roper
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 297 +
drivers/gpu/drm/i915/gt/intel_gt.h | 15 -
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 448
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 37 ++
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/intel_uncore.c | 112 -
drivers/gpu/drm/i915/intel_uncore.h | 8 -
14 files changed, 495 insertions(+), 433 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d2b18f03a33c..08f5d0d6e83a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -103,6 +103,7 @@ gt-y += \
gt/intel_gt_debugfs.o \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
+ gt/intel_gt_mcr.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 47b5e0e342ab..da30503d3ca2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -13,6 +13,7 @@
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gt/intel_gt.h"
+#include "gt/intel_gt_mcr.h"
#include "gt/intel_region_lmem.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f0acf8518a51..244af1bdb7db 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -21,8 +21,9 @@
#include "intel_engine_user.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
-#include "intel_gt_requests.h"
+#include "intel_gt_mcr.h"
#include "intel_gt_pm.h"
+#include "intel_gt_requests.h"
#include "intel_lrc.h"
#include "intel_lrc_reg.h"
#include "intel_reset.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f33290358c51..be9877c4b496 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -17,6 +17,7 @@
#include "intel_gt_clock_utils.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_gmch.h"
+#include "intel_gt_mcr.h"
#include "intel_gt_pm.h"
#include "intel_gt_regs.h"
#include "intel_gt_requests.h"
@@ -102,107 +103,13 @@ int intel_gt_assign_ggtt(struct intel_gt *gt)
return gt->ggtt ? 0 : -ENOMEM;
}
-static const char * const intel_steering_types[] = {
- "L3BANK",
- "MSLICE",
- "LNCF",
- "INSTANCE 0",
-};
-
-static const struct intel_mmio_range icl_l3bank_steering_table[] = {
- { 0x00B100, 0x00B3FF },
- {},
-};
-
-static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
- { 0x004000, 0x004AFF },
- { 0x00C800, 0x00CFFF },
- { 0x00DD00, 0x00DDFF },
- { 0x00E900, 0x00 }, /* 0xEA00 - OxEFFF is unused */
- {},
-};
-
-static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
- { 0x00B000, 0x00B0FF },
- { 0x00D800, 0x00D8FF },
- {},
-};
-
-static const struct intel_mmio_range dg2_lncf_steering_table[] = {
- { 0x00B000, 0x00B0FF },
- { 0x00D880, 0x00D8FF },
- {},
-};
-
-/*
- * We have several types of MCR registers on PVC where steering to (0,0)
- * will always provide us with a non-terminated value. We'll stick them
- * all in the same table for simplicity.
- */
-static const struct intel_mmio_range pvc_instance0_steering_table[] = {
- { 0x004000, 0x004AFF }, /* HALF-BSLICE */
- { 0x008800, 0x00887F }, /* CC */
- { 0x008A80, 0x008AFF }, /* TILEPSMI */
- {
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT()
Looks like the logs links finally work (there was probably a big backlog to upload them after the gitlab downtime). The module_reload log shows and ext4 filesystem panic (not graphics-related). The syncobj_basic failure is an unexpected incomplete; no graphics errors in the log that I can see, although logs of periodic non-graphics warnings from xhci_hcd. Matt On Tue, Jun 14, 2022 at 01:21:49PM -0700, Vudum, Lakshminarayana wrote: > I am unable to load both the failures? Is there any other way to get these > failures? > > -Original Message- > From: Roper, Matthew D > Sent: Tuesday, June 14, 2022 1:07 PM > To: intel-gfx@lists.freedesktop.org > Cc: Vudum, Lakshminarayana > Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/pvc: Adjust EU per SS > according to HAS_ONE_EU_PER_FUSE_BIT() > > On Tue, Jun 14, 2022 at 07:20:48PM +, Patchwork wrote: > > == Series Details == > > > > Series: drm/i915/pvc: Adjust EU per SS according to > > HAS_ONE_EU_PER_FUSE_BIT() > > URL : https://patchwork.freedesktop.org/series/105010/ > > State : failure > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_11753_full -> Patchwork_105010v1_full > > > > > > Summary > > --- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_105010v1_full absolutely > > need to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_105010v1_full, please notify your bug team to > > allow them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > > > > > Participating hosts (13 -> 13) > > -- > > > > No changes in participating hosts > > > > Possible new issues > > --- > > > > Here are the unknown changes that may have been introduced in > > Patchwork_105010v1_full: > > > > ### IGT changes ### > > > > Possible regressions > > > > * igt@i915_module_load@reload-with-fault-injection: > > - shard-snb: [PASS][1] -> [DMESG-WARN][2] > >[1]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-snb5/igt@i915_module_l...@reload-with-fault-injection.html > >[2]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105010v1/shard-snb5/igt@i915_module_l...@reload-with-fault-injection.html > > > > * igt@syncobj_basic@bad-create-flags: > > - shard-skl: NOTRUN -> [INCOMPLETE][3] > >[3]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105010v1/shard-skl3/igt@syncobj_ba...@bad-create-flags.html > > The failure logs for the two hits above don't seem to have been uploaded > to the server so I can't see exactly what went wrong. However this > patch is modifying xehp_sseu_info_init() which only gets executed on > Xe_HP-based platforms, so it would not change the behavior of SNB or > SKL. > > > Matt > > > > > > > Known issues > > > > > > Here are the changes found in Patchwork_105010v1_full that come from > > known issues: > > > > ### CI changes ### > > > > Issues hit > > > > * boot: > > - shard-apl: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], > > [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], > > [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], > > [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], > > [PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [FAIL][31], > > [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], > > [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], > > [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], > > [PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#4386]) > >[4]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl1/boot.html > >[5]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl1/boot.html > >[6]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl1/boot.html > >[7]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl1/boot.html > >[8]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl2/boot.html > >[9]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl2/boot.html > >[10]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl2/boot.html > >[11]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl2/boot.html > >[12]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl3/boot.html > >[13]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl3/boot.html > >[14]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl3/boot.html > >[15]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl4/boot.html > >[16]: > > https://intel-gfx-ci.01.o
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT()
On Tue, Jun 14, 2022 at 07:20:48PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT() > URL : https://patchwork.freedesktop.org/series/105010/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11753_full -> Patchwork_105010v1_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_105010v1_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_105010v1_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (13 -> 13) > -- > > No changes in participating hosts > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_105010v1_full: > > ### IGT changes ### > > Possible regressions > > * igt@i915_module_load@reload-with-fault-injection: > - shard-snb: [PASS][1] -> [DMESG-WARN][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-snb5/igt@i915_module_l...@reload-with-fault-injection.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105010v1/shard-snb5/igt@i915_module_l...@reload-with-fault-injection.html > > * igt@syncobj_basic@bad-create-flags: > - shard-skl: NOTRUN -> [INCOMPLETE][3] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105010v1/shard-skl3/igt@syncobj_ba...@bad-create-flags.html The failure logs for the two hits above don't seem to have been uploaded to the server so I can't see exactly what went wrong. However this patch is modifying xehp_sseu_info_init() which only gets executed on Xe_HP-based platforms, so it would not change the behavior of SNB or SKL. Matt > > > Known issues > > > Here are the changes found in Patchwork_105010v1_full that come from known > issues: > > ### CI changes ### > > Issues hit > > * boot: > - shard-apl: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], > [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], > [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], > [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], > [PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [FAIL][31], > [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], > [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], > [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], > [PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#4386]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl1/boot.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl1/boot.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl1/boot.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl1/boot.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl2/boot.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl2/boot.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl2/boot.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl2/boot.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl3/boot.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl3/boot.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl3/boot.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl4/boot.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl4/boot.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl4/boot.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl6/boot.html >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl6/boot.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl6/boot.html >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl6/boot.html >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl7/boot.html >[23]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl7/boot.html >[24]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl7/boot.html >[25]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl7/boot.html >[26]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-apl8/boot.html >[27]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11753/shard-ap
[Intel-gfx] [PATCH] drm/i915/pvc: Add recommended MMIO setting
As with past platforms, the bspec's performance tuning guide provides
recommended MMIO settings. Although not technically "workarounds" we
apply these through the workaround framework to ensure that they're
re-applied at the proper times (e.g., on engine resets) and that any
conflicts with real workarounds are flagged.
Bspec: 72161
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 226557018037..07ef111947b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -981,6 +981,11 @@
#define XEHP_L3SCQREG7 _MMIO(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
+#define XEHPC_L3SCRUB _MMIO(0xb18c)
+#define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12)
+#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
+#define SCRUB_RATE_4B_PER_CLK
REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
+
#define L3SQCREG1_CCS0 _MMIO(0xb200)
#define FLUSHALLNONCOH REG_BIT(5)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1e982ac931dc..c4af51144216 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2679,6 +2679,15 @@ general_render_compute_wa_init(struct intel_engine_cs
*engine, struct i915_wa_li
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_PONTEVECCHIO(i915)) {
+ /*
+* The following is not actually a "workaround" but rather
+* a recommended tuning setting documented in the bspec's
+* performance guide section.
+*/
+ wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED |
SCRUB_RATE_4B_PER_CLK);
+ }
+
if (IS_XEHPSDV(i915)) {
/* Wa_1409954639 */
wa_masked_en(wal,
--
2.35.3
[Intel-gfx] [PATCH 2/2] drm/i915/gt: Cleanup interface for MCR operations
Let's replace the assortment of intel_gt_* and intel_uncore_* functions
that operate on MCR registers with a cleaner set of interfaces:
* intel_gt_mcr_read -- unicast read from specific instance
* intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated
instance
* intel_gt_mcr_unicast_write -- unicast write to specific instance
* intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
We'll also replace the historic "slice" and "subslice" terminology with
"group" and "instance" to match the documentation for more recent
platforms; these days MCR steering applies to more types of replication
than just slice/subslice.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ++-
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 225 +++-
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 43 ++--
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
8 files changed, 174 insertions(+), 145 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index da30503d3ca2..fa54823d1219 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -835,7 +835,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915,
u16 type,
} else {
resource_size_t lmem_range;
- lmem_range = intel_gt_read_register(&i915->gt0,
XEHPSDV_TILE0_ADDR_RANGE) & 0x;
+ lmem_range = intel_gt_mcr_read_any(&i915->gt0,
XEHPSDV_TILE0_ADDR_RANGE) & 0x;
lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
lmem_size *= SZ_1G;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 244af1bdb7db..136cc44c3deb 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1428,14 +1428,6 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs
*engine)
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
}
-static u32
-read_subslice_reg(const struct intel_engine_cs *engine,
- int slice, int subslice, i915_reg_t reg)
-{
- return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
- slice, subslice);
-}
-
/* NB: please notice the memset */
void intel_engine_get_instdone(const struct intel_engine_cs *engine,
struct intel_instdone *instdone)
@@ -1469,28 +1461,33 @@ void intel_engine_get_instdone(const struct
intel_engine_cs *engine,
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
for_each_instdone_gslice_dss_xehp(i915, sseu, iter,
slice, subslice) {
instdone->sampler[slice][subslice] =
- read_subslice_reg(engine, slice,
subslice,
-
GEN7_SAMPLER_INSTDONE);
+ intel_gt_mcr_read(engine->gt,
+ GEN7_SAMPLER_INSTDONE,
+ slice, subslice);
instdone->row[slice][subslice] =
- read_subslice_reg(engine, slice,
subslice,
- GEN7_ROW_INSTDONE);
+ intel_gt_mcr_read(engine->gt,
+ GEN7_ROW_INSTDONE,
+ slice, subslice);
}
} else {
for_each_instdone_slice_subslice(i915, sseu, slice,
subslice) {
instdone->sampler[slice][subslice] =
- read_subslice_reg(engine, slice,
subslice,
-
GEN7_SAMPLER_INSTDONE);
+ intel_gt_mcr_read(engine->gt,
+ GEN7_SAMPLER_INSTDONE,
+ slice, subslice);
instdone->row[slice][subslice] =
- read_subslice_reg(engine, slice,
subslice,
- GEN7_ROW_INSTDONE);
+ intel_gt_mcr_read(engine->gt,
+
[Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling
Multicast/replicated (MCR) registers on Intel hardware are a purely GT-specific concept. Rather than leaving MCR register handling spread across several places throughout the driver (intel_uncore.c, intel_gt.c, etc.) with confusing combinations of handler functions living in different namespaces, let's consolidate it all into a single place (intel_gt_mcr.c) and provide a more consistent and clearly-documented interface for the rest of the driver to access such registers: * intel_gt_mcr_read -- unicast read from specific instance * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated instance * intel_gt_mcr_unicast_write -- unicast write to specific instance * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances Matt Roper (2): drm/i915/gt: Move multicast register handling to a dedicated file drm/i915/gt: Cleanup interface for MCR operations drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 36 +- drivers/gpu/drm/i915/gt/intel_gt.c | 297 +--- drivers/gpu/drm/i915/gt/intel_gt.h | 15 - drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 483 drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 34 ++ drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 2 - drivers/gpu/drm/i915/intel_uncore.c | 112 - drivers/gpu/drm/i915/intel_uncore.h | 8 - 14 files changed, 551 insertions(+), 460 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.h -- 2.35.3
[Intel-gfx] [PATCH 1/2] drm/i915/gt: Move multicast register handling to a dedicated file
Handling of multicast/replicated registers is spread across intel_gt.c
and intel_uncore.c today. As multicast handling and the related
steering logic gets more complicated with the addition of new platforms
and new rules it makes sense to centralize it all in one place.
For now the existing functions have been moved to the new .c/.h as-is.
Function renames and updates to operate in a more consistent manner will
be done in subsequent patches.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 297 +
drivers/gpu/drm/i915/gt/intel_gt.h | 15 -
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 448
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 37 ++
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/intel_uncore.c | 112 -
drivers/gpu/drm/i915/intel_uncore.h | 8 -
14 files changed, 495 insertions(+), 433 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d2b18f03a33c..08f5d0d6e83a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -103,6 +103,7 @@ gt-y += \
gt/intel_gt_debugfs.o \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
+ gt/intel_gt_mcr.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 47b5e0e342ab..da30503d3ca2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -13,6 +13,7 @@
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gt/intel_gt.h"
+#include "gt/intel_gt_mcr.h"
#include "gt/intel_region_lmem.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f0acf8518a51..244af1bdb7db 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -21,8 +21,9 @@
#include "intel_engine_user.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
-#include "intel_gt_requests.h"
+#include "intel_gt_mcr.h"
#include "intel_gt_pm.h"
+#include "intel_gt_requests.h"
#include "intel_lrc.h"
#include "intel_lrc_reg.h"
#include "intel_reset.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f33290358c51..be9877c4b496 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -17,6 +17,7 @@
#include "intel_gt_clock_utils.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_gmch.h"
+#include "intel_gt_mcr.h"
#include "intel_gt_pm.h"
#include "intel_gt_regs.h"
#include "intel_gt_requests.h"
@@ -102,107 +103,13 @@ int intel_gt_assign_ggtt(struct intel_gt *gt)
return gt->ggtt ? 0 : -ENOMEM;
}
-static const char * const intel_steering_types[] = {
- "L3BANK",
- "MSLICE",
- "LNCF",
- "INSTANCE 0",
-};
-
-static const struct intel_mmio_range icl_l3bank_steering_table[] = {
- { 0x00B100, 0x00B3FF },
- {},
-};
-
-static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
- { 0x004000, 0x004AFF },
- { 0x00C800, 0x00CFFF },
- { 0x00DD00, 0x00DDFF },
- { 0x00E900, 0x00 }, /* 0xEA00 - OxEFFF is unused */
- {},
-};
-
-static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
- { 0x00B000, 0x00B0FF },
- { 0x00D800, 0x00D8FF },
- {},
-};
-
-static const struct intel_mmio_range dg2_lncf_steering_table[] = {
- { 0x00B000, 0x00B0FF },
- { 0x00D880, 0x00D8FF },
- {},
-};
-
-/*
- * We have several types of MCR registers on PVC where steering to (0,0)
- * will always provide us with a non-terminated value. We'll stick them
- * all in the same table for simplicity.
- */
-static const struct intel_mmio_range pvc_instance0_steering_table[] = {
- { 0x004000, 0x004AFF }, /* HALF-BSLICE */
- { 0x008800, 0x00887F }, /* CC */
- { 0x008A80, 0x008AFF }, /* TILEPSMI */
- { 0x00B000,
[Intel-gfx] [PATCH] drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT()
If we're treating each bit in the EU fuse register as a single EU
instead of a pair of EUs, then that also cuts the number of potential
EUs per subslice in half.
Fixes: 5ac342ef84d7 ("drm/i915/pvc: Add SSEU changes")
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7ef75f0d9c9e..c6d3050604c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -229,7 +229,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
*/
intel_sseu_set_info(sseu, 1,
32 * max(num_geometry_regs, num_compute_regs),
- 16);
+ HAS_ONE_EU_PER_FUSE_BIT(gt->i915) ? 8 : 16);
sseu->has_xehp_dss = 1;
xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,
--
2.35.3
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pvc: Add register steering (rev2)
On Thu, Jun 09, 2022 at 02:17:54PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/pvc: Add register steering (rev2) > URL : https://patchwork.freedesktop.org/series/104691/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11740_full -> Patchwork_104691v2_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_104691v2_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_104691v2_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (13 -> 13) > -- > > No changes in participating hosts > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_104691v2_full: > > ### IGT changes ### > > Possible regressions > > * igt@gem_exec_capture@pi@vecs0: > - shard-skl: NOTRUN -> [INCOMPLETE][1] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v2/shard-skl4/igt@gem_exec_capture@p...@vecs0.html Unexpected incomplete. Not related to this patch. Matt > > > Known issues > > > Here are the changes found in Patchwork_104691v2_full that come from known > issues: > > ### CI changes ### > > Possible fixes > > * boot: > - shard-glk: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], > [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], > [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], > [FAIL][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], > [PASS][24], [PASS][25], [PASS][26]) ([i915#4392]) -> ([PASS][27], [PASS][28], > [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], > [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], > [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], > [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk9/boot.html >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk8/boot.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk8/boot.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk8/boot.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk7/boot.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk7/boot.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk6/boot.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk6/boot.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk5/boot.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk5/boot.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk5/boot.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk4/boot.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk4/boot.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk4/boot.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk3/boot.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk3/boot.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk3/boot.html >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk2/boot.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk2/boot.html >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk2/boot.html >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk1/boot.html >[23]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk1/boot.html >[24]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk1/boot.html >[25]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk9/boot.html >[26]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11740/shard-glk9/boot.html >[27]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v2/shard-glk2/boot.html >[28]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v2/shard-glk3/boot.html >[29]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v2/shard-glk9/boot.html >[30]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v2/shard-glk9/boot.html >[31]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v2/shard-glk8/boot.html >[32]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v2/sha
[Intel-gfx] [CI] drm/i915/pvc: Add register steering
Ponte Vecchio no longer has MSLICE or LNCF steering, but the bspec does
document several new types of multicast register ranges. Fortunately,
most of the different MCR types all provide valid values at instance
(0,0) so there's no need to read fuse registers and calculate a
non-terminated instance. We'll lump all of those range types (BSLICE,
HALFBSLICE, TILEPSMI, CC, and L3BANK) into a single category called
"INSTANCE0" to keep things simple. We'll also perform explicit steering
for each of these multicast register types, even if the implicit
steering setup for COMPUTE/DSS ranges would have worked too; this is
based on guidance from our hardware architects who suggested that we
move away from implicit steering and start explicitly steer all MCR
register accesses on modern platforms (we'll work on transitioning
COMPUTE/DSS to explicit steering in the future).
Note that there's one additional MCR range type defined in the bspec
(SQIDI) that we don't handle here. Those ranges use a different
steering control register that we never touch; since instance 0 is also
always a valid setting there, we can just ignore those ranges.
Finally, we'll rename the HAS_MSLICES() macro to HAS_MSLICE_STEERING().
PVC hardware still has units referred to as mslices, but there's no
register steering based on mslice for this platform.
v2:
- Rebase on other recent changes
- Swap two table rows to keep table sorted & easy to read. (Harish)
Bspec: 67609
Signed-off-by: Matt Roper
Reviewed-by: Harish Chegondi
---
drivers/gpu/drm/i915/gt/intel_gt.c | 50 ++---
drivers/gpu/drm/i915/gt/intel_gt_types.h| 7 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 16 +++
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/intel_device_info.h| 2 +-
6 files changed, 71 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index ddfb98f70489..f33290358c51 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -106,6 +106,7 @@ static const char * const intel_steering_types[] = {
"L3BANK",
"MSLICE",
"LNCF",
+ "INSTANCE 0",
};
static const struct intel_mmio_range icl_l3bank_steering_table[] = {
@@ -133,6 +134,27 @@ static const struct intel_mmio_range
dg2_lncf_steering_table[] = {
{},
};
+/*
+ * We have several types of MCR registers on PVC where steering to (0,0)
+ * will always provide us with a non-terminated value. We'll stick them
+ * all in the same table for simplicity.
+ */
+static const struct intel_mmio_range pvc_instance0_steering_table[] = {
+ { 0x004000, 0x004AFF }, /* HALF-BSLICE */
+ { 0x008800, 0x00887F }, /* CC */
+ { 0x008A80, 0x008AFF }, /* TILEPSMI */
+ { 0x00B000, 0x00B0FF }, /* HALF-BSLICE */
+ { 0x00B100, 0x00B3FF }, /* L3BANK */
+ { 0x00C800, 0x00CFFF }, /* HALF-BSLICE */
+ { 0x00D800, 0x00D8FF }, /* HALF-BSLICE */
+ { 0x00DD00, 0x00DDFF }, /* BSLICE */
+ { 0x00E900, 0x00E9FF }, /* HALF-BSLICE */
+ { 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */
+ { 0x00F000, 0x00 }, /* HALF-BSLICE */
+ { 0x024180, 0x0241FF }, /* HALF-BSLICE */
+ {},
+};
+
int intel_gt_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -146,7 +168,7 @@ int intel_gt_init_mmio(struct intel_gt *gt)
* An mslice is unavailable only if both the meml3 for the slice is
* disabled *and* all of the DSS in the slice (quadrant) are disabled.
*/
- if (HAS_MSLICES(i915)) {
+ if (HAS_MSLICE_STEERING(i915)) {
gt->info.mslice_mask =
intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
GEN_DSS_PER_MSLICE);
@@ -158,7 +180,9 @@ int intel_gt_init_mmio(struct intel_gt *gt)
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
- if (IS_DG2(i915)) {
+ if (IS_PONTEVECCHIO(i915)) {
+ gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
+ } else if (IS_DG2(i915)) {
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
gt->steering_table[LNCF] = dg2_lncf_steering_table;
} else if (IS_XEHPSDV(i915)) {
@@ -172,7 +196,11 @@ int intel_gt_init_mmio(struct intel_gt *gt)
GEN10_L3BANK_MASK;
if (!gt->info.l3bank_mask) /* should be impossible! */
drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
- } else if (HAS_MSLICES(i915)) {
+
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: More PVC+DG2 workarounds
5#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 > [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 > [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 > [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 > [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 > [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 > [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 > [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 > [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 > [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 > [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 > [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 > [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 > [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 > [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 > [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 > [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 > [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 > [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 > [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 > [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 > [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 > [i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464 > [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536 > [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 > [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 > [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 > [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 > [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 > [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 > [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701 > [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 > [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 > [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778 > [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826 > [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 > [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 > [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 > [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 > [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 > [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 > [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 > [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 > [i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278 > [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43 > [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 > [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369 > [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 > [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 > [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 > [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 > [i915#4793]: https://gitlab.freedesktop.org/drm/intel/issues/4793 > [i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807 > [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 > [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 > [i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842 > [i915#4852]:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/xehp: Correct steering initialization
On Wed, Jun 08, 2022 at 08:23:34AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/xehp: Correct steering initialization > URL : https://patchwork.freedesktop.org/series/104842/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11732_full -> Patchwork_104842v1_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_104842v1_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_104842v1_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (10 -> 13) > -- > > Additional (3): shard-rkl shard-dg1 shard-tglu > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_104842v1_full: > > ### IGT changes ### > > Possible regressions > > * igt@i915_module_load@reload-with-fault-injection: > - shard-snb: [PASS][1] -> [DMESG-WARN][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-snb6/igt@i915_module_l...@reload-with-fault-injection.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104842v1/shard-snb2/igt@i915_module_l...@reload-with-fault-injection.html Filesystem panic; not related to i915. > > * igt@i915_pm_sseu@full-enable: > - shard-skl: NOTRUN -> [FAIL][3] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104842v1/shard-skl7/igt@i915_pm_s...@full-enable.html This Xe_HP change wouldn't have affected the behavior of SKL. I don't see a preexisting bug that matches this though. > > * igt@kms_flip@flip-vs-panning-vs-hang: > - shard-kbl: NOTRUN -> [INCOMPLETE][4] >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104842v1/shard-kbl1/igt@kms_f...@flip-vs-panning-vs-hang.html <2>[ 427.216493] softdog: Initiating panic <0>[ 427.216501] Kernel panic - not syncing: Software Watchdog Timer expired It doesn't seem like anything was actually hung before the watchdog fired though. Not sure what the cause is, but not related to this patch. Patch applied to drm-intel-gt-next. Thanks Bala for the review. Matt > > > Known issues > > > Here are the changes found in Patchwork_104842v1_full that come from known > issues: > > ### CI changes ### > > Issues hit > > * boot: > - shard-glk: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], > [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], > [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], > [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], > [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], > [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], > [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], > [PASS][45], [PASS][46], [PASS][47], [PASS][48], [FAIL][49], [PASS][50], > [PASS][51], [PASS][52], [PASS][53]) ([i915#4392]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk7/boot.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk7/boot.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk6/boot.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk6/boot.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk5/boot.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk5/boot.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk4/boot.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk4/boot.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk4/boot.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk4/boot.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk3/boot.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk3/boot.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk8/boot.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk3/boot.html >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk2/boot.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk2/boot.html >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk2/boot.html >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk8/boot.html >[23]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk9/boot.html >[24]: > https://intel-gf
