Re: [Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed

[Oscar Mateo Lozano]

On 6/15/2018 1:59 AM, Chris Wilson wrote:

For each platform, we have a few registers that rewritten with multiple
values -- they are not part of a sequence, just different parts of a
masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact.

While adjusting the construction of the wa table, make it non fatal so
that the driver still loads but keeping the warning and extra details
for inspection.


A while ago I sent a patch 
(https://patchwork.freedesktop.org/patch/205035/) that uses simple MMIO 
writes to apply ctx workarounds. This is possible since we now have 
proper golden contexts, and avoids the need for these patches.
It also has the advantage that an improperly classified WA doesn't get 
lost (we still need the classification if we want to properly validate 
the WAs, but that's a different story).

Are we sure we prefer to do this instead?



Signed-off-by: Chris Wilson 
Cc: Oscar Mateo 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
---
  drivers/gpu/drm/i915/i915_debugfs.c  | 25 ++
  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
  drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
  3 files changed, 52 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index c600279d3db5..f78895ffab9b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3378,28 +3378,13 @@ static int i915_shared_dplls_info(struct seq_file *m, 
void *unused)
  
  static int i915_wa_registers(struct seq_file *m, void *unused)

  {
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct i915_workarounds *workarounds = _priv->workarounds;
+   struct i915_workarounds *wa = _to_i915(m->private)->workarounds;
int i;
  
-	intel_runtime_pm_get(dev_priv);

-
-   seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
-   for (i = 0; i < workarounds->count; ++i) {
-   i915_reg_t addr;
-   u32 mask, value, read;
-   bool ok;
-
-   addr = workarounds->reg[i].addr;
-   mask = workarounds->reg[i].mask;
-   value = workarounds->reg[i].value;
-   read = I915_READ(addr);
-   ok = (value & mask) == (read & mask);
-   seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: 
%s\n",
-  i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : 
"FAIL");
-   }
-
-   intel_runtime_pm_put(dev_priv);
+   seq_printf(m, "Workarounds applied: %d\n", wa->count);
+   for (i = 0; i < wa->count; ++i)
+   seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
+  wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c12de678e32..91c389622217 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1308,7 +1308,7 @@ struct i915_frontbuffer_tracking {
  };
  
  struct i915_wa_reg {

-   i915_reg_t addr;
+   u32 addr;
u32 value;
/* bitmask representing WA bits */
u32 mask;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..f8bb32e974f6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,29 +48,58 @@
   * - Public functions to init or apply the given workaround type.
   */
  
-static int wa_add(struct drm_i915_private *dev_priv,

- i915_reg_t addr,
- const u32 mask, const u32 val)
+static void wa_add(struct drm_i915_private *i915,
+  i915_reg_t reg, const u32 mask, const u32 val)
  {
-   const unsigned int idx = dev_priv->workarounds.count;
+   struct i915_workarounds *wa = >workarounds;
+   unsigned int start = 0, end = wa->count;
+   unsigned int addr = i915_mmio_reg_offset(reg);
+   struct i915_wa_reg *r;
+
+   while (start < end) {
+   unsigned int mid = start + (end - start) / 2;
+
+   if (wa->reg[mid].addr < addr) {
+   start = mid + 1;
+   } else if (wa->reg[mid].addr > addr) {
+   end = mid;
+   } else {
+   r = >reg[mid];
+
+   if ((mask & ~r->mask) == 0) {
+   DRM_ERROR("Discarding overwritten w/a for reg %04x 
(mask: %08x, value: %08x)\n",
+ addr, r->mask, r->value);
+
+   r->value &= ~mask;
+   }
+
+   r->value |= val;
+   r->mask  |= mask;
+   return;
+   }
+   }
  
-	if (WARN_ON(idx >= I915_MAX_WA_REGS))

-  

Re: [Intel-gfx] [RFC PATCH] drm/i915/guc: New interface files for GuC starting in Gen11

[Oscar Mateo Lozano]

On 5/29/2018 7:59 AM, Michal Wajdeczko wrote:

Hi,

On Fri, 25 May 2018 23:59:35 +0200, Oscar Mateo 
wrote:


GuC interface has been redesigned (or cleaned up, rather) starting
with Gen11, as a stepping stone towards a new branching strategy
that helps maintain backwards compatibility with previous Gens, as
well as sideward compatibility with other OSes.

The interface is split in two header files: one for the KMD and one
for clients of the GuC (which, in our case, happens to be the KMD
as well). SLPC interface files will come at a later date.

Could we get eyes on the new interface header files, to make sure the
GuC team is moving in the right direction?

Signed-off-by: Oscar Mateo 
Cc: Joonas Lahtinen 
Cc: Kevin Rogovin 
Cc: John A Spotswood 
Cc: Anusha Srivatsa 
Cc: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Cc: Michel Thierry 
Cc: Chris Wilson 
Cc: Michał Winiarski 
Cc: Tomasz Lis 
Cc: Jon Ewins 
Cc: Sujaritha Sundaresan 
Cc: Jalpa Patel 
Cc: Jackie Li 
---
 drivers/gpu/drm/i915/intel_guc_client_interface.h | 255 +++
 drivers/gpu/drm/i915/intel_guc_kmd_interface.h    | 847 
++

 2 files changed, 1102 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_client_interface.h
 create mode 100644 drivers/gpu/drm/i915/intel_guc_kmd_interface.h


can we name these files as:

drivers/gpu/drm/i915/intel_guc_interface.h
drivers/gpu/drm/i915/intel_guc_interface_client.h
or
drivers/gpu/drm/i915/intel_guc_defs.h
drivers/gpu/drm/i915/intel_guc_defs_client.h
or
drivers/gpu/drm/i915/guc/guc.h
drivers/gpu/drm/i915/guc/guc_client.h


I'm fine with any of these names.





diff --git a/drivers/gpu/drm/i915/intel_guc_client_interface.h 
b/drivers/gpu/drm/i915/intel_guc_client_interface.h

new file mode 100644
index 000..1ef91a7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_client_interface.h
@@ -0,0 +1,255 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#ifndef _INTEL_GUC_CLIENT_INTERFACE_H_
+#define _INTEL_GUC_CLIENT_INTERFACE_H_
+


need to include types.h for u32


Will do.




+#pragma pack(1)
+
+/* 

+ ** Engines 
**
+ 
*/


no fancy markups, please



Ok.


+
+#define GUC_MAX_ENGINE_INSTANCE_PER_CLASS    4
+#define GUC_MAX_SCHEDULABLE_ENGINE_CLASS    5
+#define GUC_MAX_ENGINE_CLASS_COUNT    6
+#define GUC_ENGINE_INVALID    6


hmm, why not 7 or 127 ?
maybe if we need value for INVALID we should use 0 or -1 (~0)


I'll pass this comment to the GuC team.




+
+/* Engine Class that uKernel can schedule on. This is just a SW 
enumeration.

+ * HW configuration will depend on the Platform and SKU
+ */
+enum uk_engine_class {


why there is new prefix "uk" ?


uk stands for uKernel. In this case, I'm guessing it is used to 
differentiate between the engine class defined by hardware vs. the one 
defined by the uKernel.



+    UK_RENDER_ENGINE_CLASS = 0,
+    UK_VDECENC_ENGINE_CLASS = 1,
+    UK_VE_ENGINE_CLASS = 2,
+    UK_BLT_COPY_ENGINE_CLASS = 3,
+    UK_RESERVED_ENGINE_CLASS = 4,
+    UK_OTHER_ENGINE_CLASS = 5,


either use valid names or drop RESERVED/OTHER as values
  from 0 to GUC_MAX_ENGINE_CLASS_COUNT are 'reserved' by
definition unless explicitly defined ;)


I'll drop them.




+};


as we don't use enum in binary struct definitions, then maybe we
should define all engine classes with #define as:

#define ENGINE_CLASS_INVALID  0
#define ENGINE_CLASS_ALL  0
#define ENGINE_CLASS_RENDER   1
#define ENGINE_CLASS_VDECENC  2
...
#define ENGINE_CLASS_MAX  7



I can pass this comment to the GuC team. Or we can use defines for the 
Linux header files, but then we might start deviating again from a 
common interface naming.



what if future HW will support more than 7 engine classes
or they will be so different that they deserve separate id?
why


I imagine that's what the reserved is for. I cannot think of many more 
engine classes, but I probably lack imagination.





+
+/* Engine Instance that uKernel can schedule on */
+enum uk_engine_instance {
+    UK_ENGINE_INSTANCE_0 = 0,
+    UK_ENGINE_INSTANCE_1 = 1,
+    UK_ENGINE_INSTANCE_2 = 2,
+    UK_ENGINE_INSTANCE_3 = 3,
+    UK_INVALID_ENGINE_INSTANCE = GUC_MAX_ENGINE_INSTANCE_PER_CLASS,
+    UK_ENGINE_ALL_INSTANCES = UK_INVALID_ENGINE_INSTANCE
+};


I'm not sure why we would need this enum as we already have
GUC_MAX_ENGINE_INSTANCE_PER_CLASS and can easily identify
instance as [0 ... GUC_MAX_ENGINE_INSTANCE_PER_CLASS), or
maybe more intuitive would be use normal indexing and use 0
to indicate INVALID/AUTO/ALL instance ?

#define ENGINE_INSTANCE_INVALID  0
#define ENGINE_INSTANCE_ALL  0
#define ENGINE_INSTANCE_MAX  4



I can pass this comment along.


+
+/* Target Engine 

Re: [Intel-gfx] [PATCH v4 1/3] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo Lozano]

On 5/18/2018 3:39 PM, Yunwei Zhang wrote:

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
  - use fls() instead of find_last_bit() (Chris)
  - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
  - rebase on latest tip
v5:
  - Added references (Mika)
  - Change the ordered of passing arguments and etc. (Ursulin)
v7:
  - Moved WA explanation Comments(Oscar)
  - Rebased.
v8:
  - Renamed sanitize_mcr to calculate_s_ss_select. (Oscar)
  - calculate s/ss selector instead of whole mcr. (Oscar)
v9:
  - Updated function name (Oscar)
  - Remove redundant variables (Oscar)
v10:
  - Separate pre-GEN10 and GEN11 mask. (Oscar)

Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Signed-off-by: Yunwei Zhang 


Reviewed-by: Oscar Mateo 


---
  drivers/gpu/drm/i915/i915_drv.h  |  2 ++
  drivers/gpu/drm/i915/intel_engine_cs.c   | 30 +-
  drivers/gpu/drm/i915/intel_workarounds.c | 27 +++
  3 files changed, 54 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e33c380..3b8a047 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2744,6 +2744,8 @@ int vlv_force_gfx_clock(struct drm_i915_private 
*dev_priv, bool on);
  int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
  int intel_engines_init(struct drm_i915_private *dev_priv);
  
+u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);

+
  /* intel_hotplug.c */
  void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
   u32 pin_mask, u32 long_mask);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 26f9f8a..832419e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -819,12 +819,29 @@ const char *i915_cache_level_str(struct drm_i915_private 
*i915, int type)
}
  }
  
+u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)

+{
+   const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+   u32 mcr_s_ss_select;
+   u32 slice = fls(sseu->slice_mask);
+   u32 subslice = fls(sseu->subslice_mask[slice]);
+
+   if (INTEL_GEN(dev_priv) == 10)
+   mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
+ GEN8_MCR_SUBSLICE(subslice);
+   else
+   mcr_s_ss_select = 0;
+
+   return mcr_s_ss_select;
+}
+
  static inline uint32_t
  read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
  int subslice, i915_reg_t reg)
  {
uint32_t mcr_slice_subslice_mask;
uint32_t mcr_slice_subslice_select;
+   uint32_t default_mcr_s_ss_select;
uint32_t mcr;
uint32_t ret;
enum forcewake_domains fw_domains;
@@ -841,6 +858,8 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int 
slice,
GEN8_MCR_SUBSLICE(subslice);
}
  
+	default_mcr_s_ss_select = intel_calculate_mcr_s_ss_select(dev_priv);

+
fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
FW_REG_READ);
fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
@@ -851,11 +870,10 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int 
slice,
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
  
  	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);

-   /*
-* The HW expects the slice and sublice selectors to be reset to 0
-* after reading out the registers.
-*/
-   WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+
+   WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
+default_mcr_s_ss_select);
+
mcr &= ~mcr_slice_subslice_mask;
mcr |= mcr_slice_subslice_select;

Re: [Intel-gfx] [PATCH v3 3/3] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Oscar Mateo Lozano]

On 5/18/2018 3:41 PM, Yunwei Zhang wrote:

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

References: HSDES#1405586840

v2:
  - use fls instead of find_last_bit (Chris)
  - use is_power_of_2() instead of counting bit set (Chris)
v3:
  - rebase on latest tip
v5:
  - Added references (Mika)
  - Move local variable into scope where they are used (Ursulin)
  - use a new local variable to reduce long line of code (Ursulin)
v6:
  - Some coding style and use more local variables for clearer
logic (Ursulin)

Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Signed-off-by: Yunwei Zhang 


Reviewed-by: Oscar Mateo 


---
  drivers/gpu/drm/i915/i915_reg.h  |  4 
  drivers/gpu/drm/i915/intel_workarounds.c | 35 
  2 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb..9137b1c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2709,6 +2709,10 @@ enum i915_power_well_id {
  #define   GEN10_F2_SS_DIS_SHIFT   18
  #define   GEN10_F2_SS_DIS_MASK(0xf << GEN10_F2_SS_DIS_SHIFT)
  
+#define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)

+#define GEN10_L3BANK_PAIR_COUNT 4
+#define GEN10_L3BANK_MASK   0x0F
+
  #define GEN8_EU_DISABLE0  _MMIO(0x9134)
  #define   GEN8_EU_DIS0_S0_MASK0xff
  #define   GEN8_EU_DIS0_S1_SHIFT   24
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index 2deec58..cea5710 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -674,9 +674,44 @@ static void cfl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
  
  static void wa_init_mcr(struct drm_i915_private *dev_priv)

  {
+   const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
u32 mcr;
u32 mcr_slice_subslice_mask;
  
+	/*

+* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
+* L3Banks could be fused off in single slice scenario. If that is
+* the case, we might need to program MCR select to a valid L3Bank
+* by default, to make sure we correctly read certain registers
+* later on (in the range 0xB100 - 0xB3FF).
+* This might be incompatible with
+* WaProgramMgsrForCorrectSliceSpecificMmioReads.
+* Fortunately, this should not happen in production hardware, so
+* we only assert that this is the case (instead of implementing
+* something more complex that requires checking the range of every
+* MMIO read).
+*/
+   if (INTEL_GEN(dev_priv) >= 10 &&
+   is_power_of_2(sseu->slice_mask)) {
+   /*
+* read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+* enabled subslice, no need to redirect MCR packet
+*/
+   u32 slice = fls(sseu->slice_mask);
+   u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+   u8 ss_mask = sseu->subslice_mask[slice];
+
+   u8 enabled_mask = (ss_mask | ss_mask >>
+  GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
+   u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
+
+   /*
+* Production silicon should have matched L3Bank and
+* subslice enabled
+*/
+   WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+   }
+
mcr = I915_READ(GEN8_MCR_SELECTOR);
  
  	if (INTEL_GEN(dev_priv) >= 11)


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Re: [Intel-gfx] [PATCH v4 2/3] drm/i915/icl: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo Lozano]

On 5/18/2018 3:40 PM, Yunwei Zhang wrote:

WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.

References: HSD#1405586840, BSID#0575

v2:
  - GEN11 mask is different from its predecessors. (Oscar)
  - Better separate GEN10 and GEN11. (Oscar)

Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Signed-off-by: Yunwei Zhang 


Reviewed-by: Oscar Mateo 


---
  drivers/gpu/drm/i915/intel_engine_cs.c   |  3 +++
  drivers/gpu/drm/i915/intel_workarounds.c | 12 +---
  2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 832419e..9b13ee3 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -829,6 +829,9 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private 
*dev_priv)
if (INTEL_GEN(dev_priv) == 10)
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
  GEN8_MCR_SUBSLICE(subslice);
+   else if (INTEL_GEN(dev_priv) >= 11)
+   mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
+ GEN11_MCR_SUBSLICE(subslice);
else
mcr_s_ss_select = 0;
  
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c

index 720d863..2deec58 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -679,10 +679,14 @@ static void wa_init_mcr(struct drm_i915_private *dev_priv)
  
  	mcr = I915_READ(GEN8_MCR_SELECTOR);
  
-	mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |

- GEN8_MCR_SUBSLICE_MASK;
+   if (INTEL_GEN(dev_priv) >= 11)
+   mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+ GEN11_MCR_SUBSLICE_MASK;
+   else
+   mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+ GEN8_MCR_SUBSLICE_MASK;
/*
-* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
 * Before any MMIO read into slice/subslice specific registers, MCR
 * packet control register needs to be programmed to point to any
 * enabled s/ss pair. Otherwise, incorrect values will be returned.
@@ -719,6 +723,8 @@ static void cnl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
  
  static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)

  {
+   wa_init_mcr(dev_priv);
+
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));


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Re: [Intel-gfx] [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers

[Oscar Mateo Lozano]

On 5/17/2018 3:59 PM, Paulo Zanoni wrote:

Em Qui, 2018-05-17 às 10:04 -0700, Oscar Mateo Lozano escreveu:

On 5/17/2018 9:55 AM, Michel Thierry wrote:

On 5/16/2018 4:39 PM, Paulo Zanoni wrote:

Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:

Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in
the
Gen11 interrupt repartitioning scheme.

Note that the equivalent to the PM ISR & IIR cannot be read
without
affecting the current state of the system, so I've opted for
leaving
them out. See gen11_service_one_iir() for more info.

I can't find this function. Did you mean something else?


s/gen11_service_one_iir/gen11_reset_one_iir/


Yup, that's right. Thanks Michel, I didn't realize this had been
renamed
in upstream.

I fixed this in the commit message, did a small bikeshed on the single-
if-with-braces and merged the patch.


Thanks Paulo.


I downloaded your patch through patchwork and it changed your name
(patch author) from "Oscar Mateo" to "Oscar Mateo Lozano" (then dim
push-queued complained the patch was missing author Signed-off-by due
to the name difference, which made me notice it). You may want to
either fix your name in patchwork so it appears as "Oscar Mateo" or
change your git configuration to add the missing name.


Sorry about that, it seems I registered with my two surnames instead of 
the first one that I usually employ.


Is it possible to change the name in patchwork? I don't see a way. Do 
you know if anybody has direct access to the database?



Thanks for the patch and reviews.

Thanks,
Paulo




v2: else if !!! (Paulo)
v3: another else if (Vinay)
v4:
- Rebased
- Renamed patch
- Improved the ordering of GENs
- Improved the printing of per-GEN info
v5: Avoid maybe-unitialized & add comment explaining the lack
  of PM ISR & IIR

Suggested-by: Paulo Zanoni <paulo.r.zan...@intel.com>
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaum...@intel.com>
---
   drivers/gpu/drm/i915/i915_debugfs.c   | 34
-
-
   drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++-
   drivers/gpu/drm/i915/i915_gpu_error.h |  2 +-
   3 files changed, 35 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d663a9e0..d992dd2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct
seq_file *m, void *unused)
 intel_uncore_forcewake_put(dev_priv,
FORCEWAKE_ALL);
   -if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
-pm_ier = I915_READ(GEN6_PMIER);
-pm_imr = I915_READ(GEN6_PMIMR);
-pm_isr = I915_READ(GEN6_PMISR);
-pm_iir = I915_READ(GEN6_PMIIR);
-pm_mask = I915_READ(GEN6_PMINTRMSK);
-} else {
+if (INTEL_GEN(dev_priv) >= 11) {
+pm_ier =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+pm_imr =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
+/*
+ * The equivalent to the PM ISR & IIR cannot
be read
+ * without affecting the current state of
the system
+ */
+pm_isr = 0;
+pm_iir = 0;
+} else if (INTEL_GEN(dev_priv) >= 8) {
   pm_ier = I915_READ(GEN8_GT_IER(2));
   pm_imr = I915_READ(GEN8_GT_IMR(2));
   pm_isr = I915_READ(GEN8_GT_ISR(2));
   pm_iir = I915_READ(GEN8_GT_IIR(2));
-pm_mask = I915_READ(GEN6_PMINTRMSK);
+} else {
+pm_ier = I915_READ(GEN6_PMIER);
+pm_imr = I915_READ(GEN6_PMIMR);
+pm_isr = I915_READ(GEN6_PMISR);
+pm_iir = I915_READ(GEN6_PMIIR);
   }
+pm_mask = I915_READ(GEN6_PMINTRMSK);
+
   seq_printf(m, "Video Turbo Mode: %s\n",
  yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
   seq_printf(m, "HW control enabled: %s\n",
@@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct
seq_file
*m, void *unused)
   seq_printf(m, "SW control enabled: %s\n",
  yesno((rpmodectl &
GEN6_RP_MEDIA_MODE_MASK) ==
 GEN6_RP_MEDIA_SW_MODE));
-seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x
IIR=0x%08x, MASK=0x%08x\n",
-   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
+
+seq_printf(m, "PM IER=0x%08x IMR=0x%08x,
MASK=0x%08x\n",
+   pm_ier, pm_imr, pm_mask);
+if (INTEL_GEN(dev_priv) < 11) {
+seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
+

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo Lozano]

On 5/18/2018 11:12 AM, Yunwei Zhang wrote:

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

References: HSD#1405586840, BSID#0575

v2:
  - use fls() instead of find_last_bit() (Chris)
  - added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
  - rebase on latest tip
v5:
  - Added references (Mika)
  - Change the ordered of passing arguments and etc. (Ursulin)
v7:
  - Moved WA explanation Comments(Oscar)
  - Rebased.
v8:
  - Renamed sanitize_mcr to calculate_s_ss_select. (Oscar)
  - calculate s/ss selector instead of whole mcr. (Oscar)

Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Signed-off-by: Yunwei Zhang 
---
  drivers/gpu/drm/i915/i915_drv.h  |  2 ++
  drivers/gpu/drm/i915/intel_engine_cs.c   | 33 +++-
  drivers/gpu/drm/i915/intel_workarounds.c | 32 +++
  3 files changed, 62 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e33c380..e697785 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2744,6 +2744,8 @@ int vlv_force_gfx_clock(struct drm_i915_private 
*dev_priv, bool on);
  int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
  int intel_engines_init(struct drm_i915_private *dev_priv);
  
+u32 intel_calculate_s_ss_select(struct drm_i915_private *dev_priv);

+


Maybe intel_calculate_mcr_s_ss_select is beter?




  /* intel_hotplug.c */
  void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
   u32 pin_mask, u32 long_mask);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 26f9f8a..511975f 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -819,12 +819,32 @@ const char *i915_cache_level_str(struct drm_i915_private 
*i915, int type)
}
  }
  
+u32 intel_calculate_s_ss_select(struct drm_i915_private *dev_priv)

+{
+   const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+   u32 mcr_s_ss_mask;
+   u32 mcr_s_ss_select;
+   u32 slice = fls(sseu->slice_mask);
+   u32 subslice = fls(sseu->subslice_mask[slice]);
+
+   mcr_s_ss_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;


Do we need this for anything?


+
+   if (INTEL_GEN(dev_priv) == 10)
+   mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
+ GEN8_MCR_SUBSLICE(subslice);
+   else
+   mcr_s_ss_select = 0;
+
+   return mcr_s_ss_select;
+}
+
  static inline uint32_t
  read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
  int subslice, i915_reg_t reg)
  {
uint32_t mcr_slice_subslice_mask;
uint32_t mcr_slice_subslice_select;
+   uint32_t default_mcr_s_ss_select;
uint32_t mcr;
uint32_t ret;
enum forcewake_domains fw_domains;
@@ -841,6 +861,8 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int 
slice,
GEN8_MCR_SUBSLICE(subslice);
}
  
+	default_mcr_s_ss_select = intel_calculate_s_ss_select(dev_priv);

+
fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
FW_REG_READ);
fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
@@ -851,11 +873,10 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int 
slice,
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
  
  	mcr = I915_READ_FW(GEN8_MCR_SELECTOR);

-   /*
-* The HW expects the slice and sublice selectors to be reset to 0
-* after reading out the registers.
-*/
-   WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+
+   WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
+default_mcr_s_ss_select);
+
mcr &= ~mcr_slice_subslice_mask;
mcr |= mcr_slice_subslice_select;

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/icl: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads

[Oscar Mateo Lozano]

On 5/18/2018 11:13 AM, Yunwei Zhang wrote:

WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.

References: HSD#1405586840, BSID#0575

Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
Signed-off-by: Yunwei Zhang 
---
  drivers/gpu/drm/i915/intel_engine_cs.c   | 2 +-
  drivers/gpu/drm/i915/intel_workarounds.c | 5 -
  2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 511975f..9ce4dd6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -829,7 +829,7 @@ u32 intel_calculate_s_ss_select(struct drm_i915_private 
*dev_priv)
  
  	mcr_s_ss_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
  
-	if (INTEL_GEN(dev_priv) == 10)

+   if (INTEL_GEN(dev_priv) >= 10)
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
  GEN8_MCR_SUBSLICE(subslice);


Wait, shouldn't these be GEN11_MCR_SLICE() and GEN11_MCR_SUBSLICE() in 
the case of ICL?



else
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index d814368..bbf3de5 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -686,7 +686,7 @@ static void wa_init_mcr(struct drm_i915_private *dev_priv)
mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
  GEN8_MCR_SUBSLICE_MASK;
/*
-* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
 * Before any MMIO read into slice/subslice specific registers, MCR
 * packet control register needs to be programmed to point to any
 * enabled s/ss pair. Otherwise, incorrect values will be returned.
@@ -724,6 +724,9 @@ static void cnl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
  
  static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)

  {
+   /* WaProgramMgsrForCorrectSliceSpecificMmioReads: icl */
+   wa_init_mcr(dev_priv);
+
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));


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Re: [Intel-gfx] [PATCH] drm/i915/icl: Read the correct Gen11 interrupt registers

[Oscar Mateo Lozano]

On 5/17/2018 9:55 AM, Michel Thierry wrote:

On 5/16/2018 4:39 PM, Paulo Zanoni wrote:

Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:

Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in the
Gen11 interrupt repartitioning scheme.

Note that the equivalent to the PM ISR & IIR cannot be read without
affecting the current state of the system, so I've opted for leaving
them out. See gen11_service_one_iir() for more info.


I can't find this function. Did you mean something else?



s/gen11_service_one_iir/gen11_reset_one_iir/



Yup, that's right. Thanks Michel, I didn't realize this had been renamed 
in upstream.







v2: else if !!! (Paulo)
v3: another else if (Vinay)
v4:
   - Rebased
   - Renamed patch
   - Improved the ordering of GENs
   - Improved the printing of per-GEN info
v5: Avoid maybe-unitialized & add comment explaining the lack
 of PM ISR & IIR

Suggested-by: Paulo Zanoni 
Signed-off-by: Oscar Mateo 
Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
Cc: Sagar Arun Kamble 
Cc: Vinay Belgaumkar 
---
  drivers/gpu/drm/i915/i915_debugfs.c   | 34 -
-
  drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++-
  drivers/gpu/drm/i915/i915_gpu_error.h |  2 +-
  3 files changed, 35 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d663a9e0..d992dd2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1170,19 +1170,28 @@ static int i915_frequency_info(struct
seq_file *m, void *unused)
    intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  -    if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
-    pm_ier = I915_READ(GEN6_PMIER);
-    pm_imr = I915_READ(GEN6_PMIMR);
-    pm_isr = I915_READ(GEN6_PMISR);
-    pm_iir = I915_READ(GEN6_PMIIR);
-    pm_mask = I915_READ(GEN6_PMINTRMSK);
-    } else {
+    if (INTEL_GEN(dev_priv) >= 11) {
+    pm_ier =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+    pm_imr =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
+    /*
+ * The equivalent to the PM ISR & IIR cannot
be read
+ * without affecting the current state of
the system
+ */
+    pm_isr = 0;
+    pm_iir = 0;
+    } else if (INTEL_GEN(dev_priv) >= 8) {
  pm_ier = I915_READ(GEN8_GT_IER(2));
  pm_imr = I915_READ(GEN8_GT_IMR(2));
  pm_isr = I915_READ(GEN8_GT_ISR(2));
  pm_iir = I915_READ(GEN8_GT_IIR(2));
-    pm_mask = I915_READ(GEN6_PMINTRMSK);
+    } else {
+    pm_ier = I915_READ(GEN6_PMIER);
+    pm_imr = I915_READ(GEN6_PMIMR);
+    pm_isr = I915_READ(GEN6_PMISR);
+    pm_iir = I915_READ(GEN6_PMIIR);
  }
+    pm_mask = I915_READ(GEN6_PMINTRMSK);
+
  seq_printf(m, "Video Turbo Mode: %s\n",
 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
  seq_printf(m, "HW control enabled: %s\n",
@@ -1190,8 +1199,13 @@ static int i915_frequency_info(struct seq_file
*m, void *unused)
  seq_printf(m, "SW control enabled: %s\n",
 yesno((rpmodectl &
GEN6_RP_MEDIA_MODE_MASK) ==
    GEN6_RP_MEDIA_SW_MODE));
-    seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x
IIR=0x%08x, MASK=0x%08x\n",
-   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
+
+    seq_printf(m, "PM IER=0x%08x IMR=0x%08x,
MASK=0x%08x\n",
+   pm_ier, pm_imr, pm_mask);
+    if (INTEL_GEN(dev_priv) < 11) {
+    seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
+   pm_isr, pm_iir);
+    }
  seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
 rps->pm_intrmsk_mbz);
  seq_printf(m, "GT_PERF_STATUS: 0x%08x\n",
gt_perf_status);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b98cd44..d9f2f69 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1675,7 +1675,16 @@ static void capture_reg_state(struct
i915_gpu_state *error)
  }
    /* 4: Everything else */
-    if (INTEL_GEN(dev_priv) >= 8) {
+    if (INTEL_GEN(dev_priv) >= 11) {
+    error->ier = I915_READ(GEN8_DE_MISC_IER);
+    error->gtier[0] =
I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
+    error->gtier[1] =
I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
+    error->gtier[2] =
I915_READ(GEN11_GUC_SG_INTR_ENABLE);
+    error->gtier[3] =
I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+    error->gtier[4] =
I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);
+    error->gtier[5] =
I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);
+    error->ngtier = 6;
+    } else if 

Re: [Intel-gfx] [PATCH v2 00/22] Workarounds for Icelake

[Oscar Mateo Lozano]

On 5/2/2018 1:40 PM, Chris Wilson wrote:

Quoting Oscar Mateo (2018-05-02 21:33:59)

List of GT workarounds for Icelake that we have been carrying in internal.

(Is (checkpatch
  (((going to complain)
(that this isn't))
   (lisp?
-Chris


Maybe. Or maybe checkpatch has given up completely on checking the 
parentheses in the WAs?

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Re: [Intel-gfx] [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Oscar Mateo Lozano]

On 5/2/2018 3:23 AM, Mika Kuoppala wrote:

Oscar Mateo  writes:


Revert to an L3 non-hash model, for performance reasons.

v2:
   - Place the WA name above the actual change
   - Improve the register naming
v3:
   - Rebased
   - Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring

Cc: Mika Kuoppala 
Signed-off-by: Oscar Mateo 
---
  drivers/gpu/drm/i915/i915_reg.h  |  6 ++
  drivers/gpu/drm/i915/intel_workarounds.c | 20 
  2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a6b1f85..5637cd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,12 @@ enum {
  #define GEN8_GARBCNTL _MMIO(0xB004)
  #define   GEN9_GAPS_TSV_CREDIT_DISABLE(1 << 7)
  #define   GEN11_ARBITRATION_PRIO_ORDER_MASK   (0x3f << 22)
+#define   GEN11_HASH_CTRL_EXCL_MASK(0x7f << 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0(1 << 0)
+
+#define GEN11_GLBLINVL _MMIO(0xB404)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0   (1 << 0)

(1 << 5)


+#define   GEN11_BANK_HASH_ADDR_EXCL_MASK   (0x3f << 5)

0x7f
-Mika


Lordy! Thanks for spotting this. Also, I went back to the HSD looking 
for the source of the mistake and the WA has been updated with more 
steps, so I'll send a new version.


-- Oscar



  
  #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)

  #define   DFR_DISABLE (1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c 
b/drivers/gpu/drm/i915/intel_workarounds.c
index ffd27a1..83a53cc 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -704,11 +704,23 @@ static void icl_gt_workarounds_apply(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
  
-	/* Wa_1405543622:icl

-* Formerly known as WaGAPZPriorityScheme
+   I915_WRITE(GEN8_GARBCNTL,
+  /* Wa_1604223664:icl
+   * Formerly known as WaL3BankAddressHashing
+   */
+  ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+   GEN11_HASH_CTRL_EXCL_BIT0 |
+   /* Wa_1405543622:icl
+* Formerly known as WaGAPZPriorityScheme
+*/
+   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+   /* Wa_1604223664:icl
+* Formerly known as WaL3BankAddressHashing
 */
-   I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
-  GEN11_ARBITRATION_PRIO_ORDER_MASK));
+   I915_WRITE(GEN11_GLBLINVL,
+  ((I915_READ(GEN11_GLBLINVL) & 
~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+   GEN11_BANK_HASH_ADDR_EXCL_BIT0));
  }
  
  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)

--
1.9.1


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Re: [Intel-gfx] [PATCH v2 0/8] Enable HuC authentication in Icelake

[Oscar Mateo Lozano]

Obviously the subject is wrong: it should say 0/5 instead of 0/8 (I 
copied the subject from the cover letter meant from internal, without 
realizing the number of patches was different).



On 5/2/2018 12:03 PM, Oscar Mateo wrote:

Bare minimum number of patches to get the GuC to authenticate the
HuC correctly (i915.enable_guc=2).

Oscar Mateo (5):
   drm/i915/icl/guc: Do not allow GuC submission on Icelake for now
   drm/i915/icl/guc: Pass the bare minimum GuC init parameters for
 Icelake
   drm/i915/icl/guc: Define the GuC firmware version for Icelake
   drm/i915/icl/huc: Correctly authenticate the HuC for Icelake
   drm/i915/icl/huc: Define the HuC firmware version for Icelake


Joonas: can you take a look at these? The Media team is blocked on these 
patches.


Thanks,
Oscar


  drivers/gpu/drm/i915/intel_guc.c  | 10 --
  drivers/gpu/drm/i915/intel_guc_fw.c   |  9 +
  drivers/gpu/drm/i915/intel_guc_fwif.h |  1 +
  drivers/gpu/drm/i915/intel_guc_reg.h  |  3 +++
  drivers/gpu/drm/i915/intel_huc.c  | 23 +++
  drivers/gpu/drm/i915/intel_huc_fw.c   | 11 +++
  drivers/gpu/drm/i915/intel_uc.c   | 10 ++
  7 files changed, 61 insertions(+), 6 deletions(-)



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