[Intel-gfx] [PATCH v5] drm/i915/debugfs : PCU PM_REQ and PM_RES registers
This debugfs provides the display PM debug information like Time
to Next VBI and Time to Next Fill from Display Engine <-> PCU Mailbox.
V2:
Added a functional print to debugfs. [Jani Nikula]
V3:
Used separate variables to store the register values and also
used REG_GENMASK and REG_BIT for mask preparation. [Anshuman Gupta]
Removed reading of register contents. Replaced local variable with yesno().
Placed register macros separately, distinguishing from other
macros. [Jani Nikula]
V4 : Used i915 as local variable. [Anshuman Gupta, Jani Nikula]
V5 : Added wakeref to wakeup device. [Chris Wilson]
Signed-off-by: Saichandana S
---
.../drm/i915/display/intel_display_debugfs.c | 24 +++
drivers/gpu/drm/i915/i915_reg.h | 9 +++
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d6e4a9237bda..29aaa41fdeec 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -591,6 +591,29 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
return 0;
}
+static int i915_pcu_pm_req_res_info(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_csr *csr = &i915->csr;
+ intel_wakeref_t wakeref;
+
+ if (!HAS_CSR(i915))
+ return -ENODEV;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+ if (!csr->dmc_payload)
+ return 0;
+ seq_printf(m, "Time to Next Fill : 0x%08x\n",
+ intel_de_read(i915, PM_RSP_DBG_0) & PM_RESP_TTNF_MASK);
+ seq_printf(m, "Time to Next VBI : 0x%08x\n",
+ (intel_de_read(i915, PM_RSP_DBG_0) & PM_RESP_TTNVBI_MASK) >>
16);
+ seq_printf(m, "Selective Exit Latency : 0x%08x\n",
+ intel_de_read(i915, PM_RSP_DBG_1) &
PM_RESP_SEL_EXIT_LATENCY_MASK);
+
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+ return 0;
+}
+
static void intel_seq_print_mode(struct seq_file *m, int tabs,
const struct drm_display_mode *mode)
{
@@ -2128,6 +2151,7 @@ static const struct drm_info_list
intel_display_debugfs_list[] = {
{"i915_edp_psr_status", i915_edp_psr_status, 0},
{"i915_power_domain_info", i915_power_domain_info, 0},
{"i915_dmc_info", i915_dmc_info, 0},
+ {"i915_pcu_pm_req_res_info", i915_pcu_pm_req_res_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 224ad897af34..93d319bf80fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12525,4 +12525,13 @@ enum skl_power_gate {
#define TGL_ROOT_DEVICE_SKU_ULX0x2
#define TGL_ROOT_DEVICE_SKU_ULT0x4
+/*These registers are of functional registers for PM debug request and
response registers*/
+#define PM_REQ_DBG_0 _MMIO(0x45284)
+#define PM_REQ_DBG_1 _MMIO(0x45288)
+#define PM_RSP_DBG_0 _MMIO(0x4528C)
+#define PM_RESP_TTNF_MASKREG_GENMASK(15, 0)
+#define PM_RESP_TTNVBI_MASK REG_GENMASK(31, 16)
+#define PM_RSP_DBG_1 _MMIO(0x45290)
+#define PM_RESP_SEL_EXIT_LATENCY_MASKREG_GENMASK(2, 0)
+
#endif /* _I915_REG_H_ */
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915/debugfs : PM_REQ and PM_RES registers
PM_REQ register provides the value of the last PM request, response
from PCU to PM_DBG_{REQ,RSP} . This debugfs provides DC9 Ready
status but will also be used by DC9 IGT test . It will also print
the useful debug information from Display Engine to PCU mailbox register.
B.Spec : 49501, 49502
V2:
Added a functional print to debugfs. [Jani Nikula]
V3:
Used separate variables to store the register values and
also used REG_GENMASK and REG_BIT for mask preparation. [Anshuman Gupta]
Removed reading of register contents. Replaced local variable
with yesno(). Placed register macros separately, distinguishing from
other macros. [Jani Nikula]
V4 : Used i915 as a local variable. [Anshuman Gupta, Jani Nikula]
Signed-off-by: Saichandana S
---
.../drm/i915/display/intel_display_debugfs.c | 23 +++
drivers/gpu/drm/i915/i915_reg.h | 10
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..afed22903ac7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -559,6 +559,28 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
return 0;
}
+static int i915_pm_req_res_info(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_csr *csr = &i915->csr;
+ u32 DC9_status;
+
+ if (!HAS_CSR(i915))
+ return -ENODEV;
+ if (!csr->dmc_payload)
+ return 0;
+ DC9_status = intel_de_read(i915, PM_RSP_DBG_1) & PM_RESP_DC9_READY;
+
+ seq_printf(m, "Time to Next Fill : 0x%08x\n",
+ intel_de_read(i915, PM_RSP_DBG_0) & PM_RESP_TTNF_MASK);
+ seq_printf(m, "Time to Next VBI : 0x%08x\n",
+ (intel_de_read(i915, PM_RSP_DBG_0) & PM_RESP_TTNVBI_MASK) >>
16);
+ seq_printf(m, "Selective Exit Latency : 0x%08x\n",
+ intel_de_read(i915, PM_RSP_DBG_1) &
PM_RESP_SEL_EXIT_LATENCY_MASK);
+ seq_printf(m, "DC9 Ready : %s\n", yesno(DC9_status));
+ return 0;
+}
+
static void intel_seq_print_mode(struct seq_file *m, int tabs,
const struct drm_display_mode *mode)
{
@@ -2100,6 +2122,7 @@ static const struct drm_info_list
intel_display_debugfs_list[] = {
{"i915_edp_psr_status", i915_edp_psr_status, 0},
{"i915_power_domain_info", i915_power_domain_info, 0},
{"i915_dmc_info", i915_dmc_info, 0},
+ {"i915_pm_req_res_info", i915_pm_req_res_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..8c91d598dc29 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12423,4 +12423,14 @@ enum skl_power_gate {
#define TGL_ROOT_DEVICE_SKU_ULX0x2
#define TGL_ROOT_DEVICE_SKU_ULT0x4
+/*These registers are of functional registers for PM debug request and
response registers*/
+#define PM_REQ_DBG_0 _MMIO(0x45284)
+#define PM_REQ_DBG_1 _MMIO(0x45288)
+#define PM_RSP_DBG_0 _MMIO(0x4528C)
+#define PM_RESP_TTNF_MASKREG_GENMASK(15, 0)
+#define PM_RESP_TTNVBI_MASK REG_GENMASK(31, 16)
+#define PM_RSP_DBG_1 _MMIO(0x45290)
+#define PM_RESP_SEL_EXIT_LATENCY_MASKREG_GENMASK(2, 0)
+#define PM_RESP_DC9_READYREG_BIT(15)
+
#endif /* _I915_REG_H_ */
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/debugfs : PM_REQ and PM_RES registers
PM_REQ register provides the value of the last PM request from PCU to
Display Engine. PM_RES register provides the value of the last PM
response from Display Engine to PCU.
This debugfs will be used by DC9 IGT test to know about "DC9 Ready"
status.
B.Spec : 49501, 49502
V2:
Added a functional print to debugfs. [Jani Nikula]
V3:
Used separate variables to store the register values and
also used REG_GENMASK and REG_BIT for mask preparation. [Anshuman Gupta]
Removed reading of register contents. Replaced local variable
with yesno(). Placed register macros separately, distinguishing from
other macros. [Jani Nikula]
Signed-off-by: Saichandana S
---
.../drm/i915/display/intel_display_debugfs.c | 23 +++
drivers/gpu/drm/i915/i915_reg.h | 10
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..e5997debb8e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -559,6 +559,28 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
return 0;
}
+static int i915_pm_req_res_info(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_csr *csr = &dev_priv->csr;
+ u32 DC9_status;
+
+ if (!HAS_CSR(dev_priv))
+ return -ENODEV;
+ if (!csr->dmc_payload)
+ return 0;
+ DC9_status = intel_de_read(dev_priv, PM_RSP_DBG_1) & PM_RESP_DC9_READY;
+
+ seq_printf(m, "Time to Next Fill : 0x%08x\n",
+ intel_de_read(dev_priv, PM_RSP_DBG_0) & PM_RESP_TTNF_MASK);
+ seq_printf(m, "Time to Next VBI : 0x%08x\n",
+ (intel_de_read(dev_priv, PM_RSP_DBG_0) &
PM_RESP_TTNVBI_MASK) >> 16);
+ seq_printf(m, "Selective Exit Latency : 0x%08x\n",
+ intel_de_read(dev_priv, PM_RSP_DBG_1) &
PM_RESP_SEL_EXIT_LATENCY_MASK);
+ seq_printf(m, "DC9 Ready : %s\n", yesno(DC9_status));
+ return 0;
+}
+
static void intel_seq_print_mode(struct seq_file *m, int tabs,
const struct drm_display_mode *mode)
{
@@ -2100,6 +2122,7 @@ static const struct drm_info_list
intel_display_debugfs_list[] = {
{"i915_edp_psr_status", i915_edp_psr_status, 0},
{"i915_power_domain_info", i915_power_domain_info, 0},
{"i915_dmc_info", i915_dmc_info, 0},
+ {"i915_pm_req_res_info", i915_pm_req_res_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..8c91d598dc29 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12423,4 +12423,14 @@ enum skl_power_gate {
#define TGL_ROOT_DEVICE_SKU_ULX0x2
#define TGL_ROOT_DEVICE_SKU_ULT0x4
+/*These registers are of functional registers for PM debug request and
response registers*/
+#define PM_REQ_DBG_0 _MMIO(0x45284)
+#define PM_REQ_DBG_1 _MMIO(0x45288)
+#define PM_RSP_DBG_0 _MMIO(0x4528C)
+#define PM_RESP_TTNF_MASKREG_GENMASK(15, 0)
+#define PM_RESP_TTNVBI_MASK REG_GENMASK(31, 16)
+#define PM_RSP_DBG_1 _MMIO(0x45290)
+#define PM_RESP_SEL_EXIT_LATENCY_MASKREG_GENMASK(2, 0)
+#define PM_RESP_DC9_READYREG_BIT(15)
+
#endif /* _I915_REG_H_ */
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/debugfs : PM_REQ and PM_RES registers
From: Saichandana
PM_REQ register provides the value of the last PM request from PCU to
Display Engine.PM_RES register provides the value of the last PM
response from Display Engine to PCU.This debugfs will be used by
DC9 IGT test to know about "DC9 Ready" status.
B.Spec : 49501, 49502
Signed-off-by: Saichandana
---
.../drm/i915/display/intel_display_debugfs.c | 30 +++
drivers/gpu/drm/i915/i915_reg.h | 8 +
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..551fb1a90bb3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -559,6 +559,36 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
return 0;
}
+static int i915_pm_req_res_info(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_csr *csr = &dev_priv->csr;
+ const char *status;
+
+ if (!HAS_CSR(dev_priv))
+ return -ENODEV;
+ if (!csr->dmc_payload)
+ return 0;
+ seq_printf(m, "PM debug request 0 (0x45284): 0x%08x\n",
+ intel_de_read(dev_priv, PM_REQ_DBG_0));
+ seq_printf(m, "PM debug request 1 (0x45288): 0x%08x\n",
+ intel_de_read(dev_priv, PM_REQ_DBG_1));
+ seq_printf(m, "PM debug response 0 (0x4528C): 0x%08x\n",
+ intel_de_read(dev_priv, PM_RSP_DBG_0));
+ seq_printf(m, "PM debug response 1 (0x45290): 0x%08x\n",
+ intel_de_read(dev_priv, PM_RSP_DBG_1));
+ status = (intel_de_read(dev_priv, PM_RSP_DBG_1) & MASK_DC9_BIT) ? "yes"
: "no";
+
+ seq_printf(m, "Time to Next Fill = 0x%0x\n",
+ (intel_de_read(dev_priv, PM_RSP_DBG_0) & ~MASK_RSP_0));
+ seq_printf(m, "Time to Next VBI = 0x%0x\n",
+ ((intel_de_read(dev_priv, PM_RSP_DBG_0) & MASK_RSP_0)) >>
16);
+ seq_printf(m, "Selective Exit Latency = 0x%0x\n",
+ (intel_de_read(dev_priv, PM_RSP_DBG_1) & MASK_RSP_1));
+ seq_printf(m, "DC9 Ready = %s\n", status);
+ return 0;
+}
+
static void intel_seq_print_mode(struct seq_file *m, int tabs,
const struct drm_display_mode *mode)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..3e9ed555f928 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -371,6 +371,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define VLV_G3DCTL _MMIO(0x9024)
#define VLV_GSCKGCTL _MMIO(0x9028)
+#define PM_REQ_DBG_0 _MMIO(0x45284)
+#define PM_REQ_DBG_1 _MMIO(0x45288)
+#define PM_RSP_DBG_0 _MMIO(0x4528C)
+#define PM_RSP_DBG_1 _MMIO(0x45290)
+#define MASK_RSP_0 (0x << 16)
+#define MASK_RSP_1 (7 << 0)
+#define MASK_DC9_BIT (1 << 17)
+
#define GEN6_MBCTL _MMIO(0x0907c)
#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/debugfs : PM_REQ and PM_RES register debugfs
From: Saichandana
PM_REQ register provides the value of the last PM request from PCU to
Display Engine.PM_RES register provides the value of the last PM response from
Display Engine to PCU.
This debugfs will be used by DC9 IGT test to know about "DC9 Ready"
status.
B.Spec : 49501, 49502
Signed-off-by: Saichandana
---
.../drm/i915/display/intel_display_debugfs.c | 24 +++
drivers/gpu/drm/i915/i915_reg.h | 5
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..09e734e54032 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -559,6 +559,29 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
return 0;
}
+static int i915_pm_req_res_info(struct seq_file *m, void *unused)
+{
+struct drm_i915_private *dev_priv = node_to_i915(m->private);
+struct intel_csr *csr = &dev_priv->csr;
+
+if (!HAS_CSR(dev_priv))
+return -ENODEV;
+
+if (!csr->dmc_payload)
+return 0;
+
+seq_printf(m, "PM debug request 0 (0x45284) : 0x%x\n",
+intel_de_read(dev_priv, PM_REQ_DBG_0));
+seq_printf(m, "PM debug request 1 (0x45288) : 0x%x\n",
+intel_de_read(dev_priv, PM_REQ_DBG_1));
+seq_printf(m, "PM debug response 0 (0x4528C) : 0x%x\n",
+intel_de_read(dev_priv, PM_RSP_DBG_0));
+seq_printf(m, "PM debug response 1 (0x45290) : 0x%x\n",
+intel_de_read(dev_priv, PM_RSP_DBG_1));
+
+return 0;
+}
+
static void intel_seq_print_mode(struct seq_file *m, int tabs,
const struct drm_display_mode *mode)
{
@@ -2100,6 +2123,7 @@ static const struct drm_info_list
intel_display_debugfs_list[] = {
{"i915_edp_psr_status", i915_edp_psr_status, 0},
{"i915_power_domain_info", i915_power_domain_info, 0},
{"i915_dmc_info", i915_dmc_info, 0},
+ {"i915_pm_req_res_info", i915_pm_req_res_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..b477a1f7b1bd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -371,6 +371,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define VLV_G3DCTL _MMIO(0x9024)
#define VLV_GSCKGCTL _MMIO(0x9028)
+#define PM_REQ_DBG_0 _MMIO(0x45284)
+#define PM_REQ_DBG_1 _MMIO(0x45288)
+#define PM_RSP_DBG_0 _MMIO(0x4528C)
+#define PM_RSP_DBG_1 _MMIO(0x45290)
+
#define GEN6_MBCTL _MMIO(0x0907c)
#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
