[Intel-gfx] [PATCH] drm/i915: Clamp efficient frequency to valid range
From: Tom O'Rourke Tom.O'rou...@intel.com The efficient frequency (RPe) should stay in the range RPn = RPe = RP0. The pcode clamps the returned value internally on Broadwell but not on Haswell. Fix for missing range check in commit 93ee29203f506582cca2bcec5f05041526d9ab0a Author: Tom O'Rourke Tom.O'rou...@intel.com Date: Wed Nov 19 14:21:52 2014 -0800 drm/i915: Use efficient frequency for HSW/BDW Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-February/059802.html Reported-by: Michael Auchter a...@phire.org Suggested-by: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com --- drivers/gpu/drm/i915/intel_pm.c |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a3b979d..602c443 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3998,7 +3998,10 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) ddcc_status); if (0 == ret) dev_priv-rps.efficient_freq = - (ddcc_status 8) 0xff; + clamp_t(u8, + ((ddcc_status 8) 0xff), + dev_priv-rps.min_freq, + dev_priv-rps.max_freq); } /* Preserve min/max settings in case of re-init */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/4] Update turbo (rps) min frequency for HSW/BDW
From: Tom O'Rourke Tom.O'rou...@intel.com These patches update the turbo minimum frequency to match the values used for Windows and Android. v2: Updated patches 1 and 2 based on comments from Daniel and Chris. Added 2 related patches. Tom O'Rourke (4): drm/i915: Use efficient frequency for HSW/BDW drm/i915: Keep min freq above floor on HSW/BDW drm/i915: change initial rps frequency for gen8 drm/i915: Update ring freq for full gpu freq range drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c | 51 +++ 2 files changed, 37 insertions(+), 15 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/4] drm/i915: Keep min freq above floor on HSW/BDW
From: Tom O'Rourke Tom.O'rou...@intel.com
Set the min_freq_softlimit to max(RPe, 450MHz).
Setting a floor can ensure a minimum experience
level. The 450MHz value came from a power and
performance study of various types of workloads
(3D, Media, GPGPU, idle, etc).
v2: rebased
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2434542..9f9afb3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4649,7 +4649,8 @@ static void gen6_init_rps_frequencies(struct drm_device
*dev)
if (dev_priv-rps.min_freq_softlimit == 0) {
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
dev_priv-rps.min_freq_softlimit =
- dev_priv-rps.efficient_freq;
+ /* max(RPe, 450 MHz) */
+ max(dev_priv-rps.efficient_freq, (u8) 9);
else
dev_priv-rps.min_freq_softlimit =
dev_priv-rps.min_freq;
--
1.7.9.5
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[Intel-gfx] [PATCH 3/4] drm/i915: change initial rps frequency for gen8
From: Tom O'Rourke Tom.O'rou...@intel.com In gen8_enable_rps, change the initial rps setting to the min_freq_softlimit (same as gen6_enable_rps). Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com --- drivers/gpu/drm/i915/intel_pm.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9f9afb3..4fd063f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4772,7 +4772,8 @@ static void gen8_enable_rps(struct drm_device *dev) /* 6: Ring frequency + overclocking (our driver does this later */ - gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) 0xff00) 8); + dev_priv-rps.power = HIGH_POWER; /* force a reset */ + gen6_set_rps(dev_priv-dev, dev_priv-rps.min_freq_softlimit); gen6_enable_rps_interrupts(dev); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: Update ring freq for full gpu freq range
From: Tom O'Rourke Tom.O'rou...@intel.com
In __gen6_update_ring_freq, use the full range of
possible gpu frequencies from max_freq to min_freq.
The actual gpu frequency could be outside the range
from max_freq_softlimit to min_freq_softlimit due
to power/thermal constraints.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4fd063f..2f744aa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4926,9 +4926,9 @@ static void __gen6_update_ring_freq(struct drm_device
*dev)
* to use for memory access. We do this by specifying the IA frequency
* the PCU should use as a reference to determine the ring frequency.
*/
- for (gpu_freq = dev_priv-rps.max_freq_softlimit; gpu_freq =
dev_priv-rps.min_freq_softlimit;
+ for (gpu_freq = dev_priv-rps.max_freq; gpu_freq =
dev_priv-rps.min_freq;
gpu_freq--) {
- int diff = dev_priv-rps.max_freq_softlimit - gpu_freq;
+ int diff = dev_priv-rps.max_freq - gpu_freq;
unsigned int ia_freq = 0, ring_freq = 0;
if (INTEL_INFO(dev)-gen = 8) {
--
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[Intel-gfx] [PATCH v2 1/4] drm/i915: Use efficient frequency for HSW/BDW
From: Tom O'Rourke Tom.O'rou...@intel.com
Added gen6_init_rps_frequencies() to initialize
the rps frequency values. This function replaces
parse_rp_state_cap(). In addition to reading RPn,
RP0, and RP1 from RP_STATE_CAP register, the new
function reads efficient frequency (aka RPe) from
pcode for Haswell and Broadwell and sets the turbo
softlimits. The turbo minimum frequency softlimit
is set to RPe for Haswell and Broadwell and to RPn
otherwise.
For RPe, the efficiency is based on the frequency/power
ratio (MHz/W); this is considering GT power and not
package power. The efficent frequency is the highest
frequency for which the frequency/power ratio is within
some threshold of the highest frequency/power ratio.
A fixed decrease in frequency results in smaller
decrease in power at frequencies less than RPe than
at frequencies above RPe.
v2: Following suggestions from Chris Wilson and
Daniel Vetter to extend and rename parse_rp_state_cap
and to open-code a poorly named function.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_pm.c | 43 ---
2 files changed, 32 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7a77cd5..3a51c05 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6038,6 +6038,7 @@ enum punit_power_well {
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids)(((vids) * 5) + 245)
#define DISPLAY_IPS_CONTROL 0x19
+#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN6_PCODE_DATA0x138128
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8e2dca0..2434542 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4615,25 +4615,45 @@ int intel_enable_rc6(const struct drm_device *dev)
return i915.enable_rc6;
}
-static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32
rp_state_cap)
+static void gen6_init_rps_frequencies(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ uint32_t rp_state_cap;
+ u32 ddcc_status = 0;
+ int ret;
+
+ rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
/* All of these values are in units of 50MHz */
dev_priv-rps.cur_freq = 0;
- /* static values from HW: RP0 RPe RP1 RPn (min_freq) */
- dev_priv-rps.rp1_freq = (rp_state_cap 8) 0xff;
+ /* static values from HW: RP0 RP1 RPn (min_freq) */
dev_priv-rps.rp0_freq = (rp_state_cap 0) 0xff;
+ dev_priv-rps.rp1_freq = (rp_state_cap 8) 0xff;
dev_priv-rps.min_freq = (rp_state_cap 16) 0xff;
- /* XXX: only BYT has a special efficient freq */
- dev_priv-rps.efficient_freq= dev_priv-rps.rp1_freq;
/* hw_max = RP0 until we check for overclocking */
dev_priv-rps.max_freq = dev_priv-rps.rp0_freq;
+ dev_priv-rps.efficient_freq = dev_priv-rps.rp1_freq;
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ ret = sandybridge_pcode_read(dev_priv,
+ HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ ddcc_status);
+ if (0 == ret)
+ dev_priv-rps.efficient_freq =
+ (ddcc_status 8) 0xff;
+ }
+
/* Preserve min/max settings in case of re-init */
if (dev_priv-rps.max_freq_softlimit == 0)
dev_priv-rps.max_freq_softlimit = dev_priv-rps.max_freq;
- if (dev_priv-rps.min_freq_softlimit == 0)
- dev_priv-rps.min_freq_softlimit = dev_priv-rps.min_freq;
+ if (dev_priv-rps.min_freq_softlimit == 0) {
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ dev_priv-rps.min_freq_softlimit =
+ dev_priv-rps.efficient_freq;
+ else
+ dev_priv-rps.min_freq_softlimit =
+ dev_priv-rps.min_freq;
+ }
}
static void gen9_enable_rps(struct drm_device *dev)
@@ -4692,8 +4712,8 @@ static void gen8_enable_rps(struct drm_device *dev)
/* 2a: Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
- rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
- parse_rp_state_cap(dev_priv, rp_state_cap);
+ /* Initialize rps frequencies */
+ gen6_init_rps_frequencies(dev);
/* 2b: Program RC6 thresholds.*/
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
@@ -4786,9 +4806,8 @@ static void gen6_enable_rps(struct drm_device *dev)
gen6_gt_force_wake_get
[Intel-gfx] [PATCH] drm/i915: Extend pcode mailbox interface
From: Tom O'Rourke Tom.O'rou...@intel.com
In sandybridge_pcode_read and sandybridge_pcode_write,
extend the mbox parameter from u8 to u32.
On Haswell and Sandybridge, bits 7:0 encode the mailbox
command and bits 28:8 are used for address control for
specific commands.
Based on suggestion from Ville Syrjälä.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |4 ++--
drivers/gpu/drm/i915/intel_pm.c |4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f3035c..4dea835 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2954,8 +2954,8 @@ void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv, int fw_engine);
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
-int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32
*val);
-int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32
val);
+int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32
*val);
+int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32
val);
/* intel_sideband.c */
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9e87265..21faa92 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7154,7 +7154,7 @@ void intel_init_pm(struct drm_device *dev)
}
}
-int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32
*val)
+int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32
*val)
{
WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
@@ -7180,7 +7180,7 @@ int sandybridge_pcode_read(struct drm_i915_private
*dev_priv, u8 mbox, u32 *val)
return 0;
}
-int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32
val)
+int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32
val)
{
WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
--
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[Intel-gfx] [PATCH 1/2] drm/i915: Use efficient frequency for HSW/BDW
From: Tom O'Rourke Tom.O'rou...@intel.com
Updated gen6|8_enable_rps() for Haswell and Broadwell
to use the efficient frequency read from pcode.
Added hsw_use_efficient_freq() to read efficient
frequency (aka RPe) from pcode. The efficiency is
based on the frequency/power ratio (MHz/W); this is
considering GT power and not package power. The
efficent frequency is the highest frequency for which
the frequency/power ratio is within some threshold of
the highest frequency/power ratio.
Also set the min_freq_softlimit to the efficient
frequency. A fixed decrease in frequency results in
smaller decrease in power at frequencies less than RPe
than at frequencies above RPe.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_pm.c | 22 ++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d43fa0e..6fbfdec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6010,6 +6010,7 @@ enum punit_power_well {
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids)(((vids) * 5) + 245)
#define DISPLAY_IPS_CONTROL 0x19
+#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN6_PCODE_DATA0x138128
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 300d7e5..e4347d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4706,6 +4706,18 @@ static void parse_rp_state_cap(struct drm_i915_private
*dev_priv, u32 rp_state_c
dev_priv-rps.min_freq_softlimit = dev_priv-rps.min_freq;
}
+static void hsw_use_efficient_freq(struct drm_i915_private *dev_priv)
+{
+ u32 ddcc_status = 0;
+ int ret;
+
+ ret = sandybridge_pcode_read(dev_priv,
+ HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ ddcc_status);
+ if (0 == ret)
+ dev_priv-rps.efficient_freq = (ddcc_status 8) 0xff;
+}
+
static void gen9_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -4765,6 +4777,11 @@ static void gen8_enable_rps(struct drm_device *dev)
rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
parse_rp_state_cap(dev_priv, rp_state_cap);
+ if (IS_BROADWELL(dev)) {
+ hsw_use_efficient_freq(dev_priv);
+ dev_priv-rps.min_freq_softlimit = dev_priv-rps.efficient_freq;
+ }
+
/* 2b: Program RC6 thresholds.*/
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 16);
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
@@ -4860,6 +4877,11 @@ static void gen6_enable_rps(struct drm_device *dev)
parse_rp_state_cap(dev_priv, rp_state_cap);
+ if (IS_HASWELL(dev)) {
+ hsw_use_efficient_freq(dev_priv);
+ dev_priv-rps.min_freq_softlimit = dev_priv-rps.efficient_freq;
+ }
+
/* disable the counters and set deterministic thresholds */
I915_WRITE(GEN6_RC_CONTROL, 0);
--
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[Intel-gfx] [PATCH 2/2] drm/i915: Keep min freq above floor on HSW/BDW
From: Tom O'Rourke Tom.O'rou...@intel.com
Set the min_freq_softlimit to max(RPe, 450MHz).
Setting a floor can ensure a minimum experience
level. The 450MHz value came from a power and
performance study of various types of workloads
(3D, Media, GPGPU, idle, etc).
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e4347d9..1244ff8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4779,7 +4779,8 @@ static void gen8_enable_rps(struct drm_device *dev)
if (IS_BROADWELL(dev)) {
hsw_use_efficient_freq(dev_priv);
- dev_priv-rps.min_freq_softlimit = dev_priv-rps.efficient_freq;
+ dev_priv-rps.min_freq_softlimit =
+ max(dev_priv-rps.efficient_freq, (u8) 9); /* 450 MHz */
}
/* 2b: Program RC6 thresholds.*/
@@ -4879,7 +4880,8 @@ static void gen6_enable_rps(struct drm_device *dev)
if (IS_HASWELL(dev)) {
hsw_use_efficient_freq(dev_priv);
- dev_priv-rps.min_freq_softlimit = dev_priv-rps.efficient_freq;
+ dev_priv-rps.min_freq_softlimit =
+ max(dev_priv-rps.efficient_freq, (u8) 9); /* 450 MHz */
}
/* disable the counters and set deterministic thresholds */
--
1.7.9.5
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[Intel-gfx] [PATCH 0/2] Update turbo (rps) min frequency for HSW/BDW
From: Tom O'Rourke Tom.O'rou...@intel.com These patches update the turbo minimum frequency to match the values used for Windows and Android. The refactoring in Imre's recent series [Intel-gfx] [PATCH 0/8] sanitize RPS interrupt enabling/disabling conflicts with these changes. Those conflicts should not be difficult to resolve. Tom O'Rourke (2): drm/i915: Use efficient frequency for HSW/BDW drm/i915: Keep min freq above floor on HSW/BDW drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_pm.c | 24 2 files changed, 25 insertions(+) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add haswell_pcode_write function
From: Tom O'Rourke Tom.O'rou...@intel.com
Based on sandybridge_pcode_write, haswell_pcode_write has an
additional field for address control.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_pm.c |9 +++--
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f00e58..fd8b550 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2950,6 +2950,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv, int fw_engine);
void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32
*val);
+int haswell_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val,
u32 control);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32
val);
/* intel_sideband.c */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6fbfdec..b674050 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6011,6 +6011,7 @@ enum punit_power_well {
#define GEN6_DECODE_RC6_VID(vids)(((vids) * 5) + 245)
#define DISPLAY_IPS_CONTROL 0x19
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
+#define HSW_PCODE_ADDR_CNTL(cntl)((cntl 8) 0x1f00)
#define GEN6_PCODE_DATA0x138128
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1244ff8..9c47bc8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7277,7 +7277,7 @@ int sandybridge_pcode_read(struct drm_i915_private
*dev_priv, u8 mbox, u32 *val)
return 0;
}
-int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32
val)
+int haswell_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val,
u32 control)
{
WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
@@ -7287,7 +7287,7 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
}
I915_WRITE(GEN6_PCODE_DATA, val);
- I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
+ I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox |
HSW_PCODE_ADDR_CNTL(control));
if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) GEN6_PCODE_READY) == 0,
500)) {
@@ -7300,6 +7300,11 @@ int sandybridge_pcode_write(struct drm_i915_private
*dev_priv, u8 mbox, u32 val)
return 0;
}
+int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32
val)
+{
+ return haswell_pcode_write(dev_priv, mbox, val, 0);
+}
+
static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
{
int div;
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915/chv: Fix drm/i915/chv: Add a bunch of pre production workarounds
From: Tom O'Rourke Tom.O'rou...@intel.com Correct a merge mishap in commit e4443e459ccf43f2c139358400365fd6a839d40d. Wa*:chv belongs in cherryview_enable_rps, not gen8_enable_rps. Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 18f0ba0..c6e893b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3520,15 +3520,11 @@ static void gen8_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); - /* WaDisablePwrmtrEvent:chv (pre-production hw) */ - I915_WRITE(0xA80C, I915_READ(0xA80C) 0x00ff); - I915_WRITE(0xA810, I915_READ(0xA810) 0xff00); - /* 5: Enable RPS */ I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO | GEN6_RP_MEDIA_HW_NORMAL_MODE | - GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ + GEN6_RP_MEDIA_IS_GFX | GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_AVG); @@ -4022,10 +4018,14 @@ static void cherryview_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); + /* WaDisablePwrmtrEvent:chv (pre-production hw) */ + I915_WRITE(0xA80C, I915_READ(0xA80C) 0x00ff); + I915_WRITE(0xA810, I915_READ(0xA810) 0xff00); + /* 5: Enable RPS */ I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_HW_NORMAL_MODE | - GEN6_RP_MEDIA_IS_GFX | + GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_AVG); -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/chv: WaDisablePwrmtrEvent:chv on CHV only
From: Tom O'Rourke Tom.O'rou...@intel.com
In gen8_enable_rps, don't write CHV registers unless IS_CHERRYVIEW.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d9c5918..3d3e402 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3522,8 +3522,10 @@ static void gen8_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
/* WaDisablePwrmtrEvent:chv (pre-production hw) */
- I915_WRITE(0xA80C, I915_READ(0xA80C) 0x00ff);
- I915_WRITE(0xA810, I915_READ(0xA810) 0xff00);
+ if (IS_CHERRYVIEW(dev)) {
+ I915_WRITE(0xA80C, I915_READ(0xA80C) 0x00ff);
+ I915_WRITE(0xA810, I915_READ(0xA810) 0xff00);
+ }
/* 5: Enable RPS */
I915_WRITE(GEN6_RP_CONTROL,
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915/bdw: Add Broadwell support for debugfs rps freq info
From: Tom O'Rourke Tom.O'rou...@intel.com
Add Broadwell support to i915_frequency_info
and extend i915_max|min_freq_get|set to (gen = 6).
v2: generalized support for i915_max|min_freq_get|set (Daniel).
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5858cbb..a75d57d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1027,7 +1027,9 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
MEMSTAT_VID_SHIFT);
seq_printf(m, Current P-state: %d\n,
(rgvstat MEMSTAT_PSTATE_MASK)
MEMSTAT_PSTATE_SHIFT);
- } else if ((IS_GEN6(dev) || IS_GEN7(dev)) !IS_VALLEYVIEW(dev)) {
+ } else if (IS_GEN6(dev)
+ || (IS_GEN7(dev) !IS_VALLEYVIEW(dev))
+ || IS_BROADWELL(dev)) {
u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -1046,7 +1048,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
reqf = I915_READ(GEN6_RPNSWREQ);
reqf = ~GEN6_TURBO_DISABLE;
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev))
reqf = 24;
else
reqf = 25;
@@ -1063,7 +1065,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev))
cagf = (rpstat HSW_CAGF_MASK) HSW_CAGF_SHIFT;
else
cagf = (rpstat GEN6_CAGF_MASK) GEN6_CAGF_SHIFT;
@@ -3500,7 +3502,7 @@ i915_max_freq_get(void *data, u64 *val)
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
- if (!(IS_GEN6(dev) || IS_GEN7(dev)))
+ if (INTEL_INFO(dev)-gen 6)
return -ENODEV;
flush_delayed_work(dev_priv-rps.delayed_resume_work);
@@ -3526,7 +3528,7 @@ i915_max_freq_set(void *data, u64 val)
u32 rp_state_cap, hw_max, hw_min;
int ret;
- if (!(IS_GEN6(dev) || IS_GEN7(dev)))
+ if (INTEL_INFO(dev)-gen 6)
return -ENODEV;
flush_delayed_work(dev_priv-rps.delayed_resume_work);
@@ -3581,7 +3583,7 @@ i915_min_freq_get(void *data, u64 *val)
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
- if (!(IS_GEN6(dev) || IS_GEN7(dev)))
+ if (INTEL_INFO(dev)-gen 6)
return -ENODEV;
flush_delayed_work(dev_priv-rps.delayed_resume_work);
@@ -3607,7 +3609,7 @@ i915_min_freq_set(void *data, u64 val)
u32 rp_state_cap, hw_max, hw_min;
int ret;
- if (!(IS_GEN6(dev) || IS_GEN7(dev)))
+ if (INTEL_INFO(dev)-gen 6)
return -ENODEV;
flush_delayed_work(dev_priv-rps.delayed_resume_work);
--
1.7.9.5
___
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[Intel-gfx] [PATCH] drm/i915/bdw: Add Broadwell support for debugfs rps freq info
From: Tom O'Rourke Tom.O'rou...@intel.com
Add Broadwell support to i915_frequency_info and i915_max|min_freq_get|set.
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 333dd12..4d3b7a4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1027,7 +1027,9 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
MEMSTAT_VID_SHIFT);
seq_printf(m, Current P-state: %d\n,
(rgvstat MEMSTAT_PSTATE_MASK)
MEMSTAT_PSTATE_SHIFT);
- } else if ((IS_GEN6(dev) || IS_GEN7(dev)) !IS_VALLEYVIEW(dev)) {
+ } else if (IS_GEN6(dev)
+ || (IS_GEN7(dev) !IS_VALLEYVIEW(dev))
+ || IS_BROADWELL(dev)) {
u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -1046,7 +1048,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
reqf = I915_READ(GEN6_RPNSWREQ);
reqf = ~GEN6_TURBO_DISABLE;
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev))
reqf = 24;
else
reqf = 25;
@@ -1063,7 +1065,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev))
cagf = (rpstat HSW_CAGF_MASK) HSW_CAGF_SHIFT;
else
cagf = (rpstat GEN6_CAGF_MASK) GEN6_CAGF_SHIFT;
@@ -3500,7 +3502,7 @@ i915_max_freq_get(void *data, u64 *val)
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
- if (!(IS_GEN6(dev) || IS_GEN7(dev)))
+ if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)))
return -ENODEV;
flush_delayed_work(dev_priv-rps.delayed_resume_work);
@@ -3526,7 +3528,7 @@ i915_max_freq_set(void *data, u64 val)
u32 rp_state_cap, hw_max, hw_min;
int ret;
- if (!(IS_GEN6(dev) || IS_GEN7(dev)))
+ if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)))
return -ENODEV;
flush_delayed_work(dev_priv-rps.delayed_resume_work);
@@ -3581,7 +3583,7 @@ i915_min_freq_get(void *data, u64 *val)
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
- if (!(IS_GEN6(dev) || IS_GEN7(dev)))
+ if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)))
return -ENODEV;
flush_delayed_work(dev_priv-rps.delayed_resume_work);
@@ -3607,7 +3609,7 @@ i915_min_freq_set(void *data, u64 val)
u32 rp_state_cap, hw_max, hw_min;
int ret;
- if (!(IS_GEN6(dev) || IS_GEN7(dev)))
+ if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)))
return -ENODEV;
flush_delayed_work(dev_priv-rps.delayed_resume_work);
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915/bdw: Use timeout mode for RC6 on bdw
Higher RC6 residency is observed using timeout mode instead of EI mode. This applies to Broadwell only. The difference is particularly noticeable with video playback. Issue: VIZ-3778 Change-Id: I62bb12e21caf19651034826b45cde7f73a80938d Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 33b2592..0d63abf 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3335,15 +3335,23 @@ static void gen8_enable_rps(struct drm_device *dev) for_each_ring(ring, dev_priv, unused) I915_WRITE(RING_MAX_IDLE(ring-mmio_base), 10); I915_WRITE(GEN6_RC_SLEEP, 0); - I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */ + if (IS_BROADWELL(dev)) + I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ + else + I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */ /* 3: Enable RC6 */ if (intel_enable_rc6(dev) INTEL_RC6_ENABLE) rc6_mask = GEN6_RC_CTL_RC6_ENABLE; intel_print_rc6_info(dev, rc6_mask); - I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | - GEN6_RC_CTL_EI_MODE(1) | - rc6_mask); + if (IS_BROADWELL(dev)) + I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | + GEN7_RC_CTL_TO_MODE | + rc6_mask); + else + I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | + GEN6_RC_CTL_EI_MODE(1) | + rc6_mask); /* 4 Program defaults and thresholds for RPS*/ I915_WRITE(GEN6_RPNSWREQ, -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Finish enabling rps before use by sysfs or debugfs
From: Tom O'Rourke Tom.O'rou...@intel.com
Enabling rps (turbo setup) was put in a work queue because it may
take quite awhile. This change flushes the work queue to initialize
rps values before use by sysfs or debugfs. Specifically,
rps.delayed_resume_work is flushed before using rps.hw_max,
rps.max_delay, rps.min_delay, or rps.cur_delay.
This change fixes a problem in sysfs where show functions using
uninitialized values show incorrect values and store functions
using uninitialized values in range checks incorrectly fail to
store valid input values. This change also addresses similar use
before initialized problems in debugfs.
Change-Id: Ib9c4f2066b65013094cb9278fc17958a964836e7
Signed-off-by: Tom O'Rourke Tom.O'rou...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 12
drivers/gpu/drm/i915/i915_sysfs.c | 10 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1d77624..52e90a1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -843,6 +843,8 @@ static int i915_cur_delayinfo(struct seq_file *m, void
*unused)
drm_i915_private_t *dev_priv = dev-dev_private;
int ret;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
if (IS_GEN5(dev)) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -1321,6 +1323,8 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
return 0;
}
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
ret = mutex_lock_interruptible(dev_priv-rps.hw_lock);
if (ret)
return ret;
@@ -1972,6 +1976,8 @@ i915_max_freq_get(void *data, u64 *val)
if (!(IS_GEN6(dev) || IS_GEN7(dev)))
return -ENODEV;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
ret = mutex_lock_interruptible(dev_priv-rps.hw_lock);
if (ret)
return ret;
@@ -1996,6 +2002,8 @@ i915_max_freq_set(void *data, u64 val)
if (!(IS_GEN6(dev) || IS_GEN7(dev)))
return -ENODEV;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
DRM_DEBUG_DRIVER(Manually setting max freq to %llu\n, val);
ret = mutex_lock_interruptible(dev_priv-rps.hw_lock);
@@ -2034,6 +2042,8 @@ i915_min_freq_get(void *data, u64 *val)
if (!(IS_GEN6(dev) || IS_GEN7(dev)))
return -ENODEV;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
ret = mutex_lock_interruptible(dev_priv-rps.hw_lock);
if (ret)
return ret;
@@ -2058,6 +2068,8 @@ i915_min_freq_set(void *data, u64 val)
if (!(IS_GEN6(dev) || IS_GEN7(dev)))
return -ENODEV;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
DRM_DEBUG_DRIVER(Manually setting min freq to %llu\n, val);
ret = mutex_lock_interruptible(dev_priv-rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index d572435..270892b 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -213,6 +213,8 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
mutex_lock(dev_priv-rps.hw_lock);
if (IS_VALLEYVIEW(dev_priv-dev)) {
u32 freq;
@@ -245,6 +247,8 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev,
struct device_attribute
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
mutex_lock(dev_priv-rps.hw_lock);
if (IS_VALLEYVIEW(dev_priv-dev))
ret = vlv_gpu_freq(dev_priv-mem_freq, dev_priv-rps.max_delay);
@@ -269,6 +273,8 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
if (ret)
return ret;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
mutex_lock(dev_priv-rps.hw_lock);
if (IS_VALLEYVIEW(dev_priv-dev)) {
@@ -317,6 +323,8 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev,
struct device_attribute
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
mutex_lock(dev_priv-rps.hw_lock);
if (IS_VALLEYVIEW(dev_priv-dev))
ret = vlv_gpu_freq(dev_priv-mem_freq, dev_priv-rps.min_delay);
@@ -341,6 +349,8 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
if (ret)
return ret;
+ flush_delayed_work(dev_priv-rps.delayed_resume_work);
+
mutex_lock(dev_priv-rps.hw_lock);
if (IS_VALLEYVIEW(dev)) {
--
1.7.9.5
