[Intel-gfx] [PATCH v5 2/2] drm/i915: Add lmem_bar_size modparam
From: Priyanka Dandamudi
For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild.
v2: Update commit message and a minor modification.(Matt)
v3: Optimised lmem bar size code and modified code to resize
bar maximum upto lmem_size instead of maximum supported size.(Nirmoy)
v4: Optimised lmem bar size code.(Nirmoy)
Cc: Matthew Auld
Cc: Nirmoy Das
Signed-off-by: Priyanka Dandamudi
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 34 ++---
drivers/gpu/drm/i915/i915_params.c | 2 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
3 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 72491ba9e72f..5ee6982248d4 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -51,15 +51,39 @@ static void i915_resize_lmem_bar(struct drm_i915_private
*i915, resource_size_t
struct pci_bus *root = pdev->bus;
struct resource *root_res;
resource_size_t rebar_size;
+ resource_size_t current_size;
u32 pci_cmd;
int i;
- rebar_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
+ current_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
- if (rebar_size != roundup_pow_of_two(lmem_size))
- rebar_size = lmem_size;
- else
- return;
+ if (i915->params.lmem_bar_size) {
+ u32 bar_sizes;
+
+ rebar_size = i915->params.lmem_bar_size *
+ (resource_size_t)SZ_1M;
+ bar_sizes = pci_rebar_get_possible_sizes(pdev,
+LMEM_BAR_NUM);
+
+ if (rebar_size == current_size)
+ return;
+
+ if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
+ rebar_size >= roundup_pow_of_two(lmem_size)) {
+ rebar_size = lmem_size;
+
+ drm_info(&i915->drm,
+"Given bar size is not within supported
size,setting it to default: %llu\n",
+(u64)lmem_size >> 20);
+ }
+ } else {
+ rebar_size = current_size;
+
+ if (rebar_size != roundup_pow_of_two(lmem_size))
+ rebar_size = lmem_size;
+ else
+ return;
+ }
/* Find out if root bus contains 64bit memory addressing */
while (root->parent)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default:
0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+ "Set the lmem bar size(in MiB).");
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms,
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
+ param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
--
2.27.0
[Intel-gfx] [PATCH v5 1/2] drm/i915: Add support for LMEM PCIe resizable bar
From: Akeem G Abodunrin
Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.
v2:Moved code to gt/intel_region_lmem.c and used only
single underscore for function names.(Jani)
v3: Optimised code.
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Michał Winiarski
Cc: Stuart Summers
Cc: Michael J Ruhl
Cc: Prathap Kumar Valsan
Cc: Jani Nikula
Signed-off-by: Priyanka Dandamudi
Reviewed-by: Matthew Auld
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 75 +
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fa7b86f83e7b..72491ba9e72f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,6 +15,79 @@
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
+static void _release_bars(struct pci_dev *pdev)
+{
+ int resno;
+
+ for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+ if (pci_resource_len(pdev, resno))
+ pci_release_resource(pdev, resno);
+ }
+}
+
+static void
+_resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ int bar_size = pci_rebar_bytes_to_size(size);
+ int ret;
+
+ _release_bars(pdev);
+
+ ret = pci_resize_resource(pdev, resno, bar_size);
+ if (ret) {
+ drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+ return;
+ }
+
+ drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915,
resource_size_t lmem_size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_bus *root = pdev->bus;
+ struct resource *root_res;
+ resource_size_t rebar_size;
+ u32 pci_cmd;
+ int i;
+
+ rebar_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
+
+ if (rebar_size != roundup_pow_of_two(lmem_size))
+ rebar_size = lmem_size;
+ else
+ return;
+
+ /* Find out if root bus contains 64bit memory addressing */
+ while (root->parent)
+ root = root->parent;
+
+ pci_bus_for_each_resource(root, root_res, i) {
+ if (root_res && root_res->flags & (IORESOURCE_MEM |
+ IORESOURCE_MEM_64) &&
upper_32_bits(root_res->start) != 0)
+ break;
+ }
+
+ /* pci_resize_resource will fail anyways */
+ if (!root_res) {
+ drm_info(&i915->drm, "Can't resize LMEM BAR - platform support
is missing\n");
+ return;
+ }
+
+ /* First disable PCI memory decoding references */
+ pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+ pci_write_config_dword(pdev, PCI_COMMAND,
+ pci_cmd & ~PCI_COMMAND_MEMORY);
+
+ _resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+ pci_assign_unassigned_bus_resources(pdev->bus);
+ pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
static int
region_lmem_release(struct intel_memory_region *mem)
{
@@ -128,6 +201,8 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
}
+ i915_resize_lmem_bar(i915, lmem_size);
+
if (i915->params.lmem_size > 0) {
lmem_size = min_t(resource_size_t, lmem_size,
mul_u32_u32(i915->params.lmem_size, SZ_1M));
--
2.27.0
[Intel-gfx] [PATCH v5 0/2] Add support for LMEM PCIe resizable bar
From: Priyanka Dandamudi Added support to resize the bar to maximum supported. Also, added new modparam lmem_bar_size which can resize the bar to one of the supported sizes. Akeem G Abodunrin (1): drm/i915: Add support for LMEM PCIe resizable bar Priyanka Dandamudi (1): drm/i915: Add lmem_bar_size modparam drivers/gpu/drm/i915/gt/intel_region_lmem.c | 99 + drivers/gpu/drm/i915/i915_params.c | 2 + drivers/gpu/drm/i915/i915_params.h | 1 + 3 files changed, 102 insertions(+) -- 2.27.0
[Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for LMEM PCIe resizable bar
From: Akeem G Abodunrin
Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.
v2:Moved code to gt/intel_region_lmem.c and used only
single underscore for function names.(Jani)
v3: Optimised code.
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Michał Winiarski
Cc: Stuart Summers
Cc: Michael J Ruhl
Cc: Prathap Kumar Valsan
Cc: Jani Nikula
Signed-off-by: Priyanka Dandamudi
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 75 +
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fa7b86f83e7b..129e5d8b080d 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,6 +15,79 @@
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
+static void _release_bars(struct pci_dev *pdev)
+{
+ int resno;
+
+ for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+ if (pci_resource_len(pdev, resno))
+ pci_release_resource(pdev, resno);
+ }
+}
+
+static void
+_resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ int bar_size = pci_rebar_bytes_to_size(size);
+ int ret;
+
+ _release_bars(pdev);
+
+ ret = pci_resize_resource(pdev, resno, bar_size);
+ if (ret) {
+ drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+ return;
+ }
+
+ drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915,
resource_size_t lmem_size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_bus *root = pdev->bus;
+ struct resource *root_res;
+ resource_size_t rebar_size;
+ u32 pci_cmd;
+ int i;
+
+ rebar_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
+
+ if (rebar_size != roundup_pow_of_two(lmem_size))
+ rebar_size = lmem_size;
+ else
+ return;
+
+ /* Find out if root bus contains 64bit memory addressing */
+ while (root->parent)
+ root = root->parent;
+
+ pci_bus_for_each_resource(root, root_res, i) {
+ if (root_res && root_res->flags & (IORESOURCE_MEM |
+ IORESOURCE_MEM_64) && root_res->start >
0x1ull)
+ break;
+ }
+
+ /* pci_resize_resource will fail anyways */
+ if (!root_res) {
+ drm_info(&i915->drm, "Can't resize LMEM BAR - platform support
is missing\n");
+ return;
+ }
+
+ /* First disable PCI memory decoding references */
+ pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+ pci_write_config_dword(pdev, PCI_COMMAND,
+ pci_cmd & ~PCI_COMMAND_MEMORY);
+
+ _resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+ pci_assign_unassigned_bus_resources(pdev->bus);
+ pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
static int
region_lmem_release(struct intel_memory_region *mem)
{
@@ -128,6 +201,8 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
}
+ i915_resize_lmem_bar(i915, lmem_size);
+
if (i915->params.lmem_size > 0) {
lmem_size = min_t(resource_size_t, lmem_size,
mul_u32_u32(i915->params.lmem_size, SZ_1M));
--
2.27.0
[Intel-gfx] [PATCH v4 2/2] drm/i915: Add lmem_bar_size modparam
From: Priyanka Dandamudi
For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild.
v2: Update commit message and a minor modification.(Matt)
v3: Optimised lmem bar size code and modified code to resize
bar maximum upto lmem_size instead of maximum supported size.(Nirmoy)
v4: Optimised lmem bar size code.(Nirmoy)
Cc: Matthew Auld
Cc: Nirmoy Das
Signed-off-by: Priyanka Dandamudi
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 33 +
drivers/gpu/drm/i915/i915_params.c | 2 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
3 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 129e5d8b080d..22dbf986217c 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -51,15 +51,38 @@ static void i915_resize_lmem_bar(struct drm_i915_private
*i915, resource_size_t
struct pci_bus *root = pdev->bus;
struct resource *root_res;
resource_size_t rebar_size;
+ resource_size_t current_size;
u32 pci_cmd;
int i;
- rebar_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
+ current_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
- if (rebar_size != roundup_pow_of_two(lmem_size))
- rebar_size = lmem_size;
- else
- return;
+ if (i915->params.lmem_bar_size) {
+ u32 bar_sizes;
+
+ rebar_size = i915->params.lmem_bar_size *
+ (resource_size_t)SZ_1M;
+ bar_sizes = pci_rebar_get_possible_sizes(pdev,
+LMEM_BAR_NUM);
+
+ if (rebar_size == current_size)
+ return;
+
+ if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
+ rebar_size >= roundup_pow_of_two(lmem_size)) {
+ rebar_size = lmem_size;
+
+ drm_info(&i915->drm, "Given bar size is not
within supported size,"
+"setting it to default:
%llu\n", lmem_size);
+ }
+ } else {
+ rebar_size = current_size;
+
+ if (rebar_size != roundup_pow_of_two(lmem_size))
+ rebar_size = lmem_size;
+ else
+ return;
+ }
/* Find out if root bus contains 64bit memory addressing */
while (root->parent)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default:
0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+ "Set the lmem bar size(in MiB).");
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms,
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
+ param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
--
2.27.0
[Intel-gfx] [PATCH v4 0/2] Add support for LMEM PCIe resizable bar
From: Priyanka Dandamudi Added support to resize the bar to maximum supported. Also, added new modparam lmem_bar_size which can resize the bar to one of the supported sizes. Akeem G Abodunrin (1): drm/i915: Add support for LMEM PCIe resizable bar Priyanka Dandamudi (1): drm/i915: Add lmem_bar_size modparam drivers/gpu/drm/i915/gt/intel_region_lmem.c | 98 + drivers/gpu/drm/i915/i915_params.c | 2 + drivers/gpu/drm/i915/i915_params.h | 1 + 3 files changed, 101 insertions(+) -- 2.27.0
[Intel-gfx] [PATCH v3 2/2] drm/i915: Add lmem_bar_size modparam
From: Priyanka Dandamudi
For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild.
v2: Update commit message and a minor modification.(Matt)
v3: Optimised lmem bar size code and modified code to resize
bar maximum upto lmem_size instead of maximum supported size.(Nirmoy)
Cc: Matthew Auld
Cc: Nirmoy Das
Signed-off-by: Priyanka Dandamudi
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 51 +++--
drivers/gpu/drm/i915/i915_params.c | 2 +
drivers/gpu/drm/i915/i915_params.h | 1 +
3 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 3e9ed395f408..2ed80c3f6064 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -14,6 +14,7 @@
#include "gt/intel_gt.h"
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
+#include "../../../pci/pci.h"
static void _release_bars(struct pci_dev *pdev)
{
@@ -44,38 +45,38 @@ _resize_bar(struct drm_i915_private *i915, int resno,
resource_size_t size)
drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
}
-/* BAR size starts from 1MB - 2^20 */
-#define BAR_SIZE_SHIFT 20
-static resource_size_t
-_lmem_rebar_size(struct drm_i915_private *i915, int resno)
-{
- struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
- u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
- resource_size_t size;
-
- if (!rebar)
- return 0;
-
- size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
-
- if (size <= pci_resource_len(pdev, resno))
- return 0;
-
- return size;
-}
-
#define LMEM_BAR_NUM 2
-static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+static void i915_resize_lmem_bar(struct drm_i915_private *i915,
resource_size_t lmem_size)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct pci_bus *root = pdev->bus;
struct resource *root_res;
- resource_size_t rebar_size = _lmem_rebar_size(i915, LMEM_BAR_NUM);
+ resource_size_t rebar_size;
+ resource_size_t current_size;
u32 pci_cmd;
int i;
- if (!rebar_size)
- return;
+ current_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
+
+ if (i915->params.lmem_bar_size) {
+ resource_size_t min_bar_size = pci_rebar_size_to_bytes
+ (__ffs(pci_rebar_get_possible_sizes(pdev,
LMEM_BAR_NUM)));
+
+ rebar_size =
pci_rebar_size_to_bytes(__fls(i915->params.lmem_bar_size));
+
+ if (rebar_size == current_size)
+ return;
+
+ if (rebar_size >= roundup_pow_of_two(lmem_size) || rebar_size <
min_bar_size)
+ rebar_size = lmem_size;
+ } else {
+ rebar_size = current_size;
+
+ if (rebar_size != roundup_pow_of_two(lmem_size))
+ rebar_size = lmem_size;
+ else
+ return;
+ }
/* Find out if root bus contains 64bit memory addressing */
while (root->parent)
@@ -217,7 +218,7 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
}
- i915_resize_lmem_bar(i915);
+ i915_resize_lmem_bar(i915, lmem_size);
if (i915->params.lmem_size > 0) {
lmem_size = min_t(resource_size_t, lmem_size,
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default:
0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+ "Set the lmem bar size(in MiB).");
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 040
[Intel-gfx] [PATCH v3 1/2] drm/i915: Add support for LMEM PCIe resizable bar
From: Akeem G Abodunrin
Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.
v2:Moved code to gt/intel_region_lmem.c and used only
single underscore for function names.(Jani)
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Michał Winiarski
Cc: Stuart Summers
Cc: Michael J Ruhl
Cc: Prathap Kumar Valsan
Cc: Jani Nikula
Signed-off-by: Priyanka Dandamudi
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 91 +
1 file changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index fa7b86f83e7b..3e9ed395f408 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -15,6 +15,95 @@
#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
+static void _release_bars(struct pci_dev *pdev)
+{
+ int resno;
+
+ for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+ if (pci_resource_len(pdev, resno))
+ pci_release_resource(pdev, resno);
+ }
+}
+
+static void
+_resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ int bar_size = pci_rebar_bytes_to_size(size);
+ int ret;
+
+ _release_bars(pdev);
+
+ ret = pci_resize_resource(pdev, resno, bar_size);
+ if (ret) {
+ drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+ return;
+ }
+
+ drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+_lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+ resource_size_t size;
+
+ if (!rebar)
+ return 0;
+
+ size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+ if (size <= pci_resource_len(pdev, resno))
+ return 0;
+
+ return size;
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_bus *root = pdev->bus;
+ struct resource *root_res;
+ resource_size_t rebar_size = _lmem_rebar_size(i915, LMEM_BAR_NUM);
+ u32 pci_cmd;
+ int i;
+
+ if (!rebar_size)
+ return;
+
+ /* Find out if root bus contains 64bit memory addressing */
+ while (root->parent)
+ root = root->parent;
+
+ pci_bus_for_each_resource(root, root_res, i) {
+ if (root_res && root_res->flags & (IORESOURCE_MEM |
+ IORESOURCE_MEM_64) && root_res->start >
0x1ull)
+ break;
+ }
+
+ /* pci_resize_resource will fail anyways */
+ if (!root_res) {
+ drm_info(&i915->drm, "Can't resize LMEM BAR - platform support
is missing\n");
+ return;
+ }
+
+ /* First disable PCI memory decoding references */
+ pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+ pci_write_config_dword(pdev, PCI_COMMAND,
+ pci_cmd & ~PCI_COMMAND_MEMORY);
+
+ _resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+ pci_assign_unassigned_bus_resources(pdev->bus);
+ pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
static int
region_lmem_release(struct intel_memory_region *mem)
{
@@ -128,6 +217,8 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
}
+ i915_resize_lmem_bar(i915);
+
if (i915->params.lmem_size > 0) {
lmem_size = min_t(resource_size_t, lmem_size,
mul_u32_u32(i915->params.lmem_size, SZ_1M));
--
2.27.0
[Intel-gfx] [PATCH v3 0/2] Add support for LMEM PCIe resizable bar
From: Priyanka Dandamudi Added support to resize the bar to maximum supported. Also, added new modparam lmem_bar_size which can resize the bar to one of the supported sizes. Akeem G Abodunrin (1): drm/i915: Add support for LMEM PCIe resizable bar Priyanka Dandamudi (1): drm/i915: Add lmem_bar_size modparam drivers/gpu/drm/i915/gt/intel_region_lmem.c | 92 + drivers/gpu/drm/i915/i915_params.c | 2 + drivers/gpu/drm/i915/i915_params.h | 1 + 3 files changed, 95 insertions(+) -- 2.27.0
[Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam
From: Priyanka Dandamudi
For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild.
v2: Update commit message and a minor modification.(Matt)
Cc: Matthew Auld
Signed-off-by: Priyanka Dandamudi
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 +++
drivers/gpu/drm/i915/i915_driver.c | 28 -
drivers/gpu/drm/i915/i915_params.c | 2 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
4 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index e9c12e0d6f59..4614c30f878f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -111,6 +111,10 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
flat_ccs_base = intel_gt_read_register(gt,
XEHPSDV_FLAT_CCS_BASE_ADDR);
flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) *
SZ_64K;
+ /* XXX: Remove this once we have small-bar uapi bits */
+ if (i915->params.lmem_bar_size > 0)
+ lmem_size = pci_resource_len(pdev, 2);
+
/* FIXME: Remove this when we have small-bar enabled */
if (pci_resource_len(pdev, 2) < lmem_size) {
drm_err(&i915->drm, "System requires small-BAR support,
which is currently unsupported on this kernel\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 4bdb471cb2e2..b2763b032012 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -362,8 +362,34 @@ static void i915_resize_lmem_bar(struct drm_i915_private
*i915)
u32 pci_cmd;
int i;
- if (!rebar_size)
+ if (i915->params.lmem_bar_size > 0) {
+ u32 lmem_bar_size;
+ u32 set_bit;
+ u32 rebar;
+ u32 msb;
+ int k;
+
+ lmem_bar_size = i915->params.lmem_bar_size;
+ rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
+ msb = __fls(rebar);
+
+ for (k = msb; k >= 0; k--) {
+ set_bit = (1 << k);
+
+ if (set_bit & rebar) {
+ if (set_bit == lmem_bar_size) {
+ rebar_size = 1ULL <<
(__fls(lmem_bar_size) +
+ BAR_SIZE_SHIFT);
+
+ if (rebar_size ==
pci_resource_len(pdev, LMEM_BAR_NUM))
+ return;
+ break;
+ }
+ }
+ }
+ } else if (!rebar_size) {
return;
+ }
/* Find out if root bus contains 64bit memory addressing */
while (root->parent)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default:
0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+ "Set the lmem bar size(in MiB).");
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms,
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
+ param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
--
2.25.1
[Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar
From: Priyanka Dandamudi Added support to resize the bar to maximum supported. Also, added new modparam lmem_bar_size which can resize the bar to one of the supported sizes. Akeem G Abodunrin (1): drm/i915: Add support for LMEM PCIe resizable bar Priyanka Dandamudi (1): drm/i915: Add lmem_bar_size modparam drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 + drivers/gpu/drm/i915/i915_driver.c | 118 drivers/gpu/drm/i915/i915_params.c | 2 + drivers/gpu/drm/i915/i915_params.h | 1 + 4 files changed, 125 insertions(+) -- 2.25.1
[Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
From: Akeem G Abodunrin
Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Michał Winiarski
Cc: Stuart Summers
Cc: Michael J Ruhl
Cc: Prathap Kumar Valsan
Signed-off-by: Priyanka Dandamudi
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_driver.c | 92 ++
1 file changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..4bdb471cb2e2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
}
+static void __release_bars(struct pci_dev *pdev)
+{
+ int resno;
+
+ for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+ if (pci_resource_len(pdev, resno))
+ pci_release_resource(pdev, resno);
+ }
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ int bar_size = pci_rebar_bytes_to_size(size);
+ int ret;
+
+ __release_bars(pdev);
+
+ ret = pci_resize_resource(pdev, resno, bar_size);
+ if (ret) {
+ drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+ return;
+ }
+
+ drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+ resource_size_t size;
+
+ if (!rebar)
+ return 0;
+
+ size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+ if (size <= pci_resource_len(pdev, resno))
+ return 0;
+
+ return size;
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_bus *root = pdev->bus;
+ struct resource *root_res;
+ resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+ u32 pci_cmd;
+ int i;
+
+ if (!rebar_size)
+ return;
+
+ /* Find out if root bus contains 64bit memory addressing */
+ while (root->parent)
+ root = root->parent;
+
+ pci_bus_for_each_resource(root, root_res, i) {
+ if (root_res && root_res->flags & (IORESOURCE_MEM |
+ IORESOURCE_MEM_64) && root_res->start >
0x1ull)
+ break;
+ }
+
+ /* pci_resize_resource will fail anyways */
+ if (!root_res) {
+ drm_info(&i915->drm, "Can't resize LMEM BAR - platform support
is missing\n");
+ return;
+ }
+
+ /* First disable PCI memory decoding references */
+ pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+ pci_write_config_dword(pdev, PCI_COMMAND,
+ pci_cmd & ~PCI_COMMAND_MEMORY);
+
+ __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+ pci_assign_unassigned_bus_resources(pdev->bus);
+ pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
/**
* i915_driver_early_probe - setup state not requiring device access
* @dev_priv: device private
@@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
disable_rpm_wakeref_asserts(&i915->runtime_pm);
+ if (HAS_LMEM(i915))
+ i915_resize_lmem_bar(i915);
+
intel_vgpu_detect(i915);
ret = intel_gt_probe_all(i915);
--
2.25.1
[Intel-gfx] [PATCH i-g-t 2/2] drm/i915: Add lmem_bar_size modparam
From: Priyanka Dandamudi
For testing purposes, support forcing the lmem_bar_size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild.
v2: Minor correction.(Matt)
Cc: Matthew Auld
Signed-off-by: Priyanka Dandamudi
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 +++
drivers/gpu/drm/i915/i915_driver.c | 28 -
drivers/gpu/drm/i915/i915_params.c | 2 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
4 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index e9c12e0d6f59..4614c30f878f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -111,6 +111,10 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
flat_ccs_base = intel_gt_read_register(gt,
XEHPSDV_FLAT_CCS_BASE_ADDR);
flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) *
SZ_64K;
+ /* XXX: Remove this once we have small-bar uapi bits */
+ if (i915->params.lmem_bar_size > 0)
+ lmem_size = pci_resource_len(pdev, 2);
+
/* FIXME: Remove this when we have small-bar enabled */
if (pci_resource_len(pdev, 2) < lmem_size) {
drm_err(&i915->drm, "System requires small-BAR support,
which is currently unsupported on this kernel\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 4bdb471cb2e2..b2763b032012 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -362,8 +362,34 @@ static void i915_resize_lmem_bar(struct drm_i915_private
*i915)
u32 pci_cmd;
int i;
- if (!rebar_size)
+ if (i915->params.lmem_bar_size > 0) {
+ u32 lmem_bar_size;
+ u32 set_bit;
+ u32 rebar;
+ u32 msb;
+ int k;
+
+ lmem_bar_size = i915->params.lmem_bar_size;
+ rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
+ msb = __fls(rebar);
+
+ for (k = msb; k >= 0; k--) {
+ set_bit = (1 << k);
+
+ if (set_bit & rebar) {
+ if (set_bit == lmem_bar_size) {
+ rebar_size = 1ULL <<
(__fls(lmem_bar_size) +
+ BAR_SIZE_SHIFT);
+
+ if (rebar_size ==
pci_resource_len(pdev, LMEM_BAR_NUM))
+ return;
+ break;
+ }
+ }
+ }
+ } else if (!rebar_size) {
return;
+ }
/* Find out if root bus contains 64bit memory addressing */
while (root->parent)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default:
0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+ "Set the lmem bar size(in MiB).");
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms,
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
+ param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
--
2.25.1
[Intel-gfx] [PATCH i-g-t 1/2] drm/i915: Add support for LMEM PCIe resizable bar
From: Akeem G Abodunrin
This patch adds support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Michał Winiarski
Cc: Stuart Summers
Cc: Michael J Ruhl
Cc: Prathap Kumar Valsan
Signed-off-by: Priyanka Dandamudi
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_driver.c | 92 ++
1 file changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..4bdb471cb2e2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
}
+static void __release_bars(struct pci_dev *pdev)
+{
+ int resno;
+
+ for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+ if (pci_resource_len(pdev, resno))
+ pci_release_resource(pdev, resno);
+ }
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ int bar_size = pci_rebar_bytes_to_size(size);
+ int ret;
+
+ __release_bars(pdev);
+
+ ret = pci_resize_resource(pdev, resno, bar_size);
+ if (ret) {
+ drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+ return;
+ }
+
+ drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+ resource_size_t size;
+
+ if (!rebar)
+ return 0;
+
+ size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+ if (size <= pci_resource_len(pdev, resno))
+ return 0;
+
+ return size;
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_bus *root = pdev->bus;
+ struct resource *root_res;
+ resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+ u32 pci_cmd;
+ int i;
+
+ if (!rebar_size)
+ return;
+
+ /* Find out if root bus contains 64bit memory addressing */
+ while (root->parent)
+ root = root->parent;
+
+ pci_bus_for_each_resource(root, root_res, i) {
+ if (root_res && root_res->flags & (IORESOURCE_MEM |
+ IORESOURCE_MEM_64) && root_res->start >
0x1ull)
+ break;
+ }
+
+ /* pci_resize_resource will fail anyways */
+ if (!root_res) {
+ drm_info(&i915->drm, "Can't resize LMEM BAR - platform support
is missing\n");
+ return;
+ }
+
+ /* First disable PCI memory decoding references */
+ pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+ pci_write_config_dword(pdev, PCI_COMMAND,
+ pci_cmd & ~PCI_COMMAND_MEMORY);
+
+ __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+ pci_assign_unassigned_bus_resources(pdev->bus);
+ pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
/**
* i915_driver_early_probe - setup state not requiring device access
* @dev_priv: device private
@@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
disable_rpm_wakeref_asserts(&i915->runtime_pm);
+ if (HAS_LMEM(i915))
+ i915_resize_lmem_bar(i915);
+
intel_vgpu_detect(i915);
ret = intel_gt_probe_all(i915);
--
2.25.1
[Intel-gfx] [PATCH i-g-t 0/2] Add support for LMEM PCIe resizable bar
From: Priyanka Dandamudi Added support to resize the bar to maximum supported. Also, added new modparam lmem_bar_size which can resize the bar to one of the supported sizes. Akeem G Abodunrin (1): drm/i915: Add support for LMEM PCIe resizable bar Priyanka Dandamudi (1): drm/i915: Add lmem_bar_size modparam drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 + drivers/gpu/drm/i915/i915_driver.c | 118 drivers/gpu/drm/i915/i915_params.c | 2 + drivers/gpu/drm/i915/i915_params.h | 1 + 4 files changed, 125 insertions(+) -- 2.25.1
[Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam
From: Priyanka Dandamudi
lmem_bar_size is used to resize lmem bar.
It sets to only one of the supported sizes.
Setting this param will be in MB unit.
Cc: Matthew Auld
Signed-off-by: Priyanka Dandamudi
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 +++
drivers/gpu/drm/i915/i915_driver.c | 25 -
drivers/gpu/drm/i915/i915_params.c | 2 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
4 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 119e53f5d9b1..d73d8b2adfa2 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -132,6 +132,9 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
mul_u32_u32(i915->params.lmem_size, SZ_1M));
}
+ if (i915->params.lmem_bar_size > 0)
+ lmem_size = pci_resource_len(pdev, 2);
+
io_start = pci_resource_start(pdev, 2);
io_size = min(pci_resource_len(pdev, 2), lmem_size);
if (!io_size)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 8d33a6a31675..2f5d7a1f1a7b 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -371,7 +371,30 @@ static void i915_resize_lmem_bar(struct drm_i915_private
*i915)
u32 pci_cmd;
int i;
- if (!rebar_size)
+ if (i915->params.lmem_bar_size > 0) {
+ u32 lmem_bar_size;
+ u32 set_bit;
+ u32 rebar;
+ u32 msb;
+ int k;
+
+ lmem_bar_size = i915->params.lmem_bar_size;
+ rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
+ msb = __fls(rebar);
+
+ for (k = msb; k >= 0; k--) {
+ set_bit = (1 << k);
+
+ if (set_bit & rebar)
+ if (set_bit == lmem_bar_size) {
+ rebar_size = 1ULL <<
(__fls(lmem_bar_size) + BAR_SIZE_SHIFT);
+
+ if (rebar_size ==
pci_resource_len(pdev, LMEM_BAR_NUM))
+ return;
+ break;
+ }
+ }
+ } else if (!rebar_size)
return;
/* Find out if root bus contains 64bit memory addressing */
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default:
0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+ "Set the lmem bar size(in MiB).");
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms,
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
+ param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
--
2.27.0
[Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
From: Akeem G Abodunrin
This patch adds support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Michał Winiarski
Cc: Stuart Summers
Cc: Michael J Ruhl
Cc: Prathap Kumar Valsan
Signed-off-by: Priyanka Dandamudi
---
drivers/gpu/drm/i915/i915_driver.c | 103 +
1 file changed, 103 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index b47746152d97..8d33a6a31675 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,106 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
}
+static void __release_bars(struct pci_dev *pdev)
+{
+ int resno;
+
+ for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+ if (pci_resource_len(pdev, resno))
+ pci_release_resource(pdev, resno);
+ }
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ int bar_size = pci_rebar_bytes_to_size(size);
+ int ret;
+
+ __release_bars(pdev);
+
+ ret = pci_resize_resource(pdev, resno, bar_size);
+ if (ret) {
+ drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+resno, 1 << bar_size, ERR_PTR(ret));
+ return;
+ }
+
+ drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+ resource_size_t size;
+
+ if (!rebar)
+ return 0;
+
+ size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+ if (size <= pci_resource_len(pdev, resno))
+ return 0;
+
+ return size;
+}
+
+/**
+ * i915_resize_lmem_bar - resize local memory BAR
+ * @i915: device private
+ *
+ * This function will attempt to resize LMEM bar to make all memory accessible.
+ * Whether it will be successful depends on both device and platform
+ * capabilities. Any errors are non-critical, even if resize fails, we go back
+ * to the previous configuration.
+ */
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_bus *root = pdev->bus;
+ struct resource *root_res;
+ resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+ u32 pci_cmd;
+ int i;
+
+ if (!rebar_size)
+ return;
+
+ /* Find out if root bus contains 64bit memory addressing */
+ while (root->parent)
+ root = root->parent;
+
+ pci_bus_for_each_resource(root, root_res, i) {
+ if (root_res &&
+ root_res->flags & (IORESOURCE_MEM |
IORESOURCE_MEM_64) &&
+ root_res->start > 0x1ull)
+ break;
+ }
+
+ /* pci_resize_resource will fail anyways */
+ if (!root_res) {
+ drm_info(&i915->drm,
+ "Can't resize LMEM BAR - platform support is
missing\n");
+ return;
+ }
+
+ /* First disable PCI memory decoding references */
+ pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+ pci_write_config_dword(pdev, PCI_COMMAND,
+ pci_cmd & ~PCI_COMMAND_MEMORY);
+
+ __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+ pci_assign_unassigned_bus_resources(pdev->bus);
+ pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
/**
* i915_driver_early_probe - setup state not requiring device access
* @dev_priv: device private
@@ -836,6 +936,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
disable_rpm_wakeref_asserts(&i915->runtime_pm);
+ if (HAS_LMEM(i915))
+ i915_resize_lmem_bar(i915);
+
intel_vgpu_detect(i915);
ret = intel_gt_probe_all(i915);
--
2.27.0
[Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar
From: Priyanka Dandamudi Added support to resize the bar to maximum supported, only when bar is not set to maximum by default. Also, added new modparam lmem_bar_size which can resize the bar provided if it is among the supported sizes. Akeem G Abodunrin (1): drm/i915: Add support for LMEM PCIe resizable bar Priyanka Dandamudi (1): drm/i915: Add lmem_bar_size modparam drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 + drivers/gpu/drm/i915/i915_driver.c | 126 drivers/gpu/drm/i915/i915_params.c | 2 + drivers/gpu/drm/i915/i915_params.h | 1 + 4 files changed, 132 insertions(+) -- 2.27.0
