Re: [Intel-gfx] [CI] drm/i915: Split GPU commands definitions into separate header
On Wed, Mar 14, 2018 at 10:19:21AM +, Chris Wilson wrote: > Quoting Chris Wilson (2018-03-13 23:19:20) > > From: Michal Wajdeczko > > > > We should not mix MMIO with MI_INSTR definitions. > > > > v2: sanitize comment, change include order (Chris) > > > > Suggested-by: Chris Wilson > > Signed-off-by: Michal Wajdeczko > > Cc: Chris Wilson > > Reviewed-by: Chris Wilson > > Signed-off-by: Chris Wilson > > Link: > > https://patchwork.freedesktop.org/patch/msgid/20180313124109.39216-1-michal.wajdec...@intel.com > > Doesn't like it when I send it either? Very odd. Indeed. Same patch, different sender and it goes missing again. There is no parse error and when the patchwork is fed with the patch manually it goes through just fine. There's no sign of the patch ever reaching the server. Looks like it gets discarded somewhere on the way. Ccing Daniel, maybe he will be able to help with root causing. -- Cheers, Arek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI] drm/i915: Split GPU commands definitions into separate header
Quoting Chris Wilson (2018-03-13 23:19:20) > From: Michal Wajdeczko > > We should not mix MMIO with MI_INSTR definitions. > > v2: sanitize comment, change include order (Chris) > > Suggested-by: Chris Wilson > Signed-off-by: Michal Wajdeczko > Cc: Chris Wilson > Reviewed-by: Chris Wilson > Signed-off-by: Chris Wilson > Link: > https://patchwork.freedesktop.org/patch/msgid/20180313124109.39216-1-michal.wajdec...@intel.com Doesn't like it when I send it either? Very odd. > --- > drivers/gpu/drm/i915/i915_reg.h | 263 > drivers/gpu/drm/i915/intel_gpu_commands.h | 274 > ++ > drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +- > 3 files changed, 276 insertions(+), 264 deletions(-) > create mode 100644 drivers/gpu/drm/i915/intel_gpu_commands.h > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e8e912f08e22..756c865a13ba 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -430,145 +430,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define VGA_CR_INDEX_CGA 0x3d4 > #define VGA_CR_DATA_CGA 0x3d5 > > -/* > - * Instruction field definitions used by the command parser > - */ > -#define INSTR_CLIENT_SHIFT 29 > -#define INSTR_MI_CLIENT 0x0 > -#define INSTR_BC_CLIENT 0x2 > -#define INSTR_RC_CLIENT 0x3 > -#define INSTR_SUBCLIENT_SHIFT 27 > -#define INSTR_SUBCLIENT_MASK0x1800 > -#define INSTR_MEDIA_SUBCLIENT 0x2 > -#define INSTR_26_TO_24_MASK0x700 > -#define INSTR_26_TO_24_SHIFT 24 > - > -/* > - * Memory interface instructions used by the kernel > - */ > -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) > -/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ > -#define MI_GLOBAL_GTT(1<<22) > - > -#define MI_NOOPMI_INSTR(0, 0) > -#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) > -#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) > -#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) > -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) > -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) > -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) > -#define MI_FLUSH MI_INSTR(0x04, 0) > -#define MI_READ_FLUSH(1 << 0) > -#define MI_EXE_FLUSH (1 << 1) > -#define MI_NO_WRITE_FLUSH(1 << 2) > -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ > -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count > */ > -#define MI_INVALIDATE_ISP(1 << 5) /* invalidate indirect state > pointers */ > -#define MI_REPORT_HEAD MI_INSTR(0x07, 0) > -#define MI_ARB_ON_OFF MI_INSTR(0x08, 0) > -#define MI_ARB_ENABLE(1<<0) > -#define MI_ARB_DISABLE (0<<0) > -#define MI_BATCH_BUFFER_ENDMI_INSTR(0x0a, 0) > -#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) > -#define MI_SUSPEND_FLUSH_EN (1<<0) > -#define MI_SET_APPID MI_INSTR(0x0e, 0) > -#define MI_OVERLAY_FLIPMI_INSTR(0x11, 0) > -#define MI_OVERLAY_CONTINUE (0x0<<21) > -#define MI_OVERLAY_ON(0x1<<21) > -#define MI_OVERLAY_OFF (0x2<<21) > -#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) > -#define MI_DISPLAY_FLIPMI_INSTR(0x14, 2) > -#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) > -#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) > -/* IVB has funny definitions for which plane to flip. */ > -#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) > -#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) > -#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) > -#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) > -#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) > -#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) > -/* SKL ones */ > -#define MI_DISPLAY_FLIP_SKL_PLANE_1_A(0 << 8) > -#define MI_DISPLAY_FLIP_SKL_PLANE_1_B(1 << 8) > -#define MI_DISPLAY_FLIP_SKL_PLANE_1_C(2 << 8) > -#define MI_DISPLAY_FLIP_SKL_PLANE_2_A(4 << 8) > -#define MI_DISPLAY_FLIP_SKL_PLANE_2_B(5 << 8) > -#define MI_DISPLAY_FLIP_SKL_PLANE_2_C(6 << 8) > -#define MI_DISPLAY_FLIP_SKL_PLANE_3_A(7 << 8) > -#define MI_DISPLAY_FLIP_SKL_PLANE_3_B(8 << 8) > -#define MI_DISPLAY_FLIP_SKL_PLANE_3_C(9 << 8) > -#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ > -#define MI_SEMAPHORE_GLOBAL_GTT(1<<22) > -#define MI_SEMAPHORE_UPDATE (1<<21) > -#define MI_SEMAPHORE_COMPARE (1<<20) > -#define MI_SEMAPHORE_REGISTER(1<<18) > -#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ > -#define MI_SEMAPHORE_SYNC_VER(1<<16) /* RCS wait for VECS > (RVESYNC) */ > -#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ > -#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS
[Intel-gfx] [CI] drm/i915: Split GPU commands definitions into separate header
From: Michal Wajdeczko We should not mix MMIO with MI_INSTR definitions. v2: sanitize comment, change include order (Chris) Suggested-by: Chris Wilson Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20180313124109.39216-1-michal.wajdec...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 263 drivers/gpu/drm/i915/intel_gpu_commands.h | 274 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +- 3 files changed, 276 insertions(+), 264 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_gpu_commands.h diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e8e912f08e22..756c865a13ba 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -430,145 +430,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VGA_CR_INDEX_CGA 0x3d4 #define VGA_CR_DATA_CGA 0x3d5 -/* - * Instruction field definitions used by the command parser - */ -#define INSTR_CLIENT_SHIFT 29 -#define INSTR_MI_CLIENT 0x0 -#define INSTR_BC_CLIENT 0x2 -#define INSTR_RC_CLIENT 0x3 -#define INSTR_SUBCLIENT_SHIFT 27 -#define INSTR_SUBCLIENT_MASK0x1800 -#define INSTR_MEDIA_SUBCLIENT 0x2 -#define INSTR_26_TO_24_MASK0x700 -#define INSTR_26_TO_24_SHIFT 24 - -/* - * Memory interface instructions used by the kernel - */ -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) -/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ -#define MI_GLOBAL_GTT(1<<22) - -#define MI_NOOPMI_INSTR(0, 0) -#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) -#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) -#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) -#define MI_FLUSH MI_INSTR(0x04, 0) -#define MI_READ_FLUSH(1 << 0) -#define MI_EXE_FLUSH (1 << 1) -#define MI_NO_WRITE_FLUSH(1 << 2) -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ -#define MI_INVALIDATE_ISP(1 << 5) /* invalidate indirect state pointers */ -#define MI_REPORT_HEAD MI_INSTR(0x07, 0) -#define MI_ARB_ON_OFF MI_INSTR(0x08, 0) -#define MI_ARB_ENABLE(1<<0) -#define MI_ARB_DISABLE (0<<0) -#define MI_BATCH_BUFFER_ENDMI_INSTR(0x0a, 0) -#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) -#define MI_SUSPEND_FLUSH_EN (1<<0) -#define MI_SET_APPID MI_INSTR(0x0e, 0) -#define MI_OVERLAY_FLIPMI_INSTR(0x11, 0) -#define MI_OVERLAY_CONTINUE (0x0<<21) -#define MI_OVERLAY_ON(0x1<<21) -#define MI_OVERLAY_OFF (0x2<<21) -#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) -#define MI_DISPLAY_FLIPMI_INSTR(0x14, 2) -#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) -#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) -/* IVB has funny definitions for which plane to flip. */ -#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) -#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) -#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) -#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) -#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) -#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) -/* SKL ones */ -#define MI_DISPLAY_FLIP_SKL_PLANE_1_A(0 << 8) -#define MI_DISPLAY_FLIP_SKL_PLANE_1_B(1 << 8) -#define MI_DISPLAY_FLIP_SKL_PLANE_1_C(2 << 8) -#define MI_DISPLAY_FLIP_SKL_PLANE_2_A(4 << 8) -#define MI_DISPLAY_FLIP_SKL_PLANE_2_B(5 << 8) -#define MI_DISPLAY_FLIP_SKL_PLANE_2_C(6 << 8) -#define MI_DISPLAY_FLIP_SKL_PLANE_3_A(7 << 8) -#define MI_DISPLAY_FLIP_SKL_PLANE_3_B(8 << 8) -#define MI_DISPLAY_FLIP_SKL_PLANE_3_C(9 << 8) -#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ -#define MI_SEMAPHORE_GLOBAL_GTT(1<<22) -#define MI_SEMAPHORE_UPDATE (1<<21) -#define MI_SEMAPHORE_COMPARE (1<<20) -#define MI_SEMAPHORE_REGISTER(1<<18) -#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ -#define MI_SEMAPHORE_SYNC_VER(1<<16) /* RCS wait for VECS (RVESYNC) */ -#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ -#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ -#define MI_SEMAPHORE_SYNC_VEV(1<<16) /* VCS wait for VECS (VVESYNC) */ -#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ -#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ -#define MI_SEMAPHORE_SYNC_VEB(1<<16) /*
