subject:"\[Intel\-gfx\] \[CI 1\/2\] drm\/i915\/icl\: Add allowed DP rates for Icelake"

Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

2018-06-13 Thread Paulo Zanoni

Em Qua, 2018-06-13 às 13:15 -0700, Manasi Navare escreveu:
> On Wed, Jun 13, 2018 at 12:42:20PM -0700, Paulo Zanoni wrote:
> > Em Ter, 2018-06-12 às 11:37 -0700, Manasi Navare escreveu:
> > > On Tue, Jun 12, 2018 at 03:15:53PM +0300, Ville Syrjälä wrote:
> > > > On Mon, Jun 11, 2018 at 03:26:54PM -0700, Paulo Zanoni wrote:
> > > > > From: Manasi Navare 
> > > > > 
> > > > > For ICL, on Combo PHY the allowed max rates are:
> > > > >  - HBR3 8.1 eDP (DDIA)
> > > > >  - HBR2 5.4 DisplayPort (DDIB)
> > > > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > > > >  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > > > >  - DP on legacy connector - DDIC/D/E/F)
> > > > > 
> > > > > Cc: Rodrigo Vivi 
> > > > > Cc: Jani Nikula 
> > > > > Reviewed-by: James Ausmus 
> > > > > Signed-off-by: Manasi Navare 
> > > > > Signed-off-by: James Ausmus 
> > > > > [Paulo: bikeshed to keep future platforms on "else".]
> > > > > Signed-off-by: Paulo Zanoni 
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_dp.c | 21 +++--
> > > > >  1 file changed, 19 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > index 37b9f62aeb6e..8371159cc192 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > @@ -256,6 +256,20 @@ static int cnl_max_source_rate(struct
> > > > > intel_dp *intel_dp)
> > > > >   return 81;
> > > > >  }
> > > > >  
> > > > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > > > +{
> > > > > + struct intel_digital_port *dig_port =
> > > > > dp_to_dig_port(intel_dp);
> > > > > + enum port port = dig_port->base.port;
> > > > > +
> > > > > + /* On Combo PHY port A max speed is HBR3 for all
> > > > > Vccio
> > > > > voltages
> > > > > +  * and on Combo PHY Port B the maximum supported is
> > > > > HBR2.
> > > > > +  */
> > > > 
> > > > And what about the other ports? If port B is the only
> > > > exception why are we even discussing port A specifically
> > > > here?
> > > 
> > > All the MG PHY ports (C/D/E/F)  support a max of HBR3 that is
> > > 81
> > > but for
> > > Combo PHY ports which is Port A or B, HBR3 only supported for
> > > Port A
> > > but for Port B it is max of HBR2 which is 54 hence the
> > > comment
> > > for Combo PHY
> > > ports and if port B then just return HBR2
> > 
> > I think Ville's point was that having a comment that only discusses
> > ports A and B on code that handles all ports gives the impression
> > that
> > perhaps the code is "forgetting" to consider the other ports, or
> > something like that. Which makes sense to me.
> > 
> > Perhaps to address this issue we could either reword the comment to
> > include C-F or simply just remove it, since the commit message
> > should
> > be enough and the comment only says what the code says.
> > 
> 
> Yes I agree. Lets remove the comment in the code since the commit
> message
> covers that part.
> Should I send a new revision for this with comment removed?

Feel free to do it, otherwise I can do it while applying since it's a
trivial change.

Thanks,
Paulo

> 
> Manasi 
> 
> > > 
> > > Manasi
> > > 
> > > > 
> > > > > + if (port == PORT_B)
> > > > > + return 54;
> > > > > +
> > > > > + return 81;
> > > > > +}
> > > > > +
> > > > >  static void
> > > > >  intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > > >  {
> > > > > @@ -285,10 +299,13 @@ intel_dp_set_source_rates(struct
> > > > > intel_dp
> > > > > *intel_dp)
> > > > >   /* This should only be done once */
> > > > >   WARN_ON(intel_dp->source_rates || intel_dp-
> > > > > > num_source_rates);
> > > > > 
> > > > >  
> > > > > - if (IS_CANNONLAKE(dev_priv)) {
> > > > > + if (INTEL_GEN(dev_priv) >= 10) {
> > > > >   source_rates = cnl_rates;
> > > > >   size = ARRAY_SIZE(cnl_rates);
> > > > > - max_rate = cnl_max_source_rate(intel_dp);
> > > > > + if (INTEL_GEN(dev_priv) == 10)
> > > > > + max_rate =
> > > > > cnl_max_source_rate(intel_dp);
> > > > > + else
> > > > > + max_rate =
> > > > > icl_max_source_rate(intel_dp);
> > > > >   } else if (IS_GEN9_LP(dev_priv)) {
> > > > >   source_rates = bxt_rates;
> > > > >   size = ARRAY_SIZE(bxt_rates);
> > > > > -- 
> > > > > 2.14.4
> > > > > 
> > > > > ___
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > > 
> > > > -- 
> > > > Ville Syrjälä
> > > > Intel
> > > > ___
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
> > > ___
> > >

Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

2018-06-13 Thread Manasi Navare

On Wed, Jun 13, 2018 at 12:42:20PM -0700, Paulo Zanoni wrote:
> Em Ter, 2018-06-12 às 11:37 -0700, Manasi Navare escreveu:
> > On Tue, Jun 12, 2018 at 03:15:53PM +0300, Ville Syrjälä wrote:
> > > On Mon, Jun 11, 2018 at 03:26:54PM -0700, Paulo Zanoni wrote:
> > > > From: Manasi Navare 
> > > > 
> > > > For ICL, on Combo PHY the allowed max rates are:
> > > >  - HBR3 8.1 eDP (DDIA)
> > > >  - HBR2 5.4 DisplayPort (DDIB)
> > > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > > >  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > > >  - DP on legacy connector - DDIC/D/E/F)
> > > > 
> > > > Cc: Rodrigo Vivi 
> > > > Cc: Jani Nikula 
> > > > Reviewed-by: James Ausmus 
> > > > Signed-off-by: Manasi Navare 
> > > > Signed-off-by: James Ausmus 
> > > > [Paulo: bikeshed to keep future platforms on "else".]
> > > > Signed-off-by: Paulo Zanoni 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dp.c | 21 +++--
> > > >  1 file changed, 19 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 37b9f62aeb6e..8371159cc192 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -256,6 +256,20 @@ static int cnl_max_source_rate(struct
> > > > intel_dp *intel_dp)
> > > > return 81;
> > > >  }
> > > >  
> > > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > > +{
> > > > +   struct intel_digital_port *dig_port =
> > > > dp_to_dig_port(intel_dp);
> > > > +   enum port port = dig_port->base.port;
> > > > +
> > > > +   /* On Combo PHY port A max speed is HBR3 for all Vccio
> > > > voltages
> > > > +* and on Combo PHY Port B the maximum supported is
> > > > HBR2.
> > > > +*/
> > > 
> > > And what about the other ports? If port B is the only
> > > exception why are we even discussing port A specifically
> > > here?
> > 
> > All the MG PHY ports (C/D/E/F)  support a max of HBR3 that is 81
> > but for
> > Combo PHY ports which is Port A or B, HBR3 only supported for Port A
> > but for Port B it is max of HBR2 which is 54 hence the comment
> > for Combo PHY
> > ports and if port B then just return HBR2
> 
> I think Ville's point was that having a comment that only discusses
> ports A and B on code that handles all ports gives the impression that
> perhaps the code is "forgetting" to consider the other ports, or
> something like that. Which makes sense to me.
> 
> Perhaps to address this issue we could either reword the comment to
> include C-F or simply just remove it, since the commit message should
> be enough and the comment only says what the code says.
>

Yes I agree. Lets remove the comment in the code since the commit message
covers that part.
Should I send a new revision for this with comment removed?

Manasi 

> > 
> > Manasi
> > 
> > > 
> > > > +   if (port == PORT_B)
> > > > +   return 54;
> > > > +
> > > > +   return 81;
> > > > +}
> > > > +
> > > >  static void
> > > >  intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > >  {
> > > > @@ -285,10 +299,13 @@ intel_dp_set_source_rates(struct intel_dp
> > > > *intel_dp)
> > > > /* This should only be done once */
> > > > WARN_ON(intel_dp->source_rates || intel_dp-
> > > > >num_source_rates);
> > > >  
> > > > -   if (IS_CANNONLAKE(dev_priv)) {
> > > > +   if (INTEL_GEN(dev_priv) >= 10) {
> > > > source_rates = cnl_rates;
> > > > size = ARRAY_SIZE(cnl_rates);
> > > > -   max_rate = cnl_max_source_rate(intel_dp);
> > > > +   if (INTEL_GEN(dev_priv) == 10)
> > > > +   max_rate =
> > > > cnl_max_source_rate(intel_dp);
> > > > +   else
> > > > +   max_rate =
> > > > icl_max_source_rate(intel_dp);
> > > > } else if (IS_GEN9_LP(dev_priv)) {
> > > > source_rates = bxt_rates;
> > > > size = ARRAY_SIZE(bxt_rates);
> > > > -- 
> > > > 2.14.4
> > > > 
> > > > ___
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

2018-06-13 Thread Paulo Zanoni

Em Ter, 2018-06-12 às 11:37 -0700, Manasi Navare escreveu:
> On Tue, Jun 12, 2018 at 03:15:53PM +0300, Ville Syrjälä wrote:
> > On Mon, Jun 11, 2018 at 03:26:54PM -0700, Paulo Zanoni wrote:
> > > From: Manasi Navare 
> > > 
> > > For ICL, on Combo PHY the allowed max rates are:
> > >  - HBR3 8.1 eDP (DDIA)
> > >  - HBR2 5.4 DisplayPort (DDIB)
> > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > >  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > >  - DP on legacy connector - DDIC/D/E/F)
> > > 
> > > Cc: Rodrigo Vivi 
> > > Cc: Jani Nikula 
> > > Reviewed-by: James Ausmus 
> > > Signed-off-by: Manasi Navare 
> > > Signed-off-by: James Ausmus 
> > > [Paulo: bikeshed to keep future platforms on "else".]
> > > Signed-off-by: Paulo Zanoni 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 21 +++--
> > >  1 file changed, 19 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 37b9f62aeb6e..8371159cc192 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -256,6 +256,20 @@ static int cnl_max_source_rate(struct
> > > intel_dp *intel_dp)
> > >   return 81;
> > >  }
> > >  
> > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > +{
> > > + struct intel_digital_port *dig_port =
> > > dp_to_dig_port(intel_dp);
> > > + enum port port = dig_port->base.port;
> > > +
> > > + /* On Combo PHY port A max speed is HBR3 for all Vccio
> > > voltages
> > > +  * and on Combo PHY Port B the maximum supported is
> > > HBR2.
> > > +  */
> > 
> > And what about the other ports? If port B is the only
> > exception why are we even discussing port A specifically
> > here?
> 
> All the MG PHY ports (C/D/E/F)  support a max of HBR3 that is 81
> but for
> Combo PHY ports which is Port A or B, HBR3 only supported for Port A
> but for Port B it is max of HBR2 which is 54 hence the comment
> for Combo PHY
> ports and if port B then just return HBR2

I think Ville's point was that having a comment that only discusses
ports A and B on code that handles all ports gives the impression that
perhaps the code is "forgetting" to consider the other ports, or
something like that. Which makes sense to me.

Perhaps to address this issue we could either reword the comment to
include C-F or simply just remove it, since the commit message should
be enough and the comment only says what the code says.

> 
> Manasi
> 
> > 
> > > + if (port == PORT_B)
> > > + return 54;
> > > +
> > > + return 81;
> > > +}
> > > +
> > >  static void
> > >  intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > >  {
> > > @@ -285,10 +299,13 @@ intel_dp_set_source_rates(struct intel_dp
> > > *intel_dp)
> > >   /* This should only be done once */
> > >   WARN_ON(intel_dp->source_rates || intel_dp-
> > > >num_source_rates);
> > >  
> > > - if (IS_CANNONLAKE(dev_priv)) {
> > > + if (INTEL_GEN(dev_priv) >= 10) {
> > >   source_rates = cnl_rates;
> > >   size = ARRAY_SIZE(cnl_rates);
> > > - max_rate = cnl_max_source_rate(intel_dp);
> > > + if (INTEL_GEN(dev_priv) == 10)
> > > + max_rate =
> > > cnl_max_source_rate(intel_dp);
> > > + else
> > > + max_rate =
> > > icl_max_source_rate(intel_dp);
> > >   } else if (IS_GEN9_LP(dev_priv)) {
> > >   source_rates = bxt_rates;
> > >   size = ARRAY_SIZE(bxt_rates);
> > > -- 
> > > 2.14.4
> > > 
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

2018-06-12 Thread Manasi Navare

On Tue, Jun 12, 2018 at 03:15:53PM +0300, Ville Syrjälä wrote:
> On Mon, Jun 11, 2018 at 03:26:54PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare 
> > 
> > For ICL, on Combo PHY the allowed max rates are:
> >  - HBR3 8.1 eDP (DDIA)
> >  - HBR2 5.4 DisplayPort (DDIB)
> > and for MG PHY/TC DDI Ports allowed DP rates are:
> >  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> >  - DP on legacy connector - DDIC/D/E/F)
> > 
> > Cc: Rodrigo Vivi 
> > Cc: Jani Nikula 
> > Reviewed-by: James Ausmus 
> > Signed-off-by: Manasi Navare 
> > Signed-off-by: James Ausmus 
> > [Paulo: bikeshed to keep future platforms on "else".]
> > Signed-off-by: Paulo Zanoni 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 21 +++--
> >  1 file changed, 19 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 37b9f62aeb6e..8371159cc192 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -256,6 +256,20 @@ static int cnl_max_source_rate(struct intel_dp 
> > *intel_dp)
> > return 81;
> >  }
> >  
> > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > +{
> > +   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +   enum port port = dig_port->base.port;
> > +
> > +   /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> > +* and on Combo PHY Port B the maximum supported is HBR2.
> > +*/
> 
> And what about the other ports? If port B is the only
> exception why are we even discussing port A specifically
> here?

All the MG PHY ports (C/D/E/F)  support a max of HBR3 that is 81 but for
Combo PHY ports which is Port A or B, HBR3 only supported for Port A
but for Port B it is max of HBR2 which is 54 hence the comment for Combo PHY
ports and if port B then just return HBR2

Manasi

> 
> > +   if (port == PORT_B)
> > +   return 54;
> > +
> > +   return 81;
> > +}
> > +
> >  static void
> >  intel_dp_set_source_rates(struct intel_dp *intel_dp)
> >  {
> > @@ -285,10 +299,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > /* This should only be done once */
> > WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> >  
> > -   if (IS_CANNONLAKE(dev_priv)) {
> > +   if (INTEL_GEN(dev_priv) >= 10) {
> > source_rates = cnl_rates;
> > size = ARRAY_SIZE(cnl_rates);
> > -   max_rate = cnl_max_source_rate(intel_dp);
> > +   if (INTEL_GEN(dev_priv) == 10)
> > +   max_rate = cnl_max_source_rate(intel_dp);
> > +   else
> > +   max_rate = icl_max_source_rate(intel_dp);
> > } else if (IS_GEN9_LP(dev_priv)) {
> > source_rates = bxt_rates;
> > size = ARRAY_SIZE(bxt_rates);
> > -- 
> > 2.14.4
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

2018-06-12 Thread Ville Syrjälä

On Mon, Jun 11, 2018 at 03:26:54PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare 
> 
> For ICL, on Combo PHY the allowed max rates are:
>  - HBR3 8.1 eDP (DDIA)
>  - HBR2 5.4 DisplayPort (DDIB)
> and for MG PHY/TC DDI Ports allowed DP rates are:
>  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
>  - DP on legacy connector - DDIC/D/E/F)
> 
> Cc: Rodrigo Vivi 
> Cc: Jani Nikula 
> Reviewed-by: James Ausmus 
> Signed-off-by: Manasi Navare 
> Signed-off-by: James Ausmus 
> [Paulo: bikeshed to keep future platforms on "else".]
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 21 +++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 37b9f62aeb6e..8371159cc192 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -256,6 +256,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
>   return 81;
>  }
>  
> +static int icl_max_source_rate(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum port port = dig_port->base.port;
> +
> + /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> +  * and on Combo PHY Port B the maximum supported is HBR2.
> +  */

And what about the other ports? If port B is the only
exception why are we even discussing port A specifically
here?

> + if (port == PORT_B)
> + return 54;
> +
> + return 81;
> +}
> +
>  static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
> @@ -285,10 +299,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>   /* This should only be done once */
>   WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>  
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 10) {
>   source_rates = cnl_rates;
>   size = ARRAY_SIZE(cnl_rates);
> - max_rate = cnl_max_source_rate(intel_dp);
> + if (INTEL_GEN(dev_priv) == 10)
> + max_rate = cnl_max_source_rate(intel_dp);
> + else
> + max_rate = icl_max_source_rate(intel_dp);
>   } else if (IS_GEN9_LP(dev_priv)) {
>   source_rates = bxt_rates;
>   size = ARRAY_SIZE(bxt_rates);
> -- 
> 2.14.4
> 
> ___
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-- 
Ville Syrjälä
Intel
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[Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

2018-06-11 Thread Paulo Zanoni

From: Manasi Navare 

For ICL, on Combo PHY the allowed max rates are:
 - HBR3 8.1 eDP (DDIA)
 - HBR2 5.4 DisplayPort (DDIB)
and for MG PHY/TC DDI Ports allowed DP rates are:
 - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
 - DP on legacy connector - DDIC/D/E/F)

Cc: Rodrigo Vivi 
Cc: Jani Nikula 
Reviewed-by: James Ausmus 
Signed-off-by: Manasi Navare 
Signed-off-by: James Ausmus 
[Paulo: bikeshed to keep future platforms on "else".]
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_dp.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 37b9f62aeb6e..8371159cc192 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -256,6 +256,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
return 81;
 }
 
+static int icl_max_source_rate(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   enum port port = dig_port->base.port;
+
+   /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
+* and on Combo PHY Port B the maximum supported is HBR2.
+*/
+   if (port == PORT_B)
+   return 54;
+
+   return 81;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
@@ -285,10 +299,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
/* This should only be done once */
WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 
-   if (IS_CANNONLAKE(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 10) {
source_rates = cnl_rates;
size = ARRAY_SIZE(cnl_rates);
-   max_rate = cnl_max_source_rate(intel_dp);
+   if (INTEL_GEN(dev_priv) == 10)
+   max_rate = cnl_max_source_rate(intel_dp);
+   else
+   max_rate = icl_max_source_rate(intel_dp);
} else if (IS_GEN9_LP(dev_priv)) {
source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
-- 
2.14.4

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Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

[Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake

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