Re: [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr
> -Original Message- > From: Jani Nikula > Sent: Friday, May 21, 2021 12:45 AM > To: De Marchi, Lucas ; Srivatsa, Anusha > > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names > containing csr > > On Tue, 18 May 2021, Lucas De Marchi wrote: > > On Tue, May 18, 2021 at 02:34:42PM -0700, Anusha Srivatsa wrote: > >>Rename all occurences of CSR_* with DMC_* > >> > >>Cc: Jani Nikula > >>Signed-off-by: Anusha Srivatsa > > > > > > Reviewed-by: Lucas De Marchi > > We failed to take GVT into account, and apparently neither CI or Anusha has > CONFIG_DRM_I915_GVT=y. They use the register definitions, and this broke > the build. > > Anusha, please enable the config, and fix the fallout. Cc: the patch to GVT > folks for ack. On it. Anusha > > > Thanks, > Jani. > > > > > > > Lucas De Marchi > > > >>--- > >> drivers/gpu/drm/i915/display/intel_csr.c | 167 +- > >> drivers/gpu/drm/i915/display/intel_csr.h | 6 +- > >> .../drm/i915/display/intel_display_debugfs.c | 16 +- > >> .../drm/i915/display/intel_display_power.c| 14 +- > >> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- > >> drivers/gpu/drm/i915/i915_reg.h | 28 +-- > >> 6 files changed, 117 insertions(+), 118 deletions(-) > >> > >>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c > >>b/drivers/gpu/drm/i915/display/intel_csr.c > >>index 5ed286dc6720..f2124796ce77 100644 > >>--- a/drivers/gpu/drm/i915/display/intel_csr.c > >>+++ b/drivers/gpu/drm/i915/display/intel_csr.c > >>@@ -30,10 +30,9 @@ > >> #include "intel_de.h" > >> > >> /** > >>- * DOC: csr support for dmc > >>+ * DOC: DMC firmware support > >> * > >>- * Display Context Save and Restore (CSR) firmware support added from > >>gen9 > >>- * onwards to drive newly added DMC (Display microcontroller) in > >>display > >>+ * From gen9 onwards we have newly added DMC (Display > >>+ microcontroller) in display > >> * engine to save and restore the state of display engine when it > >>enter into > >> * low-power state and comes back to normal. > >> */ > >>@@ -44,55 +43,55 @@ > >>__stringify(major) "_" \ > >>__stringify(minor) ".bin" > >> > >>-#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE > >>+#define GEN12_DMC_MAX_FW_SIZE > ICL_DMC_MAX_FW_SIZE > >> > >>-#define ADLS_CSR_PATH DMC_PATH(adls, 2, 01) > >>-#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1) > >>-MODULE_FIRMWARE(ADLS_CSR_PATH); > >>+#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) > >>+#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) > >>+MODULE_FIRMWARE(ADLS_DMC_PATH); > >> > >>-#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02) > >>-#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) > >>-MODULE_FIRMWARE(DG1_CSR_PATH); > >>+#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) > >>+#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) > >>+MODULE_FIRMWARE(DG1_DMC_PATH); > >> > >>-#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02) > >>-#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) > >>-MODULE_FIRMWARE(RKL_CSR_PATH); > >>+#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02) > >>+#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) > >>+MODULE_FIRMWARE(RKL_DMC_PATH); > >> > >>-#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08) > >>-#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8) > >>-MODULE_FIRMWARE(TGL_CSR_PATH); > >>+#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08) > >>+#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) > >>+MODULE_FIRMWARE(TGL_DMC_PATH); > >> > >>-#define ICL_CSR_PATH DMC_PATH(icl, 1, 09) > >>-#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9) > >>-#define ICL_CSR_MAX_FW_SIZE0x6000 > >>-MODULE_FIRMWARE(ICL_CSR_PATH); > >>+#define ICL_DMC_PATH DMC_PATH(icl, 1, 09) > >>+#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) > >>+#define ICL_DMC_MAX_FW_SIZE0x6000 > >>+MODULE_FIRMWARE(ICL_DMC_PATH); > >> > >
Re: [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr
On Tue, 18 May 2021, Lucas De Marchi wrote: > On Tue, May 18, 2021 at 02:34:42PM -0700, Anusha Srivatsa wrote: >>Rename all occurences of CSR_* with DMC_* >> >>Cc: Jani Nikula >>Signed-off-by: Anusha Srivatsa > > > Reviewed-by: Lucas De Marchi We failed to take GVT into account, and apparently neither CI or Anusha has CONFIG_DRM_I915_GVT=y. They use the register definitions, and this broke the build. Anusha, please enable the config, and fix the fallout. Cc: the patch to GVT folks for ack. Thanks, Jani. > > Lucas De Marchi > >>--- >> drivers/gpu/drm/i915/display/intel_csr.c | 167 +- >> drivers/gpu/drm/i915/display/intel_csr.h | 6 +- >> .../drm/i915/display/intel_display_debugfs.c | 16 +- >> .../drm/i915/display/intel_display_power.c| 14 +- >> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- >> drivers/gpu/drm/i915/i915_reg.h | 28 +-- >> 6 files changed, 117 insertions(+), 118 deletions(-) >> >>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c >>b/drivers/gpu/drm/i915/display/intel_csr.c >>index 5ed286dc6720..f2124796ce77 100644 >>--- a/drivers/gpu/drm/i915/display/intel_csr.c >>+++ b/drivers/gpu/drm/i915/display/intel_csr.c >>@@ -30,10 +30,9 @@ >> #include "intel_de.h" >> >> /** >>- * DOC: csr support for dmc >>+ * DOC: DMC firmware support >> * >>- * Display Context Save and Restore (CSR) firmware support added from gen9 >>- * onwards to drive newly added DMC (Display microcontroller) in display >>+ * From gen9 onwards we have newly added DMC (Display microcontroller) in >>display >> * engine to save and restore the state of display engine when it enter into >> * low-power state and comes back to normal. >> */ >>@@ -44,55 +43,55 @@ >> __stringify(major) "_" \ >> __stringify(minor) ".bin" >> >>-#define GEN12_CSR_MAX_FW_SIZEICL_CSR_MAX_FW_SIZE >>+#define GEN12_DMC_MAX_FW_SIZEICL_DMC_MAX_FW_SIZE >> >>-#define ADLS_CSR_PATHDMC_PATH(adls, 2, 01) >>-#define ADLS_CSR_VERSION_REQUIREDCSR_VERSION(2, 1) >>-MODULE_FIRMWARE(ADLS_CSR_PATH); >>+#define ADLS_DMC_PATHDMC_PATH(adls, 2, 01) >>+#define ADLS_DMC_VERSION_REQUIREDDMC_VERSION(2, 1) >>+MODULE_FIRMWARE(ADLS_DMC_PATH); >> >>-#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02) >>-#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) >>-MODULE_FIRMWARE(DG1_CSR_PATH); >>+#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) >>+#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) >>+MODULE_FIRMWARE(DG1_DMC_PATH); >> >>-#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02) >>-#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) >>-MODULE_FIRMWARE(RKL_CSR_PATH); >>+#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02) >>+#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) >>+MODULE_FIRMWARE(RKL_DMC_PATH); >> >>-#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08) >>-#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8) >>-MODULE_FIRMWARE(TGL_CSR_PATH); >>+#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08) >>+#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) >>+MODULE_FIRMWARE(TGL_DMC_PATH); >> >>-#define ICL_CSR_PATH DMC_PATH(icl, 1, 09) >>-#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9) >>-#define ICL_CSR_MAX_FW_SIZE 0x6000 >>-MODULE_FIRMWARE(ICL_CSR_PATH); >>+#define ICL_DMC_PATH DMC_PATH(icl, 1, 09) >>+#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) >>+#define ICL_DMC_MAX_FW_SIZE 0x6000 >>+MODULE_FIRMWARE(ICL_DMC_PATH); >> >>-#define CNL_CSR_PATH DMC_PATH(cnl, 1, 07) >>-#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) >>-#define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE >>-MODULE_FIRMWARE(CNL_CSR_PATH); >>+#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07) >>+#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) >>+#define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE >>+MODULE_FIRMWARE(CNL_DMC_PATH); >> >>-#define GLK_CSR_PATH DMC_PATH(glk, 1, 04) >>-#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) >>-#define GLK_CSR_MAX_FW_SIZE 0x4000 >>-MODULE_FIRMWARE(GLK_CSR_PATH); >>+#define GLK_DMC_PATH DMC_PATH(glk, 1, 04) >>+#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) >>+#define GLK_DMC_MAX_FW_SIZE 0x4000 >>+MODULE_FIRMWARE(GLK_DMC_PATH); >> >>-#define KBL_CSR_PATH DMC_PATH(kbl, 1, 04) >>-#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) >>-#define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE >>-MODULE_FIRMWARE(KBL_CSR_PATH); >>+#define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) >>+#define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) >>+#define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE >>+MODULE_FIRMWARE(KBL_DMC_PATH); >> >>-#define SKL_CSR_PATH DMC_PATH(skl, 1, 27) >>-#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
Re: [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr
On Tue, May 18, 2021 at 02:34:42PM -0700, Anusha Srivatsa wrote: Rename all occurences of CSR_* with DMC_* Cc: Jani Nikula Signed-off-by: Anusha Srivatsa Reviewed-by: Lucas De Marchi Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_csr.c | 167 +- drivers/gpu/drm/i915/display/intel_csr.h | 6 +- .../drm/i915/display/intel_display_debugfs.c | 16 +- .../drm/i915/display/intel_display_power.c| 14 +- drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- drivers/gpu/drm/i915/i915_reg.h | 28 +-- 6 files changed, 117 insertions(+), 118 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 5ed286dc6720..f2124796ce77 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -30,10 +30,9 @@ #include "intel_de.h" /** - * DOC: csr support for dmc + * DOC: DMC firmware support * - * Display Context Save and Restore (CSR) firmware support added from gen9 - * onwards to drive newly added DMC (Display microcontroller) in display + * From gen9 onwards we have newly added DMC (Display microcontroller) in display * engine to save and restore the state of display engine when it enter into * low-power state and comes back to normal. */ @@ -44,55 +43,55 @@ __stringify(major) "_" \ __stringify(minor) ".bin" -#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE +#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE -#define ADLS_CSR_PATH DMC_PATH(adls, 2, 01) -#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1) -MODULE_FIRMWARE(ADLS_CSR_PATH); +#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) +#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) +MODULE_FIRMWARE(ADLS_DMC_PATH); -#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02) -#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) -MODULE_FIRMWARE(DG1_CSR_PATH); +#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) +#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +MODULE_FIRMWARE(DG1_DMC_PATH); -#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02) -#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) -MODULE_FIRMWARE(RKL_CSR_PATH); +#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02) +#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +MODULE_FIRMWARE(RKL_DMC_PATH); -#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08) -#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8) -MODULE_FIRMWARE(TGL_CSR_PATH); +#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08) +#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) +MODULE_FIRMWARE(TGL_DMC_PATH); -#define ICL_CSR_PATH DMC_PATH(icl, 1, 09) -#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9) -#define ICL_CSR_MAX_FW_SIZE0x6000 -MODULE_FIRMWARE(ICL_CSR_PATH); +#define ICL_DMC_PATH DMC_PATH(icl, 1, 09) +#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) +#define ICL_DMC_MAX_FW_SIZE0x6000 +MODULE_FIRMWARE(ICL_DMC_PATH); -#define CNL_CSR_PATH DMC_PATH(cnl, 1, 07) -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) -#define CNL_CSR_MAX_FW_SIZEGLK_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(CNL_CSR_PATH); +#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07) +#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) +#define CNL_DMC_MAX_FW_SIZEGLK_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(CNL_DMC_PATH); -#define GLK_CSR_PATH DMC_PATH(glk, 1, 04) -#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define GLK_CSR_MAX_FW_SIZE0x4000 -MODULE_FIRMWARE(GLK_CSR_PATH); +#define GLK_DMC_PATH DMC_PATH(glk, 1, 04) +#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) +#define GLK_DMC_MAX_FW_SIZE0x4000 +MODULE_FIRMWARE(GLK_DMC_PATH); -#define KBL_CSR_PATH DMC_PATH(kbl, 1, 04) -#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define KBL_CSR_MAX_FW_SIZEBXT_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(KBL_CSR_PATH); +#define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) +#define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) +#define KBL_DMC_MAX_FW_SIZEBXT_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(KBL_DMC_PATH); -#define SKL_CSR_PATH DMC_PATH(skl, 1, 27) -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27) -#define SKL_CSR_MAX_FW_SIZEBXT_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(SKL_CSR_PATH); +#define SKL_DMC_PATH DMC_PATH(skl, 1, 27) +#define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) +#define SKL_DMC_MAX_FW_SIZEBXT_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(SKL_DMC_PATH); -#define BXT_CSR_PATH DMC_PATH(bxt, 1, 07) -#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) -#define BXT_CSR_MAX_FW_SIZE0x3000
[Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr
Rename all occurences of CSR_* with DMC_* Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 167 +- drivers/gpu/drm/i915/display/intel_csr.h | 6 +- .../drm/i915/display/intel_display_debugfs.c | 16 +- .../drm/i915/display/intel_display_power.c| 14 +- drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- drivers/gpu/drm/i915/i915_reg.h | 28 +-- 6 files changed, 117 insertions(+), 118 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 5ed286dc6720..f2124796ce77 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -30,10 +30,9 @@ #include "intel_de.h" /** - * DOC: csr support for dmc + * DOC: DMC firmware support * - * Display Context Save and Restore (CSR) firmware support added from gen9 - * onwards to drive newly added DMC (Display microcontroller) in display + * From gen9 onwards we have newly added DMC (Display microcontroller) in display * engine to save and restore the state of display engine when it enter into * low-power state and comes back to normal. */ @@ -44,55 +43,55 @@ __stringify(major) "_" \ __stringify(minor) ".bin" -#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE +#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE -#define ADLS_CSR_PATH DMC_PATH(adls, 2, 01) -#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1) -MODULE_FIRMWARE(ADLS_CSR_PATH); +#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) +#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) +MODULE_FIRMWARE(ADLS_DMC_PATH); -#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02) -#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) -MODULE_FIRMWARE(DG1_CSR_PATH); +#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) +#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +MODULE_FIRMWARE(DG1_DMC_PATH); -#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02) -#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) -MODULE_FIRMWARE(RKL_CSR_PATH); +#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02) +#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +MODULE_FIRMWARE(RKL_DMC_PATH); -#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08) -#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8) -MODULE_FIRMWARE(TGL_CSR_PATH); +#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08) +#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) +MODULE_FIRMWARE(TGL_DMC_PATH); -#define ICL_CSR_PATH DMC_PATH(icl, 1, 09) -#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9) -#define ICL_CSR_MAX_FW_SIZE0x6000 -MODULE_FIRMWARE(ICL_CSR_PATH); +#define ICL_DMC_PATH DMC_PATH(icl, 1, 09) +#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) +#define ICL_DMC_MAX_FW_SIZE0x6000 +MODULE_FIRMWARE(ICL_DMC_PATH); -#define CNL_CSR_PATH DMC_PATH(cnl, 1, 07) -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) -#define CNL_CSR_MAX_FW_SIZEGLK_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(CNL_CSR_PATH); +#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07) +#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) +#define CNL_DMC_MAX_FW_SIZEGLK_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(CNL_DMC_PATH); -#define GLK_CSR_PATH DMC_PATH(glk, 1, 04) -#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define GLK_CSR_MAX_FW_SIZE0x4000 -MODULE_FIRMWARE(GLK_CSR_PATH); +#define GLK_DMC_PATH DMC_PATH(glk, 1, 04) +#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) +#define GLK_DMC_MAX_FW_SIZE0x4000 +MODULE_FIRMWARE(GLK_DMC_PATH); -#define KBL_CSR_PATH DMC_PATH(kbl, 1, 04) -#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define KBL_CSR_MAX_FW_SIZEBXT_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(KBL_CSR_PATH); +#define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) +#define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) +#define KBL_DMC_MAX_FW_SIZEBXT_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(KBL_DMC_PATH); -#define SKL_CSR_PATH DMC_PATH(skl, 1, 27) -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27) -#define SKL_CSR_MAX_FW_SIZEBXT_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(SKL_CSR_PATH); +#define SKL_DMC_PATH DMC_PATH(skl, 1, 27) +#define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) +#define SKL_DMC_MAX_FW_SIZEBXT_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(SKL_DMC_PATH); -#define BXT_CSR_PATH DMC_PATH(bxt, 1, 07) -#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) -#define BXT_CSR_MAX_FW_SIZE0x3000 -MODULE_FIRMWARE(BXT_CSR_PATH); +#define BXT_DMC_PATH DMC_PATH(bxt, 1, 07) +#define
[Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr
Rename all occurences of CSR_* with DMC_* Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 167 +- drivers/gpu/drm/i915/display/intel_csr.h | 6 +- .../drm/i915/display/intel_display_debugfs.c | 16 +- .../drm/i915/display/intel_display_power.c| 14 +- drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- drivers/gpu/drm/i915/i915_reg.h | 28 +-- 6 files changed, 117 insertions(+), 118 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 5ed286dc6720..f2124796ce77 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -30,10 +30,9 @@ #include "intel_de.h" /** - * DOC: csr support for dmc + * DOC: DMC firmware support * - * Display Context Save and Restore (CSR) firmware support added from gen9 - * onwards to drive newly added DMC (Display microcontroller) in display + * From gen9 onwards we have newly added DMC (Display microcontroller) in display * engine to save and restore the state of display engine when it enter into * low-power state and comes back to normal. */ @@ -44,55 +43,55 @@ __stringify(major) "_" \ __stringify(minor) ".bin" -#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE +#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE -#define ADLS_CSR_PATH DMC_PATH(adls, 2, 01) -#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1) -MODULE_FIRMWARE(ADLS_CSR_PATH); +#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) +#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) +MODULE_FIRMWARE(ADLS_DMC_PATH); -#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02) -#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) -MODULE_FIRMWARE(DG1_CSR_PATH); +#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) +#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +MODULE_FIRMWARE(DG1_DMC_PATH); -#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02) -#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) -MODULE_FIRMWARE(RKL_CSR_PATH); +#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02) +#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +MODULE_FIRMWARE(RKL_DMC_PATH); -#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08) -#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8) -MODULE_FIRMWARE(TGL_CSR_PATH); +#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08) +#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) +MODULE_FIRMWARE(TGL_DMC_PATH); -#define ICL_CSR_PATH DMC_PATH(icl, 1, 09) -#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9) -#define ICL_CSR_MAX_FW_SIZE0x6000 -MODULE_FIRMWARE(ICL_CSR_PATH); +#define ICL_DMC_PATH DMC_PATH(icl, 1, 09) +#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) +#define ICL_DMC_MAX_FW_SIZE0x6000 +MODULE_FIRMWARE(ICL_DMC_PATH); -#define CNL_CSR_PATH DMC_PATH(cnl, 1, 07) -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) -#define CNL_CSR_MAX_FW_SIZEGLK_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(CNL_CSR_PATH); +#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07) +#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) +#define CNL_DMC_MAX_FW_SIZEGLK_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(CNL_DMC_PATH); -#define GLK_CSR_PATH DMC_PATH(glk, 1, 04) -#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define GLK_CSR_MAX_FW_SIZE0x4000 -MODULE_FIRMWARE(GLK_CSR_PATH); +#define GLK_DMC_PATH DMC_PATH(glk, 1, 04) +#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) +#define GLK_DMC_MAX_FW_SIZE0x4000 +MODULE_FIRMWARE(GLK_DMC_PATH); -#define KBL_CSR_PATH DMC_PATH(kbl, 1, 04) -#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define KBL_CSR_MAX_FW_SIZEBXT_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(KBL_CSR_PATH); +#define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) +#define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) +#define KBL_DMC_MAX_FW_SIZEBXT_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(KBL_DMC_PATH); -#define SKL_CSR_PATH DMC_PATH(skl, 1, 27) -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27) -#define SKL_CSR_MAX_FW_SIZEBXT_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(SKL_CSR_PATH); +#define SKL_DMC_PATH DMC_PATH(skl, 1, 27) +#define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) +#define SKL_DMC_MAX_FW_SIZEBXT_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(SKL_DMC_PATH); -#define BXT_CSR_PATH DMC_PATH(bxt, 1, 07) -#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) -#define BXT_CSR_MAX_FW_SIZE0x3000 -MODULE_FIRMWARE(BXT_CSR_PATH); +#define BXT_DMC_PATH DMC_PATH(bxt, 1, 07) +#define
