[Intel-gfx] [PATCH] Enable dithering for intel VCH DVO
Hi Daniel, hi Ville,
did you get the attached patch? This enables dithering for the iVCH DVO
chip and improves image quality for 24 pipes on 18bpp displays greatly.
Thanks for reviewing and considering this patch.
Thomas Richter
>From 3d0b1a15302aa704c7cf4ebbf7c2b8a1566b9beb Mon Sep 17 00:00:00 2001
From: Thomas Richter
Date: Sat, 28 Mar 2015 10:57:46 +0100
Subject: [PATCH 1/1] Enabled dithering in the intel VCH DVO for 18bpp
pipelines.
Signed-off-by: Thomas Richter
---
drivers/gpu/drm/i915/dvo_ivch.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c
index 0f2587f..89b08a8 100644
--- a/drivers/gpu/drm/i915/dvo_ivch.c
+++ b/drivers/gpu/drm/i915/dvo_ivch.c
@@ -23,6 +23,9 @@
* Authors:
*Eric Anholt
*
+ * Minor modifications (Dithering enable):
+ *Thomas Richter
+ *
*/
#include "dvo.h"
@@ -59,6 +62,8 @@
# define VR01_DVO_BYPASS_ENABLE (1 << 1)
/** Enables the DVO clock */
# define VR01_DVO_ENABLE (1 << 0)
+/** Enable dithering for 18bpp panels. Not documented. */
+# define VR01_DITHER_ENABLE (1 << 4)
/*
* LCD Interface Format
@@ -74,6 +79,8 @@
# define VR10_INTERFACE_2X18 (2 << 2)
/** Enables 2x24-bit LVDS output */
# define VR10_INTERFACE_2X24 (3 << 2)
+/** Mask that defines the depth of the pipeline */
+# define VR10_INTERFACE_DEPTH_MASK (3 << 2)
/*
* VR20 LCD Horizontal Display Size
@@ -342,9 +349,15 @@ static void ivch_mode_set(struct intel_dvo_device *dvo,
struct drm_display_mode *adjusted_mode)
{
uint16_t vr40 = 0;
- uint16_t vr01;
+ uint16_t vr01 = 0;
+ uint16_t vr10;
+
+ ivch_read(dvo, VR10, &vr10);
+ /* Enable dithering for 18 bpp pipelines */
+ vr10 &= VR10_INTERFACE_DEPTH_MASK;
+ if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18)
+ vr01 = VR01_DITHER_ENABLE;
- vr01 = 0;
vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
VR40_HORIZONTAL_INTERP_ENABLE);
@@ -353,7 +366,7 @@ static void ivch_mode_set(struct intel_dvo_device *dvo,
uint16_t x_ratio, y_ratio;
vr01 |= VR01_PANEL_FIT_ENABLE;
- vr40 |= VR40_CLOCK_GATING_ENABLE;
+ vr40 |= VR40_CLOCK_GATING_ENABLE | VR40_ENHANCED_PANEL_FITTING;
x_ratio = (((mode->hdisplay - 1) << 16) /
(adjusted_mode->hdisplay - 1)) >> 2;
y_ratio = (((mode->vdisplay - 1) << 16) /
@@ -380,6 +393,8 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo)
DRM_DEBUG_KMS("VR00: 0x%04x\n", val);
ivch_read(dvo, VR01, &val);
DRM_DEBUG_KMS("VR01: 0x%04x\n", val);
+ ivch_read(dvo, VR10, &val);
+ DRM_DEBUG_KMS("VR10: 0x%04x\n", val);
ivch_read(dvo, VR30, &val);
DRM_DEBUG_KMS("VR30: 0x%04x\n", val);
ivch_read(dvo, VR40, &val);
--
1.7.10.4
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Re: [Intel-gfx] [PATCH] Enable dithering for intel VCH DVO
On Mon, Mar 30, 2015 at 10:18:53AM +0200, Thomas Richter wrote:
> Hi Daniel, hi Ville,
>
> did you get the attached patch? This enables dithering for the iVCH DVO
> chip and improves image quality for 24 pipes on 18bpp displays greatly.
>
> Thanks for reviewing and considering this patch.
Yeah that one worked better. Queued for -next, thanks for the patch.
-Daniel
>
> Thomas Richter
>
> From 3d0b1a15302aa704c7cf4ebbf7c2b8a1566b9beb Mon Sep 17 00:00:00 2001
> From: Thomas Richter
> Date: Sat, 28 Mar 2015 10:57:46 +0100
> Subject: [PATCH 1/1] Enabled dithering in the intel VCH DVO for 18bpp
> pipelines.
>
>
> Signed-off-by: Thomas Richter
> ---
> drivers/gpu/drm/i915/dvo_ivch.c | 21 ++---
> 1 file changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c
> index 0f2587f..89b08a8 100644
> --- a/drivers/gpu/drm/i915/dvo_ivch.c
> +++ b/drivers/gpu/drm/i915/dvo_ivch.c
> @@ -23,6 +23,9 @@
> * Authors:
> *Eric Anholt
> *
> + * Minor modifications (Dithering enable):
> + *Thomas Richter
> + *
> */
>
> #include "dvo.h"
> @@ -59,6 +62,8 @@
> # define VR01_DVO_BYPASS_ENABLE (1 << 1)
> /** Enables the DVO clock */
> # define VR01_DVO_ENABLE (1 << 0)
> +/** Enable dithering for 18bpp panels. Not documented. */
> +# define VR01_DITHER_ENABLE (1 << 4)
>
> /*
> * LCD Interface Format
> @@ -74,6 +79,8 @@
> # define VR10_INTERFACE_2X18 (2 << 2)
> /** Enables 2x24-bit LVDS output */
> # define VR10_INTERFACE_2X24 (3 << 2)
> +/** Mask that defines the depth of the pipeline */
> +# define VR10_INTERFACE_DEPTH_MASK (3 << 2)
>
> /*
> * VR20 LCD Horizontal Display Size
> @@ -342,9 +349,15 @@ static void ivch_mode_set(struct intel_dvo_device *dvo,
> struct drm_display_mode *adjusted_mode)
> {
> uint16_t vr40 = 0;
> - uint16_t vr01;
> + uint16_t vr01 = 0;
> + uint16_t vr10;
> +
> + ivch_read(dvo, VR10, &vr10);
> + /* Enable dithering for 18 bpp pipelines */
> + vr10 &= VR10_INTERFACE_DEPTH_MASK;
> + if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18)
> + vr01 = VR01_DITHER_ENABLE;
>
> - vr01 = 0;
> vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
> VR40_HORIZONTAL_INTERP_ENABLE);
>
> @@ -353,7 +366,7 @@ static void ivch_mode_set(struct intel_dvo_device *dvo,
> uint16_t x_ratio, y_ratio;
>
> vr01 |= VR01_PANEL_FIT_ENABLE;
> - vr40 |= VR40_CLOCK_GATING_ENABLE;
> + vr40 |= VR40_CLOCK_GATING_ENABLE | VR40_ENHANCED_PANEL_FITTING;
> x_ratio = (((mode->hdisplay - 1) << 16) /
> (adjusted_mode->hdisplay - 1)) >> 2;
> y_ratio = (((mode->vdisplay - 1) << 16) /
> @@ -380,6 +393,8 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo)
> DRM_DEBUG_KMS("VR00: 0x%04x\n", val);
> ivch_read(dvo, VR01, &val);
> DRM_DEBUG_KMS("VR01: 0x%04x\n", val);
> + ivch_read(dvo, VR10, &val);
> + DRM_DEBUG_KMS("VR10: 0x%04x\n", val);
> ivch_read(dvo, VR30, &val);
> DRM_DEBUG_KMS("VR30: 0x%04x\n", val);
> ivch_read(dvo, VR40, &val);
> --
> 1.7.10.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] Enable dithering for intel VCH DVO
On Mon, 30 Mar 2015, Thomas Richter wrote: > Hi Daniel, hi Ville, > > did you get the attached patch? This enables dithering for the iVCH DVO > chip and improves image quality for 24 pipes on 18bpp displays greatly. > > Thanks for reviewing and considering this patch. Thomas, I've observed many times in the past there's something funny with how you reply to mails on intel-gfx, and I've told you before. Like this one has headers: References: <20150327140357.GV23521@phenom.ffwll.local> <1427693592-12941-1-git-send-email-ander.conselvan.de.olive...@intel.com> <28056_1427699754_5518F829_28056_1298_1_20150330071734.GH23521@phenom.ffwll.local> In-Reply-To: <28056_1427699754_5518F829_28056_1298_1_20150330071734.GH23521@phenom.ffwll.local> The first two referenced Message-IDs are valid for messages in Ander's patch series [1], while the third one doesn't even exist *unless* the apparently bogus prefix "28056_1427699754_5518F829_28056_1298_1_" is removed. And even that then is in Ander's patch series. Your message has nothing to do with that thread. Please check your setup. Please don't keep replying to unrelated threads. Note that just changing the subject does not make your reply become a new, independent thread. Much appreciated, Jani. [1] http://mid.gmane.org/1426861099-28445-1-git-send-email-ander.conselvan.de.olive...@intel.com -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
