Re: [Intel-gfx] [PATCH] [WIP] i965: Use up to 80 WM threads on GT2.
On Mon, 28 Mar 2011 21:43:28 -0700, Eric Anholt e...@anholt.net wrote: On Mon, 28 Mar 2011 15:22:35 -0700, Ian Romanick i...@freedesktop.org wrote: So, we're currently using too many threads in some cases? Could this be related to bug #35730? In that case the failure seems to be limited to SugarBay. I believe that's GT1, but I can never get the code names for these chips straight. Nope, note how instead of using that original wm_max_threads value, 40 is hardcoded in the place that should have been using it. But for DevSmallGT (which *is* GT1 right?) max VS threads is only 24. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] [WIP] i965: Use up to 80 WM threads on GT2.
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/28/2011 10:55 AM, Eric Anholt wrote: Here's an idea for an SNB performance improvement from the specs. It says that on GT2 you should be able to use 80 threads if WIZ Hashing Disable in GT_MODE register enabled. On my system (supposedly GT2), that bit (bit 6 of 0x20d0) is unset. In testing, with intel_reg_write 0x20d0 0x00400040 (it only successfully took once, I suspect due to FORCEWAKE, which also means that I can't necessarily trust that the bit was unset originally), I got only hangs from 3D. So, we're currently using too many threads in some cases? Could this be related to bug #35730? In that case the failure seems to be limited to SugarBay. I believe that's GT1, but I can never get the code names for these chips straight. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org/ iEYEARECAAYFAk2RCisACgkQX1gOwKyEAw8nRgCgnC1HMyfVwx5MLiaVF4mVzprQ oD4An2DMFJdXfYKOyvehR7x6qAQnYix6 =4m/t -END PGP SIGNATURE- ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] [WIP] i965: Use up to 80 WM threads on GT2.
On Mon, Mar 28, 2011 at 10:55:40AM -0700, Eric Anholt wrote: --- I suspect due to FORCEWAKE, which also means that I can't necessarily trust that the bit was unset originally), I got only hangs from 3D. If you want to get some more possibly garbage data, you can set forcewake from userspace, and hope the kernel doesn't unset it :). intel_reg_write 0xa18c 1 # check for ack intel_reg_read 0x130090 I've never tried it, but it might work at least for reading that first bit. I'm currenty working around this with 1301105269-23970-1-git-send-email-...@bwidawsk.net and a hack in the kernel to do a get() and never do a put. Ben ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] [WIP] i965: Use up to 80 WM threads on GT2.
On 2011/3/29 6:22, Ian Romanick wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/28/2011 10:55 AM, Eric Anholt wrote: Here's an idea for an SNB performance improvement from the specs. It says that on GT2 you should be able to use 80 threads if WIZ Hashing Disable in GT_MODE register enabled. On my system (supposedly GT2), that bit (bit 6 of 0x20d0) is unset. In testing, with intel_reg_write 0x20d0 0x00400040 (it only successfully took once, I suspect due to FORCEWAKE, which also means that I can't necessarily trust that the bit was unset originally), I got only hangs from 3D. So, we're currently using too many threads in some cases? Could this be related to bug #35730? In that case the failure seems to be limited to SugarBay. I believe that's GT1, but I can never get the code names for these chips straight. The system environment description section in bug #35730 already mention it's rev09 GT1 Thanks --Shuang -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org/ iEYEARECAAYFAk2RCisACgkQX1gOwKyEAw8nRgCgnC1HMyfVwx5MLiaVF4mVzprQ oD4An2DMFJdXfYKOyvehR7x6qAQnYix6 =4m/t -END PGP SIGNATURE- ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] [WIP] i965: Use up to 80 WM threads on GT2.
On Mon, 28 Mar 2011 15:37:37 -0700, Ben Widawsky b...@bwidawsk.net wrote: On Mon, Mar 28, 2011 at 10:55:40AM -0700, Eric Anholt wrote: --- I suspect due to FORCEWAKE, which also means that I can't necessarily trust that the bit was unset originally), I got only hangs from 3D. If you want to get some more possibly garbage data, you can set forcewake from userspace, and hope the kernel doesn't unset it :). intel_reg_write 0xa18c 1 # check for ack intel_reg_read 0x130090 I've never tried it, but it might work at least for reading that first bit. I'm currenty working around this with 1301105269-23970-1-git-send-email-...@bwidawsk.net and a hack in the kernel to do a get() and never do a put. I'm tempted by the idea of having a kernel interface for unpriveleged interfaces for reading these regs, which would allow for non-root gpu_top in addition to doing the forcewake. It'll suck to maintain a list of unpriveleged-OK regs, though. pgpNdsRbrNP28.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
