[Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.
v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
and use the value directly.(More such defines can be removed
as part of future patches). (Ville)
v3: Use values directly instead of accessing the defines
everytime for min and max DSC BPC.
Cc: Ville Syrjälä
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0eb5d66f87a7..947c7e911304 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -69,8 +69,6 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
-#define DP_DSC_MIN_SUPPORTED_BPC 8
-#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1914,11 +1912,17 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
- conn_state->max_requested_bpc);
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (INTEL_GEN(dev_priv) >= 12)
+ dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10,
+ conn_state->max_requested_bpc);
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
- if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
+
+ /* Min Input BPC for ICL+ is 8 */
+ if (pipe_bpp < 8 * 3) {
DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
return -EINVAL;
}
--
2.21.0
___
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Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
On Tue, Jul 16, 2019 at 01:26:19PM -0700, Srivatsa, Anusha wrote:
>
>
> >-Original Message-
> >From: Navare, Manasi D
> >Sent: Tuesday, July 16, 2019 11:15 AM
> >To: Srivatsa, Anusha
> >Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä
> >
> >Subject: Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
> >
> >On Mon, Jul 15, 2019 at 04:40:56PM -0700, Anusha Srivatsa wrote:
> >> DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But DSC
> >> engine in TGL supports 8, 10 and 12 BPC.
> >> Add 12 BPC support for DSC while calculating compression
> >> configuration.
> >>
> >> v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC and use
> >> the value directly.(More such defines can be removed as part of future
> >> patches). (Ville)
> >
> >IMO what Ville asked to do in his comment was to remove all the #defines for
> >the
> >max DSC BPC so remove the ones for 8 and 10 also to mak eit more readable and
> >that user does not have to hunt for the #defines for either of these.
>
> Yes those changes can be part of a following patch. This is TGL specific.
IMO, you could just make them in the same patch since they are minor changes
happening because of diferent max limits for TGL, so just say in the commit
message
while at it also remove the #defines and use the values directly for ICL limits
as well.
Manasi
>
> Anusha
> >>
> >> Cc: Ville Syrjälä
> >> Cc: Manasi Navare
> >> Signed-off-by: Anusha Srivatsa
> >> ---
> >> drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
> >> 1 file changed, 6 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index 0eb5d66f87a7..aa8bfb754fc1 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct
> >intel_dp *intel_dp,
> >>if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> >>return -EINVAL;
> >>
> >> - dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> - conn_state->max_requested_bpc);
> >> + /* Max DSC Input BPC for TGL+ is 12 */
> >> + if (INTEL_GEN(dev_priv) >= 12)
> >> + dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
> >> + else
> >> + dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> + conn_state->max_requested_bpc);
> >
> >Use 10 here directly
> >
> >>
> >>pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> >>if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> >
> >Use 8 here directly
> >
> >Manasi
> >> --
> >> 2.21.0
> >>
___
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Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 16, 2019 11:15 AM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä
>
>Subject: Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
>
>On Mon, Jul 15, 2019 at 04:40:56PM -0700, Anusha Srivatsa wrote:
>> DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But DSC
>> engine in TGL supports 8, 10 and 12 BPC.
>> Add 12 BPC support for DSC while calculating compression
>> configuration.
>>
>> v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC and use
>> the value directly.(More such defines can be removed as part of future
>> patches). (Ville)
>
>IMO what Ville asked to do in his comment was to remove all the #defines for
>the
>max DSC BPC so remove the ones for 8 and 10 also to mak eit more readable and
>that user does not have to hunt for the #defines for either of these.
Yes those changes can be part of a following patch. This is TGL specific.
Anusha
>>
>> Cc: Ville Syrjälä
>> Cc: Manasi Navare
>> Signed-off-by: Anusha Srivatsa
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 0eb5d66f87a7..aa8bfb754fc1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct
>intel_dp *intel_dp,
>> if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>> return -EINVAL;
>>
>> -dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> -conn_state->max_requested_bpc);
>> +/* Max DSC Input BPC for TGL+ is 12 */
>> +if (INTEL_GEN(dev_priv) >= 12)
>> +dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
>> +else
>> +dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> +conn_state->max_requested_bpc);
>
>Use 10 here directly
>
>>
>> pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>> if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
>
>Use 8 here directly
>
>Manasi
>> --
>> 2.21.0
>>
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Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
On Mon, Jul 15, 2019 at 04:40:56PM -0700, Anusha Srivatsa wrote:
> DSC engine on ICL supports only 8 and 10 BPC as the input
> BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> Add 12 BPC support for DSC while calculating compression
> configuration.
>
> v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
> and use the value directly.(More such defines can be removed
> as part of future patches). (Ville)
IMO what Ville asked to do in his comment was to remove all the #defines
for the max DSC BPC so remove the ones for 8 and 10 also to mak eit more
readable
and that user does not have to hunt for the #defines for either of these.
>
> Cc: Ville Syrjälä
> Cc: Manasi Navare
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0eb5d66f87a7..aa8bfb754fc1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> return -EINVAL;
>
> - dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> - conn_state->max_requested_bpc);
> + /* Max DSC Input BPC for TGL+ is 12 */
> + if (INTEL_GEN(dev_priv) >= 12)
> + dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
> + else
> + dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> + conn_state->max_requested_bpc);
Use 10 here directly
>
> pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
Use 8 here directly
Manasi
> --
> 2.21.0
>
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[Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.
v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
and use the value directly.(More such defines can be removed
as part of future patches). (Ville)
Cc: Ville Syrjälä
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0eb5d66f87a7..aa8bfb754fc1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
- conn_state->max_requested_bpc);
+ /* Max DSC Input BPC for TGL+ is 12 */
+ if (INTEL_GEN(dev_priv) >= 12)
+ dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
+ else
+ dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
+ conn_state->max_requested_bpc);
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
--
2.21.0
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Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, July 12, 2019 10:34 AM
>To: Srivatsa, Anusha
>Cc: Navare, Manasi D ; intel-
>g...@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported
>by TGL
>
>On Fri, Jul 12, 2019 at 05:29:16PM +, Srivatsa, Anusha wrote:
>>
>>
>> >-Original Message-
>> >From: Navare, Manasi D
>> >Sent: Thursday, July 11, 2019 10:24 AM
>> >To: Ville Syrjälä
>> >Cc: Srivatsa, Anusha ; intel-
>> >g...@lists.freedesktop.org
>> >Subject: Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs
>> >supported by TGL
>> >
>> >On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
>> >> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
>> >> > DSC engine on ICL supports only 8 and 10 BPC as the input BPC.
>> >> > But DSC engine in TGL supports 8, 10 and 12 BPC.
>> >> > Add 12 BPC support for DSC while calculating compression
>> >> > configuration.
>> >> >
>> >> > Cc: Manasi Navare
>> >> > Signed-off-by: Anusha Srivatsa
>> >> > ---
>> >> > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
>> >> > 1 file changed, 7 insertions(+), 2 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > index 0bdb7ecc5a81..cd089643c80d 100644
>> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > @@ -71,6 +71,7 @@
>> >> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
>> >> > #define DP_DSC_MIN_SUPPORTED_BPC 8
>> >> > #define DP_DSC_MAX_SUPPORTED_BPC 10
>> >> > +#define TGL_DP_DSC_MAX_SUPPORTED_BPC 12
>> >>
>> >> These defines aren't doing any good IMO. I'd just nuke them.
>> >
>> >So just remove all the #defines and use the values directly?
>>
>> Wont it make it less readable?
>
>It will be more readable because you don't have to go looking for those
>defines.
Ok. Then remove all #defines like Manasi pointed out?
Anusha
>>
>> >>
>> >> >
>> >> > /* DP DSC throughput values used for slice count calculations
>> >> > KPixels/s */
>> >> > #define DP_DSC_PEAK_PIXEL_RATE 272
>> >> > @@ -1911,8 +1912,12 @@ static int
>> >> > intel_dp_dsc_compute_config(struct
>> >intel_dp *intel_dp,
>> >> > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>> >> > return -EINVAL;
>> >> >
>> >> > - dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> >> > - conn_state->max_requested_bpc);
>> >> > + if (INTEL_GEN(dev_priv) > 11)
>> >>
>> >> More customarily >= 12
>> >
>> >I agree
>>
>> Makes sense.
>>
>> Anusha
>> >Manasi
>> >
>> >>
>> >> > + dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
>> >> > + conn_state->max_requested_bpc);
>> >> > + else
>> >> > + dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> >> > + conn_state->max_requested_bpc);
>> >> >
>> >> > pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>> >> > if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
>> >> > --
>> >> > 2.21.0
>> >> >
>> >> > ___
>> >> > Intel-gfx mailing list
>> >> > Intel-gfx@lists.freedesktop.org
>> >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >>
>> >> --
>> >> Ville Syrjälä
>> >> Intel
>> >> ___
>> >> Intel-gfx mailing list
>> >> Intel-gfx@lists.freedesktop.org
>> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
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Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
On Fri, Jul 12, 2019 at 05:29:16PM +, Srivatsa, Anusha wrote:
>
>
> >-Original Message-
> >From: Navare, Manasi D
> >Sent: Thursday, July 11, 2019 10:24 AM
> >To: Ville Syrjälä
> >Cc: Srivatsa, Anusha ; intel-
> >g...@lists.freedesktop.org
> >Subject: Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs
> >supported
> >by TGL
> >
> >On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
> >> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
> >> > DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But
> >> > DSC engine in TGL supports 8, 10 and 12 BPC.
> >> > Add 12 BPC support for DSC while calculating compression
> >> > configuration.
> >> >
> >> > Cc: Manasi Navare
> >> > Signed-off-by: Anusha Srivatsa
> >> > ---
> >> > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
> >> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > index 0bdb7ecc5a81..cd089643c80d 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > @@ -71,6 +71,7 @@
> >> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> >> > #define DP_DSC_MIN_SUPPORTED_BPC8
> >> > #define DP_DSC_MAX_SUPPORTED_BPC10
> >> > +#define TGL_DP_DSC_MAX_SUPPORTED_BPC12
> >>
> >> These defines aren't doing any good IMO. I'd just nuke them.
> >
> >So just remove all the #defines and use the values directly?
>
> Wont it make it less readable?
It will be more readable because you don't have to go looking for those
defines.
>
> >>
> >> >
> >> > /* DP DSC throughput values used for slice count calculations KPixels/s
> >> > */
> >> > #define DP_DSC_PEAK_PIXEL_RATE 272
> >> > @@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct
> >intel_dp *intel_dp,
> >> > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> >> > return -EINVAL;
> >> >
> >> > -dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> > -conn_state->max_requested_bpc);
> >> > +if (INTEL_GEN(dev_priv) > 11)
> >>
> >> More customarily >= 12
> >
> >I agree
>
> Makes sense.
>
> Anusha
> >Manasi
> >
> >>
> >> > +dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
> >> > +conn_state->max_requested_bpc);
> >> > +else
> >> > +dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> > +conn_state->max_requested_bpc);
> >> >
> >> > pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> >> > if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> >> > --
> >> > 2.21.0
> >> >
> >> > ___
> >> > Intel-gfx mailing list
> >> > Intel-gfx@lists.freedesktop.org
> >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>
> >> --
> >> Ville Syrjälä
> >> Intel
> >> ___
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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Intel
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Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
>-Original Message-
>From: Navare, Manasi D
>Sent: Thursday, July 11, 2019 10:24 AM
>To: Ville Syrjälä
>Cc: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported
>by TGL
>
>On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
>> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
>> > DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But
>> > DSC engine in TGL supports 8, 10 and 12 BPC.
>> > Add 12 BPC support for DSC while calculating compression
>> > configuration.
>> >
>> > Cc: Manasi Navare
>> > Signed-off-by: Anusha Srivatsa
>> > ---
>> > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
>> > 1 file changed, 7 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 0bdb7ecc5a81..cd089643c80d 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -71,6 +71,7 @@
>> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER61440
>> > #define DP_DSC_MIN_SUPPORTED_BPC 8
>> > #define DP_DSC_MAX_SUPPORTED_BPC 10
>> > +#define TGL_DP_DSC_MAX_SUPPORTED_BPC 12
>>
>> These defines aren't doing any good IMO. I'd just nuke them.
>
>So just remove all the #defines and use the values directly?
Wont it make it less readable?
>>
>> >
>> > /* DP DSC throughput values used for slice count calculations KPixels/s */
>> > #define DP_DSC_PEAK_PIXEL_RATE272
>> > @@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct
>intel_dp *intel_dp,
>> >if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>> >return -EINVAL;
>> >
>> > - dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> > - conn_state->max_requested_bpc);
>> > + if (INTEL_GEN(dev_priv) > 11)
>>
>> More customarily >= 12
>
>I agree
Makes sense.
Anusha
>Manasi
>
>>
>> > + dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
>> > + conn_state->max_requested_bpc);
>> > + else
>> > + dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> > + conn_state->max_requested_bpc);
>> >
>> >pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>> >if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
>> > --
>> > 2.21.0
>> >
>> > ___
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Ville Syrjälä
>> Intel
>> ___
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>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
> > DSC engine on ICL supports only 8 and 10 BPC as the input
> > BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> > Add 12 BPC support for DSC while calculating compression
> > configuration.
> >
> > Cc: Manasi Navare
> > Signed-off-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0bdb7ecc5a81..cd089643c80d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -71,6 +71,7 @@
> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > #define DP_DSC_MIN_SUPPORTED_BPC 8
> > #define DP_DSC_MAX_SUPPORTED_BPC 10
> > +#define TGL_DP_DSC_MAX_SUPPORTED_BPC 12
>
> These defines aren't doing any good IMO. I'd just nuke them.
So just remove all the #defines and use the values directly?
>
> >
> > /* DP DSC throughput values used for slice count calculations KPixels/s */
> > #define DP_DSC_PEAK_PIXEL_RATE 272
> > @@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct
> > intel_dp *intel_dp,
> > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > return -EINVAL;
> >
> > - dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> > - conn_state->max_requested_bpc);
> > + if (INTEL_GEN(dev_priv) > 11)
>
> More customarily >= 12
I agree
Manasi
>
> > + dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
> > + conn_state->max_requested_bpc);
> > + else
> > + dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> > + conn_state->max_requested_bpc);
> >
> > pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> > if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> > --
> > 2.21.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
> DSC engine on ICL supports only 8 and 10 BPC as the input
> BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> Add 12 BPC support for DSC while calculating compression
> configuration.
>
> Cc: Manasi Navare
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0bdb7ecc5a81..cd089643c80d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -71,6 +71,7 @@
> #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> #define DP_DSC_MIN_SUPPORTED_BPC 8
> #define DP_DSC_MAX_SUPPORTED_BPC 10
> +#define TGL_DP_DSC_MAX_SUPPORTED_BPC 12
These defines aren't doing any good IMO. I'd just nuke them.
>
> /* DP DSC throughput values used for slice count calculations KPixels/s */
> #define DP_DSC_PEAK_PIXEL_RATE 272
> @@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> return -EINVAL;
>
> - dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> - conn_state->max_requested_bpc);
> + if (INTEL_GEN(dev_priv) > 11)
More customarily >= 12
> + dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
> + conn_state->max_requested_bpc);
> + else
> + dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> + conn_state->max_requested_bpc);
>
> pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> --
> 2.21.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0bdb7ecc5a81..cd089643c80d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -71,6 +71,7 @@
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
#define DP_DSC_MIN_SUPPORTED_BPC 8
#define DP_DSC_MAX_SUPPORTED_BPC 10
+#define TGL_DP_DSC_MAX_SUPPORTED_BPC 12
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
- conn_state->max_requested_bpc);
+ if (INTEL_GEN(dev_priv) > 11)
+ dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
+ conn_state->max_requested_bpc);
+ else
+ dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
+ conn_state->max_requested_bpc);
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
--
2.21.0
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