[Intel-gfx] [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default

2015-03-31 Thread Rodrigo Vivi 
Program the default initial value of the L3SqcReg1 on BDW for performance

v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.

v3: Spec shows now a different value. It tells us to set to 0x784000
instead the 0x61 that is there already.
Also rebased after a long time so using WA_WRITE now.

Cc: Mika Kuoppala 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e1a0fd9..7f8b69a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
 #define GEN7_L3SQCREG1 0xB010
 #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
 
+#define GEN8_L3SQCREG1 0xB100
+#define  BDW_WA_L3SQCREG1_DEFAULT  0x784000
+
 #define GEN7_L3CNTLREG10xB01C
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL   0x3C47FF8C
 #define  GEN7_L3AGDIS  (1<<19)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index abe062a..c02fccc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
GEN6_WIZ_HASHING_MASK,
GEN6_WIZ_HASHING_16x4);
 
+   /* WaProgramL3SqcReg1Default:bdw */
+   WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+
return 0;
 }
 
-- 
2.1.0

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[Intel-gfx] [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default

2014-09-30 Thread Rodrigo Vivi 
Program the default initial value of the L3SqcReg1 on BDW for performance

v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.

Cc: Mika Kuoppala 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 36a847a..33143cc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4972,6 +4972,9 @@ enum punit_power_well {
 #define GEN7_L3SQCREG1 0xB010
 #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
 
+#define GEN8_L3SQCREG1 0xB100
+#define  BDW_WA_L3SQCREG1_DEFAULT  0x0061
+
 #define GEN7_L3CNTLREG10xB01C
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL   0x3C47FF8C
 #define  GEN7_L3AGDIS  (1<<19)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 816a692..a37675d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
 * update the number of dwords required based on the
 * actual number of workarounds applied
 */
-   ret = intel_ring_begin(ring, 18);
+   ret = intel_ring_begin(ring, 21);
if (ret)
return ret;
 
@@ -751,6 +751,9 @@ static int bdw_init_workarounds(struct intel_engine_cs 
*ring)
intel_ring_emit_wa(ring, GEN7_GT_MODE,
   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
 
+   /* WaProgramL3SqcReg1Default:bdw */
+   intel_ring_emit_wa(ring, GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+
intel_ring_advance(ring);
 
DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
-- 
1.9.3

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Re: [Intel-gfx] [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default

2015-03-31 Thread shuang . he 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 6107
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV -2  272/272  270/272
ILK -1  302/302  301/302
SNB  303/303  303/303
IVB -1  338/338  337/338
BYT  287/287  287/287
HSW  361/361  361/361
BDW  308/308  308/308
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
 PNV  igt@gem_userptr_blits@coherency-sync  CRASH(2)PASS(3)  
CRASH(1)PASS(1)
 PNV  igt@gem_tiled_pread_pwrite  FAIL(3)PASS(2)  FAIL(1)PASS(1)
*ILK  igt@gem_unfence_active_buffers  PASS(2)  DMESG_WARN(1)PASS(1)
(dmesg patch 
applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...bsd_ring_idle@Hangcheck
 timer elapsed... bsd ring idle
 IVB  igt@gem_storedw_batches_loop@normal  DMESG_WARN(1)PASS(1)  
DMESG_WARN(1)PASS(1)
(dmesg patch 
applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck
 timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
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Re: [Intel-gfx] [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default

2015-04-01 Thread Jani Nikula 
On Wed, 01 Apr 2015, Rodrigo Vivi  wrote:
> Program the default initial value of the L3SqcReg1 on BDW for performance
>
> v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
>
> v3: Spec shows now a different value. It tells us to set to 0x784000
> instead the 0x61 that is there already.
> Also rebased after a long time so using WA_WRITE now.
>
> Cc: Mika Kuoppala 
> Signed-off-by: Rodrigo Vivi 

Cc: stable?

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e1a0fd9..7f8b69a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
>  #define GEN7_L3SQCREG1   0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE   0x00D3
>  
> +#define GEN8_L3SQCREG1   0xB100
> +#define  BDW_WA_L3SQCREG1_DEFAULT0x784000
> +
>  #define GEN7_L3CNTLREG1  0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
>  #define  GEN7_L3AGDIS(1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index abe062a..c02fccc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs 
> *ring)
>   GEN6_WIZ_HASHING_MASK,
>   GEN6_WIZ_HASHING_16x4);
>  
> + /* WaProgramL3SqcReg1Default:bdw */
> + WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +
>   return 0;
>  }
>  
> -- 
> 2.1.0
>
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Re: [Intel-gfx] [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default

2015-04-01 Thread Ville Syrjälä 
On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> Program the default initial value of the L3SqcReg1 on BDW for performance
> 
> v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
> 
> v3: Spec shows now a different value. It tells us to set to 0x784000
> instead the 0x61 that is there already.
> Also rebased after a long time so using WA_WRITE now.

Told you so ;)

http://lists.freedesktop.org/archives/intel-gfx/2014-September/052999.html

> 
> Cc: Mika Kuoppala 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e1a0fd9..7f8b69a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
>  #define GEN7_L3SQCREG1   0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE   0x00D3
>  
> +#define GEN8_L3SQCREG1   0xB100
> +#define  BDW_WA_L3SQCREG1_DEFAULT0x784000
> +
>  #define GEN7_L3CNTLREG1  0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
>  #define  GEN7_L3AGDIS(1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index abe062a..c02fccc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs 
> *ring)
>   GEN6_WIZ_HASHING_MASK,
>   GEN6_WIZ_HASHING_16x4);
>  
> + /* WaProgramL3SqcReg1Default:bdw */
> + WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +
>   return 0;
>  }
>  
> -- 
> 2.1.0
> 
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Re: [Intel-gfx] [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default

2015-04-01 Thread Vivi, Rodrigo 
On Wed, 2015-04-01 at 11:31 +0300, Ville Syrjälä wrote:
> On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> > Program the default initial value of the L3SqcReg1 on BDW for performance
> > 
> > v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
> > 
> > v3: Spec shows now a different value. It tells us to set to 0x784000
> > instead the 0x61 that is there already.
> > Also rebased after a long time so using WA_WRITE now.
> 
> Told you so ;)
> 
> http://lists.freedesktop.org/archives/intel-gfx/2014-September/052999.html

ops, sorry! but now BSpec is updated at least...

So rv-b? :)
> 
> > 
> > Cc: Mika Kuoppala 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 3 +++
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
> >  2 files changed, 6 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 7e1a0fd9..7f8b69a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
> >  #define GEN7_L3SQCREG1 0xB010
> >  #define  VLV_B0_WA_L3SQCREG1_VALUE 0x00D3
> >  
> > +#define GEN8_L3SQCREG1 0xB100
> > +#define  BDW_WA_L3SQCREG1_DEFAULT  0x784000
> > +
> >  #define GEN7_L3CNTLREG10xB01C
> >  #define  GEN7_WA_FOR_GEN7_L3_CONTROL   0x3C47FF8C
> >  #define  GEN7_L3AGDIS  (1<<19)
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index abe062a..c02fccc 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs 
> > *ring)
> > GEN6_WIZ_HASHING_MASK,
> > GEN6_WIZ_HASHING_16x4);
> >  
> > +   /* WaProgramL3SqcReg1Default:bdw */
> > +   WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> > +
> > return 0;
> >  }
> >  
> > -- 
> > 2.1.0
> > 
> > ___
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> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

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Re: [Intel-gfx] [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default

2015-04-01 Thread Ville Syrjälä 
On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> Program the default initial value of the L3SqcReg1 on BDW for performance
> 
> v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
> 
> v3: Spec shows now a different value. It tells us to set to 0x784000
> instead the 0x61 that is there already.
> Also rebased after a long time so using WA_WRITE now.
> 
> Cc: Mika Kuoppala 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e1a0fd9..7f8b69a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5325,6 +5325,9 @@ enum skl_disp_power_wells {
>  #define GEN7_L3SQCREG1   0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE   0x00D3
>  
> +#define GEN8_L3SQCREG1   0xB100
> +#define  BDW_WA_L3SQCREG1_DEFAULT0x784000
> +
>  #define GEN7_L3CNTLREG1  0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
>  #define  GEN7_L3AGDIS(1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index abe062a..c02fccc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs 
> *ring)
>   GEN6_WIZ_HASHING_MASK,
>   GEN6_WIZ_HASHING_16x4);
>  
> + /* WaProgramL3SqcReg1Default:bdw */
> + WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +
>   return 0;
>  }
>  
> -- 
> 2.1.0
> 
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Re: [Intel-gfx] [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default

2015-04-07 Thread Daniel Vetter 
On Wed, Apr 01, 2015 at 06:41:32PM +0300, Ville Syrjälä wrote:
> On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> > Program the default initial value of the L3SqcReg1 on BDW for performance
> > 
> > v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
> > 
> > v3: Spec shows now a different value. It tells us to set to 0x784000
> > instead the 0x61 that is there already.
> > Also rebased after a long time so using WA_WRITE now.
> > 
> > Cc: Mika Kuoppala 
> > Signed-off-by: Rodrigo Vivi 
> 
> Reviewed-by: Ville Syrjälä 

Queued for -next, thanks for the patch.
-Daniel
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Re: [Intel-gfx] [PATCH] drm/i915/bdw: WaProgramL3SqcReg1Default

2014-10-01 Thread Mika Kuoppala 
Rodrigo Vivi  writes:

> Program the default initial value of the L3SqcReg1 on BDW for performance
>
> v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
>
> Cc: Mika Kuoppala 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 36a847a..33143cc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4972,6 +4972,9 @@ enum punit_power_well {
>  #define GEN7_L3SQCREG1   0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE   0x00D3
>  
> +#define GEN8_L3SQCREG1   0xB100
> +#define  BDW_WA_L3SQCREG1_DEFAULT0x0061
> +

This is the default value after reset. I have experimented with other
values and nothing improves above noise level. Further, my suggestion to
using 0x0081 will cause a gpu hang...so there is dragons here.

As you are writing the same default value that is already in register,
and there is no indication that we should refresh anything, I would
say this patch is not needed until someone comes along and shows
something better than what the default is.

Thanks,
-Mika

>  #define GEN7_L3CNTLREG1  0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
>  #define  GEN7_L3AGDIS(1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 816a692..a37675d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine_cs 
> *ring)
>* update the number of dwords required based on the
>* actual number of workarounds applied
>*/
> - ret = intel_ring_begin(ring, 18);
> + ret = intel_ring_begin(ring, 21);
>   if (ret)
>   return ret;
>  
> @@ -751,6 +751,9 @@ static int bdw_init_workarounds(struct intel_engine_cs 
> *ring)
>   intel_ring_emit_wa(ring, GEN7_GT_MODE,
>  GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
>  
> + /* WaProgramL3SqcReg1Default:bdw */
> + intel_ring_emit_wa(ring, GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +
>   intel_ring_advance(ring);
>  
>   DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
> -- 
> 1.9.3
>
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