Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
On 09/28/2017 01:56 PM, Oscar Mateo wrote: On 09/28/2017 02:46 AM, Chris Wilson wrote: Stealing the thread for another gem_workarounds conundrum. After a reset, we lose the RING_FORCE_TO_NONPRIV registers. If they where in the context image as we presumed, the values would be retained and they can be read back from before reset, so it's not the case of write-only register! So are they the mythical powercontext but require an LRI after reset to restore the settings for all logical contexts? Or can we make those into regular MMIO? -Chris I cannot see these in any the context image formats, no matter the GEN, so I suspect they are regular (but privileged) MMIO registers. I think by "These are global registers and power context save/restored" they simply mean that they survive RC6. And, sure enough, these registers do appear in the "Render Engine Power Context" (save/restored by PM), not to be confused with the "Register State Context" (the usual HW context) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
On 09/28/2017 02:46 AM, Chris Wilson wrote: Stealing the thread for another gem_workarounds conundrum. After a reset, we lose the RING_FORCE_TO_NONPRIV registers. If they where in the context image as we presumed, the values would be retained and they can be read back from before reset, so it's not the case of write-only register! So are they the mythical powercontext but require an LRI after reset to restore the settings for all logical contexts? Or can we make those into regular MMIO? -Chris I cannot see these in any the context image formats, no matter the GEN, so I suspect they are regular (but privileged) MMIO registers. I think by "These are global registers and power context save/restored" they simply mean that they survive RC6. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
Stealing the thread for another gem_workarounds conundrum. After a reset, we lose the RING_FORCE_TO_NONPRIV registers. If they where in the context image as we presumed, the values would be retained and they can be read back from before reset, so it's not the case of write-only register! So are they the mythical powercontext but require an LRI after reset to restore the settings for all logical contexts? Or can we make those into regular MMIO? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
Quoting Oscar Mateo (2017-09-27 18:37:07)
>
>
> On 09/27/2017 03:37 AM, Mika Kuoppala wrote:
> > Chris Wilson writes:
> >
> >> Quoting Rodrigo Vivi (2017-08-23 00:27:15)
> >>> To avoid a potential hang condition with TLB invalidation
> >>> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
> >>>
> >>> Same workaround was in place for previous platforms,
> >>> but the change for CNL is more on the register offset.
> >>> But also BSpec doesn't mention the bit 15 as set on gen9
> >>> platforms and mark bit as reserved on CNL.
> >>>
> >>> Cc: Mika Kuoppala
> >>> Cc: Oscar Mateo
> >>> Signed-off-by: Rodrigo Vivi
> >>> ---
> >>> drivers/gpu/drm/i915/i915_reg.h| 1 +
> >>> drivers/gpu/drm/i915/intel_engine_cs.c | 4
> >>> 2 files changed, 5 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >>> b/drivers/gpu/drm/i915/i915_reg.h
> >>> index d4ecb1905ad8..f31fab2651fb 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> @@ -7024,6 +7024,7 @@ enum {
> >>>
> >>> /* GEN8 chicken */
> >>> #define HDC_CHICKEN0 _MMIO(0x7300)
> >>> +#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> >>> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
> >>> #define HDC_FENCE_DEST_SLM_DISABLE(1<<14)
> >>> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> >>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> b/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> index d23f18874309..26c35ce5f240 100644
> >>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct
> >>> intel_engine_cs *engine)
> >>> struct drm_i915_private *dev_priv = engine->i915;
> >>> int ret;
> >>>
> >>> + /* WaForceContextSaveRestoreNonCoherent:cnl */
> >>> + WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> >>> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> >> This register is not sticky (i.e. does not retain its value even with a
> >> powercontext loaded). Does it even exist?
> >> -Chris
> > That is a good question. The documentation indicates it does
> > and evidence indicates that it doesn't.
> >
> > I will check when I get cnl unless someone beats me to it.
> >
> > -Mika
>
> H... there is a "programming note" in the BSpec for CNL+ that says:
>
> "The register is write-only from LRI command. However, it is readable
> for context save."
Ugh. So gem_workarounds can't read it directly or via SRM to check we
set it. But if we dumped the context image, we could find it. The test
will just have to learn to live without it.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
On 09/27/2017 03:37 AM, Mika Kuoppala wrote:
Chris Wilson writes:
Quoting Rodrigo Vivi (2017-08-23 00:27:15)
To avoid a potential hang condition with TLB invalidation
we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
Same workaround was in place for previous platforms,
but the change for CNL is more on the register offset.
But also BSpec doesn't mention the bit 15 as set on gen9
platforms and mark bit as reserved on CNL.
Cc: Mika Kuoppala
Cc: Oscar Mateo
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4ecb1905ad8..f31fab2651fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7024,6 +7024,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
+#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE(1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d23f18874309..26c35ce5f240 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs
*engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
+ /* WaForceContextSaveRestoreNonCoherent:cnl */
+ WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
This register is not sticky (i.e. does not retain its value even with a
powercontext loaded). Does it even exist?
-Chris
That is a good question. The documentation indicates it does
and evidence indicates that it doesn't.
I will check when I get cnl unless someone beats me to it.
-Mika
H... there is a "programming note" in the BSpec for CNL+ that says:
"The register is write-only from LRI command. However, it is readable
for context save."
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
Chris Wilson writes:
> Quoting Rodrigo Vivi (2017-08-23 00:27:15)
>> To avoid a potential hang condition with TLB invalidation
>> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>>
>> Same workaround was in place for previous platforms,
>> but the change for CNL is more on the register offset.
>> But also BSpec doesn't mention the bit 15 as set on gen9
>> platforms and mark bit as reserved on CNL.
>>
>> Cc: Mika Kuoppala
>> Cc: Oscar Mateo
>> Signed-off-by: Rodrigo Vivi
>> ---
>> drivers/gpu/drm/i915/i915_reg.h| 1 +
>> drivers/gpu/drm/i915/intel_engine_cs.c | 4
>> 2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index d4ecb1905ad8..f31fab2651fb 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7024,6 +7024,7 @@ enum {
>>
>> /* GEN8 chicken */
>> #define HDC_CHICKEN0 _MMIO(0x7300)
>> +#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
>> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
>> #define HDC_FENCE_DEST_SLM_DISABLE(1<<14)
>> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
>> b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index d23f18874309..26c35ce5f240 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct
>> intel_engine_cs *engine)
>> struct drm_i915_private *dev_priv = engine->i915;
>> int ret;
>>
>> + /* WaForceContextSaveRestoreNonCoherent:cnl */
>> + WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
>> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
>
> This register is not sticky (i.e. does not retain its value even with a
> powercontext loaded). Does it even exist?
> -Chris
That is a good question. The documentation indicates it does
and evidence indicates that it doesn't.
I will check when I get cnl unless someone beats me to it.
-Mika
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
Quoting Rodrigo Vivi (2017-08-23 00:27:15)
> To avoid a potential hang condition with TLB invalidation
> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>
> Same workaround was in place for previous platforms,
> but the change for CNL is more on the register offset.
> But also BSpec doesn't mention the bit 15 as set on gen9
> platforms and mark bit as reserved on CNL.
>
> Cc: Mika Kuoppala
> Cc: Oscar Mateo
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h| 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 4
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4ecb1905ad8..f31fab2651fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7024,6 +7024,7 @@ enum {
>
> /* GEN8 chicken */
> #define HDC_CHICKEN0 _MMIO(0x7300)
> +#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
> #define HDC_FENCE_DEST_SLM_DISABLE(1<<14)
> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d23f18874309..26c35ce5f240 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs
> *engine)
> struct drm_i915_private *dev_priv = engine->i915;
> int ret;
>
> + /* WaForceContextSaveRestoreNonCoherent:cnl */
> + WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
This register is not sticky (i.e. does not retain its value even with a
powercontext loaded). Does it even exist?
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
patch merged to dinq. thanks for the review and suggestion.
On Wed, Aug 23, 2017 at 1:35 PM, Rodrigo Vivi wrote:
> To avoid a potential hang condition with TLB invalidation
> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>
> Same workaround was in place for previous platforms,
> but the register offset has changed for CNL.
> But also BSpec doesn't mention the bit 15 as set on gen9
> platforms and mark bit as reserved on CNL.
>
> v2: Improve commit message accepting Oscar's suggestion.
>
> Cc: Mika Kuoppala
> Cc: Oscar Mateo
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: Oscar Mateo
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20170822232715.3220-1-rodrigo.v...@intel.com
with proper link fixed when merging, instead of this one...
> ---
> drivers/gpu/drm/i915/i915_reg.h| 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 4
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d9b0249fe5a1..c59c590e45c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7024,6 +7024,7 @@ enum {
>
> /* GEN8 chicken */
> #define HDC_CHICKEN0 _MMIO(0x7300)
> +#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
> #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
> #define HDC_FENCE_DEST_SLM_DISABLE(1<<14)
> #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d7e1ccf778a2..a6ac9d0a4156 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs
> *engine)
> struct drm_i915_private *dev_priv = engine->i915;
> int ret;
>
> + /* WaForceContextSaveRestoreNonCoherent:cnl */
> + WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> +
> /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
> WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> --
> 2.13.2
>
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--
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Blog: http://blog.vivi.eng.br
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[Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
To avoid a potential hang condition with TLB invalidation
we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
Same workaround was in place for previous platforms,
but the register offset has changed for CNL.
But also BSpec doesn't mention the bit 15 as set on gen9
platforms and mark bit as reserved on CNL.
v2: Improve commit message accepting Oscar's suggestion.
Cc: Mika Kuoppala
Cc: Oscar Mateo
Signed-off-by: Rodrigo Vivi
Reviewed-by: Oscar Mateo
Link:
https://patchwork.freedesktop.org/patch/msgid/20170822232715.3220-1-rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d9b0249fe5a1..c59c590e45c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7024,6 +7024,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
+#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE(1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d7e1ccf778a2..a6ac9d0a4156 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs
*engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
+ /* WaForceContextSaveRestoreNonCoherent:cnl */
+ WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+
/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
--
2.13.2
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
On 08/22/2017 04:27 PM, Rodrigo Vivi wrote:
To avoid a potential hang condition with TLB invalidation
we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
Same workaround was in place for previous platforms,
but the change for CNL is more on the register offset.
"but the register offset has changed for CNL"?
But also BSpec doesn't mention the bit 15 as set on gen9
platforms and mark bit as reserved on CNL.
Cc: Mika Kuoppala
Cc: Oscar Mateo
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 4
2 files changed, 5 insertions(+)
Reviewed-by: Oscar Mateo
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4ecb1905ad8..f31fab2651fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7024,6 +7024,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
+#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d23f18874309..26c35ce5f240 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs
*engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
+ /* WaForceContextSaveRestoreNonCoherent:cnl */
+ WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+
/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
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[Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
To avoid a potential hang condition with TLB invalidation
we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
Same workaround was in place for previous platforms,
but the change for CNL is more on the register offset.
But also BSpec doesn't mention the bit 15 as set on gen9
platforms and mark bit as reserved on CNL.
Cc: Mika Kuoppala
Cc: Oscar Mateo
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4ecb1905ad8..f31fab2651fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7024,6 +7024,7 @@ enum {
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
+#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE(1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d23f18874309..26c35ce5f240 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs
*engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
+ /* WaForceContextSaveRestoreNonCoherent:cnl */
+ WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+
/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
--
2.13.2
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