Re: [Intel-gfx] [PATCH] drm/i915/display Try YCbCr420 color when RGB fails
On Mon, May 03, 2021 at 01:39:04PM +0200, Werner Sembach wrote:
> Thanks for the feedback. I got some questions below.
> > On Thu, Apr 29, 2021 at 02:05:53PM +0200, Werner Sembach wrote:
> >> When encoder validation of a display mode fails, retry with less bandwidth
> >> heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups
> >> to support 4k60Hz output, which previously failed silently.
> >>
> >> AMDGPU had nearly the exact same issue. This problem description is
> >> therefore copied from my commit message of the AMDGPU patch.
> >>
> >> On some setups, while the monitor and the gpu support display modes with
> >> pixel clocks of up to 600MHz, the link encoder might not. This prevents
> >> YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be
> >> possible. However, which color mode is used is decided before the link
> >> encoder capabilities are checked. This patch fixes the problem by retrying
> >> to find a display mode with YCbCr420 enforced and using it, if it is
> >> valid.
> >>
> >> I'm not entierly sure if the second
> >> "if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))" check in
> >> intel_hdmi_compute_config(...) after forcing ycbcr420 is necessary. I
> >> included it to better be safe then sorry.
> >>
> >> Signed-off-by: Werner Sembach
> >> Cc:
> >> ---
> >> Rebased from 5.12 to drm-tip and resend to resolve merge conflict.
> >>
> >> >From 876c1c8d970ff2a411ee8d08651bd4edbe9ecb3d Mon Sep 17 00:00:00 2001
> >> From: Werner Sembach
> >> Date: Thu, 29 Apr 2021 13:59:30 +0200
> >> Subject: [PATCH] Retry using YCbCr420 encoding if clock setup for RGB fails
> >>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_hdmi.c | 80 +--
> >> 1 file changed, 60 insertions(+), 20 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> >> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> >> index 46de56af33db..c9b5a7d7f9c6 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> >> @@ -1861,6 +1861,30 @@ static int intel_hdmi_port_clock(int clock, int bpc)
> >>return clock * bpc / 8;
> >> }
> >>
> >> +static enum drm_mode_status
> >> +intel_hdmi_check_bpc(struct intel_hdmi *hdmi, int clock, bool
> >> has_hdmi_sink, struct drm_i915_private *dev_priv)
> > Don't pass dev_priv. It can be extracted from the intel_hdmi.
> >
> > The name of the function isn't really sitting super well with me.
> > I guess I'd just call it something like intel_hdmi_mode_clock_valid().
> >
> > We should also split this big patch up into smaller parts. Just this
> > mechanical extraction of this function without any functional changes
> > could be a nice first patch in the series.
> >
> >> +{
> >> + enum drm_mode_status status;
> >> +
> >> + /* check if we can do 8bpc */
> >> + status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
> >> + true, has_hdmi_sink);
> >> +
> >> + if (has_hdmi_sink) {
> >> + /* if we can't do 8bpc we may still be able to do 12bpc */
> >> + if (status != MODE_OK && !HAS_GMCH(dev_priv))
> >> + status = hdmi_port_clock_valid(hdmi,
> >> intel_hdmi_port_clock(clock, 12),
> >> + true, has_hdmi_sink);
> >> +
> >> + /* if we can't do 8,12bpc we may still be able to do 10bpc */
> >> + if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
> >> + status = hdmi_port_clock_valid(hdmi,
> >> intel_hdmi_port_clock(clock, 10),
> >> + true, has_hdmi_sink);
> >> + }
> >> +
> >> + return status;
> >> +}
> >> +
> >> static enum drm_mode_status
> >> intel_hdmi_mode_valid(struct drm_connector *connector,
> >> struct drm_display_mode *mode)
> >> @@ -1891,23 +1915,18 @@ intel_hdmi_mode_valid(struct drm_connector
> >> *connector,
> >>if (drm_mode_is_420_only(>display_info, mode))
> >>clock /= 2;
> >>
> >> - /* check if we can do 8bpc */
> >> - status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
> >> - true, has_hdmi_sink);
> >> + status = intel_hdmi_check_bpc(hdmi, clock, has_hdmi_sink, dev_priv);
> >>
> >> - if (has_hdmi_sink) {
> >> - /* if we can't do 8bpc we may still be able to do 12bpc */
> >> - if (status != MODE_OK && !HAS_GMCH(dev_priv))
> >> - status = hdmi_port_clock_valid(hdmi,
> >> intel_hdmi_port_clock(clock, 12),
> >> - true, has_hdmi_sink);
> >> + if (status != MODE_OK) {
> >> + if (drm_mode_is_420_also(>display_info, mode)) {
> > We also need a connector->ycbcr_420_allowed check here.
> >
> >> + /* if we can't do full color resolution we may still be
> >> able to do reduced color resolution */
> >> + clock /= 2;
> >>
> >> -
Re: [Intel-gfx] [PATCH] drm/i915/display Try YCbCr420 color when RGB fails
Thanks for the feedback. I got some questions below.
> On Thu, Apr 29, 2021 at 02:05:53PM +0200, Werner Sembach wrote:
>> When encoder validation of a display mode fails, retry with less bandwidth
>> heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups
>> to support 4k60Hz output, which previously failed silently.
>>
>> AMDGPU had nearly the exact same issue. This problem description is
>> therefore copied from my commit message of the AMDGPU patch.
>>
>> On some setups, while the monitor and the gpu support display modes with
>> pixel clocks of up to 600MHz, the link encoder might not. This prevents
>> YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be
>> possible. However, which color mode is used is decided before the link
>> encoder capabilities are checked. This patch fixes the problem by retrying
>> to find a display mode with YCbCr420 enforced and using it, if it is
>> valid.
>>
>> I'm not entierly sure if the second
>> "if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))" check in
>> intel_hdmi_compute_config(...) after forcing ycbcr420 is necessary. I
>> included it to better be safe then sorry.
>>
>> Signed-off-by: Werner Sembach
>> Cc:
>> ---
>> Rebased from 5.12 to drm-tip and resend to resolve merge conflict.
>>
>> >From 876c1c8d970ff2a411ee8d08651bd4edbe9ecb3d Mon Sep 17 00:00:00 2001
>> From: Werner Sembach
>> Date: Thu, 29 Apr 2021 13:59:30 +0200
>> Subject: [PATCH] Retry using YCbCr420 encoding if clock setup for RGB fails
>>
>> ---
>> drivers/gpu/drm/i915/display/intel_hdmi.c | 80 +--
>> 1 file changed, 60 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> index 46de56af33db..c9b5a7d7f9c6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> @@ -1861,6 +1861,30 @@ static int intel_hdmi_port_clock(int clock, int bpc)
>> return clock * bpc / 8;
>> }
>>
>> +static enum drm_mode_status
>> +intel_hdmi_check_bpc(struct intel_hdmi *hdmi, int clock, bool
>> has_hdmi_sink, struct drm_i915_private *dev_priv)
> Don't pass dev_priv. It can be extracted from the intel_hdmi.
>
> The name of the function isn't really sitting super well with me.
> I guess I'd just call it something like intel_hdmi_mode_clock_valid().
>
> We should also split this big patch up into smaller parts. Just this
> mechanical extraction of this function without any functional changes
> could be a nice first patch in the series.
>
>> +{
>> +enum drm_mode_status status;
>> +
>> +/* check if we can do 8bpc */
>> +status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
>> + true, has_hdmi_sink);
>> +
>> +if (has_hdmi_sink) {
>> +/* if we can't do 8bpc we may still be able to do 12bpc */
>> +if (status != MODE_OK && !HAS_GMCH(dev_priv))
>> +status = hdmi_port_clock_valid(hdmi,
>> intel_hdmi_port_clock(clock, 12),
>> + true, has_hdmi_sink);
>> +
>> +/* if we can't do 8,12bpc we may still be able to do 10bpc */
>> +if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
>> +status = hdmi_port_clock_valid(hdmi,
>> intel_hdmi_port_clock(clock, 10),
>> + true, has_hdmi_sink);
>> +}
>> +
>> +return status;
>> +}
>> +
>> static enum drm_mode_status
>> intel_hdmi_mode_valid(struct drm_connector *connector,
>>struct drm_display_mode *mode)
>> @@ -1891,23 +1915,18 @@ intel_hdmi_mode_valid(struct drm_connector
>> *connector,
>> if (drm_mode_is_420_only(>display_info, mode))
>> clock /= 2;
>>
>> -/* check if we can do 8bpc */
>> -status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
>> - true, has_hdmi_sink);
>> +status = intel_hdmi_check_bpc(hdmi, clock, has_hdmi_sink, dev_priv);
>>
>> -if (has_hdmi_sink) {
>> -/* if we can't do 8bpc we may still be able to do 12bpc */
>> -if (status != MODE_OK && !HAS_GMCH(dev_priv))
>> -status = hdmi_port_clock_valid(hdmi,
>> intel_hdmi_port_clock(clock, 12),
>> - true, has_hdmi_sink);
>> +if (status != MODE_OK) {
>> +if (drm_mode_is_420_also(>display_info, mode)) {
> We also need a connector->ycbcr_420_allowed check here.
>
>> +/* if we can't do full color resolution we may still be
>> able to do reduced color resolution */
>> +clock /= 2;
>>
>> -/* if we can't do 8,12bpc we may still be able to do 10bpc */
>> -if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
>> -status = hdmi_port_clock_valid(hdmi,
>>
Re: [Intel-gfx] [PATCH] drm/i915/display Try YCbCr420 color when RGB fails
On Thu, Apr 29, 2021 at 02:05:53PM +0200, Werner Sembach wrote:
> When encoder validation of a display mode fails, retry with less bandwidth
> heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups
> to support 4k60Hz output, which previously failed silently.
>
> AMDGPU had nearly the exact same issue. This problem description is
> therefore copied from my commit message of the AMDGPU patch.
>
> On some setups, while the monitor and the gpu support display modes with
> pixel clocks of up to 600MHz, the link encoder might not. This prevents
> YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be
> possible. However, which color mode is used is decided before the link
> encoder capabilities are checked. This patch fixes the problem by retrying
> to find a display mode with YCbCr420 enforced and using it, if it is
> valid.
>
> I'm not entierly sure if the second
> "if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))" check in
> intel_hdmi_compute_config(...) after forcing ycbcr420 is necessary. I
> included it to better be safe then sorry.
>
> Signed-off-by: Werner Sembach
> Cc:
> ---
> Rebased from 5.12 to drm-tip and resend to resolve merge conflict.
>
> >From 876c1c8d970ff2a411ee8d08651bd4edbe9ecb3d Mon Sep 17 00:00:00 2001
> From: Werner Sembach
> Date: Thu, 29 Apr 2021 13:59:30 +0200
> Subject: [PATCH] Retry using YCbCr420 encoding if clock setup for RGB fails
>
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 80 +--
> 1 file changed, 60 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 46de56af33db..c9b5a7d7f9c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1861,6 +1861,30 @@ static int intel_hdmi_port_clock(int clock, int bpc)
> return clock * bpc / 8;
> }
>
> +static enum drm_mode_status
> +intel_hdmi_check_bpc(struct intel_hdmi *hdmi, int clock, bool has_hdmi_sink,
> struct drm_i915_private *dev_priv)
Don't pass dev_priv. It can be extracted from the intel_hdmi.
The name of the function isn't really sitting super well with me.
I guess I'd just call it something like intel_hdmi_mode_clock_valid().
We should also split this big patch up into smaller parts. Just this
mechanical extraction of this function without any functional changes
could be a nice first patch in the series.
> +{
> + enum drm_mode_status status;
> +
> + /* check if we can do 8bpc */
> + status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
> +true, has_hdmi_sink);
> +
> + if (has_hdmi_sink) {
> + /* if we can't do 8bpc we may still be able to do 12bpc */
> + if (status != MODE_OK && !HAS_GMCH(dev_priv))
> + status = hdmi_port_clock_valid(hdmi,
> intel_hdmi_port_clock(clock, 12),
> +true, has_hdmi_sink);
> +
> + /* if we can't do 8,12bpc we may still be able to do 10bpc */
> + if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
> + status = hdmi_port_clock_valid(hdmi,
> intel_hdmi_port_clock(clock, 10),
> +true, has_hdmi_sink);
> + }
> +
> + return status;
> +}
> +
> static enum drm_mode_status
> intel_hdmi_mode_valid(struct drm_connector *connector,
> struct drm_display_mode *mode)
> @@ -1891,23 +1915,18 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> if (drm_mode_is_420_only(>display_info, mode))
> clock /= 2;
>
> - /* check if we can do 8bpc */
> - status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
> -true, has_hdmi_sink);
> + status = intel_hdmi_check_bpc(hdmi, clock, has_hdmi_sink, dev_priv);
>
> - if (has_hdmi_sink) {
> - /* if we can't do 8bpc we may still be able to do 12bpc */
> - if (status != MODE_OK && !HAS_GMCH(dev_priv))
> - status = hdmi_port_clock_valid(hdmi,
> intel_hdmi_port_clock(clock, 12),
> -true, has_hdmi_sink);
> + if (status != MODE_OK) {
> + if (drm_mode_is_420_also(>display_info, mode)) {
We also need a connector->ycbcr_420_allowed check here.
> + /* if we can't do full color resolution we may still be
> able to do reduced color resolution */
> + clock /= 2;
>
> - /* if we can't do 8,12bpc we may still be able to do 10bpc */
> - if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
> - status = hdmi_port_clock_valid(hdmi,
> intel_hdmi_port_clock(clock, 10),
> -true, has_hdmi_sink);
> + status =
[Intel-gfx] [PATCH] drm/i915/display Try YCbCr420 color when RGB fails
When encoder validation of a display mode fails, retry with less bandwidth
heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups
to support 4k60Hz output, which previously failed silently.
AMDGPU had nearly the exact same issue. This problem description is
therefore copied from my commit message of the AMDGPU patch.
On some setups, while the monitor and the gpu support display modes with
pixel clocks of up to 600MHz, the link encoder might not. This prevents
YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be
possible. However, which color mode is used is decided before the link
encoder capabilities are checked. This patch fixes the problem by retrying
to find a display mode with YCbCr420 enforced and using it, if it is
valid.
I'm not entierly sure if the second
"if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))" check in
intel_hdmi_compute_config(...) after forcing ycbcr420 is necessary. I
included it to better be safe then sorry.
Signed-off-by: Werner Sembach
Cc:
---
Rebased from 5.12 to drm-tip and resend to resolve merge conflict.
>From 876c1c8d970ff2a411ee8d08651bd4edbe9ecb3d Mon Sep 17 00:00:00 2001
From: Werner Sembach
Date: Thu, 29 Apr 2021 13:59:30 +0200
Subject: [PATCH] Retry using YCbCr420 encoding if clock setup for RGB fails
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 80 +--
1 file changed, 60 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 46de56af33db..c9b5a7d7f9c6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1861,6 +1861,30 @@ static int intel_hdmi_port_clock(int clock, int bpc)
return clock * bpc / 8;
}
+static enum drm_mode_status
+intel_hdmi_check_bpc(struct intel_hdmi *hdmi, int clock, bool has_hdmi_sink,
struct drm_i915_private *dev_priv)
+{
+ enum drm_mode_status status;
+
+ /* check if we can do 8bpc */
+ status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
+ true, has_hdmi_sink);
+
+ if (has_hdmi_sink) {
+ /* if we can't do 8bpc we may still be able to do 12bpc */
+ if (status != MODE_OK && !HAS_GMCH(dev_priv))
+ status = hdmi_port_clock_valid(hdmi,
intel_hdmi_port_clock(clock, 12),
+ true, has_hdmi_sink);
+
+ /* if we can't do 8,12bpc we may still be able to do 10bpc */
+ if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
+ status = hdmi_port_clock_valid(hdmi,
intel_hdmi_port_clock(clock, 10),
+ true, has_hdmi_sink);
+ }
+
+ return status;
+}
+
static enum drm_mode_status
intel_hdmi_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -1891,23 +1915,18 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
if (drm_mode_is_420_only(>display_info, mode))
clock /= 2;
- /* check if we can do 8bpc */
- status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
- true, has_hdmi_sink);
+ status = intel_hdmi_check_bpc(hdmi, clock, has_hdmi_sink, dev_priv);
- if (has_hdmi_sink) {
- /* if we can't do 8bpc we may still be able to do 12bpc */
- if (status != MODE_OK && !HAS_GMCH(dev_priv))
- status = hdmi_port_clock_valid(hdmi,
intel_hdmi_port_clock(clock, 12),
- true, has_hdmi_sink);
+ if (status != MODE_OK) {
+ if (drm_mode_is_420_also(>display_info, mode)) {
+ /* if we can't do full color resolution we may still be
able to do reduced color resolution */
+ clock /= 2;
- /* if we can't do 8,12bpc we may still be able to do 10bpc */
- if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
- status = hdmi_port_clock_valid(hdmi,
intel_hdmi_port_clock(clock, 10),
- true, has_hdmi_sink);
+ status = intel_hdmi_check_bpc(hdmi, clock,
has_hdmi_sink, dev_priv);
+ }
+ if (status != MODE_OK)
+ return status;
}
- if (status != MODE_OK)
- return status;
return intel_mode_valid_max_plane_size(dev_priv, mode, false);
}
@@ -1990,14 +2009,17 @@ static bool hdmi_deep_color_possible(const struct
intel_crtc_state *crtc_state,
static int
intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+ const struct drm_connector_state *conn_state,
+
[Intel-gfx] [PATCH] drm/i915/display Try YCbCr420 color when RGB fails
When encoder validation of a display mode fails, retry with less bandwidth
heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups
to support 4k60Hz output, which previously failed silently.
AMDGPU had nearly the exact same issue. This problem description is
therefore copied from my commit message of the AMDGPU patch.
On some setups, while the monitor and the gpu support display modes with
pixel clocks of up to 600MHz, the link encoder might not. This prevents
YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be
possible. However, which color mode is used is decided before the link
encoder capabilities are checked. This patch fixes the problem by retrying
to find a display mode with YCbCr420 enforced and using it, if it is
valid.
I'm not entierly sure if the second
"if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))" check in
intel_hdmi_compute_config(...) after forcing ycbcr420 is necessary. I
included it to better be safe then sorry.
Signed-off-by: Werner Sembach
Cc:
---
>From c7499210af78e15a2aea2178000958f26e0d43a0 Mon Sep 17 00:00:00 2001
From: Werner Sembach
Date: Tue, 30 Mar 2021 15:07:34 +0200
Subject: [PATCH] Retry using YCbCr420 encoding if clock setup for RGB fails
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 78 +--
1 file changed, 59 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 95919d325b0b..273685c0e395 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2233,6 +2233,29 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
return MODE_OK;
}
+static enum drm_mode_status
+intel_hdmi_check_bpc(struct intel_hdmi *hdmi, int clock, bool has_hdmi_sink,
struct drm_i915_private *dev_priv)
+{
+ enum drm_mode_status status;
+
+ /* check if we can do 8bpc */
+ status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink);
+
+ if (has_hdmi_sink) {
+ /* if we can't do 8bpc we may still be able to do 12bpc */
+ if (status != MODE_OK && !HAS_GMCH(dev_priv))
+ status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
+ true, has_hdmi_sink);
+
+ /* if we can't do 8,12bpc we may still be able to do 10bpc */
+ if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
+ status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
+ true, has_hdmi_sink);
+ }
+
+ return status;
+}
+
static enum drm_mode_status
intel_hdmi_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@@ -2263,22 +2286,18 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
if (drm_mode_is_420_only(>display_info, mode))
clock /= 2;
- /* check if we can do 8bpc */
- status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink);
+ status = intel_hdmi_check_bpc(hdmi, clock, has_hdmi_sink, dev_priv);
- if (has_hdmi_sink) {
- /* if we can't do 8bpc we may still be able to do 12bpc */
- if (status != MODE_OK && !HAS_GMCH(dev_priv))
- status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
- true, has_hdmi_sink);
+ if (status != MODE_OK) {
+ if (drm_mode_is_420_also(>display_info, mode)) {
+ /* if we can't do full color resolution we may still be
able to do reduced color resolution */
+ clock /= 2;
- /* if we can't do 8,12bpc we may still be able to do 10bpc */
- if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
- status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
- true, has_hdmi_sink);
+ status = intel_hdmi_check_bpc(hdmi, clock,
has_hdmi_sink, dev_priv);
+ }
+ if (status != MODE_OK)
+ return status;
}
- if (status != MODE_OK)
- return status;
return intel_mode_valid_max_plane_size(dev_priv, mode, false);
}
@@ -2361,14 +2380,17 @@ static bool hdmi_deep_color_possible(const struct
intel_crtc_state *crtc_state,
static int
intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+ const struct drm_connector_state *conn_state,
+ const bool force_ycbcr420)
{
struct drm_connector *connector = conn_state->connector;
struct drm_i915_private *i915 = to_i915(connector->dev);
const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
- if
