Re: [Intel-gfx] [PATCH] drm/i915/gvt: Fix build failure after intel_engine_cs change

[Chris Wilson]

On Tue, Oct 18, 2016 at 09:40:07AM +0800, Zhenyu Wang wrote:
> Change GVT-g code reference for intel_engine_cs from static array to
> allocated pointer after commit 3b3f1650b1ca ("drm/i915: Allocate
> intel_engine_cs structure only for the enabled engines").

You also need to enable deprecation warnings and fix the use of obsolete
functions.
-Chris

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Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] drm/i915/gvt: Fix build failure after intel_engine_cs change

[Zhenyu Wang]

On 2016.10.18 09:47:56 +0300, Joonas Lahtinen wrote:
> On ti, 2016-10-18 at 09:40 +0800, Zhenyu Wang wrote:
> > @@ -134,7 +134,7 @@ static int render_mmio_to_ring_id(struct intel_gvt 
> > *gvt, unsigned int reg)
> >  
> >     reg &= ~GENMASK(11, 0);
> >     for (i = 0; i < I915_NUM_ENGINES; i++) {
> > -   if (gvt->dev_priv->engine[i].mmio_base == reg)
> > +   if (gvt->dev_priv->engine[i]->mmio_base == reg)
> >     return i;
> >     }
> 
> This loop is bad now that engine[i] might be NULL. Use for_each_engine
> instead.
> 

yes, we're fixing this with newly merged code and testing for VM,
should be fixed in next pull request.

Thanks

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Re: [Intel-gfx] [PATCH] drm/i915/gvt: Fix build failure after intel_engine_cs change

[Joonas Lahtinen]

On ti, 2016-10-18 at 09:40 +0800, Zhenyu Wang wrote:
> @@ -134,7 +134,7 @@ static int render_mmio_to_ring_id(struct intel_gvt *gvt, 
> unsigned int reg)
>  
>   reg &= ~GENMASK(11, 0);
>   for (i = 0; i < I915_NUM_ENGINES; i++) {
> - if (gvt->dev_priv->engine[i].mmio_base == reg)
> + if (gvt->dev_priv->engine[i]->mmio_base == reg)
>   return i;
>   }

This loop is bad now that engine[i] might be NULL. Use for_each_engine
instead.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH] drm/i915/gvt: Fix build failure after intel_engine_cs change

[Zhenyu Wang]

Change GVT-g code reference for intel_engine_cs from static array to
allocated pointer after commit 3b3f1650b1ca ("drm/i915: Allocate
intel_engine_cs structure only for the enabled engines").

Signed-off-by: Zhenyu Wang 
---
 drivers/gpu/drm/i915/gvt/execlist.c  | 2 +-
 drivers/gpu/drm/i915/gvt/handlers.c  | 2 +-
 drivers/gpu/drm/i915/gvt/scheduler.c | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/execlist.c 
b/drivers/gpu/drm/i915/gvt/execlist.c
index 4a00ee7..c50a3d1 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -39,7 +39,7 @@
 #define _EL_OFFSET_STATUS_PTR   0x3A0
 
 #define execlist_ring_mmio(gvt, ring_id, offset) \
-   (gvt->dev_priv->engine[ring_id].mmio_base + (offset))
+   (gvt->dev_priv->engine[ring_id]->mmio_base + (offset))
 
 #define valid_context(ctx) ((ctx)->valid)
 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index d59a934..e8ec403 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -134,7 +134,7 @@ static int render_mmio_to_ring_id(struct intel_gvt *gvt, 
unsigned int reg)
 
reg &= ~GENMASK(11, 0);
for (i = 0; i < I915_NUM_ENGINES; i++) {
-   if (gvt->dev_priv->engine[i].mmio_base == reg)
+   if (gvt->dev_priv->engine[i]->mmio_base == reg)
return i;
}
return -1;
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 732672b..b15cdf5 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -68,7 +68,7 @@ static int populate_shadow_context(struct intel_vgpu_workload 
*workload)
workload->ctx_desc.lrca);
 
context_page_num = intel_lr_context_size(
-   >dev_priv->engine[ring_id]);
+   gvt->dev_priv->engine[ring_id]);
 
context_page_num = context_page_num >> PAGE_SHIFT;
 
@@ -171,7 +171,7 @@ static int dispatch_workload(struct intel_vgpu_workload 
*workload)
shadow_ctx->desc_template = workload->ctx_desc.addressing_mode <<
GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
-   workload->req = i915_gem_request_alloc(_priv->engine[ring_id],
+   workload->req = i915_gem_request_alloc(dev_priv->engine[ring_id],
   shadow_ctx);
if (IS_ERR_OR_NULL(workload->req)) {
gvt_err("fail to allocate gem request\n");
@@ -298,7 +298,7 @@ static void update_guest_context(struct intel_vgpu_workload 
*workload)
workload->ctx_desc.lrca);
 
context_page_num = intel_lr_context_size(
-   >dev_priv->engine[ring_id]);
+   gvt->dev_priv->engine[ring_id]);
 
context_page_num = context_page_num >> PAGE_SHIFT;
 
-- 
2.9.3

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