On Thu, Feb 21, 2019 at 12:35:19AM +0530, Uma Shankar wrote:
> gamma mode mask was not considering the 30th and 31st bits.
> Due to this state readout was masking these bits, causing a
> mismatch and false warning, even though the registers were
> updated correctly. Dropped the gamma mode mask as it is
> redundant and ideally entire register content should be
> matching. This resolves the state mismatch warnings.
>
> Signed-off-by: Uma Shankar
Thanks. Pushed with
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109624
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> drivers/gpu/drm/i915/intel_display.c | 3 +--
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a5a4736..514494f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7142,7 +7142,6 @@ enum {
> #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> #define PRE_CSC_GAMMA_ENABLE(1 << 31)
> #define POST_CSC_GAMMA_ENABLE (1 << 30)
> -#define GAMMA_MODE_MODE_MASK(3 << 0)
> #define GAMMA_MODE_MODE_8BIT(0 << 0)
> #define GAMMA_MODE_MODE_10BIT (1 << 0)
> #define GAMMA_MODE_MODE_12BIT (2 << 0)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 415d896..fa7c39e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9897,8 +9897,7 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
> intel_get_pipe_src_size(crtc, pipe_config);
> intel_get_crtc_ycbcr_config(crtc, pipe_config);
>
> - pipe_config->gamma_mode =
> - I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
> + pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
>
> if (INTEL_GEN(dev_priv) >= 9) {
> u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
> --
> 1.9.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
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--
Ville Syrjälä
Intel
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