Re: [Intel-gfx] [PATCH] drm/i915/icl: Skip DSI path in DDI vswing programming.

2018-12-07 Thread Dhinakaran Pandiyan 
On Fri, 2018-12-07 at 16:07 +0200, Imre Deak wrote:
> Hi DK,
> 
> On Thu, Dec 06, 2018 at 03:43:55PM -0800, Dhinakaran Pandiyan wrote:
> > DSI implements it's own pre_enable hook, encoder output type is
> > never
> > DSI.
> > 
> > Cc: Manasi Navare 
> > Cc: Paulo Zanoni 
> > Cc: James Ausmus 
> > Fixes: fb5c8e9d4350 ("drm/i915/icl: Implement voltage swing
> > programming sequence for Combo PHY DDI")
> > Signed-off-by: Dhinakaran Pandiyan 
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 9 ++---
> >  1 file changed, 2 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index f3e1d6a0b7dd..5792632fa6a3 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2489,13 +2489,8 @@ static void
> > icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > /* Set DisableTap2 and DisableTap3 if MIPI DSI
> >  * Clear DisableTap2 and DisableTap3 for all other Ports
> >  */
> > -   if (type == INTEL_OUTPUT_DSI) {
> > -   val |= TAP2_DISABLE;
> > -   val |= TAP3_DISABLE;
> > -   } else {
> > -   val &= ~TAP2_DISABLE;
> > -   val &= ~TAP3_DISABLE;
> > -   }
> > +   val &= ~TAP2_DISABLE;
> > +   val &= ~TAP3_DISABLE;
> 
> note that Clint's patch at
> https://patchwork.freedesktop.org/patch/265848/
> solves this as well. We could minimize the churn by applying only
> that.
Absolutely. Thanks for pointing it out.


-DK

> 
> > I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> >  
> > /* Program PORT_TX_DW2 */
> > -- 
> > 2.17.1
> > 
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [Intel-gfx] [PATCH] drm/i915/icl: Skip DSI path in DDI vswing programming.

2018-12-07 Thread Imre Deak 
Hi DK,

On Thu, Dec 06, 2018 at 03:43:55PM -0800, Dhinakaran Pandiyan wrote:
> DSI implements it's own pre_enable hook, encoder output type is never
> DSI.
> 
> Cc: Manasi Navare 
> Cc: Paulo Zanoni 
> Cc: James Ausmus 
> Fixes: fb5c8e9d4350 ("drm/i915/icl: Implement voltage swing programming 
> sequence for Combo PHY DDI")
> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 9 ++---
>  1 file changed, 2 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f3e1d6a0b7dd..5792632fa6a3 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2489,13 +2489,8 @@ static void icl_ddi_combo_vswing_program(struct 
> drm_i915_private *dev_priv,
>   /* Set DisableTap2 and DisableTap3 if MIPI DSI
>* Clear DisableTap2 and DisableTap3 for all other Ports
>*/
> - if (type == INTEL_OUTPUT_DSI) {
> - val |= TAP2_DISABLE;
> - val |= TAP3_DISABLE;
> - } else {
> - val &= ~TAP2_DISABLE;
> - val &= ~TAP3_DISABLE;
> - }
> + val &= ~TAP2_DISABLE;
> + val &= ~TAP3_DISABLE;

note that Clint's patch at
https://patchwork.freedesktop.org/patch/265848/
solves this as well. We could minimize the churn by applying only that.

>   I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>  
>   /* Program PORT_TX_DW2 */
> -- 
> 2.17.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH] drm/i915/icl: Skip DSI path in DDI vswing programming.

2018-12-06 Thread Dhinakaran Pandiyan 
DSI implements it's own pre_enable hook, encoder output type is never
DSI.

Cc: Manasi Navare 
Cc: Paulo Zanoni 
Cc: James Ausmus 
Fixes: fb5c8e9d4350 ("drm/i915/icl: Implement voltage swing programming 
sequence for Combo PHY DDI")
Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/intel_ddi.c | 9 ++---
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3e1d6a0b7dd..5792632fa6a3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2489,13 +2489,8 @@ static void icl_ddi_combo_vswing_program(struct 
drm_i915_private *dev_priv,
/* Set DisableTap2 and DisableTap3 if MIPI DSI
 * Clear DisableTap2 and DisableTap3 for all other Ports
 */
-   if (type == INTEL_OUTPUT_DSI) {
-   val |= TAP2_DISABLE;
-   val |= TAP3_DISABLE;
-   } else {
-   val &= ~TAP2_DISABLE;
-   val &= ~TAP3_DISABLE;
-   }
+   val &= ~TAP2_DISABLE;
+   val &= ~TAP3_DISABLE;
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
 
/* Program PORT_TX_DW2 */
-- 
2.17.1

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