Re: [Intel-gfx] [PATCH] drm/i915/icp: Add Interrupt Support
Em Ter, 2018-06-26 às 13:52 -0700, Anusha Srivatsa escreveu: > This patch addresses Interrupts from south display engine (SDE). > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. > Introduce these registers and their intended values. > > Introduce icp_irq_handler(). > > The icp_irq_postinstall() takes care of > enabling all PCH interrupt sources, to unmask > them as needed with SDEIMR, as is done > done by ibx_irq_pre_postinstall() for earlier platforms. > We do not need to explicitly call the ibx_irq_pre_postinstall(). > > Also, while changing these, > s/CPT/PPT/CPT-CNP comment. > > v2: > - remove redundant register defines.(Lucas) > - Change register names to be more consistent with > previous platforms (Lucas) > > v3: > -Reorder bit defines to a more appropriate location. > Change the comments. Confirm in the commit message that > icp_irq_postinstall() need not go to > ibx_irq_pre_postinstall() and ibx_irq_postinstall() > as in earlier platforms. (Paulo) > > Cc: Lucas De Marchi > Cc: Paulo Zanoni > Cc: Dhinakaran Pandiyan > Cc: Ville Syrjala > Signed-off-by: Anusha Srivatsa > [Paulo: coding style bikesheds and rebases]. > Signed-off-by: Paulo Zanoni Merged. Thanks everybody for the help. > --- > drivers/gpu/drm/i915/i915_irq.c | 134 > +++- > drivers/gpu/drm/i915/i915_reg.h | 42 - > 2 files changed, 173 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > b/drivers/gpu/drm/i915/i915_irq.c > index 46aaef5..7a7c4a2 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -122,6 +122,15 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = { > [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG > }; > > +static const u32 hpd_icp[HPD_NUM_PINS] = { > + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP, > + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP, > + [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP, > + [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP, > + [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP, > + [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP > +}; > + > /* IIR can theoretically queue up two events. Be paranoid. */ > #define GEN8_IRQ_RESET_NDX(type, which) do { \ > I915_WRITE(GEN8_##type##_IMR(which), 0x); \ > @@ -1586,6 +1595,34 @@ static bool bxt_port_hotplug_long_detect(enum > port port, u32 val) > } > } > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 > val) > +{ > + switch (port) { > + case PORT_A: > + return val & ICP_DDIA_HPD_LONG_DETECT; > + case PORT_B: > + return val & ICP_DDIB_HPD_LONG_DETECT; > + default: > + return false; > + } > +} > + > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val) > +{ > + switch (port) { > + case PORT_C: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); > + case PORT_D: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); > + case PORT_E: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); > + case PORT_F: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); > + default: > + return false; > + } > +} > + > static bool spt_port_hotplug2_long_detect(enum port port, u32 val) > { > switch (port) { > @@ -2385,6 +2422,43 @@ static void cpt_irq_handler(struct > drm_i915_private *dev_priv, u32 pch_iir) > cpt_serr_int_handler(dev_priv); > } > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 > pch_iir) > +{ > + u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > + u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; > + u32 pin_mask = 0, long_mask = 0; > + > + if (ddi_hotplug_trigger) { > + u32 dig_hotplug_reg; > + > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI); > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg); > + > + intel_get_hpd_pins(dev_priv, _mask, _mask, > +ddi_hotplug_trigger, > +dig_hotplug_reg, hpd_icp, > +icp_ddi_port_hotplug_long_detect) > ; > + } > + > + if (tc_hotplug_trigger) { > + u32 dig_hotplug_reg; > + > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC); > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg); > + > + intel_get_hpd_pins(dev_priv, _mask, _mask, > +tc_hotplug_trigger, > +dig_hotplug_reg, hpd_icp, > +icp_tc_port_hotplug_long_detect); > + } > + > + if (pin_mask) > + intel_hpd_irq_handler(dev_priv, pin_mask, > long_mask); > + > + if (pch_iir & SDE_GMBUS_ICP) > + gmbus_irq_handler(dev_priv); > +} > + > static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 > pch_iir) > { > u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & >
Re: [Intel-gfx] [PATCH] drm/i915/icp: Add Interrupt Support
On Tue, Jun 26, 2018 at 1:56 PM Anusha Srivatsa wrote: > > This patch addresses Interrupts from south display engine (SDE). > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. > Introduce these registers and their intended values. > > Introduce icp_irq_handler(). > > The icp_irq_postinstall() takes care of > enabling all PCH interrupt sources, to unmask > them as needed with SDEIMR, as is done > done by ibx_irq_pre_postinstall() for earlier platforms. > We do not need to explicitly call the ibx_irq_pre_postinstall(). > > Also, while changing these, > s/CPT/PPT/CPT-CNP comment. > > v2: > - remove redundant register defines.(Lucas) > - Change register names to be more consistent with > previous platforms (Lucas) > > v3: > -Reorder bit defines to a more appropriate location. > Change the comments. Confirm in the commit message that > icp_irq_postinstall() need not go to > ibx_irq_pre_postinstall() and ibx_irq_postinstall() > as in earlier platforms. (Paulo) > > Cc: Lucas De Marchi Better now. Reviewed-by: Lucas De Marchi Lucas De Marchi > Cc: Paulo Zanoni > Cc: Dhinakaran Pandiyan > Cc: Ville Syrjala > Signed-off-by: Anusha Srivatsa > [Paulo: coding style bikesheds and rebases]. > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_irq.c | 134 > +++- > drivers/gpu/drm/i915/i915_reg.h | 42 - > 2 files changed, 173 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 46aaef5..7a7c4a2 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -122,6 +122,15 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = { > [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG > }; > > +static const u32 hpd_icp[HPD_NUM_PINS] = { > + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP, > + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP, > + [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP, > + [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP, > + [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP, > + [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP > +}; > + > /* IIR can theoretically queue up two events. Be paranoid. */ > #define GEN8_IRQ_RESET_NDX(type, which) do { \ > I915_WRITE(GEN8_##type##_IMR(which), 0x); \ > @@ -1586,6 +1595,34 @@ static bool bxt_port_hotplug_long_detect(enum port > port, u32 val) > } > } > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 val) > +{ > + switch (port) { > + case PORT_A: > + return val & ICP_DDIA_HPD_LONG_DETECT; > + case PORT_B: > + return val & ICP_DDIB_HPD_LONG_DETECT; > + default: > + return false; > + } > +} > + > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val) > +{ > + switch (port) { > + case PORT_C: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); > + case PORT_D: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); > + case PORT_E: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); > + case PORT_F: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); > + default: > + return false; > + } > +} > + > static bool spt_port_hotplug2_long_detect(enum port port, u32 val) > { > switch (port) { > @@ -2385,6 +2422,43 @@ static void cpt_irq_handler(struct drm_i915_private > *dev_priv, u32 pch_iir) > cpt_serr_int_handler(dev_priv); > } > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > +{ > + u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > + u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; > + u32 pin_mask = 0, long_mask = 0; > + > + if (ddi_hotplug_trigger) { > + u32 dig_hotplug_reg; > + > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI); > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg); > + > + intel_get_hpd_pins(dev_priv, _mask, _mask, > + ddi_hotplug_trigger, > + dig_hotplug_reg, hpd_icp, > + icp_ddi_port_hotplug_long_detect); > + } > + > + if (tc_hotplug_trigger) { > + u32 dig_hotplug_reg; > + > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC); > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg); > + > + intel_get_hpd_pins(dev_priv, _mask, _mask, > + tc_hotplug_trigger, > + dig_hotplug_reg, hpd_icp, > + icp_tc_port_hotplug_long_detect); > + } > + > + if (pin_mask) > + intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); > + > + if (pch_iir & SDE_GMBUS_ICP) > + gmbus_irq_handler(dev_priv); > +} > + > static void spt_irq_handler(struct
Re: [Intel-gfx] [PATCH] drm/i915/icp: Add Interrupt Support
Em Ter, 2018-06-26 às 13:52 -0700, Anusha Srivatsa escreveu: > This patch addresses Interrupts from south display engine (SDE). > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. > Introduce these registers and their intended values. > > Introduce icp_irq_handler(). > > The icp_irq_postinstall() takes care of > enabling all PCH interrupt sources, to unmask > them as needed with SDEIMR, as is done > done by ibx_irq_pre_postinstall() for earlier platforms. > We do not need to explicitly call the ibx_irq_pre_postinstall(). > > Also, while changing these, > s/CPT/PPT/CPT-CNP comment. > > v2: > - remove redundant register defines.(Lucas) > - Change register names to be more consistent with > previous platforms (Lucas) > > v3: > -Reorder bit defines to a more appropriate location. > Change the comments. Confirm in the commit message that > icp_irq_postinstall() need not go to > ibx_irq_pre_postinstall() and ibx_irq_postinstall() > as in earlier platforms. (Paulo) > > Cc: Lucas De Marchi > Cc: Paulo Zanoni > Cc: Dhinakaran Pandiyan > Cc: Ville Syrjala > Signed-off-by: Anusha Srivatsa > [Paulo: coding style bikesheds and rebases]. > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_irq.c | 134 > +++- > drivers/gpu/drm/i915/i915_reg.h | 42 - > 2 files changed, 173 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > b/drivers/gpu/drm/i915/i915_irq.c > index 46aaef5..7a7c4a2 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -122,6 +122,15 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = { > [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG > }; > > +static const u32 hpd_icp[HPD_NUM_PINS] = { > + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP, > + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP, > + [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP, > + [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP, > + [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP, > + [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP > +}; > + > /* IIR can theoretically queue up two events. Be paranoid. */ > #define GEN8_IRQ_RESET_NDX(type, which) do { \ > I915_WRITE(GEN8_##type##_IMR(which), 0x); \ > @@ -1586,6 +1595,34 @@ static bool bxt_port_hotplug_long_detect(enum > port port, u32 val) > } > } > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 > val) > +{ > + switch (port) { > + case PORT_A: > + return val & ICP_DDIA_HPD_LONG_DETECT; > + case PORT_B: > + return val & ICP_DDIB_HPD_LONG_DETECT; > + default: > + return false; > + } > +} > + > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val) > +{ > + switch (port) { > + case PORT_C: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); > + case PORT_D: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); > + case PORT_E: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); > + case PORT_F: > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); > + default: > + return false; > + } > +} > + > static bool spt_port_hotplug2_long_detect(enum port port, u32 val) > { > switch (port) { > @@ -2385,6 +2422,43 @@ static void cpt_irq_handler(struct > drm_i915_private *dev_priv, u32 pch_iir) > cpt_serr_int_handler(dev_priv); > } > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 > pch_iir) > +{ > + u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > + u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; > + u32 pin_mask = 0, long_mask = 0; > + > + if (ddi_hotplug_trigger) { > + u32 dig_hotplug_reg; > + > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI); > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg); > + > + intel_get_hpd_pins(dev_priv, _mask, _mask, > +ddi_hotplug_trigger, > +dig_hotplug_reg, hpd_icp, > +icp_ddi_port_hotplug_long_detect) > ; > + } > + > + if (tc_hotplug_trigger) { > + u32 dig_hotplug_reg; > + > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC); > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg); > + > + intel_get_hpd_pins(dev_priv, _mask, _mask, > +tc_hotplug_trigger, > +dig_hotplug_reg, hpd_icp, > +icp_tc_port_hotplug_long_detect); > + } > + > + if (pin_mask) > + intel_hpd_irq_handler(dev_priv, pin_mask, > long_mask); > + > + if (pch_iir & SDE_GMBUS_ICP) > + gmbus_irq_handler(dev_priv); > +} > + > static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 > pch_iir) > { > u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & > @@ -2804,8 +2878,11 @@
[Intel-gfx] [PATCH] drm/i915/icp: Add Interrupt Support
This patch addresses Interrupts from south display engine (SDE). ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. Introduce these registers and their intended values. Introduce icp_irq_handler(). The icp_irq_postinstall() takes care of enabling all PCH interrupt sources, to unmask them as needed with SDEIMR, as is done done by ibx_irq_pre_postinstall() for earlier platforms. We do not need to explicitly call the ibx_irq_pre_postinstall(). Also, while changing these, s/CPT/PPT/CPT-CNP comment. v2: - remove redundant register defines.(Lucas) - Change register names to be more consistent with previous platforms (Lucas) v3: -Reorder bit defines to a more appropriate location. Change the comments. Confirm in the commit message that icp_irq_postinstall() need not go to ibx_irq_pre_postinstall() and ibx_irq_postinstall() as in earlier platforms. (Paulo) Cc: Lucas De Marchi Cc: Paulo Zanoni Cc: Dhinakaran Pandiyan Cc: Ville Syrjala Signed-off-by: Anusha Srivatsa [Paulo: coding style bikesheds and rebases]. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 134 +++- drivers/gpu/drm/i915/i915_reg.h | 42 - 2 files changed, 173 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 46aaef5..7a7c4a2 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -122,6 +122,15 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = { [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG }; +static const u32 hpd_icp[HPD_NUM_PINS] = { + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP, + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP, + [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP, + [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP, + [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP, + [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP +}; + /* IIR can theoretically queue up two events. Be paranoid. */ #define GEN8_IRQ_RESET_NDX(type, which) do { \ I915_WRITE(GEN8_##type##_IMR(which), 0x); \ @@ -1586,6 +1595,34 @@ static bool bxt_port_hotplug_long_detect(enum port port, u32 val) } } +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 val) +{ + switch (port) { + case PORT_A: + return val & ICP_DDIA_HPD_LONG_DETECT; + case PORT_B: + return val & ICP_DDIB_HPD_LONG_DETECT; + default: + return false; + } +} + +static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val) +{ + switch (port) { + case PORT_C: + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); + case PORT_D: + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); + case PORT_E: + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); + case PORT_F: + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); + default: + return false; + } +} + static bool spt_port_hotplug2_long_detect(enum port port, u32 val) { switch (port) { @@ -2385,6 +2422,43 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) cpt_serr_int_handler(dev_priv); } +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) +{ + u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; + u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; + u32 pin_mask = 0, long_mask = 0; + + if (ddi_hotplug_trigger) { + u32 dig_hotplug_reg; + + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI); + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg); + + intel_get_hpd_pins(dev_priv, _mask, _mask, + ddi_hotplug_trigger, + dig_hotplug_reg, hpd_icp, + icp_ddi_port_hotplug_long_detect); + } + + if (tc_hotplug_trigger) { + u32 dig_hotplug_reg; + + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC); + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg); + + intel_get_hpd_pins(dev_priv, _mask, _mask, + tc_hotplug_trigger, + dig_hotplug_reg, hpd_icp, + icp_tc_port_hotplug_long_detect); + } + + if (pin_mask) + intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); + + if (pch_iir & SDE_GMBUS_ICP) + gmbus_irq_handler(dev_priv); +} + static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) { u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & @@ -2804,8 +2878,11 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) I915_WRITE(SDEIIR, iir); ret = IRQ_HANDLED; - if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) || -