Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259

2019-09-09 Thread Daniele Ceraolo Spurio 



On 9/6/19 6:10 PM, Matt Roper wrote:

On Fri, Sep 06, 2019 at 03:46:42PM -0700, Daniele Ceraolo Spurio wrote:



On 9/6/19 3:41 PM, Radhakrishna Sripada wrote:

Disable CPS aware color pipe by setting chicken bit.

BSpec: 52890
HSDES: 1409142259

Cc: Stuart Summers 
Cc: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
---
   drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
   drivers/gpu/drm/i915/i915_reg.h | 1 +
   2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 243d3f77be13..14e3f9677b06 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -894,6 +894,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, 
struct i915_wa_list *wal)
   static void
   tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
   {
+   wa_init_mcr(i915, wal);


this is not part of the WA you're trying to apply, right?


+
+   /* Wa_1409142259 */
+   WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);


AFAICS the register is part of the render context, so shouldn't we set this
as part of the ctx_workarounds? that's what we do for another WA on the same
register on ICL.


How do you usually determine if a register is part of the context or
not?  This one doesn't have the "This Register is saved and restored as
part of Context" notation that other context registers have, so is there
somewhere else we're supposed to find that information?



Most of the context registers are not tagged that way. The golden 
reference for what's in the context is the context image page (Bspec 
46255 for TGL).


Daniele



Matt



Daniele


   }
   static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 006cffd56be2..53e07882efb7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7668,6 +7668,7 @@ enum {
   #define GEN11_COMMON_SLICE_CHICKEN3  _MMIO(0x7304)
 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
+  #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE   (1 << 9)
   #define HIZ_CHICKEN  _MMIO(0x7018)
   # define CHV_HZ_8X8_MODE_IN_1X   (1 << 15)


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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259

2019-09-06 Thread Matt Roper 
On Fri, Sep 06, 2019 at 03:46:42PM -0700, Daniele Ceraolo Spurio wrote:
> 
> 
> On 9/6/19 3:41 PM, Radhakrishna Sripada wrote:
> > Disable CPS aware color pipe by setting chicken bit.
> > 
> > BSpec: 52890
> > HSDES: 1409142259
> > 
> > Cc: Stuart Summers 
> > Cc: Matt Roper 
> > Signed-off-by: Radhakrishna Sripada 
> > ---
> >   drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> >   drivers/gpu/drm/i915/i915_reg.h | 1 +
> >   2 files changed, 6 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 243d3f77be13..14e3f9677b06 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -894,6 +894,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, 
> > struct i915_wa_list *wal)
> >   static void
> >   tgl_gt_workarounds_init(struct drm_i915_private *i915, struct 
> > i915_wa_list *wal)
> >   {
> > +   wa_init_mcr(i915, wal);
> 
> this is not part of the WA you're trying to apply, right?
> 
> > +
> > +   /* Wa_1409142259 */
> > +   WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > + GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> 
> AFAICS the register is part of the render context, so shouldn't we set this
> as part of the ctx_workarounds? that's what we do for another WA on the same
> register on ICL.

How do you usually determine if a register is part of the context or
not?  This one doesn't have the "This Register is saved and restored as
part of Context" notation that other context registers have, so is there
somewhere else we're supposed to find that information?


Matt

> 
> Daniele
> 
> >   }
> >   static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 006cffd56be2..53e07882efb7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7668,6 +7668,7 @@ enum {
> >   #define GEN11_COMMON_SLICE_CHICKEN3   _MMIO(0x7304)
> > #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC  (1 << 11)
> > +  #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE   (1 << 9)
> >   #define HIZ_CHICKEN   _MMIO(0x7018)
> >   # define CHV_HZ_8X8_MODE_IN_1X(1 << 15)
> > 
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259

2019-09-06 Thread Matt Roper 
On Fri, Sep 06, 2019 at 03:41:42PM -0700, Radhakrishna Sripada wrote:
> Disable CPS aware color pipe by setting chicken bit.
> 
> BSpec: 52890

BSpec: 45829

as well ("This bit must be programmed to 1").  

Reviewed-by: Matt Roper 

> HSDES: 1409142259
> 
> Cc: Stuart Summers 
> Cc: Matt Roper 
> Signed-off-by: Radhakrishna Sripada 
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 243d3f77be13..14e3f9677b06 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -894,6 +894,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, 
> struct i915_wa_list *wal)
>  static void
>  tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
> *wal)
>  {
> + wa_init_mcr(i915, wal);
> +
> + /* Wa_1409142259 */
> + WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> +   GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 006cffd56be2..53e07882efb7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7668,6 +7668,7 @@ enum {
>  
>  #define GEN11_COMMON_SLICE_CHICKEN3  _MMIO(0x7304)
>#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
> +  #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
>  
>  #define HIZ_CHICKEN  _MMIO(0x7018)
>  # define CHV_HZ_8X8_MODE_IN_1X   (1 << 15)
> -- 
> 2.20.1
> 

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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259

2019-09-06 Thread Daniele Ceraolo Spurio 



On 9/6/19 3:41 PM, Radhakrishna Sripada wrote:

Disable CPS aware color pipe by setting chicken bit.

BSpec: 52890
HSDES: 1409142259

Cc: Stuart Summers 
Cc: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
---
  drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
  drivers/gpu/drm/i915/i915_reg.h | 1 +
  2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 243d3f77be13..14e3f9677b06 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -894,6 +894,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, 
struct i915_wa_list *wal)
  static void
  tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
  {
+   wa_init_mcr(i915, wal);


this is not part of the WA you're trying to apply, right?


+
+   /* Wa_1409142259 */
+   WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);


AFAICS the register is part of the render context, so shouldn't we set 
this as part of the ctx_workarounds? that's what we do for another WA on 
the same register on ICL.


Daniele


  }
  
  static void

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 006cffd56be2..53e07882efb7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7668,6 +7668,7 @@ enum {
  
  #define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)

#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC  (1 << 11)
+  #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE   (1 << 9)
  
  #define HIZ_CHICKEN	_MMIO(0x7018)

  # define CHV_HZ_8X8_MODE_IN_1X(1 << 15)


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[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259

2019-09-06 Thread Radhakrishna Sripada 
Disable CPS aware color pipe by setting chicken bit.

BSpec: 52890
HSDES: 1409142259

Cc: Stuart Summers 
Cc: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 243d3f77be13..14e3f9677b06 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -894,6 +894,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, 
struct i915_wa_list *wal)
 static void
 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
 {
+   wa_init_mcr(i915, wal);
+
+   /* Wa_1409142259 */
+   WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 006cffd56be2..53e07882efb7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7668,6 +7668,7 @@ enum {
 
 #define GEN11_COMMON_SLICE_CHICKEN3_MMIO(0x7304)
   #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC   (1 << 11)
+  #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE   (1 << 9)
 
 #define HIZ_CHICKEN_MMIO(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
-- 
2.20.1

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