Re: [Intel-gfx] [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3)

2015-06-24 Thread Ville Syrjälä 
On Tue, Jun 23, 2015 at 02:14:26PM -0700, Bob Paauwe wrote:
 The registers and process differ from other platforms. If the hardware
 was programmed incorrectly, this will return invalid cdclk values, which
 should then cause reprogramming of the hardware.
 
 v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
 v3: Make less assumptions about the hardware state (Ville)
 
 Cc: Ville Syrjälä ville.syrj...@linux.intel.com
 Cc: Imre Deak imre.d...@intel.com
 Cc: Matt Roper matthew.d.ro...@intel.com
 Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
 Signed-off-by: Matt Roper matthew.d.ro...@intel.com

Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com

 ---
  drivers/gpu/drm/i915/intel_display.c | 31 +++
  1 file changed, 31 insertions(+)
 
 diff --git a/drivers/gpu/drm/i915/intel_display.c 
 b/drivers/gpu/drm/i915/intel_display.c
 index c38c297..201826e 100644
 --- a/drivers/gpu/drm/i915/intel_display.c
 +++ b/drivers/gpu/drm/i915/intel_display.c
 @@ -6687,6 +6687,34 @@ static int skylake_get_display_clock_speed(struct 
 drm_device *dev)
   return 24000;
  }
  
 +static int broxton_get_display_clock_speed(struct drm_device *dev)
 +{
 + struct drm_i915_private *dev_priv = to_i915(dev);
 + uint32_t cdctl = I915_READ(CDCLK_CTL);
 + uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL)  BXT_DE_PLL_RATIO_MASK;
 + uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
 + int cdclk;
 +
 + if (!(pll_enab  BXT_DE_PLL_PLL_ENABLE))
 + return 19200;
 +
 + cdclk = 19200 * pll_ratio / 2;
 +
 + switch (cdctl  BXT_CDCLK_CD2X_DIV_SEL_MASK) {
 + case BXT_CDCLK_CD2X_DIV_SEL_1:
 + return cdclk;  /* 576MHz or 624MHz */
 + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
 + return cdclk * 2 / 3; /* 384MHz */
 + case BXT_CDCLK_CD2X_DIV_SEL_2:
 + return cdclk / 2; /* 288MHz */
 + case BXT_CDCLK_CD2X_DIV_SEL_4:
 + return cdclk / 4; /* 144MHz */
 + }
 +
 + /* error case, do as if DE PLL isn't enabled */
 + return 19200;
 +}
 +
  static int broadwell_get_display_clock_speed(struct drm_device *dev)
  {
   struct drm_i915_private *dev_priv = dev-dev_private;
 @@ -14649,6 +14677,9 @@ static void intel_init_display(struct drm_device *dev)
   if (IS_SKYLAKE(dev))
   dev_priv-display.get_display_clock_speed =
   skylake_get_display_clock_speed;
 + else if (IS_BROXTON(dev))
 + dev_priv-display.get_display_clock_speed =
 + broxton_get_display_clock_speed;
   else if (IS_BROADWELL(dev))
   dev_priv-display.get_display_clock_speed =
   broadwell_get_display_clock_speed;
 -- 
 2.1.0

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3)

2015-06-24 Thread Daniel Vetter 
On Wed, Jun 24, 2015 at 03:49:22PM +0300, Ville Syrjälä wrote:
 On Tue, Jun 23, 2015 at 02:14:26PM -0700, Bob Paauwe wrote:
  The registers and process differ from other platforms. If the hardware
  was programmed incorrectly, this will return invalid cdclk values, which
  should then cause reprogramming of the hardware.
  
  v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
  v3: Make less assumptions about the hardware state (Ville)
  
  Cc: Ville Syrjälä ville.syrj...@linux.intel.com
  Cc: Imre Deak imre.d...@intel.com
  Cc: Matt Roper matthew.d.ro...@intel.com
  Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
  Signed-off-by: Matt Roper matthew.d.ro...@intel.com
 
 Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3)

2015-06-23 Thread Bob Paauwe 
The registers and process differ from other platforms. If the hardware
was programmed incorrectly, this will return invalid cdclk values, which
should then cause reprogramming of the hardware.

v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
v3: Make less assumptions about the hardware state (Ville)

Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Imre Deak imre.d...@intel.com
Cc: Matt Roper matthew.d.ro...@intel.com
Signed-off-by: Bob Paauwe bob.j.paa...@intel.com
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
 drivers/gpu/drm/i915/intel_display.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c38c297..201826e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6687,6 +6687,34 @@ static int skylake_get_display_clock_speed(struct 
drm_device *dev)
return 24000;
 }
 
+static int broxton_get_display_clock_speed(struct drm_device *dev)
+{
+   struct drm_i915_private *dev_priv = to_i915(dev);
+   uint32_t cdctl = I915_READ(CDCLK_CTL);
+   uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL)  BXT_DE_PLL_RATIO_MASK;
+   uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
+   int cdclk;
+
+   if (!(pll_enab  BXT_DE_PLL_PLL_ENABLE))
+   return 19200;
+
+   cdclk = 19200 * pll_ratio / 2;
+
+   switch (cdctl  BXT_CDCLK_CD2X_DIV_SEL_MASK) {
+   case BXT_CDCLK_CD2X_DIV_SEL_1:
+   return cdclk;  /* 576MHz or 624MHz */
+   case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+   return cdclk * 2 / 3; /* 384MHz */
+   case BXT_CDCLK_CD2X_DIV_SEL_2:
+   return cdclk / 2; /* 288MHz */
+   case BXT_CDCLK_CD2X_DIV_SEL_4:
+   return cdclk / 4; /* 144MHz */
+   }
+
+   /* error case, do as if DE PLL isn't enabled */
+   return 19200;
+}
+
 static int broadwell_get_display_clock_speed(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -14649,6 +14677,9 @@ static void intel_init_display(struct drm_device *dev)
if (IS_SKYLAKE(dev))
dev_priv-display.get_display_clock_speed =
skylake_get_display_clock_speed;
+   else if (IS_BROXTON(dev))
+   dev_priv-display.get_display_clock_speed =
+   broxton_get_display_clock_speed;
else if (IS_BROADWELL(dev))
dev_priv-display.get_display_clock_speed =
broadwell_get_display_clock_speed;
-- 
2.1.0

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