[Intel-gfx] [PATCH] drm/i915: Allow concurrent read access between CPU and GPU domain
Similar to allowing a buffer to be simultaneously read by the GPU and
through the GTT, we wish to allow readback of the pages through the CPU
domain whilst they are also being read by the GPU. Domain coherency
is managed by allowing multiple readers, but only a single writer.
This is used by mesa for its program cache which it may search for every
new program every frame and then renews should it need to add. During
renewal, mesa copies the program bo currently executing through a CPU
mapping onto the new bo. This patch allows the search and that copy to
proceed without causing a stall on the current batch.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d2b5326..704d3a6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3179,9 +3179,11 @@ i915_gem_object_set_to_cpu_domain(struct
drm_i915_gem_object *obj, bool write)
if (ret)
return ret;
- ret = i915_gem_object_wait_rendering(obj);
- if (ret)
- return ret;
+ if (write || obj->pending_gpu_write) {
+ ret = i915_gem_object_wait_rendering(obj);
+ if (ret)
+ return ret;
+ }
i915_gem_object_flush_gtt_write_domain(obj);
--
1.7.9.5
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Re: [Intel-gfx] [PATCH] drm/i915: Allow concurrent read access between CPU and GPU domain
On Tue, 10 Apr 2012 11:52:50 +0100, Chris Wilson wrote: > Similar to allowing a buffer to be simultaneously read by the GPU and > through the GTT, we wish to allow readback of the pages through the CPU > domain whilst they are also being read by the GPU. Domain coherency > is managed by allowing multiple readers, but only a single writer. > > This is used by mesa for its program cache which it may search for every > new program every frame and then renews should it need to add. During > renewal, mesa copies the program bo currently executing through a CPU > mapping onto the new bo. This patch allows the search and that copy to > proceed without causing a stall on the current batch. At Daniel's request, I added i-g-t/gem_cpu_concurrent_blit to catch the possible bugs that may have been introduced by this patch. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Allow concurrent read access between CPU and GPU domain
On Tue, Apr 10, 2012 at 10:35:19PM +0100, Chris Wilson wrote: > On Tue, 10 Apr 2012 11:52:50 +0100, Chris Wilson > wrote: > > Similar to allowing a buffer to be simultaneously read by the GPU and > > through the GTT, we wish to allow readback of the pages through the CPU > > domain whilst they are also being read by the GPU. Domain coherency > > is managed by allowing multiple readers, but only a single writer. > > > > This is used by mesa for its program cache which it may search for every > > new program every frame and then renews should it need to add. During > > renewal, mesa copies the program bo currently executing through a CPU > > mapping onto the new bo. This patch allows the search and that copy to > > proceed without causing a stall on the current batch. > > At Daniel's request, I added i-g-t/gem_cpu_concurrent_blit to catch the > possible bugs that may have been introduced by this patch. Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
