Re: [Intel-gfx] [PATCH] drm/i915: Fix VLV CRC reading.

2014-06-10 Thread Daniel Vetter 
On Thu, Jun 05, 2014 at 02:28:17PM -0700, Rodrigo Vivi wrote:
 Adding missing Display mmio reg offset.
 
 Credits-to: Laws, Philip philip.l...@intel.com
 Cc: He, Shuang shuang...@intel.com
 Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com

Is there no bugzilla that pipe crc tests on DP/eDP ports aren't working on
byt? Can you please chase this down with QA?

Patch is queued for -next.

Thanks, Daniel

 ---
  drivers/gpu/drm/i915/i915_reg.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
 index 286f05c..05e2541 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -2627,7 +2627,7 @@ enum punit_power_well {
  
  #define PORT_DFT_I9XX0x61150
  #define   DC_BALANCE_RESET   (1  25)
 -#define PORT_DFT2_G4X0x61154
 +#define PORT_DFT2_G4X(dev_priv-info.display_mmio_offset + 
 0x61154)
  #define   DC_BALANCE_RESET_VLV   (1  31)
  #define   PIPE_SCRAMBLE_RESET_MASK   (0x3  0)
  #define   PIPE_B_SCRAMBLE_RESET  (1  1)
 -- 
 1.9.3
 
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Re: [Intel-gfx] [PATCH] drm/i915: Fix VLV CRC reading.

2014-06-09 Thread Ville Syrjälä 
On Thu, Jun 05, 2014 at 02:28:17PM -0700, Rodrigo Vivi wrote:
 Adding missing Display mmio reg offset.
 
 Credits-to: Laws, Philip philip.l...@intel.com
 Cc: He, Shuang shuang...@intel.com
 Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com

Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com

 ---
  drivers/gpu/drm/i915/i915_reg.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
 index 286f05c..05e2541 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -2627,7 +2627,7 @@ enum punit_power_well {
  
  #define PORT_DFT_I9XX0x61150
  #define   DC_BALANCE_RESET   (1  25)
 -#define PORT_DFT2_G4X0x61154
 +#define PORT_DFT2_G4X(dev_priv-info.display_mmio_offset + 
 0x61154)
  #define   DC_BALANCE_RESET_VLV   (1  31)
  #define   PIPE_SCRAMBLE_RESET_MASK   (0x3  0)
  #define   PIPE_B_SCRAMBLE_RESET  (1  1)
 -- 
 1.9.3
 
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[Intel-gfx] [PATCH] drm/i915: Fix VLV CRC reading.

2014-06-05 Thread Rodrigo Vivi 
Adding missing Display mmio reg offset.

Credits-to: Laws, Philip philip.l...@intel.com
Cc: He, Shuang shuang...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 286f05c..05e2541 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2627,7 +2627,7 @@ enum punit_power_well {
 
 #define PORT_DFT_I9XX  0x61150
 #define   DC_BALANCE_RESET (1  25)
-#define PORT_DFT2_G4X  0x61154
+#define PORT_DFT2_G4X  (dev_priv-info.display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV (1  31)
 #define   PIPE_SCRAMBLE_RESET_MASK (0x3  0)
 #define   PIPE_B_SCRAMBLE_RESET(1  1)
-- 
1.9.3

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