Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)
Quoting Bob Paauwe (2018-09-10 21:34:00)
> On Mon, 10 Sep 2018 20:56:51 +0100
> Chris Wilson wrote:
>
> > Quoting Bob Paauwe (2018-09-10 18:12:25)
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > index d6f7b9fe1d26..e0619952ff52 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -299,6 +299,7 @@ static const struct intel_device_info
> > > intel_sandybridge_m_gt2_info = {
> > > .has_rc6p = 1, \
> > > .has_aliasing_ppgtt = 1, \
> > > .has_full_ppgtt = 1, \
> > > + .full_ppgtt_bits = 32, \
> > > GEN_DEFAULT_PIPEOFFSETS, \
> > > GEN_DEFAULT_PAGE_SIZES, \
> > > IVB_CURSOR_OFFSETS
> > > @@ -353,6 +354,7 @@ static const struct intel_device_info
> > > intel_valleyview_info = {
> > > .has_hotplug = 1,
> > > .has_aliasing_ppgtt = 1,
> > > .has_full_ppgtt = 1,
> > > + .full_ppgtt_bits = 32,
> > > .has_snoop = true,
> > > .has_coherent_ggtt = false,
> > > .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> >
> > To be pedant, .bits = 31 for gen6/7.
> > -Chris
>
> If I'm reading the code right, these use a different method of setting
> the vm.total so won't use the .full_ppgtt_bits.
>
> I don't know enough about this, but would it make sense to modify
> gen6_ppgtt_create() to use .full_ppgtt_bits (with it set correctly to
> 31) or maybe just not set .full_ppgtt_bits for those platforms or set
> the value correctly and ignore it for now?
One of our goals is to remove the differences where none exist...
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)
On Mon, 10 Sep 2018 20:56:51 +0100
Chris Wilson wrote:
> Quoting Bob Paauwe (2018-09-10 18:12:25)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index d6f7b9fe1d26..e0619952ff52 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -299,6 +299,7 @@ static const struct intel_device_info
> > intel_sandybridge_m_gt2_info = {
> > .has_rc6p = 1, \
> > .has_aliasing_ppgtt = 1, \
> > .has_full_ppgtt = 1, \
> > + .full_ppgtt_bits = 32, \
> > GEN_DEFAULT_PIPEOFFSETS, \
> > GEN_DEFAULT_PAGE_SIZES, \
> > IVB_CURSOR_OFFSETS
> > @@ -353,6 +354,7 @@ static const struct intel_device_info
> > intel_valleyview_info = {
> > .has_hotplug = 1,
> > .has_aliasing_ppgtt = 1,
> > .has_full_ppgtt = 1,
> > + .full_ppgtt_bits = 32,
> > .has_snoop = true,
> > .has_coherent_ggtt = false,
> > .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
>
> To be pedant, .bits = 31 for gen6/7.
> -Chris
If I'm reading the code right, these use a different method of setting
the vm.total so won't use the .full_ppgtt_bits.
I don't know enough about this, but would it make sense to modify
gen6_ppgtt_create() to use .full_ppgtt_bits (with it set correctly to
31) or maybe just not set .full_ppgtt_bits for those platforms or set
the value correctly and ignore it for now?
Bob
--
--
Bob Paauwe
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)
Quoting Bob Paauwe (2018-09-10 18:12:25)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d6f7b9fe1d26..e0619952ff52 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -299,6 +299,7 @@ static const struct intel_device_info
> intel_sandybridge_m_gt2_info = {
> .has_rc6p = 1, \
> .has_aliasing_ppgtt = 1, \
> .has_full_ppgtt = 1, \
> + .full_ppgtt_bits = 32, \
> GEN_DEFAULT_PIPEOFFSETS, \
> GEN_DEFAULT_PAGE_SIZES, \
> IVB_CURSOR_OFFSETS
> @@ -353,6 +354,7 @@ static const struct intel_device_info
> intel_valleyview_info = {
> .has_hotplug = 1,
> .has_aliasing_ppgtt = 1,
> .has_full_ppgtt = 1,
> + .full_ppgtt_bits = 32,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
To be pedant, .bits = 31 for gen6/7.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)
On Mon, 10 Sep 2018 10:32:42 -0700
Rodrigo Vivi wrote:
> On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
> 1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> > range full ppgtt and may actually be something other than 48 bits.
> >
> > Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> > describe that a 4 level walk table extended range PPGTT is being
> > used. Add a new device info field that specifies the number of
> > bits to prepare for cases where the range is not 32 or 48 bits.
> >
> > v2: keep USES_FULL_PPGTT() unchanged (Chris)
> > v3: Simplify condition in gen8_ppgtt_create() (Chris)
> > Remove unecessary line coninuations (Bob)
> > Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> >
> > Signed-off-by: Bob Paauwe
> > CC: Rodrigo Vivi
> > CC: Michel Thierry
> > CC: Chris Wilson
> >
> > Additional work to rename 48bit to 4 level
>
> Thanks for the additional work.
> Bikeshed on this comment here: Shouldn't this be mentioned on the
> "v3" portion directly instead of the middle of tags' block?
Oops, that was just a rebase squash failure on my part and shouldn't be
there at all.
>
> >
> > Signed-off-by: Bob Paauwe
> > ---
> > drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> > drivers/gpu/drm/i915/i915_gem_gtt.c | 24
> >
> > drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++--
> > drivers/gpu/drm/i915/i915_pci.c | 7 +--
> > drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
> > drivers/gpu/drm/i915/i915_vgpu.c | 4 ++--
> > drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
> > drivers/gpu/drm/i915/intel_device_info.h | 4 +++-
> > drivers/gpu/drm/i915/intel_lrc.c | 8
> > drivers/gpu/drm/i915/selftests/huge_pages.c | 8
> > drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
> > 13 files changed, 39 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c
> > b/drivers/gpu/drm/i915/gvt/vgpu.c
> > index a4e8e3cf74fd..52bebd67173a 100644
> > --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> > @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> > vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
> > vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
> >
> > - vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> > + vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
> > vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
> > vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 5a4da5b723fd..a367686fd735 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> >
> > #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
> > #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
> > -#define USES_FULL_48BIT_PPGTT(dev_priv)(i915_modparams.enable_ppgtt ==
> > 3)
> > +#define USES_FULL_4LVL_PPGTT(dev_priv)
> > ((dev_priv)->info.full_ppgtt_bits > 32)
>
> another bikeshed: FULL_4LVL_PPGTT or just 4LVL_PPGTT?
I don't have any strong opinion here but can see that "FULL" is a bit
redundant when thinking of this an option/enhancement to FULL_PPGTT.
>
> > #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> > GEM_BUG_ON((sizes) == 0); \
> > ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index f15a039772db..1add339ca6be 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -249,7 +249,7 @@ static u32 default_desc_template(const struct
> > drm_i915_private *i915,
> > desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
> >
> > address_mode = INTEL_LEGACY_32B_CONTEXT;
> > - if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> > + if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
> > address_mode = INTEL_LEGACY_64B_CONTEXT;
> > desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index eb0e446d6482..c66bbf409791 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct
> > drm_i915_private *dev_priv,
> > int enable_ppgtt)
> > {
> > bool has_full_ppgtt;
> > - bool has_full_48bit_ppgtt;
> > + b
Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)
On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
>
> Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range PPGTT is being
> used. Add a new device info field that specifies the number of
> bits to prepare for cases where the range is not 32 or 48 bits.
>
> v2: keep USES_FULL_PPGTT() unchanged (Chris)
> v3: Simplify condition in gen8_ppgtt_create() (Chris)
> Remove unecessary line coninuations (Bob)
> Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
>
> Signed-off-by: Bob Paauwe
> CC: Rodrigo Vivi
> CC: Michel Thierry
> CC: Chris Wilson
>
> Additional work to rename 48bit to 4 level
Thanks for the additional work.
Bikeshed on this comment here: Shouldn't this be mentioned on the
"v3" portion directly instead of the middle of tags' block?
>
> Signed-off-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 24
>
> drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++--
> drivers/gpu/drm/i915/i915_pci.c | 7 +--
> drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
> drivers/gpu/drm/i915/i915_vgpu.c | 4 ++--
> drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
> drivers/gpu/drm/i915/intel_device_info.h | 4 +++-
> drivers/gpu/drm/i915/intel_lrc.c | 8
> drivers/gpu/drm/i915/selftests/huge_pages.c | 8
> drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
> 13 files changed, 39 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index a4e8e3cf74fd..52bebd67173a 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>
> - vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> + vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5a4da5b723fd..a367686fd735 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>
> #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
> #define USES_FULL_PPGTT(dev_priv)(i915_modparams.enable_ppgtt >= 2)
> -#define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt ==
> 3)
> +#define USES_FULL_4LVL_PPGTT(dev_priv)
> ((dev_priv)->info.full_ppgtt_bits > 32)
another bikeshed: FULL_4LVL_PPGTT or just 4LVL_PPGTT?
> #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> GEM_BUG_ON((sizes) == 0); \
> ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index f15a039772db..1add339ca6be 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -249,7 +249,7 @@ static u32 default_desc_template(const struct
> drm_i915_private *i915,
> desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>
> address_mode = INTEL_LEGACY_32B_CONTEXT;
> - if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> + if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
> address_mode = INTEL_LEGACY_64B_CONTEXT;
> desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index eb0e446d6482..c66bbf409791 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private
> *dev_priv,
> int enable_ppgtt)
> {
> bool has_full_ppgtt;
> - bool has_full_48bit_ppgtt;
> + bool has_full_4lvl_ppgtt;
>
> if (!dev_priv->info.has_aliasing_ppgtt)
> return 0;
>
> has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> - has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> + has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
>
> if (intel_vgpu_active(dev_priv)) {
> /* GVT-g has no support for 32bit ppgtt */
> has_full_ppgtt = false;
> - has_full_48bit
[Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)
48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.
Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
v2: keep USES_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
Remove unecessary line coninuations (Bob)
Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
Additional work to rename 48bit to 4 level
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 24
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++--
drivers/gpu/drm/i915/i915_pci.c | 7 +--
drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
drivers/gpu/drm/i915/i915_vgpu.c | 4 ++--
drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 4 +++-
drivers/gpu/drm/i915/intel_lrc.c | 8
drivers/gpu/drm/i915/selftests/huge_pages.c | 8
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
13 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index a4e8e3cf74fd..52bebd67173a 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
- vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+ vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a4da5b723fd..a367686fd735 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)(i915_modparams.enable_ppgtt ==
3)
+#define USES_FULL_4LVL_PPGTT(dev_priv) ((dev_priv)->info.full_ppgtt_bits > 32)
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..1add339ca6be 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -249,7 +249,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
address_mode = INTEL_LEGACY_32B_CONTEXT;
- if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+ if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
address_mode = INTEL_LEGACY_64B_CONTEXT;
desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eb0e446d6482..c66bbf409791 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv,
int enable_ppgtt)
{
bool has_full_ppgtt;
- bool has_full_48bit_ppgtt;
+ bool has_full_4lvl_ppgtt;
if (!dev_priv->info.has_aliasing_ppgtt)
return 0;
has_full_ppgtt = dev_priv->info.has_full_ppgtt;
- has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
+ has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
if (intel_vgpu_active(dev_priv)) {
/* GVT-g has no support for 32bit ppgtt */
has_full_ppgtt = false;
- has_full_48bit_ppgtt =
intel_vgpu_has_full_48bit_ppgtt(dev_priv);
+ has_full_4lvl_ppgtt = intel_vgpu_has_full_4lvl_ppgtt(dev_priv);
}
/*
@@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv,
if (enable_ppgtt == 2 && has_full_ppgtt)
return 2;
- if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
+ if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
