Re: [Intel-gfx] [PATCH] drm/i915: Read CHV_PLL_DW8 from the correct offset
On Wed, Mar 11, 2015 at 08:20:44PM -0700, Todd Previte wrote: On 3/11/2015 1:52 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com We accidentally pass 'pipe' instead of 'port' to CHV_PLL_DW8() and with PIPE_C we end up at register offset 0x8320 which isn't the 0x8020 we wanted. Fix it. The problem was fortunately caught by the sanity check in vlv_dpio_read(): WARNING: CPU: 1 PID: 238 at ../drivers/gpu/drm/i915/intel_sideband.c:200 vlv_dpio_read+0x77/0x80 [i915]() DPIO read pipe C reg 0x8320 == 0x The problem got introduced with this commit: commit 71af07f91f12bbab96335e202c82525d31680960 Author: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com Date: Thu Mar 5 19:33:08 2015 +0530 drm/i915: Update prop, int co-eff and gain threshold for CHV Cc: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ecbad5a..198e5fc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6270,7 +6270,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, } vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); -dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe)); +dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); dpio_val = ~DPIO_CHV_TDC_TARGET_CNT_MASK; dpio_val |= (tribuf_calcntr DPIO_CHV_TDC_TARGET_CNT_SHIFT); vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); Looks good to me. Reviewed-by: Todd Previte tprev...@gmail.com Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Read CHV_PLL_DW8 from the correct offset
From: Ville Syrjälä ville.syrj...@linux.intel.com We accidentally pass 'pipe' instead of 'port' to CHV_PLL_DW8() and with PIPE_C we end up at register offset 0x8320 which isn't the 0x8020 we wanted. Fix it. The problem was fortunately caught by the sanity check in vlv_dpio_read(): WARNING: CPU: 1 PID: 238 at ../drivers/gpu/drm/i915/intel_sideband.c:200 vlv_dpio_read+0x77/0x80 [i915]() DPIO read pipe C reg 0x8320 == 0x The problem got introduced with this commit: commit 71af07f91f12bbab96335e202c82525d31680960 Author: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com Date: Thu Mar 5 19:33:08 2015 +0530 drm/i915: Update prop, int co-eff and gain threshold for CHV Cc: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ecbad5a..198e5fc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6270,7 +6270,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, } vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); - dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe)); + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); dpio_val = ~DPIO_CHV_TDC_TARGET_CNT_MASK; dpio_val |= (tribuf_calcntr DPIO_CHV_TDC_TARGET_CNT_SHIFT); vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); -- 2.0.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Read CHV_PLL_DW8 from the correct offset
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5936 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -15 281/281 266/281 ILK -1 308/308 307/308 SNB -1 284/284 283/284 IVB 375/375 375/375 BYT 294/294 294/294 HSW -1 384/384 383/384 BDW 315/315 315/315 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gem_fence_thrash_bo-write-verify-none PASS(3) FAIL(1) *PNV igt_gem_fence_thrash_bo-write-verify-x PASS(3) FAIL(1) *PNV igt_gem_fence_thrash_bo-write-verify-y PASS(3) FAIL(1) PNV igt_gem_userptr_blits_coherency-sync CRASH(5)PASS(2) CRASH(1) PNV igt_gen3_render_linear_blits FAIL(3)PASS(1) FAIL(1) PNV igt_gen3_render_mixed_blits FAIL(2)PASS(2) FAIL(1) PNV igt_gen3_render_tiledx_blits FAIL(4)PASS(1) FAIL(1) PNV igt_gem_fence_thrash_bo-write-verify-threaded-none CRASH(2)PASS(4) CRASH(1) *PNV igt_gem_partial_pwrite_pread_reads PASS(2) NRUN(1) *PNV igt_gem_partial_pwrite_pread_reads-display PASS(2) NRUN(1) *PNV igt_gem_pwrite_pread_display-pwrite-blt-gtt_mmap-performance PASS(2) NRUN(1) *PNV igt_gem_ringfill_blitter PASS(2) NRUN(1) *PNV igt_gem_ringfill_blitter-interruptible PASS(2) NRUN(1) *PNV igt_gem_tiled_pread_pwrite FAIL(1)PASS(2) NRUN(1) *PNV igt_gem_userptr_blits_forked-sync-mempressure-interruptible PASS(2) NRUN(1) *ILK igt_gem_unfence_active_buffers PASS(3) DMESG_WARN(1)PASS(1) *SNB igt_gem_flink_bad-open PASS(2) DMESG_WARN(1)PASS(1) *HSW igt_pm_rpm_reg-read-ioctl PASS(2) DMESG_FAIL(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Read CHV_PLL_DW8 from the correct offset
On 3/11/2015 1:52 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com We accidentally pass 'pipe' instead of 'port' to CHV_PLL_DW8() and with PIPE_C we end up at register offset 0x8320 which isn't the 0x8020 we wanted. Fix it. The problem was fortunately caught by the sanity check in vlv_dpio_read(): WARNING: CPU: 1 PID: 238 at ../drivers/gpu/drm/i915/intel_sideband.c:200 vlv_dpio_read+0x77/0x80 [i915]() DPIO read pipe C reg 0x8320 == 0x The problem got introduced with this commit: commit 71af07f91f12bbab96335e202c82525d31680960 Author: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com Date: Thu Mar 5 19:33:08 2015 +0530 drm/i915: Update prop, int co-eff and gain threshold for CHV Cc: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ecbad5a..198e5fc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6270,7 +6270,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, } vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); - dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe)); + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); dpio_val = ~DPIO_CHV_TDC_TARGET_CNT_MASK; dpio_val |= (tribuf_calcntr DPIO_CHV_TDC_TARGET_CNT_SHIFT); vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); Looks good to me. Reviewed-by: Todd Previte tprev...@gmail.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
