Re: [Intel-gfx] [PATCH] drm/i915: Rename REDIRECT_TO_GUC bit

[Chris Wilson]

On Mon, Mar 13, 2017 at 10:17:25AM +0530, Kamble, Sagar A wrote:
>  LGTM.
>  Reviewed-by: Sagar Arun Kamble [1]

Thanks, pushed
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] drm/i915: Rename REDIRECT_TO_GUC bit

[Kamble, Sagar A]

LGTM.
Reviewed-by: Sagar Arun Kamble

PS: Might need updating comments in the guc_interrupts_capture to align with 
new name and semantics of this bit
w.r.t pm_intrmsk_mbz.

On 3/12/2017 6:57 PM, Chris Wilson wrote:

The REDIRECT_TO_GUC bit is a strange beast as it is a disable bit -
setting the bit in the pm interrupt generation stops the interrupt going
to the guc (not sending it to the guc as the name implies). To help the
reader rename it to DISABLE_REDIRECT_TO_GUC so that we keep the bspec
greppable name without it being as confusing!

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Oscar Mateo 
Cc: Radoslaw Szwichtenberg 
Cc: Sagar Arun Kamble 
---
  drivers/gpu/drm/i915/i915_guc_submission.c | 4 ++--
  drivers/gpu/drm/i915/i915_irq.c| 2 +-
  drivers/gpu/drm/i915/i915_reg.h| 2 +-
  3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index ca7723fd0f79..84fd49d5680e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -975,7 +975,7 @@ static void guc_interrupts_capture(struct drm_i915_private 
*dev_priv)
 * result in the register bit being left SET!
 */
dev_priv->rps.pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
-   dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
+   dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
  }
  
  int i915_guc_submission_enable(struct drm_i915_private *dev_priv)

@@ -1037,7 +1037,7 @@ static void guc_interrupts_release(struct 
drm_i915_private *dev_priv)
I915_WRITE(GUC_VCS2_VCS1_IER, 0);
I915_WRITE(GUC_WD_VECS_IER, 0);
  
-	dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_REDIRECT_TO_GUC;

+   dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
dev_priv->rps.pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
  
  }

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a522da712cc8..89ccf3e1fda5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4282,7 +4282,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
  
  	if (INTEL_INFO(dev_priv)->gen >= 8)

-   dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_REDIRECT_TO_GUC;
+   dev_priv->rps.pm_intrmsk_mbz |= 
GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
  
  	if (IS_GEN2(dev_priv)) {

/* Gen2 doesn't have a hardware frame counter */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19d42e8813c4..5d88c35c41cd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7453,7 +7453,7 @@ enum {
  #define VLV_RCEDATA   _MMIO(0xA0BC)
  #define GEN6_RC6pp_THRESHOLD  _MMIO(0xA0C0)
  #define GEN6_PMINTRMSK_MMIO(0xA168)
-#define   GEN8_PMINTR_REDIRECT_TO_GUC  (1<<31)
+#define   GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC  (1<<31)
  #define   ARAT_EXPIRED_INTRMSK(1<<9)
  #define GEN8_MISC_CTRL0   _MMIO(0xA180)
  #define VLV_PWRDWNUPCTL   _MMIO(0xA294)


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[Intel-gfx] [PATCH] drm/i915: Rename REDIRECT_TO_GUC bit

[Chris Wilson]

The REDIRECT_TO_GUC bit is a strange beast as it is a disable bit -
setting the bit in the pm interrupt generation stops the interrupt going
to the guc (not sending it to the guc as the name implies). To help the
reader rename it to DISABLE_REDIRECT_TO_GUC so that we keep the bspec
greppable name without it being as confusing!

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Oscar Mateo 
Cc: Radoslaw Szwichtenberg 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 4 ++--
 drivers/gpu/drm/i915/i915_irq.c| 2 +-
 drivers/gpu/drm/i915/i915_reg.h| 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index ca7723fd0f79..84fd49d5680e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -975,7 +975,7 @@ static void guc_interrupts_capture(struct drm_i915_private 
*dev_priv)
 * result in the register bit being left SET!
 */
dev_priv->rps.pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
-   dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
+   dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 }
 
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
@@ -1037,7 +1037,7 @@ static void guc_interrupts_release(struct 
drm_i915_private *dev_priv)
I915_WRITE(GUC_VCS2_VCS1_IER, 0);
I915_WRITE(GUC_WD_VECS_IER, 0);
 
-   dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_REDIRECT_TO_GUC;
+   dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
dev_priv->rps.pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
 
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a522da712cc8..89ccf3e1fda5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4282,7 +4282,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
 
if (INTEL_INFO(dev_priv)->gen >= 8)
-   dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_REDIRECT_TO_GUC;
+   dev_priv->rps.pm_intrmsk_mbz |= 
GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 
if (IS_GEN2(dev_priv)) {
/* Gen2 doesn't have a hardware frame counter */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19d42e8813c4..5d88c35c41cd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7453,7 +7453,7 @@ enum {
 #define VLV_RCEDATA_MMIO(0xA0BC)
 #define GEN6_RC6pp_THRESHOLD   _MMIO(0xA0C0)
 #define GEN6_PMINTRMSK _MMIO(0xA168)
-#define   GEN8_PMINTR_REDIRECT_TO_GUC  (1<<31)
+#define   GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC  (1<<31)
 #define   ARAT_EXPIRED_INTRMSK (1<<9)
 #define GEN8_MISC_CTRL0_MMIO(0xA180)
 #define VLV_PWRDWNUPCTL_MMIO(0xA294)
-- 
2.11.0

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