[Intel-gfx] [PATCH] drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz

2015-02-26 Thread ville . syrjala 
From: Ville Syrjälä 

The current minimum vco frequency leaves us with a gap in our supported
frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a
pixel clock of 241.5 MHz, which is just withing that gap. Reduce the
allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz,
and thus allow such displays to work.

4.8 GHz is actually the documented (at least in some docs) limit of the
PLL, and we just picked 4.86 GHz originally because that was the lowest
value produced by the PLL spreadsheet, which obviously didn't consider
2560x1440 displays.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 102b12d..d437a21 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
 * them would make no difference.
 */
.dot = { .min = 25000 * 5, .max = 54 * 5},
-   .vco = { .min = 486, .max = 670 },
+   .vco = { .min = 480, .max = 670 },
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
.m2 = { .min = 24 << 22, .max = 175 << 22 },
-- 
2.0.5

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Re: [Intel-gfx] [PATCH] drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz

2015-02-28 Thread shuang . he 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 5845
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  282/282  282/282
ILK -1  308/308  307/308
SNB  326/326  326/326
IVB  379/379  379/379
BYT  294/294  294/294
HSW -1  387/387  386/387
BDW -1  316/316  315/316
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*ILK  igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible  PASS(4)  
DMESG_WARN(1)PASS(1)
*HSW  igt_gem_storedw_batches_loop_normal  PASS(4)  DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog  PASS(15)  DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [Intel-gfx] [PATCH] drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz

2015-03-04 Thread Purushothaman, Vijay A 

On 2/27/2015 12:31 AM, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä 

The current minimum vco frequency leaves us with a gap in our supported
frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a
pixel clock of 241.5 MHz, which is just withing that gap. Reduce the
allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz,
and thus allow such displays to work.

4.8 GHz is actually the documented (at least in some docs) limit of the
PLL, and we just picked 4.86 GHz originally because that was the lowest
value produced by the PLL spreadsheet, which obviously didn't consider
2560x1440 displays.

Signed-off-by: Ville Syrjälä 
---
  drivers/gpu/drm/i915/intel_display.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 102b12d..d437a21 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
 * them would make no difference.
 */
.dot = { .min = 25000 * 5, .max = 54 * 5},
-   .vco = { .min = 486, .max = 670 },
+   .vco = { .min = 480, .max = 670 },
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
.m2 = { .min = 24 << 22, .max = 175 << 22 },


Minor nitpick: typo in patch title

Reviewed-by: Vijay Purushothaman 

Thanks,
Vijay
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Re: [Intel-gfx] [PATCH] drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz

2015-03-04 Thread Ville Syrjälä 
On Wed, Mar 04, 2015 at 08:11:38PM +0530, Purushothaman, Vijay A wrote:
> On 2/27/2015 12:31 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> >
> > The current minimum vco frequency leaves us with a gap in our supported
> > frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a
> > pixel clock of 241.5 MHz, which is just withing that gap. Reduce the
> > allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz,
> > and thus allow such displays to work.
> >
> > 4.8 GHz is actually the documented (at least in some docs) limit of the
> > PLL, and we just picked 4.86 GHz originally because that was the lowest
> > value produced by the PLL spreadsheet, which obviously didn't consider
> > 2560x1440 displays.
> >
> > Signed-off-by: Ville Syrjälä 
> > ---
> >   drivers/gpu/drm/i915/intel_display.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 102b12d..d437a21 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
> >  * them would make no difference.
> >  */
> > .dot = { .min = 25000 * 5, .max = 54 * 5},
> > -   .vco = { .min = 486, .max = 670 },
> > +   .vco = { .min = 480, .max = 670 },
> > .n = { .min = 1, .max = 1 },
> > .m1 = { .min = 2, .max = 2 },
> > .m2 = { .min = 24 << 22, .max = 175 << 22 },
> 
> Minor nitpick: typo in patch title

Dang. I already fixed a typo there before sending this out, but turns
out I only managed to cchange it into a different typo :( Maybe I need
to invest in a spell checker...

> 
> Reviewed-by: Vijay Purushothaman 
> 
> Thanks,
> Vijay
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-- 
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Re: [Intel-gfx] [PATCH] drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz

2015-03-04 Thread Daniel Vetter 
On Wed, Mar 04, 2015 at 05:10:02PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 04, 2015 at 08:11:38PM +0530, Purushothaman, Vijay A wrote:
> > On 2/27/2015 12:31 AM, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä 
> > >
> > > The current minimum vco frequency leaves us with a gap in our supported
> > > frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a
> > > pixel clock of 241.5 MHz, which is just withing that gap. Reduce the
> > > allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz,
> > > and thus allow such displays to work.
> > >
> > > 4.8 GHz is actually the documented (at least in some docs) limit of the
> > > PLL, and we just picked 4.86 GHz originally because that was the lowest
> > > value produced by the PLL spreadsheet, which obviously didn't consider
> > > 2560x1440 displays.
> > >
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >   drivers/gpu/drm/i915/intel_display.c | 2 +-
> > >   1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 102b12d..d437a21 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
> > >* them would make no difference.
> > >*/
> > >   .dot = { .min = 25000 * 5, .max = 54 * 5},
> > > - .vco = { .min = 486, .max = 670 },
> > > + .vco = { .min = 480, .max = 670 },
> > >   .n = { .min = 1, .max = 1 },
> > >   .m1 = { .min = 2, .max = 2 },
> > >   .m2 = { .min = 24 << 22, .max = 175 << 22 },
> > 
> > Minor nitpick: typo in patch title
> 
> Dang. I already fixed a typo there before sending this out, but turns
> out I only managed to cchange it into a different typo :( Maybe I need
> to invest in a spell checker...

Fixed and applied, thanks.
-Daniel

> 
> > 
> > Reviewed-by: Vijay Purushothaman 
> > 
> > Thanks,
> > Vijay
> > ___
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> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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