Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
On Thu, Aug 04, 2016 at 06:31:19AM +, Yang, Libin wrote:
> Hi Ville,
>
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Thursday, August 4, 2016 2:24 PM
> > To: Yang, Libin
> > Cc: 'libin.y...@linux.intel.com' ; 'intel-
> > g...@lists.freedesktop.org' ;
> > 'jani.nik...@linux.intel.com' ; Vetter, Daniel
> > ; 'ti...@suse.de'
> > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> >
> > On Thu, Aug 04, 2016 at 06:04:10AM +, Yang, Libin wrote:
> > > Hi Ville,
> > >
> > > > -Original Message-
> > > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > > Sent: Thursday, August 4, 2016 1:39 PM
> > > > To: Yang, Libin
> > > > Cc: 'libin.y...@linux.intel.com' ;
> > > > 'intel- g...@lists.freedesktop.org'
> > > > ;
> > > > 'jani.nik...@linux.intel.com' ; Vetter,
> > > > Daniel ; 'ti...@suse.de'
> > > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > > >
> > > > On Thu, Aug 04, 2016 at 02:48:54AM +, Yang, Libin wrote:
> > > > > Hi Ville,
> > > > >
> > > > > > -Original Message-
> > > > > > From: Yang, Libin
> > > > > > Sent: Tuesday, August 2, 2016 9:59 PM
> > > > > > To: Ville Syrjälä ;
> > > > > > libin.y...@linux.intel.com
> > > > > > Cc: intel-gfx@lists.freedesktop.org;
> > > > > > jani.nik...@linux.intel.com; Vetter, Daniel
> > > > > > ; ti...@suse.de
> > > > > > Subject: RE: [PATCH] drm/i915: set proper N/M in modeset
> > > > > >
> > > > > > Hi Ville
> > > > > >
> > > > > > > -Original Message-
> > > > > > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > > > > > Sent: Tuesday, August 2, 2016 6:47 PM
> > > > > > > To: libin.y...@linux.intel.com
> > > > > > > Cc: intel-gfx@lists.freedesktop.org;
> > > > > > > jani.nik...@linux.intel.com; Vetter, Daniel
> > > > > > > ; ti...@suse.de; Yang, Libin
> > > > > > >
> > > > > > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > > > > > >
> > > > > > > On Tue, Aug 02, 2016 at 09:35:10AM +0800,
> > > > > > > libin.y...@linux.intel.com
> > > > > > wrote:
> > > > > > > > From: Libin Yang
> > > > > > > >
> > > > > > > > When modeset occurs and the LS_CLK is set to some special
> > > > > > > > values in DP mode, the N/M need to be set manually if audio is
> > playing.
> > > > > > > >
> > > > > > > > The relationship of Maud and Naud is expressed in the
> > > > > > > > following
> > > > > > > > equation:
> > > > > > > > Maud/Naud = 512 * fs / f_LS_Clk
> > > > > > > >
> > > > > > > > Please refer VESA DisplayPort Standard spec for details.
> > > > > > > >
> > > > > > > > Also, the patch applies
> > > > > > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in
> > > > > > > > modeset") to APL platform.
> > > > > > > >
> > > > > > > > Signed-off-by: Libin Yang
> > > > > > > > ---
> > > > > > > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > > > > > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > > > > > > +++--
> > > > > > > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e
> > > > > > > > 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > > @@ -7351,6 +7351,12 @@ enum {
> > > > > > > > #define _HSW_AUD_CONFIG_B 0x65100
> > > > > > > > #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe,
> > > > > > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > > > > > >
> > > > > > > > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > > > > > > > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > > > > > > > +#define HSW_AUD_M_CTS_ENABLE(pipe)
> > > > _MMIO_PIPE(pipe,
> > > > > > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > > > > > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
> > > > > > > > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
> > > > > > > > +
> > > > > > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > > > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > > > > > #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> > > > > > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > > > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > > > > > index 6700a7b..de55ecf 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > > > > > @@ -98,6 +98,22 @@ static const struct {
> > > > > > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > > > > > >
> > > > > > > > +#define LC_540M 54
> > > > > > > > +#define LC_162M 162000
> > > > > > >
> > > > > > > Do we have some explanation why 2.7 doesn't need M/N
> > > > > > > programming, but
> > > > > > > 1.62 and 5.4 do?
> > > > > >
> > > > > > I didn't use 2.7 because I can't
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi Ville,
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, August 4, 2016 2:24 PM
> To: Yang, Libin
> Cc: 'libin.y...@linux.intel.com' ; 'intel-
> g...@lists.freedesktop.org' ;
> 'jani.nik...@linux.intel.com' ; Vetter, Daniel
> ; 'ti...@suse.de'
> Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
>
> On Thu, Aug 04, 2016 at 06:04:10AM +, Yang, Libin wrote:
> > Hi Ville,
> >
> > > -Original Message-
> > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > Sent: Thursday, August 4, 2016 1:39 PM
> > > To: Yang, Libin
> > > Cc: 'libin.y...@linux.intel.com' ;
> > > 'intel- g...@lists.freedesktop.org'
> > > ;
> > > 'jani.nik...@linux.intel.com' ; Vetter,
> > > Daniel ; 'ti...@suse.de'
> > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > >
> > > On Thu, Aug 04, 2016 at 02:48:54AM +, Yang, Libin wrote:
> > > > Hi Ville,
> > > >
> > > > > -Original Message-
> > > > > From: Yang, Libin
> > > > > Sent: Tuesday, August 2, 2016 9:59 PM
> > > > > To: Ville Syrjälä ;
> > > > > libin.y...@linux.intel.com
> > > > > Cc: intel-gfx@lists.freedesktop.org;
> > > > > jani.nik...@linux.intel.com; Vetter, Daniel
> > > > > ; ti...@suse.de
> > > > > Subject: RE: [PATCH] drm/i915: set proper N/M in modeset
> > > > >
> > > > > Hi Ville
> > > > >
> > > > > > -Original Message-
> > > > > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > > > > Sent: Tuesday, August 2, 2016 6:47 PM
> > > > > > To: libin.y...@linux.intel.com
> > > > > > Cc: intel-gfx@lists.freedesktop.org;
> > > > > > jani.nik...@linux.intel.com; Vetter, Daniel
> > > > > > ; ti...@suse.de; Yang, Libin
> > > > > >
> > > > > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > > > > >
> > > > > > On Tue, Aug 02, 2016 at 09:35:10AM +0800,
> > > > > > libin.y...@linux.intel.com
> > > > > wrote:
> > > > > > > From: Libin Yang
> > > > > > >
> > > > > > > When modeset occurs and the LS_CLK is set to some special
> > > > > > > values in DP mode, the N/M need to be set manually if audio is
> playing.
> > > > > > >
> > > > > > > The relationship of Maud and Naud is expressed in the
> > > > > > > following
> > > > > > > equation:
> > > > > > > Maud/Naud = 512 * fs / f_LS_Clk
> > > > > > >
> > > > > > > Please refer VESA DisplayPort Standard spec for details.
> > > > > > >
> > > > > > > Also, the patch applies
> > > > > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in
> > > > > > > modeset") to APL platform.
> > > > > > >
> > > > > > > Signed-off-by: Libin Yang
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > > > > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > > > > > +++--
> > > > > > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e
> > > > > > > 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > > @@ -7351,6 +7351,12 @@ enum {
> > > > > > > #define _HSW_AUD_CONFIG_B0x65100
> > > > > > > #define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe,
> > > > > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > > > > >
> > > > > > > +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> > > > > > > +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> > > > > > > +#define HSW_AUD_M_CTS_ENABLE(pipe)
> > > _MMIO_PIPE(pipe,
> > > > > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > > > > +#define AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> > > > > > > +#define AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> > > > > > > +
> > > > > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > > > > #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> > > > > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > > > > index 6700a7b..de55ecf 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > > > > @@ -98,6 +98,22 @@ static const struct {
> > > > > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > > > > >
> > > > > > > +#define LC_540M 54
> > > > > > > +#define LC_162M 162000
> > > > > >
> > > > > > Do we have some explanation why 2.7 doesn't need M/N
> > > > > > programming, but
> > > > > > 1.62 and 5.4 do?
> > > > >
> > > > > I didn't use 2.7 because I can't find a mode using 2.7. So I can't do
> > > > > the
> test.
> > > > > 5.4 is for 4K and 1.62 is for 1080p.
> > > > >
> > > > > >
> > > > > > And I see you're only doing this on HSW+. Earlier platforms
> > > > > > don't need
> > > this?
> > > > >
> > > > > We are not supporting earlier platforms and I'm not su
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
On Thu, Aug 04, 2016 at 06:04:10AM +, Yang, Libin wrote:
> Hi Ville,
>
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Thursday, August 4, 2016 1:39 PM
> > To: Yang, Libin
> > Cc: 'libin.y...@linux.intel.com' ; 'intel-
> > g...@lists.freedesktop.org' ;
> > 'jani.nik...@linux.intel.com' ; Vetter, Daniel
> > ; 'ti...@suse.de'
> > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> >
> > On Thu, Aug 04, 2016 at 02:48:54AM +, Yang, Libin wrote:
> > > Hi Ville,
> > >
> > > > -Original Message-
> > > > From: Yang, Libin
> > > > Sent: Tuesday, August 2, 2016 9:59 PM
> > > > To: Ville Syrjälä ;
> > > > libin.y...@linux.intel.com
> > > > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> > > > Vetter, Daniel ; ti...@suse.de
> > > > Subject: RE: [PATCH] drm/i915: set proper N/M in modeset
> > > >
> > > > Hi Ville
> > > >
> > > > > -Original Message-
> > > > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > > > Sent: Tuesday, August 2, 2016 6:47 PM
> > > > > To: libin.y...@linux.intel.com
> > > > > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> > > > > Vetter, Daniel ; ti...@suse.de; Yang,
> > > > > Libin
> > > > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > > > >
> > > > > On Tue, Aug 02, 2016 at 09:35:10AM +0800,
> > > > > libin.y...@linux.intel.com
> > > > wrote:
> > > > > > From: Libin Yang
> > > > > >
> > > > > > When modeset occurs and the LS_CLK is set to some special values
> > > > > > in DP mode, the N/M need to be set manually if audio is playing.
> > > > > >
> > > > > > The relationship of Maud and Naud is expressed in the following
> > > > > > equation:
> > > > > > Maud/Naud = 512 * fs / f_LS_Clk
> > > > > >
> > > > > > Please refer VESA DisplayPort Standard spec for details.
> > > > > >
> > > > > > Also, the patch applies
> > > > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to
> > > > > > APL platform.
> > > > > >
> > > > > > Signed-off-by: Libin Yang
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > > > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > > > > +++--
> > > > > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > @@ -7351,6 +7351,12 @@ enum {
> > > > > > #define _HSW_AUD_CONFIG_B 0x65100
> > > > > > #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe,
> > > > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > > > >
> > > > > > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > > > > > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > > > > > +#define HSW_AUD_M_CTS_ENABLE(pipe)
> > _MMIO_PIPE(pipe,
> > > > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > > > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
> > > > > > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
> > > > > > +
> > > > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > > > #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> > > > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > > > index 6700a7b..de55ecf 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > > > @@ -98,6 +98,22 @@ static const struct {
> > > > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > > > >
> > > > > > +#define LC_540M 54
> > > > > > +#define LC_162M 162000
> > > > >
> > > > > Do we have some explanation why 2.7 doesn't need M/N programming,
> > > > > but
> > > > > 1.62 and 5.4 do?
> > > >
> > > > I didn't use 2.7 because I can't find a mode using 2.7. So I can't do
> > > > the test.
> > > > 5.4 is for 4K and 1.62 is for 1080p.
> > > >
> > > > >
> > > > > And I see you're only doing this on HSW+. Earlier platforms don't need
> > this?
> > > >
> > > > We are not supporting earlier platforms and I'm not sure whether the
> > > > old platforms supports 4K DP or not.
> > > >
> > > > >
> > > > > > +static const struct {
> > > > > > + int sample_rate;
> > > > > > + int clock;
> > > > > > + int n;
> > > > > > + int m;
> > > > >
> > > > > Can save a bit of space by using u16 for m and n.
> > > >
> > > > OK, I will do it in next version.
> > > >
> > > > >
> > > > > > +} aud_nm[] = {
> > > > > > + {48000, LC_540M, 5625, 256},`
> > > > > > + {44100, LC_540M, 9375, 392},
> > > > > > + {32000, LC_540M, 16875, 512},
> > > > > > + {48000, LC_162M, 3375, 512},
> > > > > > + {44100, LC_162M, 5625, 784},
> > > > > > + {32000, LC_162M, 10125, 1024
> > >
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi Ville,
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, August 4, 2016 2:06 PM
> To: Yang, Libin
> Cc: libin.y...@linux.intel.com; intel-gfx@lists.freedesktop.org;
> jani.nik...@linux.intel.com; Vetter, Daniel ;
> ti...@suse.de
> Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
>
> On Thu, Aug 04, 2016 at 05:46:01AM +, Yang, Libin wrote:
> > Hi Ville,
> >
> > > -Original Message-
> > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > Sent: Wednesday, August 3, 2016 12:59 AM
> > > To: Yang, Libin
> > > Cc: libin.y...@linux.intel.com; intel-gfx@lists.freedesktop.org;
> > > jani.nik...@linux.intel.com; Vetter, Daniel
> > > ; ti...@suse.de
> > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > >
> > > On Tue, Aug 02, 2016 at 01:58:51PM +, Yang, Libin wrote:
> > > > Hi Ville
> > > >
> > > > > -Original Message-
> > > > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > > > Sent: Tuesday, August 2, 2016 6:47 PM
> > > > > To: libin.y...@linux.intel.com
> > > > > Cc: intel-gfx@lists.freedesktop.org;
> > > > > jani.nik...@linux.intel.com; Vetter, Daniel
> > > > > ; ti...@suse.de; Yang, Libin
> > > > >
> > > > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > > > >
> > > > > On Tue, Aug 02, 2016 at 09:35:10AM +0800,
> > > > > libin.y...@linux.intel.com
> > > wrote:
> > > > > > From: Libin Yang
> > > > > >
> > > > > > When modeset occurs and the LS_CLK is set to some special
> > > > > > values in DP mode, the N/M need to be set manually if audio is
> playing.
> > > > > >
> > > > > > The relationship of Maud and Naud is expressed in the
> > > > > > following
> > > > > > equation:
> > > > > > Maud/Naud = 512 * fs / f_LS_Clk
> > > > > >
> > > > > > Please refer VESA DisplayPort Standard spec for details.
> > > > > >
> > > > > > Also, the patch applies
> > > > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset")
> > > > > > to APL platform.
> > > > > >
> > > > > > Signed-off-by: Libin Yang
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > > > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > > > > +++--
> > > > > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e
> > > > > > 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > @@ -7351,6 +7351,12 @@ enum {
> > > > > > #define _HSW_AUD_CONFIG_B 0x65100
> > > > > > #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe,
> > > > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > > > >
> > > > > > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > > > > > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > > > > > +#define HSW_AUD_M_CTS_ENABLE(pipe)
> > > _MMIO_PIPE(pipe,
> > > > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > > > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
> > > > > > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
> > > > > > +
> > > > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > > > #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> > > > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > > > index 6700a7b..de55ecf 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > > > @@ -98,6 +98,22 @@ static const struct {
> > > > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > > > >
> > > > > > +#define LC_540M 54
> > > > > > +#define LC_162M 162000
> > > > >
> > > > > Do we have some explanation why 2.7 doesn't need M/N
> > > > > programming, but
> > > > > 1.62 and 5.4 do?
> > > >
> > > > I didn't use 2.7 because I can't find a mode using 2.7.
> > >
> > > Hmm. Maybe we should add some knobs to force a specific bpc/link
> > > rate/number of lanes to help with this kind of testing. Currently
> > > you just get what you get, which isn't so nice when you want to test all
> variations.
> > > ...
> > > OK, so I just went ahead and did that. Here's a branch:
> > >
> > > git://github.com/vsyrjala/linux.git modparam_clock_bpp_limit
> > >
> > > For your DP testing just setting
> > > i915.max_port_clock=162000 or i915.max_port_clock=27 and then
> > > forcing a modeset should do the trick.
> >
> > Thanks for the new branch. It seems download is very slow, less than
> > 10Kib/s.
>
> github that slow for you? Weird.
>
> And I can't see a way to grab the raw patches from the github web
> interface :( so I've attached the patches to this mail in case you can't
> finish the
> git fetch in reasonable time.
>
> > So I will submit the new
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
On Thu, Aug 04, 2016 at 05:46:01AM +, Yang, Libin wrote:
> Hi Ville,
>
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Wednesday, August 3, 2016 12:59 AM
> > To: Yang, Libin
> > Cc: libin.y...@linux.intel.com; intel-gfx@lists.freedesktop.org;
> > jani.nik...@linux.intel.com; Vetter, Daniel ;
> > ti...@suse.de
> > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> >
> > On Tue, Aug 02, 2016 at 01:58:51PM +, Yang, Libin wrote:
> > > Hi Ville
> > >
> > > > -Original Message-
> > > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > > Sent: Tuesday, August 2, 2016 6:47 PM
> > > > To: libin.y...@linux.intel.com
> > > > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> > > > Vetter, Daniel ; ti...@suse.de; Yang, Libin
> > > >
> > > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > > >
> > > > On Tue, Aug 02, 2016 at 09:35:10AM +0800, libin.y...@linux.intel.com
> > wrote:
> > > > > From: Libin Yang
> > > > >
> > > > > When modeset occurs and the LS_CLK is set to some special values
> > > > > in DP mode, the N/M need to be set manually if audio is playing.
> > > > >
> > > > > The relationship of Maud and Naud is expressed in the following
> > > > > equation:
> > > > > Maud/Naud = 512 * fs / f_LS_Clk
> > > > >
> > > > > Please refer VESA DisplayPort Standard spec for details.
> > > > >
> > > > > Also, the patch applies
> > > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to
> > > > > APL platform.
> > > > >
> > > > > Signed-off-by: Libin Yang
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > > > +++--
> > > > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -7351,6 +7351,12 @@ enum {
> > > > > #define _HSW_AUD_CONFIG_B0x65100
> > > > > #define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe,
> > > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > > >
> > > > > +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> > > > > +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> > > > > +#define HSW_AUD_M_CTS_ENABLE(pipe)
> > _MMIO_PIPE(pipe,
> > > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > > +#define AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> > > > > +#define AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> > > > > +
> > > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > > #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> > > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > > index 6700a7b..de55ecf 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > > @@ -98,6 +98,22 @@ static const struct {
> > > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > > >
> > > > > +#define LC_540M 54
> > > > > +#define LC_162M 162000
> > > >
> > > > Do we have some explanation why 2.7 doesn't need M/N programming,
> > > > but
> > > > 1.62 and 5.4 do?
> > >
> > > I didn't use 2.7 because I can't find a mode using 2.7.
> >
> > Hmm. Maybe we should add some knobs to force a specific bpc/link
> > rate/number of lanes to help with this kind of testing. Currently you just
> > get
> > what you get, which isn't so nice when you want to test all variations.
> > ...
> > OK, so I just went ahead and did that. Here's a branch:
> >
> > git://github.com/vsyrjala/linux.git modparam_clock_bpp_limit
> >
> > For your DP testing just setting
> > i915.max_port_clock=162000 or i915.max_port_clock=27 and then
> > forcing a modeset should do the trick.
>
> Thanks for the new branch. It seems download is very slow, less than
> 10Kib/s.
github that slow for you? Weird.
And I can't see a way to grab the raw patches from the github web
interface :( so I've attached the patches to this mail in case you
can't finish the git fetch in reasonable time.
> So I will submit the new patches firstly and then do the test.
> Fortunately, I found there is recommended data for 340MHz in the spec.
340 MHz? There's no such link rate for DP. I'm not sure what you're
saying here...
> I copied the data to the patch and suppose the data should be accurate.
>
> >
> > > So I can't do the test.
> > > 5.4 is for 4K and 1.62 is for 1080p.
> > >
> > > >
> > > > And I see you're only doing this on HSW+. Earlier platforms don't need
> > > > this?
> > >
> > > We are not supporting earlier platforms and I'm not sure whether the
> > > old platforms supports 4K DP or not.
> >
> > SNB-IVB dot
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi Ville,
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, August 4, 2016 1:39 PM
> To: Yang, Libin
> Cc: 'libin.y...@linux.intel.com' ; 'intel-
> g...@lists.freedesktop.org' ;
> 'jani.nik...@linux.intel.com' ; Vetter, Daniel
> ; 'ti...@suse.de'
> Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
>
> On Thu, Aug 04, 2016 at 02:48:54AM +, Yang, Libin wrote:
> > Hi Ville,
> >
> > > -Original Message-
> > > From: Yang, Libin
> > > Sent: Tuesday, August 2, 2016 9:59 PM
> > > To: Ville Syrjälä ;
> > > libin.y...@linux.intel.com
> > > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> > > Vetter, Daniel ; ti...@suse.de
> > > Subject: RE: [PATCH] drm/i915: set proper N/M in modeset
> > >
> > > Hi Ville
> > >
> > > > -Original Message-
> > > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > > Sent: Tuesday, August 2, 2016 6:47 PM
> > > > To: libin.y...@linux.intel.com
> > > > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> > > > Vetter, Daniel ; ti...@suse.de; Yang,
> > > > Libin
> > > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > > >
> > > > On Tue, Aug 02, 2016 at 09:35:10AM +0800,
> > > > libin.y...@linux.intel.com
> > > wrote:
> > > > > From: Libin Yang
> > > > >
> > > > > When modeset occurs and the LS_CLK is set to some special values
> > > > > in DP mode, the N/M need to be set manually if audio is playing.
> > > > >
> > > > > The relationship of Maud and Naud is expressed in the following
> > > > > equation:
> > > > > Maud/Naud = 512 * fs / f_LS_Clk
> > > > >
> > > > > Please refer VESA DisplayPort Standard spec for details.
> > > > >
> > > > > Also, the patch applies
> > > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to
> > > > > APL platform.
> > > > >
> > > > > Signed-off-by: Libin Yang
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > > > +++--
> > > > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -7351,6 +7351,12 @@ enum {
> > > > > #define _HSW_AUD_CONFIG_B0x65100
> > > > > #define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe,
> > > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > > >
> > > > > +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> > > > > +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> > > > > +#define HSW_AUD_M_CTS_ENABLE(pipe)
> _MMIO_PIPE(pipe,
> > > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > > +#define AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> > > > > +#define AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> > > > > +
> > > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > > #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> > > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > > index 6700a7b..de55ecf 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > > @@ -98,6 +98,22 @@ static const struct {
> > > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > > >
> > > > > +#define LC_540M 54
> > > > > +#define LC_162M 162000
> > > >
> > > > Do we have some explanation why 2.7 doesn't need M/N programming,
> > > > but
> > > > 1.62 and 5.4 do?
> > >
> > > I didn't use 2.7 because I can't find a mode using 2.7. So I can't do the
> > > test.
> > > 5.4 is for 4K and 1.62 is for 1080p.
> > >
> > > >
> > > > And I see you're only doing this on HSW+. Earlier platforms don't need
> this?
> > >
> > > We are not supporting earlier platforms and I'm not sure whether the
> > > old platforms supports 4K DP or not.
> > >
> > > >
> > > > > +static const struct {
> > > > > + int sample_rate;
> > > > > + int clock;
> > > > > + int n;
> > > > > + int m;
> > > >
> > > > Can save a bit of space by using u16 for m and n.
> > >
> > > OK, I will do it in next version.
> > >
> > > >
> > > > > +} aud_nm[] = {
> > > > > + {48000, LC_540M, 5625, 256},`
> > > > > + {44100, LC_540M, 9375, 392},
> > > > > + {32000, LC_540M, 16875, 512},
> > > > > + {48000, LC_162M, 3375, 512},
> > > > > + {44100, LC_162M, 5625, 784},
> > > > > + {32000, LC_162M, 10125, 1024
> > > > > +};
> > > >
> > > > The numbers look good, but what about other sample rates? For HDMI
> > > > we go up to 192kHz, why not for DP?
> > >
> > > Our test only includes 32K, 44.1K and 48K :) I will add the support
> > > if you think we should.
> >
> > I will not add 192KHz, 96KHz and
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi Ville,
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Wednesday, August 3, 2016 12:59 AM
> To: Yang, Libin
> Cc: libin.y...@linux.intel.com; intel-gfx@lists.freedesktop.org;
> jani.nik...@linux.intel.com; Vetter, Daniel ;
> ti...@suse.de
> Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
>
> On Tue, Aug 02, 2016 at 01:58:51PM +, Yang, Libin wrote:
> > Hi Ville
> >
> > > -Original Message-
> > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > Sent: Tuesday, August 2, 2016 6:47 PM
> > > To: libin.y...@linux.intel.com
> > > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> > > Vetter, Daniel ; ti...@suse.de; Yang, Libin
> > >
> > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > >
> > > On Tue, Aug 02, 2016 at 09:35:10AM +0800, libin.y...@linux.intel.com
> wrote:
> > > > From: Libin Yang
> > > >
> > > > When modeset occurs and the LS_CLK is set to some special values
> > > > in DP mode, the N/M need to be set manually if audio is playing.
> > > >
> > > > The relationship of Maud and Naud is expressed in the following
> > > > equation:
> > > > Maud/Naud = 512 * fs / f_LS_Clk
> > > >
> > > > Please refer VESA DisplayPort Standard spec for details.
> > > >
> > > > Also, the patch applies
> > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to
> > > > APL platform.
> > > >
> > > > Signed-off-by: Libin Yang
> > > > ---
> > > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > > +++--
> > > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7351,6 +7351,12 @@ enum {
> > > > #define _HSW_AUD_CONFIG_B 0x65100
> > > > #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe,
> > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > >
> > > > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > > > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > > > +#define HSW_AUD_M_CTS_ENABLE(pipe)
> _MMIO_PIPE(pipe,
> > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
> > > > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
> > > > +
> > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > index 6700a7b..de55ecf 100644
> > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > @@ -98,6 +98,22 @@ static const struct {
> > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > >
> > > > +#define LC_540M 54
> > > > +#define LC_162M 162000
> > >
> > > Do we have some explanation why 2.7 doesn't need M/N programming,
> > > but
> > > 1.62 and 5.4 do?
> >
> > I didn't use 2.7 because I can't find a mode using 2.7.
>
> Hmm. Maybe we should add some knobs to force a specific bpc/link
> rate/number of lanes to help with this kind of testing. Currently you just get
> what you get, which isn't so nice when you want to test all variations.
> ...
> OK, so I just went ahead and did that. Here's a branch:
>
> git://github.com/vsyrjala/linux.git modparam_clock_bpp_limit
>
> For your DP testing just setting
> i915.max_port_clock=162000 or i915.max_port_clock=27 and then
> forcing a modeset should do the trick.
Thanks for the new branch. It seems download is very slow, less than
10Kib/s. So I will submit the new patches firstly and then do the test.
Fortunately, I found there is recommended data for 340MHz in the spec.
I copied the data to the patch and suppose the data should be accurate.
>
> > So I can't do the test.
> > 5.4 is for 4K and 1.62 is for 1080p.
> >
> > >
> > > And I see you're only doing this on HSW+. Earlier platforms don't need
> > > this?
> >
> > We are not supporting earlier platforms and I'm not sure whether the
> > old platforms supports 4K DP or not.
>
> SNB-IVB dotclock can go up to 360Mhz, ILK up to 405 Mhz. At least in theory.
> The DP link is limited to 4 x 2.7 for all. From the those the dotclock limit
> is the
> one you should hit first since DP can always fall back to 6bpc and that should
> be correspond to a dotclock of 480 MHz.
> Anyways, 360MHz is plenty for 4k@30.
>
>
> The question really is why we need to do this in the first place.
> There's nothing in the spec telling is it's really required. All I can find
> in the DP
> spec is "Maud value is set to 2^15 (=32,768) when the audio clock is
> asynchronous to the
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
On Thu, Aug 04, 2016 at 02:48:54AM +, Yang, Libin wrote:
> Hi Ville,
>
> > -Original Message-
> > From: Yang, Libin
> > Sent: Tuesday, August 2, 2016 9:59 PM
> > To: Ville Syrjälä ;
> > libin.y...@linux.intel.com
> > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com; Vetter,
> > Daniel
> > ; ti...@suse.de
> > Subject: RE: [PATCH] drm/i915: set proper N/M in modeset
> >
> > Hi Ville
> >
> > > -Original Message-
> > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > Sent: Tuesday, August 2, 2016 6:47 PM
> > > To: libin.y...@linux.intel.com
> > > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> > > Vetter, Daniel ; ti...@suse.de; Yang, Libin
> > >
> > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > >
> > > On Tue, Aug 02, 2016 at 09:35:10AM +0800, libin.y...@linux.intel.com
> > wrote:
> > > > From: Libin Yang
> > > >
> > > > When modeset occurs and the LS_CLK is set to some special values in
> > > > DP mode, the N/M need to be set manually if audio is playing.
> > > >
> > > > The relationship of Maud and Naud is expressed in the following
> > > > equation:
> > > > Maud/Naud = 512 * fs / f_LS_Clk
> > > >
> > > > Please refer VESA DisplayPort Standard spec for details.
> > > >
> > > > Also, the patch applies
> > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to APL
> > > > platform.
> > > >
> > > > Signed-off-by: Libin Yang
> > > > ---
> > > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > > +++--
> > > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7351,6 +7351,12 @@ enum {
> > > > #define _HSW_AUD_CONFIG_B 0x65100
> > > > #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe,
> > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > >
> > > > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > > > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > > > +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
> > > > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
> > > > +
> > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > index 6700a7b..de55ecf 100644
> > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > @@ -98,6 +98,22 @@ static const struct {
> > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > >
> > > > +#define LC_540M 54
> > > > +#define LC_162M 162000
> > >
> > > Do we have some explanation why 2.7 doesn't need M/N programming, but
> > > 1.62 and 5.4 do?
> >
> > I didn't use 2.7 because I can't find a mode using 2.7. So I can't do the
> > test.
> > 5.4 is for 4K and 1.62 is for 1080p.
> >
> > >
> > > And I see you're only doing this on HSW+. Earlier platforms don't need
> > > this?
> >
> > We are not supporting earlier platforms and I'm not sure whether the old
> > platforms supports 4K DP or not.
> >
> > >
> > > > +static const struct {
> > > > + int sample_rate;
> > > > + int clock;
> > > > + int n;
> > > > + int m;
> > >
> > > Can save a bit of space by using u16 for m and n.
> >
> > OK, I will do it in next version.
> >
> > >
> > > > +} aud_nm[] = {
> > > > + {48000, LC_540M, 5625, 256},`
> > > > + {44100, LC_540M, 9375, 392},
> > > > + {32000, LC_540M, 16875, 512},
> > > > + {48000, LC_162M, 3375, 512},
> > > > + {44100, LC_162M, 5625, 784},
> > > > + {32000, LC_162M, 10125, 1024
> > > > +};
> > >
> > > The numbers look good, but what about other sample rates? For HDMI we
> > > go up to 192kHz, why not for DP?
> >
> > Our test only includes 32K, 44.1K and 48K :) I will add the support if you
> > think
> > we should.
>
> I will not add 192KHz, 96KHz and etc rate support as based on my test
> these rate will be not used in DP. It will be converted to 48KHz.
How about basing that decision on what's actually allowed by the driver?
I can do 96kHz DP audio on my HSW just fine here. So clearly if the
display supports it, there is nothing on the ALSA side that would prevent
it from being used.
>
> >
> > >
> > > > +
> > > > /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32
> > > > audio_config_hdmi_pixel_clock(const struct drm_display_mode
> > > > *adjusted_mode) { @@ -121,20 +137,
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi Ville,
> -Original Message-
> From: Yang, Libin
> Sent: Tuesday, August 2, 2016 9:59 PM
> To: Ville Syrjälä ; libin.y...@linux.intel.com
> Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com; Vetter,
> Daniel
> ; ti...@suse.de
> Subject: RE: [PATCH] drm/i915: set proper N/M in modeset
>
> Hi Ville
>
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Tuesday, August 2, 2016 6:47 PM
> > To: libin.y...@linux.intel.com
> > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> > Vetter, Daniel ; ti...@suse.de; Yang, Libin
> >
> > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> >
> > On Tue, Aug 02, 2016 at 09:35:10AM +0800, libin.y...@linux.intel.com
> wrote:
> > > From: Libin Yang
> > >
> > > When modeset occurs and the LS_CLK is set to some special values in
> > > DP mode, the N/M need to be set manually if audio is playing.
> > >
> > > The relationship of Maud and Naud is expressed in the following
> > > equation:
> > > Maud/Naud = 512 * fs / f_LS_Clk
> > >
> > > Please refer VESA DisplayPort Standard spec for details.
> > >
> > > Also, the patch applies
> > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to APL
> > > platform.
> > >
> > > Signed-off-by: Libin Yang
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > +++--
> > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7351,6 +7351,12 @@ enum {
> > > #define _HSW_AUD_CONFIG_B0x65100
> > > #define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe,
> > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > >
> > > +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> > > +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> > > +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > +#define AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> > > +#define AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> > > +
> > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > b/drivers/gpu/drm/i915/intel_audio.c
> > > index 6700a7b..de55ecf 100644
> > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > @@ -98,6 +98,22 @@ static const struct {
> > > { 192000, TMDS_297M, 20480, 247500 }, };
> > >
> > > +#define LC_540M 54
> > > +#define LC_162M 162000
> >
> > Do we have some explanation why 2.7 doesn't need M/N programming, but
> > 1.62 and 5.4 do?
>
> I didn't use 2.7 because I can't find a mode using 2.7. So I can't do the
> test.
> 5.4 is for 4K and 1.62 is for 1080p.
>
> >
> > And I see you're only doing this on HSW+. Earlier platforms don't need this?
>
> We are not supporting earlier platforms and I'm not sure whether the old
> platforms supports 4K DP or not.
>
> >
> > > +static const struct {
> > > + int sample_rate;
> > > + int clock;
> > > + int n;
> > > + int m;
> >
> > Can save a bit of space by using u16 for m and n.
>
> OK, I will do it in next version.
>
> >
> > > +} aud_nm[] = {
> > > + {48000, LC_540M, 5625, 256},`
> > > + {44100, LC_540M, 9375, 392},
> > > + {32000, LC_540M, 16875, 512},
> > > + {48000, LC_162M, 3375, 512},
> > > + {44100, LC_162M, 5625, 784},
> > > + {32000, LC_162M, 10125, 1024
> > > +};
> >
> > The numbers look good, but what about other sample rates? For HDMI we
> > go up to 192kHz, why not for DP?
>
> Our test only includes 32K, 44.1K and 48K :) I will add the support if you
> think
> we should.
I will not add 192KHz, 96KHz and etc rate support as based on my test
these rate will be not used in DP. It will be converted to 48KHz.
>
> >
> > > +
> > > /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32
> > > audio_config_hdmi_pixel_clock(const struct drm_display_mode
> > > *adjusted_mode) { @@ -121,20 +137,50 @@ static u32
> > > audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted
> > > return hdmi_audio_clock[i].config; }
> > >
> > > -static int audio_config_get_n(const struct drm_display_mode *mode,
> > > int rate)
> > > +static int audio_config_get_n(struct intel_crtc *crtc,
> > > + const struct drm_display_mode *adjusted_mode,
> > > + int rate)
> > > +{
> > > + int i;
> > > +
> > > + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> > > + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> > > + if ((rate == aud_ncts[i].sample_rate
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
On Tue, Aug 02, 2016 at 01:58:51PM +, Yang, Libin wrote:
> Hi Ville
>
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Tuesday, August 2, 2016 6:47 PM
> > To: libin.y...@linux.intel.com
> > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com; Vetter,
> > Daniel
> > ; ti...@suse.de; Yang, Libin
> > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> >
> > On Tue, Aug 02, 2016 at 09:35:10AM +0800, libin.y...@linux.intel.com wrote:
> > > From: Libin Yang
> > >
> > > When modeset occurs and the LS_CLK is set to some special values in DP
> > > mode, the N/M need to be set manually if audio is playing.
> > >
> > > The relationship of Maud and Naud is expressed in the following
> > > equation:
> > > Maud/Naud = 512 * fs / f_LS_Clk
> > >
> > > Please refer VESA DisplayPort Standard spec for details.
> > >
> > > Also, the patch applies
> > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to APL
> > > platform.
> > >
> > > Signed-off-by: Libin Yang
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > drivers/gpu/drm/i915/intel_audio.c | 122
> > > +++--
> > > 2 files changed, 111 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7351,6 +7351,12 @@ enum {
> > > #define _HSW_AUD_CONFIG_B0x65100
> > > #define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe,
> > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > >
> > > +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> > > +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> > > +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > +#define AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> > > +#define AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> > > +
> > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > b/drivers/gpu/drm/i915/intel_audio.c
> > > index 6700a7b..de55ecf 100644
> > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > @@ -98,6 +98,22 @@ static const struct {
> > > { 192000, TMDS_297M, 20480, 247500 }, };
> > >
> > > +#define LC_540M 54
> > > +#define LC_162M 162000
> >
> > Do we have some explanation why 2.7 doesn't need M/N programming, but
> > 1.62 and 5.4 do?
>
> I didn't use 2.7 because I can't find a mode using 2.7.
Hmm. Maybe we should add some knobs to force a specific bpc/link rate/number
of lanes to help with this kind of testing. Currently you just get what
you get, which isn't so nice when you want to test all variations.
...
OK, so I just went ahead and did that. Here's a branch:
git://github.com/vsyrjala/linux.git modparam_clock_bpp_limit
For your DP testing just setting
i915.max_port_clock=162000 or i915.max_port_clock=27 and then
forcing a modeset should do the trick.
> So I can't do the test.
> 5.4 is for 4K and 1.62 is for 1080p.
>
> >
> > And I see you're only doing this on HSW+. Earlier platforms don't need this?
>
> We are not supporting earlier platforms and I'm not sure whether the
> old platforms supports 4K DP or not.
SNB-IVB dotclock can go up to 360Mhz, ILK up to 405 Mhz. At least in
theory. The DP link is limited to 4 x 2.7 for all. From the those the
dotclock limit is the one you should hit first since DP can always fall
back to 6bpc and that should be correspond to a dotclock of 480 MHz.
Anyways, 360MHz is plenty for 4k@30.
The question really is why we need to do this in the first place.
There's nothing in the spec telling is it's really required. All I can
find in the DP spec is "Maud value is set to 2^15 (=32,768) when the
audio clock is asynchronous to the LS_Clk.", and then
Thinking about it a bit more, on HSW+ we do drive DP ports with the
LCPLL, which is also reponsible for cdclk, and there are some vague
hints that audio may be clocked via cdclk. So if the DDI clock and the
audio clock are coming from the same reference, I suppose they are
considered synchronous, which may explain why this is needed. It's all
very poorly documented though, so I can't be sure.
As for the older platforms, the clocks are even less well documented.
The audio stuff is in the PCH, which is also where the DPLLs live, but
I have no idea where any audio clocks come from.
>
> >
> > > +static const struct {
> > > + int sample_rate;
> > > + int clock;
> > > + int n;
> > > + int m;
> >
> > Can save a bit of space by using u16 for m and n.
>
> OK, I will do it in next version.
>
> >
> > > +} aud_nm[] = {
> > > + {48000, LC_5
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi Jani,
> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Tuesday, August 2, 2016 6:53 PM
> To: libin.y...@linux.intel.com; intel-gfx@lists.freedesktop.org;
> ville.syrj...@linux.intel.com; Vetter, Daniel ;
> ti...@suse.de
> Cc: Yang, Libin ; Libin Yang
>
> Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
>
> On Tue, 02 Aug 2016, libin.y...@linux.intel.com wrote:
> > From: Libin Yang
> >
> > When modeset occurs and the LS_CLK is set to some special values in DP
> > mode, the N/M need to be set manually if audio is playing.
> >
> > The relationship of Maud and Naud is expressed in the following
> > equation:
> > Maud/Naud = 512 * fs / f_LS_Clk
> >
> > Please refer VESA DisplayPort Standard spec for details.
> >
> > Also, the patch applies
> > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to APL
> > platform.
>
> Whenever a commit message says "also", it makes me think the patch should
> probably be split to several patches. And that is certainly true here.
I will split the patch in next version.
Regards,
Libin
>
>
> --
> Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi Ville
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Tuesday, August 2, 2016 6:47 PM
> To: libin.y...@linux.intel.com
> Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com; Vetter,
> Daniel
> ; ti...@suse.de; Yang, Libin
> Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
>
> On Tue, Aug 02, 2016 at 09:35:10AM +0800, libin.y...@linux.intel.com wrote:
> > From: Libin Yang
> >
> > When modeset occurs and the LS_CLK is set to some special values in DP
> > mode, the N/M need to be set manually if audio is playing.
> >
> > The relationship of Maud and Naud is expressed in the following
> > equation:
> > Maud/Naud = 512 * fs / f_LS_Clk
> >
> > Please refer VESA DisplayPort Standard spec for details.
> >
> > Also, the patch applies
> > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to APL
> > platform.
> >
> > Signed-off-by: Libin Yang
> > ---
> > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > drivers/gpu/drm/i915/intel_audio.c | 122
> > +++--
> > 2 files changed, 111 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7351,6 +7351,12 @@ enum {
> > #define _HSW_AUD_CONFIG_B 0x65100
> > #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> >
> > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
> > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
> > +
> > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index 6700a7b..de55ecf 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -98,6 +98,22 @@ static const struct {
> > { 192000, TMDS_297M, 20480, 247500 }, };
> >
> > +#define LC_540M 54
> > +#define LC_162M 162000
>
> Do we have some explanation why 2.7 doesn't need M/N programming, but
> 1.62 and 5.4 do?
I didn't use 2.7 because I can't find a mode using 2.7. So I can't do the test.
5.4 is for 4K and 1.62 is for 1080p.
>
> And I see you're only doing this on HSW+. Earlier platforms don't need this?
We are not supporting earlier platforms and I'm not sure whether the
old platforms supports 4K DP or not.
>
> > +static const struct {
> > + int sample_rate;
> > + int clock;
> > + int n;
> > + int m;
>
> Can save a bit of space by using u16 for m and n.
OK, I will do it in next version.
>
> > +} aud_nm[] = {
> > + {48000, LC_540M, 5625, 256},`
> > + {44100, LC_540M, 9375, 392},
> > + {32000, LC_540M, 16875, 512},
> > + {48000, LC_162M, 3375, 512},
> > + {44100, LC_162M, 5625, 784},
> > + {32000, LC_162M, 10125, 1024
> > +};
>
> The numbers look good, but what about other sample rates? For HDMI we go
> up to 192kHz, why not for DP?
Our test only includes 32K, 44.1K and 48K :)
I will add the support if you think we should.
>
> > +
> > /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32
> > audio_config_hdmi_pixel_clock(const struct drm_display_mode
> > *adjusted_mode) { @@ -121,20 +137,50 @@ static u32
> > audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted
> > return hdmi_audio_clock[i].config;
> > }
> >
> > -static int audio_config_get_n(const struct drm_display_mode *mode,
> > int rate)
> > +static int audio_config_get_n(struct intel_crtc *crtc,
> > + const struct drm_display_mode *adjusted_mode,
> > + int rate)
> > +{
> > + int i;
> > +
> > + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> > + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> > + if ((rate == aud_ncts[i].sample_rate) &&
> > + (adjusted_mode->clock == aud_ncts[i].clock)) {
> > + return aud_ncts[i].n;
> > + }
> > + }
> > + }
> > +
> > + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> > + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> > + if ((rate == aud_nm[i].sample_rate) &&
> > + (crtc->config->port_clock == aud_nm[i].clock))
> {
> > + return aud_nm[i].n;
> > + }
> > + }
> > + }
> > + return 0;
> > +}
> > +
> > +static int audio_config_get_m(struct intel_crtc *crtc, int rate)
>
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
On Tue, 02 Aug 2016, libin.y...@linux.intel.com wrote:
> From: Libin Yang
>
> When modeset occurs and the LS_CLK is set to some
> special values in DP mode, the N/M need to be set
> manually if audio is playing.
>
> The relationship of Maud and Naud is expressed in
> the following equation:
> Maud/Naud = 512 * fs / f_LS_Clk
>
> Please refer VESA DisplayPort Standard spec for details.
>
> Also, the patch applies
> commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset")
> to APL platform.
Whenever a commit message says "also", it makes me think the patch
should probably be split to several patches. And that is certainly true
here.
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
On Tue, Aug 02, 2016 at 09:35:10AM +0800, libin.y...@linux.intel.com wrote:
> From: Libin Yang
>
> When modeset occurs and the LS_CLK is set to some
> special values in DP mode, the N/M need to be set
> manually if audio is playing.
>
> The relationship of Maud and Naud is expressed in
> the following equation:
> Maud/Naud = 512 * fs / f_LS_Clk
>
> Please refer VESA DisplayPort Standard spec for details.
>
> Also, the patch applies
> commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset")
> to APL platform.
>
> Signed-off-by: Libin Yang
> ---
> drivers/gpu/drm/i915/i915_reg.h| 6 ++
> drivers/gpu/drm/i915/intel_audio.c | 122
> +++--
> 2 files changed, 111 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8bfde75..2f9d00e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7351,6 +7351,12 @@ enum {
> #define _HSW_AUD_CONFIG_B0x65100
> #define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A,
> _HSW_AUD_CONFIG_B)
>
> +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> +#define AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> +#define AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> +
> #define _HSW_AUD_MISC_CTRL_A 0x65010
> #define _HSW_AUD_MISC_CTRL_B 0x65110
> #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index 6700a7b..de55ecf 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -98,6 +98,22 @@ static const struct {
> { 192000, TMDS_297M, 20480, 247500 },
> };
>
> +#define LC_540M 54
> +#define LC_162M 162000
Do we have some explanation why 2.7 doesn't need M/N programming,
but 1.62 and 5.4 do?
And I see you're only doing this on HSW+. Earlier platforms don't need
this?
> +static const struct {
> + int sample_rate;
> + int clock;
> + int n;
> + int m;
Can save a bit of space by using u16 for m and n.
> +} aud_nm[] = {
> + {48000, LC_540M, 5625, 256},`
> + {44100, LC_540M, 9375, 392},
> + {32000, LC_540M, 16875, 512},
> + {48000, LC_162M, 3375, 512},
> + {44100, LC_162M, 5625, 784},
> + {32000, LC_162M, 10125, 1024
> +};
The numbers look good, but what about other sample rates? For HDMI we go
up to 192kHz, why not for DP?
> +
> /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
> static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode
> *adjusted_mode)
> {
> @@ -121,20 +137,50 @@ static u32 audio_config_hdmi_pixel_clock(const struct
> drm_display_mode *adjusted
> return hdmi_audio_clock[i].config;
> }
>
> -static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
> +static int audio_config_get_n(struct intel_crtc *crtc,
> + const struct drm_display_mode *adjusted_mode,
> + int rate)
> +{
> + int i;
> +
> + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> + if ((rate == aud_ncts[i].sample_rate) &&
> + (adjusted_mode->clock == aud_ncts[i].clock)) {
> + return aud_ncts[i].n;
> + }
> + }
> + }
> +
> + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> + if ((rate == aud_nm[i].sample_rate) &&
> + (crtc->config->port_clock == aud_nm[i].clock)) {
> + return aud_nm[i].n;
> + }
> + }
> + }
> + return 0;
> +}
> +
> +static int audio_config_get_m(struct intel_crtc *crtc, int rate)
> {
> int i;
>
> - for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> - if ((rate == aud_ncts[i].sample_rate) &&
> - (mode->clock == aud_ncts[i].clock)) {
> - return aud_ncts[i].n;
> + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> + if ((rate == aud_nm[i].sample_rate) &&
> + (crtc->config->port_clock == aud_nm[i].clock)) {
> + return aud_nm[i].m;
> + }
> }
> }
> +
> return 0;
> }
>
> -static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
> +static uint32_t audio_config_setup_n_reg(struct intel_crtc *crtc,
> + int n, uint32_t val)
>
[Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
From: Libin Yang
When modeset occurs and the LS_CLK is set to some
special values in DP mode, the N/M need to be set
manually if audio is playing.
The relationship of Maud and Naud is expressed in
the following equation:
Maud/Naud = 512 * fs / f_LS_Clk
Please refer VESA DisplayPort Standard spec for details.
Also, the patch applies
commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset")
to APL platform.
Signed-off-by: Libin Yang
---
drivers/gpu/drm/i915/i915_reg.h| 6 ++
drivers/gpu/drm/i915/intel_audio.c | 122 +++--
2 files changed, 111 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bfde75..2f9d00e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7351,6 +7351,12 @@ enum {
#define _HSW_AUD_CONFIG_B 0x65100
#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A,
_HSW_AUD_CONFIG_B)
+#define _HSW_AUD_M_CTS_ENABLE_A0x65028
+#define _HSW_AUD_M_CTS_ENABLE_B0x65128
+#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
_HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
+#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
+#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
+
#define _HSW_AUD_MISC_CTRL_A 0x65010
#define _HSW_AUD_MISC_CTRL_B 0x65110
#define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
_HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 6700a7b..de55ecf 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -98,6 +98,22 @@ static const struct {
{ 192000, TMDS_297M, 20480, 247500 },
};
+#define LC_540M 54
+#define LC_162M 162000
+static const struct {
+ int sample_rate;
+ int clock;
+ int n;
+ int m;
+} aud_nm[] = {
+ {48000, LC_540M, 5625, 256},
+ {44100, LC_540M, 9375, 392},
+ {32000, LC_540M, 16875, 512},
+ {48000, LC_162M, 3375, 512},
+ {44100, LC_162M, 5625, 784},
+ {32000, LC_162M, 10125, 1024},
+};
+
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode
*adjusted_mode)
{
@@ -121,20 +137,50 @@ static u32 audio_config_hdmi_pixel_clock(const struct
drm_display_mode *adjusted
return hdmi_audio_clock[i].config;
}
-static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
+static int audio_config_get_n(struct intel_crtc *crtc,
+ const struct drm_display_mode *adjusted_mode,
+ int rate)
+{
+ int i;
+
+ if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
+ for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
+ if ((rate == aud_ncts[i].sample_rate) &&
+ (adjusted_mode->clock == aud_ncts[i].clock)) {
+ return aud_ncts[i].n;
+ }
+ }
+ }
+
+ if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
+ for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
+ if ((rate == aud_nm[i].sample_rate) &&
+ (crtc->config->port_clock == aud_nm[i].clock)) {
+ return aud_nm[i].n;
+ }
+ }
+ }
+ return 0;
+}
+
+static int audio_config_get_m(struct intel_crtc *crtc, int rate)
{
int i;
- for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
- if ((rate == aud_ncts[i].sample_rate) &&
- (mode->clock == aud_ncts[i].clock)) {
- return aud_ncts[i].n;
+ if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
+ for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
+ if ((rate == aud_nm[i].sample_rate) &&
+ (crtc->config->port_clock == aud_nm[i].clock)) {
+ return aud_nm[i].m;
+ }
}
}
+
return 0;
}
-static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
+static uint32_t audio_config_setup_n_reg(struct intel_crtc *crtc,
+int n, uint32_t val)
{
int n_low, n_up;
uint32_t tmp = val;
@@ -145,17 +191,38 @@ static uint32_t audio_config_setup_n_reg(int n, uint32_t
val)
tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
(n_low << AUD_CONFIG_LOWER_N_SHIFT) |
AUD_CONFIG_N_PROG_ENABLE);
+ if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP))
+ tmp |= AUD_CONFIG_N_VALUE_INDEX;
+ return tmp;
+}
+
+static uint32_t audio_config_setup_m_reg(struct intel_crtc *crtc,
+
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi Ville,
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, July 29, 2016 5:47 PM
> To: Yang, Libin
> Cc: libin.y...@linux.intel.com; intel-gfx@lists.freedesktop.org;
> jani.nik...@linux.intel.com; Vetter, Daniel ;
> ti...@suse.de
> Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
>
> On Fri, Jul 29, 2016 at 05:54:23AM +, Yang, Libin wrote:
> > Hi Ville,
> >
> > > -Original Message-
> > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > Sent: Thursday, July 28, 2016 3:42 PM
> > > To: libin.y...@linux.intel.com
> > > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> > > Vetter, Daniel ; ti...@suse.de; Yang, Libin
> > >
> > > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> > >
> > > On Thu, Jul 14, 2016 at 03:06:21PM +0800, libin.y...@linux.intel.com
> wrote:
> > > > From: Libin Yang
> > > >
> > > > When modeset occurs and the LS_CLK is set to some special values
> > > > in DP mode, the N/M need to be set manually if audio is playing.
> > > >
> > > > Also, the patch applies
> > > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to
> > > > APL platform.
> > > >
> > > > Signed-off-by: Libin Yang
> > > > ---
> > > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > > drivers/gpu/drm/i915/intel_audio.c | 116
> > > > -
> > > > 2 files changed, 108 insertions(+), 14 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7351,6 +7351,12 @@ enum {
> > > > #define _HSW_AUD_CONFIG_B 0x65100
> > > > #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe,
> > > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > > >
> > > > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > > > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > > > +#define HSW_AUD_M_CTS_ENABLE(pipe)
> _MMIO_PIPE(pipe,
> > > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
> > > > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
> > > > +
> > > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > > #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> > > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > > b/drivers/gpu/drm/i915/intel_audio.c
> > > > index 6700a7b..e2e4d4b 100644
> > > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > > @@ -98,6 +98,22 @@ static const struct {
> > > > { 192000, TMDS_297M, 20480, 247500 }, };
> > > >
> > > > +#define LC_533M 533250
> > > > +#define LC_148M 148500
> > > > +static const struct {
> > > > + int sample_rate;
> > > > + int clock;
> > > > + int n;
> > > > + int m;
> > > > +} aud_nm[] = {
> > > > + {48000, LC_533M, 88875, 4096},
> > > > + {44100, LC_533M, 148125, 6272},
> > > > + {32000, LC_533M, 266625, 8192},
> > > > + {48000, LC_148M, 12375, 2048},
> > > > + {44100, LC_148M, 20625, 3136},
> > > > + {32000, LC_148M, 37125, 4096},
> > > > +};
> > > > +
> > > > /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static
> > > > u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode
> > > > *adjusted_mode) { @@ -121,20 +137,50 @@ static u32
> > > > audio_config_hdmi_pixel_clock(const struct drm_display_mode
> *adjusted
> > > > return hdmi_audio_clock[i].config; }
> > > >
> > > > -static int audio_config_get_n(const struct drm_display_mode
> > > > *mode, int rate)
> > > > +static int audio_config_get_n(struct intel_crtc *crtc,
> > > > + const struct drm_display_mode *mode, int
> > > > rate) {
> > > > + int i;
> > > > +
> > > > + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> > > > + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> > > > + if ((rate == aud_ncts[i].sample_rate) &&
> > > > + (mode->clock == aud_ncts[i].clock)) {
> > > > + return aud_ncts[i].n;
> > > > + }
> > > > + }
> > > > + }
> > > > +
> > > > + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> > > > + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> > > > + if ((rate == aud_nm[i].sample_rate) &&
> > > > + (mode->clock == aud_nm[i].clock)) {
> > >
> > > So the spec says we should have "Maud / Naud = 512 * fs / f_LS_Clk",
> > > where fs is the audio sample rate, and f_LS_CLK is the link symbol clock.
> > > With that in mind this should not be looking at mode->clock
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
On Fri, Jul 29, 2016 at 05:54:23AM +, Yang, Libin wrote:
> Hi Ville,
>
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Thursday, July 28, 2016 3:42 PM
> > To: libin.y...@linux.intel.com
> > Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com; Vetter,
> > Daniel ; ti...@suse.de; Yang, Libin
> >
> > Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
> >
> > On Thu, Jul 14, 2016 at 03:06:21PM +0800, libin.y...@linux.intel.com wrote:
> > > From: Libin Yang
> > >
> > > When modeset occurs and the LS_CLK is set to some special values in DP
> > > mode, the N/M need to be set manually if audio is playing.
> > >
> > > Also, the patch applies
> > > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to APL
> > > platform.
> > >
> > > Signed-off-by: Libin Yang
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > > drivers/gpu/drm/i915/intel_audio.c | 116
> > > -
> > > 2 files changed, 108 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7351,6 +7351,12 @@ enum {
> > > #define _HSW_AUD_CONFIG_B0x65100
> > > #define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe,
> > _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> > >
> > > +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> > > +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> > > +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > > +#define AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> > > +#define AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> > > +
> > > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > > #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > > b/drivers/gpu/drm/i915/intel_audio.c
> > > index 6700a7b..e2e4d4b 100644
> > > --- a/drivers/gpu/drm/i915/intel_audio.c
> > > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > > @@ -98,6 +98,22 @@ static const struct {
> > > { 192000, TMDS_297M, 20480, 247500 }, };
> > >
> > > +#define LC_533M 533250
> > > +#define LC_148M 148500
> > > +static const struct {
> > > + int sample_rate;
> > > + int clock;
> > > + int n;
> > > + int m;
> > > +} aud_nm[] = {
> > > + {48000, LC_533M, 88875, 4096},
> > > + {44100, LC_533M, 148125, 6272},
> > > + {32000, LC_533M, 266625, 8192},
> > > + {48000, LC_148M, 12375, 2048},
> > > + {44100, LC_148M, 20625, 3136},
> > > + {32000, LC_148M, 37125, 4096},
> > > +};
> > > +
> > > /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32
> > > audio_config_hdmi_pixel_clock(const struct drm_display_mode
> > > *adjusted_mode) { @@ -121,20 +137,50 @@ static u32
> > > audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted
> > > return hdmi_audio_clock[i].config;
> > > }
> > >
> > > -static int audio_config_get_n(const struct drm_display_mode *mode,
> > > int rate)
> > > +static int audio_config_get_n(struct intel_crtc *crtc,
> > > + const struct drm_display_mode *mode, int rate) {
> > > + int i;
> > > +
> > > + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> > > + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> > > + if ((rate == aud_ncts[i].sample_rate) &&
> > > + (mode->clock == aud_ncts[i].clock)) {
> > > + return aud_ncts[i].n;
> > > + }
> > > + }
> > > + }
> > > +
> > > + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> > > + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> > > + if ((rate == aud_nm[i].sample_rate) &&
> > > + (mode->clock == aud_nm[i].clock)) {
> >
> > So the spec says we should have "Maud / Naud = 512 * fs / f_LS_Clk", where
> > fs is the audio sample rate, and f_LS_CLK is the link symbol clock.
> > With that in mind this should not be looking at mode->clock but
> > crtc->config->port_clock.
> >
> > So I don't actually understand why you say LS_CLK has "special" values.
> > It shouldn't. It's always either 162, 270, or 540 MHz.
>
> Thanks for the correction. I will use crtc->config->port_clock.
But why do you need to do it at all? The hardware can't deal with one of
the standard link rates on its own?
>
> >
> > Actually even the HDMI case is wrong in the code, it should be looking at
> > mode->crtc_clock instead of mode->clock. Or perhaps even port_clock, if my
> > reading of the HDMI spec is correct, but I never got any sane answer from
> > any hw folks to my questions about this :(
>
> I will try mode->crtc_clock later for HDMI. Thanks.
While you're
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi Ville,
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, July 28, 2016 3:42 PM
> To: libin.y...@linux.intel.com
> Cc: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com; Vetter,
> Daniel ; ti...@suse.de; Yang, Libin
>
> Subject: Re: [PATCH] drm/i915: set proper N/M in modeset
>
> On Thu, Jul 14, 2016 at 03:06:21PM +0800, libin.y...@linux.intel.com wrote:
> > From: Libin Yang
> >
> > When modeset occurs and the LS_CLK is set to some special values in DP
> > mode, the N/M need to be set manually if audio is playing.
> >
> > Also, the patch applies
> > commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to APL
> > platform.
> >
> > Signed-off-by: Libin Yang
> > ---
> > drivers/gpu/drm/i915/i915_reg.h| 6 ++
> > drivers/gpu/drm/i915/intel_audio.c | 116
> > -
> > 2 files changed, 108 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7351,6 +7351,12 @@ enum {
> > #define _HSW_AUD_CONFIG_B 0x65100
> > #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
> >
> > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > +#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
> > +#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
> > +
> > #define _HSW_AUD_MISC_CTRL_A 0x65010
> > #define _HSW_AUD_MISC_CTRL_B 0x65110
> > #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index 6700a7b..e2e4d4b 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -98,6 +98,22 @@ static const struct {
> > { 192000, TMDS_297M, 20480, 247500 }, };
> >
> > +#define LC_533M 533250
> > +#define LC_148M 148500
> > +static const struct {
> > + int sample_rate;
> > + int clock;
> > + int n;
> > + int m;
> > +} aud_nm[] = {
> > + {48000, LC_533M, 88875, 4096},
> > + {44100, LC_533M, 148125, 6272},
> > + {32000, LC_533M, 266625, 8192},
> > + {48000, LC_148M, 12375, 2048},
> > + {44100, LC_148M, 20625, 3136},
> > + {32000, LC_148M, 37125, 4096},
> > +};
> > +
> > /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32
> > audio_config_hdmi_pixel_clock(const struct drm_display_mode
> > *adjusted_mode) { @@ -121,20 +137,50 @@ static u32
> > audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted
> > return hdmi_audio_clock[i].config;
> > }
> >
> > -static int audio_config_get_n(const struct drm_display_mode *mode,
> > int rate)
> > +static int audio_config_get_n(struct intel_crtc *crtc,
> > + const struct drm_display_mode *mode, int rate) {
> > + int i;
> > +
> > + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> > + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> > + if ((rate == aud_ncts[i].sample_rate) &&
> > + (mode->clock == aud_ncts[i].clock)) {
> > + return aud_ncts[i].n;
> > + }
> > + }
> > + }
> > +
> > + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> > + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> > + if ((rate == aud_nm[i].sample_rate) &&
> > + (mode->clock == aud_nm[i].clock)) {
>
> So the spec says we should have "Maud / Naud = 512 * fs / f_LS_Clk", where
> fs is the audio sample rate, and f_LS_CLK is the link symbol clock.
> With that in mind this should not be looking at mode->clock but
> crtc->config->port_clock.
>
> So I don't actually understand why you say LS_CLK has "special" values.
> It shouldn't. It's always either 162, 270, or 540 MHz.
Thanks for the correction. I will use crtc->config->port_clock.
>
> Actually even the HDMI case is wrong in the code, it should be looking at
> mode->crtc_clock instead of mode->clock. Or perhaps even port_clock, if my
> reading of the HDMI spec is correct, but I never got any sane answer from
> any hw folks to my questions about this :(
I will try mode->crtc_clock later for HDMI. Thanks.
Regards,
Libin
>
> > + return aud_nm[i].n;
> > + }
> > + }
> > + }
> > + return 0;
> > +}
> > +
> > +static int audio_config_get_m(struct intel_crtc *crtc,
> > + const struct drm_display_mode *mode, int rate)
> > {
> > int i;
> >
> > - for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> > -
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
On Thu, Jul 14, 2016 at 03:06:21PM +0800, libin.y...@linux.intel.com wrote:
> From: Libin Yang
>
> When modeset occurs and the LS_CLK is set to some
> special values in DP mode, the N/M need to be set
> manually if audio is playing.
>
> Also, the patch applies
> commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset")
> to APL platform.
>
> Signed-off-by: Libin Yang
> ---
> drivers/gpu/drm/i915/i915_reg.h| 6 ++
> drivers/gpu/drm/i915/intel_audio.c | 116
> -
> 2 files changed, 108 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8bfde75..2f9d00e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7351,6 +7351,12 @@ enum {
> #define _HSW_AUD_CONFIG_B0x65100
> #define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A,
> _HSW_AUD_CONFIG_B)
>
> +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> +#define AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> +#define AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> +
> #define _HSW_AUD_MISC_CTRL_A 0x65010
> #define _HSW_AUD_MISC_CTRL_B 0x65110
> #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index 6700a7b..e2e4d4b 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -98,6 +98,22 @@ static const struct {
> { 192000, TMDS_297M, 20480, 247500 },
> };
>
> +#define LC_533M 533250
> +#define LC_148M 148500
> +static const struct {
> + int sample_rate;
> + int clock;
> + int n;
> + int m;
> +} aud_nm[] = {
> + {48000, LC_533M, 88875, 4096},
> + {44100, LC_533M, 148125, 6272},
> + {32000, LC_533M, 266625, 8192},
> + {48000, LC_148M, 12375, 2048},
> + {44100, LC_148M, 20625, 3136},
> + {32000, LC_148M, 37125, 4096},
> +};
> +
> /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
> static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode
> *adjusted_mode)
> {
> @@ -121,20 +137,50 @@ static u32 audio_config_hdmi_pixel_clock(const struct
> drm_display_mode *adjusted
> return hdmi_audio_clock[i].config;
> }
>
> -static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
> +static int audio_config_get_n(struct intel_crtc *crtc,
> + const struct drm_display_mode *mode, int rate)
> +{
> + int i;
> +
> + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> + if ((rate == aud_ncts[i].sample_rate) &&
> + (mode->clock == aud_ncts[i].clock)) {
> + return aud_ncts[i].n;
> + }
> + }
> + }
> +
> + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> + if ((rate == aud_nm[i].sample_rate) &&
> + (mode->clock == aud_nm[i].clock)) {
So the spec says we should have "Maud / Naud = 512 * fs / f_LS_Clk",
where fs is the audio sample rate, and f_LS_CLK is the link symbol clock.
With that in mind this should not be looking at mode->clock but
crtc->config->port_clock.
So I don't actually understand why you say LS_CLK has "special" values.
It shouldn't. It's always either 162, 270, or 540 MHz.
Actually even the HDMI case is wrong in the code, it should be
looking at mode->crtc_clock instead of mode->clock. Or perhaps even
port_clock, if my reading of the HDMI spec is correct, but I never got
any sane answer from any hw folks to my questions about this :(
> + return aud_nm[i].n;
> + }
> + }
> + }
> + return 0;
> +}
> +
> +static int audio_config_get_m(struct intel_crtc *crtc,
> + const struct drm_display_mode *mode, int rate)
> {
> int i;
>
> - for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> - if ((rate == aud_ncts[i].sample_rate) &&
> - (mode->clock == aud_ncts[i].clock)) {
> - return aud_ncts[i].n;
> + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> + if ((rate == aud_nm[i].sample_rate) &&
> + (mode->clock == aud_nm[i].clock)) {
> + return aud_nm[i].m;
> + }
> }
> }
> +
> return 0;
> }
>
> -static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
Re: [Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
Hi all,
Is there anyone can help review this patch? This patch is set N/M for audio in
DP 4k resolution. Thanks.
I calculate these values based on the DP1.2 spec chapter 6.6 on page 469:
Maud / Naud = 512 * fs / f_LS_Clk
Regards,
Libin
> -Original Message-
> From: libin.y...@linux.intel.com [mailto:libin.y...@linux.intel.com]
> Sent: Thursday, July 14, 2016 3:06 PM
> To: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
> ville.syrj...@linux.intel.com; Vetter, Daniel ;
> ti...@suse.de
> Cc: Yang, Libin ; Libin Yang
>
> Subject: [PATCH] drm/i915: set proper N/M in modeset
>
> From: Libin Yang
>
> When modeset occurs and the LS_CLK is set to some special values in DP
> mode, the N/M need to be set manually if audio is playing.
>
> Also, the patch applies
> commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset") to APL
> platform.
>
> Signed-off-by: Libin Yang
> ---
> drivers/gpu/drm/i915/i915_reg.h| 6 ++
> drivers/gpu/drm/i915/intel_audio.c | 116
> -
> 2 files changed, 108 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 8bfde75..2f9d00e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7351,6 +7351,12 @@ enum {
> #define _HSW_AUD_CONFIG_B0x65100
> #define HSW_AUD_CFG(pipe)_MMIO_PIPE(pipe,
> _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
>
> +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> +#define AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> +#define AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> +
> #define _HSW_AUD_MISC_CTRL_A 0x65010
> #define _HSW_AUD_MISC_CTRL_B 0x65110
> #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index 6700a7b..e2e4d4b 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -98,6 +98,22 @@ static const struct {
> { 192000, TMDS_297M, 20480, 247500 },
> };
>
> +#define LC_533M 533250
> +#define LC_148M 148500
> +static const struct {
> + int sample_rate;
> + int clock;
> + int n;
> + int m;
> +} aud_nm[] = {
> + {48000, LC_533M, 88875, 4096},
> + {44100, LC_533M, 148125, 6272},
> + {32000, LC_533M, 266625, 8192},
> + {48000, LC_148M, 12375, 2048},
> + {44100, LC_148M, 20625, 3136},
> + {32000, LC_148M, 37125, 4096},
> +};
> +
> /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32
> audio_config_hdmi_pixel_clock(const struct drm_display_mode
> *adjusted_mode) { @@ -121,20 +137,50 @@ static u32
> audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted
> return hdmi_audio_clock[i].config;
> }
>
> -static int audio_config_get_n(const struct drm_display_mode *mode, int
> rate)
> +static int audio_config_get_n(struct intel_crtc *crtc,
> + const struct drm_display_mode *mode, int rate) {
> + int i;
> +
> + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> + if ((rate == aud_ncts[i].sample_rate) &&
> + (mode->clock == aud_ncts[i].clock)) {
> + return aud_ncts[i].n;
> + }
> + }
> + }
> +
> + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> + if ((rate == aud_nm[i].sample_rate) &&
> + (mode->clock == aud_nm[i].clock)) {
> + return aud_nm[i].n;
> + }
> + }
> + }
> + return 0;
> +}
> +
> +static int audio_config_get_m(struct intel_crtc *crtc,
> + const struct drm_display_mode *mode, int rate)
> {
> int i;
>
> - for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> - if ((rate == aud_ncts[i].sample_rate) &&
> - (mode->clock == aud_ncts[i].clock)) {
> - return aud_ncts[i].n;
> + if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
> + for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
> + if ((rate == aud_nm[i].sample_rate) &&
> + (mode->clock == aud_nm[i].clock)) {
> + return aud_nm[i].m;
> + }
> }
> }
> +
> return 0;
> }
>
> -static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
> +static uint32_t audio_config_setup_n_reg(struct intel_crtc *crtc,
> + int n,
[Intel-gfx] [PATCH] drm/i915: set proper N/M in modeset
From: Libin Yang
When modeset occurs and the LS_CLK is set to some
special values in DP mode, the N/M need to be set
manually if audio is playing.
Also, the patch applies
commit 7e8275c2f2bb ("drm/i915: set proper N/CTS in modeset")
to APL platform.
Signed-off-by: Libin Yang
---
drivers/gpu/drm/i915/i915_reg.h| 6 ++
drivers/gpu/drm/i915/intel_audio.c | 116 -
2 files changed, 108 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bfde75..2f9d00e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7351,6 +7351,12 @@ enum {
#define _HSW_AUD_CONFIG_B 0x65100
#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A,
_HSW_AUD_CONFIG_B)
+#define _HSW_AUD_M_CTS_ENABLE_A0x65028
+#define _HSW_AUD_M_CTS_ENABLE_B0x65128
+#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
_HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
+#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
+#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
+
#define _HSW_AUD_MISC_CTRL_A 0x65010
#define _HSW_AUD_MISC_CTRL_B 0x65110
#define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
_HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 6700a7b..e2e4d4b 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -98,6 +98,22 @@ static const struct {
{ 192000, TMDS_297M, 20480, 247500 },
};
+#define LC_533M 533250
+#define LC_148M 148500
+static const struct {
+ int sample_rate;
+ int clock;
+ int n;
+ int m;
+} aud_nm[] = {
+ {48000, LC_533M, 88875, 4096},
+ {44100, LC_533M, 148125, 6272},
+ {32000, LC_533M, 266625, 8192},
+ {48000, LC_148M, 12375, 2048},
+ {44100, LC_148M, 20625, 3136},
+ {32000, LC_148M, 37125, 4096},
+};
+
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode
*adjusted_mode)
{
@@ -121,20 +137,50 @@ static u32 audio_config_hdmi_pixel_clock(const struct
drm_display_mode *adjusted
return hdmi_audio_clock[i].config;
}
-static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
+static int audio_config_get_n(struct intel_crtc *crtc,
+ const struct drm_display_mode *mode, int rate)
+{
+ int i;
+
+ if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
+ for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
+ if ((rate == aud_ncts[i].sample_rate) &&
+ (mode->clock == aud_ncts[i].clock)) {
+ return aud_ncts[i].n;
+ }
+ }
+ }
+
+ if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
+ for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
+ if ((rate == aud_nm[i].sample_rate) &&
+ (mode->clock == aud_nm[i].clock)) {
+ return aud_nm[i].n;
+ }
+ }
+ }
+ return 0;
+}
+
+static int audio_config_get_m(struct intel_crtc *crtc,
+ const struct drm_display_mode *mode, int rate)
{
int i;
- for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
- if ((rate == aud_ncts[i].sample_rate) &&
- (mode->clock == aud_ncts[i].clock)) {
- return aud_ncts[i].n;
+ if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP)) {
+ for (i = 0; i < ARRAY_SIZE(aud_nm); i++) {
+ if ((rate == aud_nm[i].sample_rate) &&
+ (mode->clock == aud_nm[i].clock)) {
+ return aud_nm[i].m;
+ }
}
}
+
return 0;
}
-static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
+static uint32_t audio_config_setup_n_reg(struct intel_crtc *crtc,
+int n, uint32_t val)
{
int n_low, n_up;
uint32_t tmp = val;
@@ -145,6 +191,23 @@ static uint32_t audio_config_setup_n_reg(int n, uint32_t
val)
tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
(n_low << AUD_CONFIG_LOWER_N_SHIFT) |
AUD_CONFIG_N_PROG_ENABLE);
+ if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP))
+ tmp |= AUD_CONFIG_N_VALUE_INDEX;
+ return tmp;
+}
+
+static uint32_t audio_config_setup_m_reg(struct intel_crtc *crtc,
+int m, uint32_t val)
+{
+ uint32_t tmp = val;
+
+ if (!intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DP))
+ return 0;
+
+
