Re: [Intel-gfx] [PATCH 01/11] drm/i915: Fix display pixel format handling
On Thu, 1 Nov 2012 16:03:13 +0200, Ville Syrjälä wrote: > On Wed, Oct 31, 2012 at 01:20:23PM -0700, Jesse Barnes wrote: > > On Wed, 31 Oct 2012 17:50:14 +0200 > > ville.syrj...@linux.intel.com wrote: > > > > > From: Ville Syrjälä > > > > > > Fix support for all RGB/BGR pixel formats (except the 16:16:16:16 float > > > format). > > > > > > Fix intel_init_framebuffer() to match hardware and driver limitations: > > > * RGB332 is not supported at all > > > * CI8 is supported > > > * XRGB1555 & co. are supported on Gen3 and earlier > > > * XRGB210101010 & co. are supported from Gen4 onwards > > > * BGR formats are supported from Gen4 onwards > > > * YUV formats are supported from Gen5 onwards (driver limitation) > > > > Yeah looks nice. I love how our definitions have the component order > > reversed relative to the fourcc-ish codes. > > Yeah. I just copied the names more or less blindly from the spec. I > usually prefer to keep register definitons and specs in sync, since > it makes it easier to search for stuff in the spec. But if people > are bothered by this mess, I won't object to changing the defns to > match the fourcc stuff. We have the same issue in userspace, where we follow the spec counter to the common convention. It is just one of those things you get used to. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/11] drm/i915: Fix display pixel format handling
On Wed, Oct 31, 2012 at 01:20:23PM -0700, Jesse Barnes wrote: > On Wed, 31 Oct 2012 17:50:14 +0200 > ville.syrj...@linux.intel.com wrote: > > > From: Ville Syrjälä > > > > Fix support for all RGB/BGR pixel formats (except the 16:16:16:16 float > > format). > > > > Fix intel_init_framebuffer() to match hardware and driver limitations: > > * RGB332 is not supported at all > > * CI8 is supported > > * XRGB1555 & co. are supported on Gen3 and earlier > > * XRGB210101010 & co. are supported from Gen4 onwards > > * BGR formats are supported from Gen4 onwards > > * YUV formats are supported from Gen5 onwards (driver limitation) > > Yeah looks nice. I love how our definitions have the component order > reversed relative to the fourcc-ish codes. Yeah. I just copied the names more or less blindly from the spec. I usually prefer to keep register definitons and specs in sync, since it makes it easier to search for stuff in the spec. But if people are bothered by this mess, I won't object to changing the defns to match the fourcc stuff. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/11] drm/i915: Fix display pixel format handling
On Wed, 31 Oct 2012 17:50:14 +0200 ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Fix support for all RGB/BGR pixel formats (except the 16:16:16:16 float > format). > > Fix intel_init_framebuffer() to match hardware and driver limitations: > * RGB332 is not supported at all > * CI8 is supported > * XRGB1555 & co. are supported on Gen3 and earlier > * XRGB210101010 & co. are supported from Gen4 onwards > * BGR formats are supported from Gen4 onwards > * YUV formats are supported from Gen5 onwards (driver limitation) Yeah looks nice. I love how our definitions have the component order reversed relative to the fourcc-ish codes. Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/11] drm/i915: Fix display pixel format handling
From: Ville Syrjälä
Fix support for all RGB/BGR pixel formats (except the 16:16:16:16 float
format).
Fix intel_init_framebuffer() to match hardware and driver limitations:
* RGB332 is not supported at all
* CI8 is supported
* XRGB1555 & co. are supported on Gen3 and earlier
* XRGB210101010 & co. are supported from Gen4 onwards
* BGR formats are supported from Gen4 onwards
* YUV formats are supported from Gen5 onwards (driver limitation)
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 17 --
drivers/gpu/drm/i915/intel_display.c | 98 ++
2 files changed, 76 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index be22aeb..da8400a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3008,12 +3008,19 @@
#define DISPPLANE_GAMMA_ENABLE (1<<30)
#define DISPPLANE_GAMMA_DISABLE 0
#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
+#define DISPPLANE_YUV422 (0x0<<26)
#define DISPPLANE_8BPP (0x2<<26)
-#define DISPPLANE_15_16BPP (0x4<<26)
-#define DISPPLANE_16BPP (0x5<<26)
-#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
-#define DISPPLANE_32BPP (0x7<<26)
-#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
+#define DISPPLANE_BGRA555(0x3<<26)
+#define DISPPLANE_BGRX555(0x4<<26)
+#define DISPPLANE_BGRX565(0x5<<26)
+#define DISPPLANE_BGRX888(0x6<<26)
+#define DISPPLANE_BGRA888(0x7<<26)
+#define DISPPLANE_RGBX101010 (0x8<<26)
+#define DISPPLANE_RGBA101010 (0x9<<26)
+#define DISPPLANE_BGRX101010 (0xa<<26)
+#define DISPPLANE_RGBX161616 (0xc<<26)
+#define DISPPLANE_RGBX888(0xe<<26)
+#define DISPPLANE_RGBA888(0xf<<26)
#define DISPPLANE_STEREO_ENABLE (1<<25)
#define DISPPLANE_STEREO_DISABLE 0
#define DISPPLANE_SEL_PIPE_SHIFT 24
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a5be346..6d3feea 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1998,24 +1998,38 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
dspcntr = I915_READ(reg);
/* Mask out pixel format bits in case we change it */
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
- switch (fb->bits_per_pixel) {
- case 8:
+ switch (fb->pixel_format) {
+ case DRM_FORMAT_C8:
dspcntr |= DISPPLANE_8BPP;
break;
- case 16:
- if (fb->depth == 15)
- dspcntr |= DISPPLANE_15_16BPP;
- else
- dspcntr |= DISPPLANE_16BPP;
- break;
- case 24:
- case 32:
- dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_ARGB1555:
+ dspcntr |= DISPPLANE_BGRX555;
+ break;
+ case DRM_FORMAT_RGB565:
+ dspcntr |= DISPPLANE_BGRX565;
+ break;
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_ARGB:
+ dspcntr |= DISPPLANE_BGRX888;
+ break;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ dspcntr |= DISPPLANE_RGBX888;
+ break;
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_ARGB2101010:
+ dspcntr |= DISPPLANE_BGRX101010;
+ break;
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ABGR2101010:
+ dspcntr |= DISPPLANE_RGBX101010;
break;
default:
- DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
+ DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
return -EINVAL;
}
+
if (INTEL_INFO(dev)->gen >= 4) {
if (obj->tiling_mode != I915_TILING_NONE)
dspcntr |= DISPPLANE_TILED;
@@ -2082,27 +2096,31 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
dspcntr = I915_READ(reg);
/* Mask out pixel format bits in case we change it */
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
- switch (fb->bits_per_pixel) {
- case 8:
+ switch (fb->pixel_format) {
+ case DRM_FORMAT_C8:
dspcntr |= DISPPLANE_8BPP;
break;
- case 16:
- if (fb->depth != 16)
- return -EINVAL;
-
- dspcntr |= DISPPLANE_16BPP;
- break;
- case 24:
- case 32:
- if (fb->depth == 24)
-
