Re: [Intel-gfx] [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface.

2014-05-07 Thread Ville Syrjälä 
On Mon, May 05, 2014 at 06:17:31PM +0530, deepa...@linux.intel.com wrote:
 From: Deepak S deepa...@linux.intel.com
 
 In BDW, Apart from unmasking up/down threshold interrupts. we need
 to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
 Interface.
 
 v2: Add (131) mask (Ville)
 
 Signed-off-by: Deepak S deepa...@linux.intel.com
 ---
  drivers/gpu/drm/i915/i915_reg.h | 1 +
  drivers/gpu/drm/i915/intel_pm.c | 2 ++
  2 files changed, 3 insertions(+)
 
 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
 index ca4f8b9..c850254 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -5112,6 +5112,7 @@ enum punit_power_well {
  #define GEN6_RC6p_THRESHOLD  0xA0BC
  #define GEN6_RC6pp_THRESHOLD 0xA0C0
  #define GEN6_PMINTRMSK   0xA168
 +#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (131)
  
  #define GEN6_PMISR   0x44020
  #define GEN6_PMIMR   0x44024 /* rps_lock */
 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
 index 0e69c97..ebb5c88 100644
 --- a/drivers/gpu/drm/i915/intel_pm.c
 +++ b/drivers/gpu/drm/i915/intel_pm.c
 @@ -3114,6 +3114,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private 
 *dev_priv, u8 val)
   if (INTEL_INFO(dev_priv-dev)-gen = 7  !IS_HASWELL(dev_priv-dev))
   mask |= GEN6_PM_RP_UP_EI_EXPIRED;
  
 + mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 +

Didn't Ben want a gen check here?

   return ~mask;
  }
  
 -- 
 1.9.1
 
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Ville Syrjälä
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[Intel-gfx] [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface.

2014-05-05 Thread deepak . s 
From: Deepak S deepa...@linux.intel.com

In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.

v2: Add (131) mask (Ville)

Signed-off-by: Deepak S deepa...@linux.intel.com
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca4f8b9..c850254 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5112,6 +5112,7 @@ enum punit_power_well {
 #define GEN6_RC6p_THRESHOLD0xA0BC
 #define GEN6_RC6pp_THRESHOLD   0xA0C0
 #define GEN6_PMINTRMSK 0xA168
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP   (131)
 
 #define GEN6_PMISR 0x44020
 #define GEN6_PMIMR 0x44024 /* rps_lock */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0e69c97..ebb5c88 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3114,6 +3114,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private 
*dev_priv, u8 val)
if (INTEL_INFO(dev_priv-dev)-gen = 7  !IS_HASWELL(dev_priv-dev))
mask |= GEN6_PM_RP_UP_EI_EXPIRED;
 
+   mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
return ~mask;
 }
 
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface.

2014-04-25 Thread Ben Widawsky 
On Mon, Apr 21, 2014 at 01:34:06PM +0530, deepa...@linux.intel.com wrote:

For backporters, putting drm/i915/bdw would be helpful.

 From: Deepak S deepa...@linux.intel.com
 
 In BDW, Apart from unmasking up/down threshold interrupts. we need
 to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
 Interface.
 
 v2: Add (131) mask (Ville)
 
 Signed-off-by: Deepak S deepa...@linux.intel.com
 ---
  drivers/gpu/drm/i915/i915_reg.h | 1 +
  drivers/gpu/drm/i915/intel_pm.c | 2 ++
  2 files changed, 3 insertions(+)
 
 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
 index c2dd436..b951d61 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -5105,6 +5105,7 @@ enum punit_power_well {
  #define GEN6_RC6p_THRESHOLD  0xA0BC
  #define GEN6_RC6pp_THRESHOLD 0xA0C0
  #define GEN6_PMINTRMSK   0xA168
 +#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (131)
  
  #define GEN6_PMISR   0x44020
  #define GEN6_PMIMR   0x44024 /* rps_lock */
 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
 index 3dccee6..f3c5bce 100644
 --- a/drivers/gpu/drm/i915/intel_pm.c
 +++ b/drivers/gpu/drm/i915/intel_pm.c
 @@ -3066,6 +3066,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private 
 *dev_priv, u8 val)
   if (INTEL_INFO(dev_priv-dev)-gen = 7  !IS_HASWELL(dev_priv-dev))
   mask |= GEN6_PM_RP_UP_EI_EXPIRED;
  
 + mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 +
   return ~mask;
  }
if (IS_BROADWELL(dev)), or gen= 8
mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;

I didn't read if CHV actually needs it, or not.

With that fixed:
Reviewed-by: Ben Widawsky b...@bwidawsk.net

-- 
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[Intel-gfx] [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface.

2014-04-21 Thread deepak . s 
From: Deepak S deepa...@linux.intel.com

In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.

v2: Add (131) mask (Ville)

Signed-off-by: Deepak S deepa...@linux.intel.com
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2dd436..b951d61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5105,6 +5105,7 @@ enum punit_power_well {
 #define GEN6_RC6p_THRESHOLD0xA0BC
 #define GEN6_RC6pp_THRESHOLD   0xA0C0
 #define GEN6_PMINTRMSK 0xA168
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP   (131)
 
 #define GEN6_PMISR 0x44020
 #define GEN6_PMIMR 0x44024 /* rps_lock */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3dccee6..f3c5bce 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3066,6 +3066,8 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private 
*dev_priv, u8 val)
if (INTEL_INFO(dev_priv-dev)-gen = 7  !IS_HASWELL(dev_priv-dev))
mask |= GEN6_PM_RP_UP_EI_EXPIRED;
 
+   mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
+
return ~mask;
 }
 
-- 
1.9.1

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