This patch configures utility pin for DSI command
mode operation as per BSPEC DSI trancoder enable
sequence.
Signed-off-by: Madhav Chauhan <madhav.chau...@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 19a3815..a175349 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -874,6 +874,21 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder
*encoder)
}
}
+static void gen11_dsi_config_utility_pin(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+
+ if (intel_dsi->operation_mode != INTEL_DSI_COMMAND_MODE)
+ return;
+
+ tmp = I915_READ(UTIL_PIN_CTL);
+ tmp |= ICL_UTIL_PIN_DIRECTION;
+ tmp |= UTIL_PIN_ENABLE;
+ I915_WRITE(UTIL_PIN_CTL, tmp);
+}
+
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
@@ -892,6 +907,9 @@ static void gen11_dsi_enable_port_and_phy(struct
intel_encoder *encoder,
/* step 4e: setup D-PHY timings */
gen11_dsi_setup_dphy_timings(encoder);
+ /* step 4f: config utility pin */
+ gen11_dsi_config_utility_pin(encoder);
+
/* step 4g: setup DSI protocol timeouts */
gen11_dsi_setup_timeouts(encoder);
--
2.7.4
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