Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-09-05 Thread Ville Syrjälä 
On Thu, Sep 04, 2014 at 10:47:41AM -0700, Clint Taylor wrote:
 On 08/26/2014 07:06 AM, Ville Syrjälä wrote:
  On Tue, Aug 26, 2014 at 03:36:07PM +0200, Daniel Vetter wrote:
  On Tue, Aug 26, 2014 at 04:21:00PM +0300, Jani Nikula wrote:
  On Tue, 26 Aug 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
  On Tue, Aug 19, 2014 at 10:00:55AM +0300, Jani Nikula wrote:
  On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
  From: Ville Syrjälä ville.syrj...@linux.intel.com
 
  Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
  and flatten the rest of the function.
 
  Please imagine adding another platform there, and realize this just adds
  unnecessary churn.
 
  I'd just add another reboot notifier then.
 
  Fair enough; it should be vlv_edp_notify_handler then. (No, don't send a
  patch to change that! ;)
 
  Frankly I don't understand the current one either. Why does it need to
  set the delay to max for instance? And does this mean that the
  PANEL_POWER_RESET bit doesn't actually work as advertised in the docs?
 
  *shrug* experimental evidence?
 
  commit 01527b3127997ef6370d5ad4fa25d96847fbf12a
  Author: Clint Taylor clinton.a.tay...@intel.com
  Date:   Mon Jul 7 13:01:46 2014 -0700
 
   drm/i915/vlv: T12 eDP panel timing enforcement during reboot
 
   The panel power sequencer on vlv doesn't appear to accept changes to 
  its
   T12 power down duration during warm reboots. This change forces a 
  delay
   for warm reboots to the T12 panel timing as defined in the VBT table 
  for
   the connected panel.
 
  So if I remember this piece of lore correctly in the past the pp was
  pessimistic, and enforced this delay on resume/boot-up, assuming you've
  shut down _right_ before the machine was lit up again. Apparently people
  where unhappy with that enforced delay and it was ditched on vlv, but then
  it broke panels if you actually managed to reboot quickly enough.
 
  IIRC the way the reset bit is documented the hardware itself is supposed
  to initiate the power off cycle when it gets some reset notification and
  it should enforce the timing before allowing the panel power to be
  re-enabled. Although it does seem that it would also reset the
  power cycle delay so it would maybe only enforce some default delay in
  that case (300ms based on the documented default value of 0x4). So if the
  panel requires more than the 300ms then I understand the msleep() here.
  I guess use of the VDD force bit just after reset might also require that
  we do the power down + wait before reset. So that part does make sense
  to me, but I still don't understand the power cycle delay=0x1f part.
 
 All eDP panels require at least 500ms according to the eDP 
 specifications T12 minimum of 500ms. The panel manufacturer's 
 specifications I have seen also have a 500ms minimum. Is the default 
 register value of 4 relevant for LVDS?

IIRC I saw 400ms mentioned for LVDS somewhere, so I have no idea why
someone made the default 300ms. Not that I actaully verified that the
reset valus is indeed 4 on actual hardware, I just read it from the spec.

  From our testing on VLV the PPS starts immediately upon ungate of the 
 display block. There is no way to stop or alter this sequence that 
 starts with the default value (4) in the register. The panel power will 
 assert at the end of the sequence. Without the msleep() adding time a 
 quick rebooting platform will not meet the 500ms minimum.

Ok so I guess in theory we could do msleep(whatever-300) and we should
still meet the panel timings, assuming we care to optimize a few hunder
ms here.

 
 power cycle delay of 0x1f was added to prevent LCD_VDD from asserting 
 before the reboot actually completes which includes the msleep() time. 
 The power cycle delay value could be computed based on the T12 time in 
 the VBT. Just setting the highest value made sense for simplicity and 
 the fact the value is reset to default during the reboot.

At that point we should have the correct t11_t12 delay programmed into the
register already. Also it shouldn't really matter what we have in there
because of the msleep(). By the time the msleep() is done and we reboot,
the register gets reset to defaul anyway, and it should be OK to enable
VDD again, even immediately rather than after the default 300ms since we
already slept for the entire power cycle delay before rebooting.

 The PANEL_POWER_RESET bit doesn't actually work as advertised 
 statement was probably in error based on my understanding of the PPS at 
 the time the patch was made.

OK, so I guess it sort of works then, except since it resets the power cycle
delay to 300ms it waits for less than it should. So yeah seems we do
need the manual sleep to make sure we don't violate the panel timings. I
guess we should then add the reboot notifier for all platforms since
this power sequencer reset behaviour isn't specific to VLV.

-- 
Ville Syrjälä
Intel OTC

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-09-04 Thread Clint Taylor 

On 08/26/2014 07:06 AM, Ville Syrjälä wrote:

On Tue, Aug 26, 2014 at 03:36:07PM +0200, Daniel Vetter wrote:

On Tue, Aug 26, 2014 at 04:21:00PM +0300, Jani Nikula wrote:

On Tue, 26 Aug 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:

On Tue, Aug 19, 2014 at 10:00:55AM +0300, Jani Nikula wrote:

On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä ville.syrj...@linux.intel.com

Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
and flatten the rest of the function.


Please imagine adding another platform there, and realize this just adds
unnecessary churn.


I'd just add another reboot notifier then.


Fair enough; it should be vlv_edp_notify_handler then. (No, don't send a
patch to change that! ;)


Frankly I don't understand the current one either. Why does it need to
set the delay to max for instance? And does this mean that the
PANEL_POWER_RESET bit doesn't actually work as advertised in the docs?


*shrug* experimental evidence?

commit 01527b3127997ef6370d5ad4fa25d96847fbf12a
Author: Clint Taylor clinton.a.tay...@intel.com
Date:   Mon Jul 7 13:01:46 2014 -0700

 drm/i915/vlv: T12 eDP panel timing enforcement during reboot

 The panel power sequencer on vlv doesn't appear to accept changes to its
 T12 power down duration during warm reboots. This change forces a delay
 for warm reboots to the T12 panel timing as defined in the VBT table for
 the connected panel.


So if I remember this piece of lore correctly in the past the pp was
pessimistic, and enforced this delay on resume/boot-up, assuming you've
shut down _right_ before the machine was lit up again. Apparently people
where unhappy with that enforced delay and it was ditched on vlv, but then
it broke panels if you actually managed to reboot quickly enough.


IIRC the way the reset bit is documented the hardware itself is supposed
to initiate the power off cycle when it gets some reset notification and
it should enforce the timing before allowing the panel power to be
re-enabled. Although it does seem that it would also reset the
power cycle delay so it would maybe only enforce some default delay in
that case (300ms based on the documented default value of 0x4). So if the
panel requires more than the 300ms then I understand the msleep() here.
I guess use of the VDD force bit just after reset might also require that
we do the power down + wait before reset. So that part does make sense
to me, but I still don't understand the power cycle delay=0x1f part.

All eDP panels require at least 500ms according to the eDP 
specifications T12 minimum of 500ms. The panel manufacturer's 
specifications I have seen also have a 500ms minimum. Is the default 
register value of 4 relevant for LVDS?


From our testing on VLV the PPS starts immediately upon ungate of the 
display block. There is no way to stop or alter this sequence that 
starts with the default value (4) in the register. The panel power will 
assert at the end of the sequence. Without the msleep() adding time a 
quick rebooting platform will not meet the 500ms minimum.


power cycle delay of 0x1f was added to prevent LCD_VDD from asserting 
before the reboot actually completes which includes the msleep() time. 
The power cycle delay value could be computed based on the T12 time in 
the VBT. Just setting the highest value made sense for simplicity and 
the fact the value is reset to default during the reboot.


The PANEL_POWER_RESET bit doesn't actually work as advertised 
statement was probably in error based on my understanding of the PPS at 
the time the patch was made.


Clint


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Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-08-26 Thread Ville Syrjälä 
On Tue, Aug 19, 2014 at 10:00:55AM +0300, Jani Nikula wrote:
 On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
  From: Ville Syrjälä ville.syrj...@linux.intel.com
 
  Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
  and flatten the rest of the function.
 
 Please imagine adding another platform there, and realize this just adds
 unnecessary churn.

I'd just add another reboot notifier then. Frankly I don't understand
the current one either. Why does it need to set the delay to max for
instance? And does this mean that the PANEL_POWER_RESET bit doesn't
actually work as advertised in the docs?

 
 BR,
 Jani.
 
 
 
  Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
  ---
   drivers/gpu/drm/i915/intel_dp.c | 24 
   1 file changed, 12 insertions(+), 12 deletions(-)
 
  diff --git a/drivers/gpu/drm/i915/intel_dp.c 
  b/drivers/gpu/drm/i915/intel_dp.c
  index 43dd226..a9ed2a6 100644
  --- a/drivers/gpu/drm/i915/intel_dp.c
  +++ b/drivers/gpu/drm/i915/intel_dp.c
  @@ -347,22 +347,22 @@ static int edp_notify_handler(struct notifier_block 
  *this, unsigned long code,
  struct drm_i915_private *dev_priv = dev-dev_private;
  u32 pp_div;
  u32 pp_ctrl_reg, pp_div_reg;
  -   enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
  +   enum pipe pipe;
   
  -   if (!is_edp(intel_dp) || code != SYS_RESTART)
  +   if (!IS_VALLEYVIEW(dev) || !is_edp(intel_dp) || code != SYS_RESTART)
  return 0;
   
  -   if (IS_VALLEYVIEW(dev)) {
  -   pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
  -   pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
  -   pp_div = I915_READ(pp_div_reg);
  -   pp_div = PP_REFERENCE_DIVIDER_MASK;
  +   pipe = vlv_power_sequencer_pipe(intel_dp);
   
  -   /* 0x1F write to PP_DIV_REG sets max cycle delay */
  -   I915_WRITE(pp_div_reg, pp_div | 0x1F);
  -   I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
  -   msleep(intel_dp-panel_power_cycle_delay);
  -   }
  +   pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
  +   pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
  +   pp_div = I915_READ(pp_div_reg);
  +   pp_div = PP_REFERENCE_DIVIDER_MASK;
  +
  +   /* 0x1F write to PP_DIV_REG sets max cycle delay */
  +   I915_WRITE(pp_div_reg, pp_div | 0x1F);
  +   I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
  +   msleep(intel_dp-panel_power_cycle_delay);
   
  return 0;
   }
  -- 
  1.8.5.5
 
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 -- 
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-- 
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Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-08-26 Thread Jani Nikula 
On Tue, 26 Aug 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
 On Tue, Aug 19, 2014 at 10:00:55AM +0300, Jani Nikula wrote:
 On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
  From: Ville Syrjälä ville.syrj...@linux.intel.com
 
  Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
  and flatten the rest of the function.
 
 Please imagine adding another platform there, and realize this just adds
 unnecessary churn.

 I'd just add another reboot notifier then.

Fair enough; it should be vlv_edp_notify_handler then. (No, don't send a
patch to change that! ;)

 Frankly I don't understand the current one either. Why does it need to
 set the delay to max for instance? And does this mean that the
 PANEL_POWER_RESET bit doesn't actually work as advertised in the docs?

*shrug* experimental evidence?

commit 01527b3127997ef6370d5ad4fa25d96847fbf12a
Author: Clint Taylor clinton.a.tay...@intel.com
Date:   Mon Jul 7 13:01:46 2014 -0700

drm/i915/vlv: T12 eDP panel timing enforcement during reboot

The panel power sequencer on vlv doesn't appear to accept changes to its
T12 power down duration during warm reboots. This change forces a delay
for warm reboots to the T12 panel timing as defined in the VBT table for
the connected panel.



 
 BR,
 Jani.
 
 
 
  Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
  ---
   drivers/gpu/drm/i915/intel_dp.c | 24 
   1 file changed, 12 insertions(+), 12 deletions(-)
 
  diff --git a/drivers/gpu/drm/i915/intel_dp.c 
  b/drivers/gpu/drm/i915/intel_dp.c
  index 43dd226..a9ed2a6 100644
  --- a/drivers/gpu/drm/i915/intel_dp.c
  +++ b/drivers/gpu/drm/i915/intel_dp.c
  @@ -347,22 +347,22 @@ static int edp_notify_handler(struct notifier_block 
  *this, unsigned long code,
 struct drm_i915_private *dev_priv = dev-dev_private;
 u32 pp_div;
 u32 pp_ctrl_reg, pp_div_reg;
  -  enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
  +  enum pipe pipe;
   
  -  if (!is_edp(intel_dp) || code != SYS_RESTART)
  +  if (!IS_VALLEYVIEW(dev) || !is_edp(intel_dp) || code != SYS_RESTART)
 return 0;
   
  -  if (IS_VALLEYVIEW(dev)) {
  -  pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
  -  pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
  -  pp_div = I915_READ(pp_div_reg);
  -  pp_div = PP_REFERENCE_DIVIDER_MASK;
  +  pipe = vlv_power_sequencer_pipe(intel_dp);
   
  -  /* 0x1F write to PP_DIV_REG sets max cycle delay */
  -  I915_WRITE(pp_div_reg, pp_div | 0x1F);
  -  I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
  -  msleep(intel_dp-panel_power_cycle_delay);
  -  }
  +  pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
  +  pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
  +  pp_div = I915_READ(pp_div_reg);
  +  pp_div = PP_REFERENCE_DIVIDER_MASK;
  +
  +  /* 0x1F write to PP_DIV_REG sets max cycle delay */
  +  I915_WRITE(pp_div_reg, pp_div | 0x1F);
  +  I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
  +  msleep(intel_dp-panel_power_cycle_delay);
   
 return 0;
   }
  -- 
  1.8.5.5
 
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 -- 
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 -- 
 Ville Syrjälä
 Intel OTC

-- 
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Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-08-26 Thread Ville Syrjälä 
On Tue, Aug 26, 2014 at 04:21:00PM +0300, Jani Nikula wrote:
 On Tue, 26 Aug 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
  On Tue, Aug 19, 2014 at 10:00:55AM +0300, Jani Nikula wrote:
  On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
   From: Ville Syrjälä ville.syrj...@linux.intel.com
  
   Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
   and flatten the rest of the function.
  
  Please imagine adding another platform there, and realize this just adds
  unnecessary churn.
 
  I'd just add another reboot notifier then.
 
 Fair enough; it should be vlv_edp_notify_handler then. (No, don't send a
 patch to change that! ;)
 
  Frankly I don't understand the current one either. Why does it need to
  set the delay to max for instance? And does this mean that the
  PANEL_POWER_RESET bit doesn't actually work as advertised in the docs?
 
 *shrug* experimental evidence?
 
 commit 01527b3127997ef6370d5ad4fa25d96847fbf12a
 Author: Clint Taylor clinton.a.tay...@intel.com
 Date:   Mon Jul 7 13:01:46 2014 -0700
 
 drm/i915/vlv: T12 eDP panel timing enforcement during reboot
 
 The panel power sequencer on vlv doesn't appear to accept changes to its
 T12 power down duration during warm reboots. This change forces a delay
 for warm reboots to the T12 panel timing as defined in the VBT table for
 the connected panel.

That explanation doesn't really make it any more clear to me. But if the
reboot notifier helps someone somehow I can live with it.

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-08-26 Thread Daniel Vetter 
On Tue, Aug 26, 2014 at 04:21:00PM +0300, Jani Nikula wrote:
 On Tue, 26 Aug 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
  On Tue, Aug 19, 2014 at 10:00:55AM +0300, Jani Nikula wrote:
  On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
   From: Ville Syrjälä ville.syrj...@linux.intel.com
  
   Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
   and flatten the rest of the function.
  
  Please imagine adding another platform there, and realize this just adds
  unnecessary churn.
 
  I'd just add another reboot notifier then.
 
 Fair enough; it should be vlv_edp_notify_handler then. (No, don't send a
 patch to change that! ;)
 
  Frankly I don't understand the current one either. Why does it need to
  set the delay to max for instance? And does this mean that the
  PANEL_POWER_RESET bit doesn't actually work as advertised in the docs?
 
 *shrug* experimental evidence?
 
 commit 01527b3127997ef6370d5ad4fa25d96847fbf12a
 Author: Clint Taylor clinton.a.tay...@intel.com
 Date:   Mon Jul 7 13:01:46 2014 -0700
 
 drm/i915/vlv: T12 eDP panel timing enforcement during reboot
 
 The panel power sequencer on vlv doesn't appear to accept changes to its
 T12 power down duration during warm reboots. This change forces a delay
 for warm reboots to the T12 panel timing as defined in the VBT table for
 the connected panel.

So if I remember this piece of lore correctly in the past the pp was
pessimistic, and enforced this delay on resume/boot-up, assuming you've
shut down _right_ before the machine was lit up again. Apparently people
where unhappy with that enforced delay and it was ditched on vlv, but then
it broke panels if you actually managed to reboot quickly enough.
-Daniel
-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-08-26 Thread Ville Syrjälä 
On Tue, Aug 26, 2014 at 03:36:07PM +0200, Daniel Vetter wrote:
 On Tue, Aug 26, 2014 at 04:21:00PM +0300, Jani Nikula wrote:
  On Tue, 26 Aug 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
   On Tue, Aug 19, 2014 at 10:00:55AM +0300, Jani Nikula wrote:
   On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
   
Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
and flatten the rest of the function.
   
   Please imagine adding another platform there, and realize this just adds
   unnecessary churn.
  
   I'd just add another reboot notifier then.
  
  Fair enough; it should be vlv_edp_notify_handler then. (No, don't send a
  patch to change that! ;)
  
   Frankly I don't understand the current one either. Why does it need to
   set the delay to max for instance? And does this mean that the
   PANEL_POWER_RESET bit doesn't actually work as advertised in the docs?
  
  *shrug* experimental evidence?
  
  commit 01527b3127997ef6370d5ad4fa25d96847fbf12a
  Author: Clint Taylor clinton.a.tay...@intel.com
  Date:   Mon Jul 7 13:01:46 2014 -0700
  
  drm/i915/vlv: T12 eDP panel timing enforcement during reboot
  
  The panel power sequencer on vlv doesn't appear to accept changes to its
  T12 power down duration during warm reboots. This change forces a delay
  for warm reboots to the T12 panel timing as defined in the VBT table for
  the connected panel.
 
 So if I remember this piece of lore correctly in the past the pp was
 pessimistic, and enforced this delay on resume/boot-up, assuming you've
 shut down _right_ before the machine was lit up again. Apparently people
 where unhappy with that enforced delay and it was ditched on vlv, but then
 it broke panels if you actually managed to reboot quickly enough.

IIRC the way the reset bit is documented the hardware itself is supposed
to initiate the power off cycle when it gets some reset notification and
it should enforce the timing before allowing the panel power to be
re-enabled. Although it does seem that it would also reset the
power cycle delay so it would maybe only enforce some default delay in
that case (300ms based on the documented default value of 0x4). So if the
panel requires more than the 300ms then I understand the msleep() here.
I guess use of the VDD force bit just after reset might also require that
we do the power down + wait before reset. So that part does make sense
to me, but I still don't understand the power cycle delay=0x1f part.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-08-19 Thread Jani Nikula 
On Mon, 18 Aug 2014, ville.syrj...@linux.intel.com wrote:
 From: Ville Syrjälä ville.syrj...@linux.intel.com

 Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
 and flatten the rest of the function.

Please imagine adding another platform there, and realize this just adds
unnecessary churn.

BR,
Jani.



 Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
 ---
  drivers/gpu/drm/i915/intel_dp.c | 24 
  1 file changed, 12 insertions(+), 12 deletions(-)

 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
 index 43dd226..a9ed2a6 100644
 --- a/drivers/gpu/drm/i915/intel_dp.c
 +++ b/drivers/gpu/drm/i915/intel_dp.c
 @@ -347,22 +347,22 @@ static int edp_notify_handler(struct notifier_block 
 *this, unsigned long code,
   struct drm_i915_private *dev_priv = dev-dev_private;
   u32 pp_div;
   u32 pp_ctrl_reg, pp_div_reg;
 - enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 + enum pipe pipe;
  
 - if (!is_edp(intel_dp) || code != SYS_RESTART)
 + if (!IS_VALLEYVIEW(dev) || !is_edp(intel_dp) || code != SYS_RESTART)
   return 0;
  
 - if (IS_VALLEYVIEW(dev)) {
 - pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 - pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 - pp_div = I915_READ(pp_div_reg);
 - pp_div = PP_REFERENCE_DIVIDER_MASK;
 + pipe = vlv_power_sequencer_pipe(intel_dp);
  
 - /* 0x1F write to PP_DIV_REG sets max cycle delay */
 - I915_WRITE(pp_div_reg, pp_div | 0x1F);
 - I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 - msleep(intel_dp-panel_power_cycle_delay);
 - }
 + pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 + pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 + pp_div = I915_READ(pp_div_reg);
 + pp_div = PP_REFERENCE_DIVIDER_MASK;
 +
 + /* 0x1F write to PP_DIV_REG sets max cycle delay */
 + I915_WRITE(pp_div_reg, pp_div | 0x1F);
 + I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 + msleep(intel_dp-panel_power_cycle_delay);
  
   return 0;
  }
 -- 
 1.8.5.5

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-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-08-18 Thread ville . syrjala 
From: Ville Syrjälä ville.syrj...@linux.intel.com

Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
and flatten the rest of the function.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 drivers/gpu/drm/i915/intel_dp.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 43dd226..a9ed2a6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -347,22 +347,22 @@ static int edp_notify_handler(struct notifier_block 
*this, unsigned long code,
struct drm_i915_private *dev_priv = dev-dev_private;
u32 pp_div;
u32 pp_ctrl_reg, pp_div_reg;
-   enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+   enum pipe pipe;
 
-   if (!is_edp(intel_dp) || code != SYS_RESTART)
+   if (!IS_VALLEYVIEW(dev) || !is_edp(intel_dp) || code != SYS_RESTART)
return 0;
 
-   if (IS_VALLEYVIEW(dev)) {
-   pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
-   pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
-   pp_div = I915_READ(pp_div_reg);
-   pp_div = PP_REFERENCE_DIVIDER_MASK;
+   pipe = vlv_power_sequencer_pipe(intel_dp);
 
-   /* 0x1F write to PP_DIV_REG sets max cycle delay */
-   I915_WRITE(pp_div_reg, pp_div | 0x1F);
-   I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
-   msleep(intel_dp-panel_power_cycle_delay);
-   }
+   pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
+   pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
+   pp_div = I915_READ(pp_div_reg);
+   pp_div = PP_REFERENCE_DIVIDER_MASK;
+
+   /* 0x1F write to PP_DIV_REG sets max cycle delay */
+   I915_WRITE(pp_div_reg, pp_div | 0x1F);
+   I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+   msleep(intel_dp-panel_power_cycle_delay);
 
return 0;
 }
-- 
1.8.5.5

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Re: [Intel-gfx] [PATCH 02/14] drm/i915: Reorganize vlv eDP reboot notifier

2014-08-18 Thread Clint Taylor 

On 08/18/2014 12:15 PM, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä ville.syrj...@linux.intel.com

Move the vlv_power_sequencer_pipe() after the IS_VALLEYVIEW() check
and flatten the rest of the function.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
  drivers/gpu/drm/i915/intel_dp.c | 24 
  1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 43dd226..a9ed2a6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -347,22 +347,22 @@ static int edp_notify_handler(struct notifier_block 
*this, unsigned long code,
struct drm_i915_private *dev_priv = dev-dev_private;
u32 pp_div;
u32 pp_ctrl_reg, pp_div_reg;
-   enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+   enum pipe pipe;

-   if (!is_edp(intel_dp) || code != SYS_RESTART)
+   if (!IS_VALLEYVIEW(dev) || !is_edp(intel_dp) || code != SYS_RESTART)
return 0;

-   if (IS_VALLEYVIEW(dev)) {
-   pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
-   pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
-   pp_div = I915_READ(pp_div_reg);
-   pp_div = PP_REFERENCE_DIVIDER_MASK;
+   pipe = vlv_power_sequencer_pipe(intel_dp);

-   /* 0x1F write to PP_DIV_REG sets max cycle delay */
-   I915_WRITE(pp_div_reg, pp_div | 0x1F);
-   I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
-   msleep(intel_dp-panel_power_cycle_delay);
-   }
+   pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
+   pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
+   pp_div = I915_READ(pp_div_reg);
+   pp_div = PP_REFERENCE_DIVIDER_MASK;
+
+   /* 0x1F write to PP_DIV_REG sets max cycle delay */
+   I915_WRITE(pp_div_reg, pp_div | 0x1F);
+   I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+   msleep(intel_dp-panel_power_cycle_delay);


Looks better..



return 0;
  }



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