subject:"\[Intel\-gfx\] \[PATCH 02\/17\] drm\/i915\/icl\: add basic support for the ICL clocks"

[Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

2018-03-22 Thread Paulo Zanoni

This commit introduces the definitions for the ICL clocks and adds the
basic functions to the shared DPLL framework. It adds code for the
Enable and Disable sequences for some PLLs, but it does not have the
code to compute the actual PLL values, which are marked as TODO
comments and should be introduced as separate commits.

Special thanks to James Ausmus for investigating and fixing a bug with
the placement of icl_unmap_plls_to_ports() function.

v2:
 - Rebase around dpll_lock changes.
v3:
 - The spec now says what the timeouts should be.
 - Touch DPCLKA_CFGCR0_ICL at the appropriate time so we don't freeze
   the machine.
 - Checkpatch found a white space problem.
 - Small adjustments before upstreaming.
v4:
 - Move the ICL checks out of the *map_plls_to_ports() functions
  (James)
 - Add extra encoder check (James)
 - Call icl_unmap_plls_to_ports() later (James)

Cc: James Ausmus 
Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_debugfs.c   |  22 +++
 drivers/gpu/drm/i915/intel_ddi.c  |  96 ++-
 drivers/gpu/drm/i915/intel_display.c  |  16 ++
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 311 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  41 +
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 6 files changed, 487 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7816cd53100a..d932f1540397 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3295,6 +3295,28 @@ static int i915_shared_dplls_info(struct seq_file *m, 
void *unused)
seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
+   seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
+   seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
+   seq_printf(m, " mg_refclkin_ctl:0x%08x\n",
+  pll->state.hw_state.mg_refclkin_ctl);
+   seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
+  pll->state.hw_state.mg_clktop2_coreclkctl1);
+   seq_printf(m, " mg_clktop2_hsclkctl:0x%08x\n",
+  pll->state.hw_state.mg_clktop2_hsclkctl);
+   seq_printf(m, " mg_pll_div0:  0x%08x\n",
+  pll->state.hw_state.mg_pll_div0);
+   seq_printf(m, " mg_pll_div1:  0x%08x\n",
+  pll->state.hw_state.mg_pll_div1);
+   seq_printf(m, " mg_pll_lf:0x%08x\n",
+  pll->state.hw_state.mg_pll_lf);
+   seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
+  pll->state.hw_state.mg_pll_frac_lock);
+   seq_printf(m, " mg_pll_ssc:   0x%08x\n",
+  pll->state.hw_state.mg_pll_ssc);
+   seq_printf(m, " mg_pll_bias:  0x%08x\n",
+  pll->state.hw_state.mg_pll_bias);
+   seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
+  pll->state.hw_state.mg_pll_tdc_coldst_bias);
}
drm_modeset_unlock_all(dev);
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8c2d778560f0..78cc332bf3fe 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -894,6 +894,23 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct 
intel_shared_dpll *pll)
}
 }
 
+static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
+  const struct intel_shared_dpll *pll)
+{
+   switch (pll->id) {
+   default:
+   MISSING_CASE(pll->id);
+   case DPLL_ID_ICL_DPLL0:
+   case DPLL_ID_ICL_DPLL1:
+   return DDI_CLK_SEL_NONE;
+   case DPLL_ID_ICL_MGPLL1:
+   case DPLL_ID_ICL_MGPLL2:
+   case DPLL_ID_ICL_MGPLL3:
+   case DPLL_ID_ICL_MGPLL4:
+   return DDI_CLK_SEL_MG;
+   }
+}
+
 /* Starting with Haswell, different DDI ports can work in FDI mode for
  * connection to the PCH-located connectors. For this, it is necessary to train
  * both the DDI port and PCH receiver for the desired DDI buffer settings.
@@ -2115,6 +2132,69 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
return DDI_BUF_TRANS_SELECT(level);
 }
 
+void icl_map_plls_to_ports(struct drm_crtc *crtc,
+  struct intel_crtc_state *crtc_state,
+  struct drm_atomic_state *old_state)
+{
+   struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+   struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+   struct drm_connector_state *conn_state;
+   struct drm_connector *conn;
+   int i;
+
+

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

2018-02-27 Thread James Ausmus

On Thu, Feb 22, 2018 at 12:55:04AM -0300, Paulo Zanoni wrote:
> This commit introduces the definitions for the ICL clocks and adds the
> basic functions to the shared DPLL framework. It adds code for the
> Enable and Disable sequences for some PLLs, but it does not have the
> code to compute the actual PLL values, which are marked as TODO
> comments and should be introduced as separate commits.
> 
> v2:
>  - Rebase around dpll_lock changes.
> v3:
>  - The spec now says what the timeouts should be.
>  - Touch DPCLKA_CFGCR0_ICL at the appropriate time so we don't freeze
>the machine.
>  - Checkpatch found a white space problem.
>  - Small adjustments before upstreaming.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c   |  22 +++
>  drivers/gpu/drm/i915/intel_ddi.c  | 102 ++-
>  drivers/gpu/drm/i915/intel_display.c  |  14 ++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 311 
> +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  41 +
>  drivers/gpu/drm/i915/intel_drv.h  |   6 +
>  6 files changed, 491 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 05b41045b8f9..7ccb5ef212a1 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3180,6 +3180,28 @@ static int i915_shared_dplls_info(struct seq_file *m, 
> void *unused)
>   seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
>   seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
>   seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
> + seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
> + seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
> + seq_printf(m, " mg_refclkin_ctl:0x%08x\n",
> +pll->state.hw_state.mg_refclkin_ctl);
> + seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
> +pll->state.hw_state.mg_clktop2_coreclkctl1);
> + seq_printf(m, " mg_clktop2_hsclkctl:0x%08x\n",
> +pll->state.hw_state.mg_clktop2_hsclkctl);
> + seq_printf(m, " mg_pll_div0:  0x%08x\n",
> +pll->state.hw_state.mg_pll_div0);
> + seq_printf(m, " mg_pll_div1:  0x%08x\n",
> +pll->state.hw_state.mg_pll_div1);
> + seq_printf(m, " mg_pll_lf:0x%08x\n",
> +pll->state.hw_state.mg_pll_lf);
> + seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
> +pll->state.hw_state.mg_pll_frac_lock);
> + seq_printf(m, " mg_pll_ssc:   0x%08x\n",
> +pll->state.hw_state.mg_pll_ssc);
> + seq_printf(m, " mg_pll_bias:  0x%08x\n",
> +pll->state.hw_state.mg_pll_bias);
> + seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
> +pll->state.hw_state.mg_pll_tdc_coldst_bias);
>   }
>   drm_modeset_unlock_all(dev);
>  
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 8ca376aca8bd..81383e3dc91f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -893,6 +893,23 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct 
> intel_shared_dpll *pll)
>   }
>  }
>  
> +static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
> +const struct intel_shared_dpll *pll)
> +{
> + switch (pll->id) {
> + default:
> + MISSING_CASE(pll->id);
> + case DPLL_ID_ICL_DPLL0:
> + case DPLL_ID_ICL_DPLL1:
> + return DDI_CLK_SEL_NONE;
> + case DPLL_ID_ICL_MGPLL1:
> + case DPLL_ID_ICL_MGPLL2:
> + case DPLL_ID_ICL_MGPLL3:
> + case DPLL_ID_ICL_MGPLL4:
> + return DDI_CLK_SEL_MG;
> + }
> +}
> +
>  /* Starting with Haswell, different DDI ports can work in FDI mode for
>   * connection to the PCH-located connectors. For this, it is necessary to 
> train
>   * both the DDI port and PCH receiver for the desired DDI buffer settings.
> @@ -2114,6 +2131,75 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>   return DDI_BUF_TRANS_SELECT(level);
>  }
>  
> +void icl_map_plls_to_ports(struct drm_crtc *crtc,
> +struct intel_crtc_state *crtc_state,
> +struct drm_atomic_state *old_state)
> +{
> + struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + struct drm_connector_state *conn_state;
> + struct drm_connector *conn;
> + int i;
> +
> + if (!IS_ICELAKE(dev_priv))
> + return;
> +
> + for_each_new_connector_in_state(old_state, conn, conn_state, i) {
> + struct

[Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

2018-02-21 Thread Paulo Zanoni

This commit introduces the definitions for the ICL clocks and adds the
basic functions to the shared DPLL framework. It adds code for the
Enable and Disable sequences for some PLLs, but it does not have the
code to compute the actual PLL values, which are marked as TODO
comments and should be introduced as separate commits.

v2:
 - Rebase around dpll_lock changes.
v3:
 - The spec now says what the timeouts should be.
 - Touch DPCLKA_CFGCR0_ICL at the appropriate time so we don't freeze
   the machine.
 - Checkpatch found a white space problem.
 - Small adjustments before upstreaming.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_debugfs.c   |  22 +++
 drivers/gpu/drm/i915/intel_ddi.c  | 102 ++-
 drivers/gpu/drm/i915/intel_display.c  |  14 ++
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 311 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  41 +
 drivers/gpu/drm/i915/intel_drv.h  |   6 +
 6 files changed, 491 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 05b41045b8f9..7ccb5ef212a1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3180,6 +3180,28 @@ static int i915_shared_dplls_info(struct seq_file *m, 
void *unused)
seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
+   seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
+   seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
+   seq_printf(m, " mg_refclkin_ctl:0x%08x\n",
+  pll->state.hw_state.mg_refclkin_ctl);
+   seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
+  pll->state.hw_state.mg_clktop2_coreclkctl1);
+   seq_printf(m, " mg_clktop2_hsclkctl:0x%08x\n",
+  pll->state.hw_state.mg_clktop2_hsclkctl);
+   seq_printf(m, " mg_pll_div0:  0x%08x\n",
+  pll->state.hw_state.mg_pll_div0);
+   seq_printf(m, " mg_pll_div1:  0x%08x\n",
+  pll->state.hw_state.mg_pll_div1);
+   seq_printf(m, " mg_pll_lf:0x%08x\n",
+  pll->state.hw_state.mg_pll_lf);
+   seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
+  pll->state.hw_state.mg_pll_frac_lock);
+   seq_printf(m, " mg_pll_ssc:   0x%08x\n",
+  pll->state.hw_state.mg_pll_ssc);
+   seq_printf(m, " mg_pll_bias:  0x%08x\n",
+  pll->state.hw_state.mg_pll_bias);
+   seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
+  pll->state.hw_state.mg_pll_tdc_coldst_bias);
}
drm_modeset_unlock_all(dev);
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8ca376aca8bd..81383e3dc91f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -893,6 +893,23 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct 
intel_shared_dpll *pll)
}
 }
 
+static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
+  const struct intel_shared_dpll *pll)
+{
+   switch (pll->id) {
+   default:
+   MISSING_CASE(pll->id);
+   case DPLL_ID_ICL_DPLL0:
+   case DPLL_ID_ICL_DPLL1:
+   return DDI_CLK_SEL_NONE;
+   case DPLL_ID_ICL_MGPLL1:
+   case DPLL_ID_ICL_MGPLL2:
+   case DPLL_ID_ICL_MGPLL3:
+   case DPLL_ID_ICL_MGPLL4:
+   return DDI_CLK_SEL_MG;
+   }
+}
+
 /* Starting with Haswell, different DDI ports can work in FDI mode for
  * connection to the PCH-located connectors. For this, it is necessary to train
  * both the DDI port and PCH receiver for the desired DDI buffer settings.
@@ -2114,6 +2131,75 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
return DDI_BUF_TRANS_SELECT(level);
 }
 
+void icl_map_plls_to_ports(struct drm_crtc *crtc,
+  struct intel_crtc_state *crtc_state,
+  struct drm_atomic_state *old_state)
+{
+   struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+   struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+   struct drm_connector_state *conn_state;
+   struct drm_connector *conn;
+   int i;
+
+   if (!IS_ICELAKE(dev_priv))
+   return;
+
+   for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+   struct intel_encoder *encoder =
+   to_intel_encoder(conn_state->best_encoder);
+   enum port port = encoder->port;
+   uint32_t val;
+
+   if

[Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

[Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

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