Re: [Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
> -Original Message-
> From: Intel-gfx On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, July 13, 2023 4:03 PM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check
> with 420 format inside the helper
>
> Move the check for limiting compressed bite_per_pixel for 420,422 formats
> in the helper to compute bits_per_pixel.
>
> Signed-off-by: Ankit Nautiyal
> ---
Looks good!
Reviewed-by: Arun R Murthy
Thanks and Regards,
Arun R Murthy
> drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e0d9618fccab..d1db457fb17c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -773,6 +773,15 @@ u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> bits_per_pixel *= 2;
>
> + /*
> + * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
> + * supported PPS value can be 63.9375 and with the further
> + * mention that for 420, 422 formats, bpp should be programmed
> double
> + * the target bpp restricting our target bpp to be 31.9375 at max.
> + */
> + if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> + bits_per_pixel = min_t(u32, bits_per_pixel, 31);
> +
> drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
> "total bw %u pixel clock %u\n",
> bits_per_pixel, timeslots,
> @@ -1738,15 +1747,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> pipe_config-
> >output_format,
> pipe_bpp,
> timeslots);
> - /*
> - * According to DSC 1.2a Section 4.1.1 Table 4.1 the
> maximum
> - * supported PPS value can be 63.9375 and with the
> further
> - * mention that bpp should be programmed double
> the target bpp
> - * restricting our target bpp to be 31.9375 at max
> - */
> - if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> - dsc_max_output_bpp = min_t(u16,
> dsc_max_output_bpp, 31 << 4);
> -
> if (!dsc_max_output_bpp) {
> drm_dbg_kms(&dev_priv->drm,
> "Compressed BPP not
> supported\n");
> --
> 2.40.1
[Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index e0d9618fccab..d1db457fb17c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -773,6 +773,15 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private
*i915,
if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
bits_per_pixel *= 2;
+ /*
+* According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
+* supported PPS value can be 63.9375 and with the further
+* mention that for 420, 422 formats, bpp should be programmed double
+* the target bpp restricting our target bpp to be 31.9375 at max.
+*/
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel = min_t(u32, bits_per_pixel, 31);
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1738,15 +1747,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
pipe_config->output_format,
pipe_bpp,
timeslots);
- /*
-* According to DSC 1.2a Section 4.1.1 Table 4.1 the
maximum
-* supported PPS value can be 63.9375 and with the
further
-* mention that bpp should be programmed double the
target bpp
-* restricting our target bpp to be 31.9375 at max
-*/
- if (pipe_config->output_format ==
INTEL_OUTPUT_FORMAT_YCBCR420)
- dsc_max_output_bpp = min_t(u16,
dsc_max_output_bpp, 31 << 4);
-
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
--
2.40.1
[Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f6061aa1cd42..e67071a6b5a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -764,6 +764,15 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private
*i915,
if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
bits_per_pixel *= 2;
+ /*
+* According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
+* supported PPS value can be 63.9375 and with the further
+* mention that for 420, 422 formats, bpp should be programmed double
+* the target bpp restricting our target bpp to be 31.9375 at max.
+*/
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel = min_t(u32, bits_per_pixel, 31);
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1729,15 +1738,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
pipe_config->output_format,
pipe_bpp,
timeslots);
- /*
-* According to DSC 1.2a Section 4.1.1 Table 4.1 the
maximum
-* supported PPS value can be 63.9375 and with the
further
-* mention that bpp should be programmed double the
target bpp
-* restricting our target bpp to be 31.9375 at max
-*/
- if (pipe_config->output_format ==
INTEL_OUTPUT_FORMAT_YCBCR420)
- dsc_max_output_bpp = min_t(u16,
dsc_max_output_bpp, 31 << 4);
-
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
--
2.40.1
