Re: [Intel-gfx] [PATCH 03/11] drm/i915/display: Consider fractional vdsc bpp while computing m_n values
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while computing m_n values.
>
> v1:
> Replace the computation of 'data_clock' with 'data_clock =
> DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng).
>
> v2:
> Rebase and pass bits_per_pixel in U6.4 format.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by: Ankit Nautiyal
> Signed-off-by: Mitul Golani
> Reviewed-by: Suraj Kandpal
> Reviewed-by: Sui Jingfeng
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_dp.c | 16
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++---
> drivers/gpu/drm/i915/display/intel_fdi.c | 3 ++-
> 4 files changed, 19 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b4a8e3087e50..125903007a29 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2415,12 +2415,12 @@ add_bw_alloc_overhead(int link_clock, int
> bw_overhead, }
>
> void
> -intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
> +intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
> int pixel_clock, int link_clock,
> int bw_overhead,
> struct intel_link_m_n *m_n)
> {
> - u32 data_clock = bits_per_pixel * pixel_clock;
> + u32 data_clock = DIV_ROUND_UP(bits_per_pixel_x16 * pixel_clock,
> 16);
> u32 data_m;
> u32 data_n;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4ad3718c3c7d..246f50d1f030 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2663,7 +2663,7 @@ static bool can_enable_drrs(struct intel_connector
> *connector, static void intel_dp_drrs_compute_config(struct intel_connector
> *connector,
>struct intel_crtc_state *pipe_config,
> - int link_bpp)
> + int link_bpp_x16)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> const struct drm_display_mode *downclock_mode = @@ -2688,7
> +2688,7 @@ intel_dp_drrs_compute_config(struct intel_connector
> *connector,
> if (pipe_config->splitter.enable)
> pixel_clock /= pipe_config->splitter.link_count;
>
> - intel_link_compute_m_n(link_bpp, pipe_config->lane_count,
> pixel_clock,
> + intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count,
> +pixel_clock,
> pipe_config->port_clock,
> intel_dp_bw_fec_overhead(pipe_config-
> >fec_enable),
> _config->dp_m2_n2);
> @@ -2792,7 +2792,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> const struct drm_display_mode *fixed_mode;
> struct intel_connector *connector = intel_dp->attached_connector;
> - int ret = 0, link_bpp;
> + int ret = 0, link_bpp_x16;
>
> if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder-
> >port != PORT_A)
> pipe_config->has_pch_encoder = true;
> @@ -2841,10 +2841,10 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> drm_dp_enhanced_frame_cap(intel_dp->dpcd);
>
> if (pipe_config->dsc.compression_enable)
> - link_bpp = to_bpp_int(pipe_config-
> >dsc.compressed_bpp_x16);
> + link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
> else
> - link_bpp = intel_dp_output_bpp(pipe_config-
> >output_format,
> -pipe_config->pipe_bpp);
> + link_bpp_x16 =
> to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
> + pipe_config-
> >pipe_bpp));
>
> if (intel_dp->mso_link_count) {
> int n = intel_dp->mso_link_count;
> @@ -2868,7 +2868,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>
> intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
>
> - intel_link_compute_m_n(link_bpp,
> + intel_link_compute_m_n(link_bpp_x16,
> pipe_config->lane_count,
> adjusted_mode->crtc_clock,
> pipe_config->port_clock,
> @@ -2884,7 +2884,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>
> intel_vrr_compute_config(pipe_config, conn_state);
> intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> - intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
> + intel_dp_drrs_compute_config(connector, pipe_config,
> link_bpp_x16);
> intel_dp_compute_vsc_sdp(intel_dp, pipe_config,
[Intel-gfx] [PATCH 03/11] drm/i915/display: Consider fractional vdsc bpp while computing m_n values
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
v1:
Replace the computation of 'data_clock' with 'data_clock =
DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng).
v2:
Rebase and pass bits_per_pixel in U6.4 format.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Mitul Golani
Reviewed-by: Suraj Kandpal
Reviewed-by: Sui Jingfeng
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dp.c | 16
drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++---
drivers/gpu/drm/i915/display/intel_fdi.c | 3 ++-
4 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b4a8e3087e50..125903007a29 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2415,12 +2415,12 @@ add_bw_alloc_overhead(int link_clock, int bw_overhead,
}
void
-intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
+intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
int pixel_clock, int link_clock,
int bw_overhead,
struct intel_link_m_n *m_n)
{
- u32 data_clock = bits_per_pixel * pixel_clock;
+ u32 data_clock = DIV_ROUND_UP(bits_per_pixel_x16 * pixel_clock, 16);
u32 data_m;
u32 data_n;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4ad3718c3c7d..246f50d1f030 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2663,7 +2663,7 @@ static bool can_enable_drrs(struct intel_connector
*connector,
static void
intel_dp_drrs_compute_config(struct intel_connector *connector,
struct intel_crtc_state *pipe_config,
-int link_bpp)
+int link_bpp_x16)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *downclock_mode =
@@ -2688,7 +2688,7 @@ intel_dp_drrs_compute_config(struct intel_connector
*connector,
if (pipe_config->splitter.enable)
pixel_clock /= pipe_config->splitter.link_count;
- intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
+ intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count,
pixel_clock,
pipe_config->port_clock,
intel_dp_bw_fec_overhead(pipe_config->fec_enable),
_config->dp_m2_n2);
@@ -2792,7 +2792,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
const struct drm_display_mode *fixed_mode;
struct intel_connector *connector = intel_dp->attached_connector;
- int ret = 0, link_bpp;
+ int ret = 0, link_bpp_x16;
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port !=
PORT_A)
pipe_config->has_pch_encoder = true;
@@ -2841,10 +2841,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
drm_dp_enhanced_frame_cap(intel_dp->dpcd);
if (pipe_config->dsc.compression_enable)
- link_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
+ link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
else
- link_bpp = intel_dp_output_bpp(pipe_config->output_format,
- pipe_config->pipe_bpp);
+ link_bpp_x16 =
to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
+
pipe_config->pipe_bpp));
if (intel_dp->mso_link_count) {
int n = intel_dp->mso_link_count;
@@ -2868,7 +2868,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
- intel_link_compute_m_n(link_bpp,
+ intel_link_compute_m_n(link_bpp_x16,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
@@ -2884,7 +2884,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_vrr_compute_config(pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
- intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
+ intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config,
conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
